JP2003338174A - Semiconductor memory device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent such a situation that data stored in a ferroelectric capacitor can not be read when read operation is performed repeatedly in a semiconductor memory device of a non-destruction read system. <P>SOLUTION: A driving circuit 5 applies read voltage to a first electrode 2a of a ferroelectric capacitor 2 storing data by deviation of polarization of a ferroelectric film 2c. A read FET 1 detects deviation of polarization of the ferroelectric film 2c when read voltage is applied to the first electrode 2a. Read voltage to be applied to the first electrode 2a is set to magnitude so that the deviation of polarization of the ferroelectric film 2c is returned to deviation before data is read when the read voltage is eliminated. A control circuit 6 prevents that voltage in a direction in which data stored in the ferroelectric film 2c is destroyed, is applied to the ferroelectric film 2c when read voltage is applied to the first electrode 2c. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a ferroelectric capacitor, and more particularly to a nondestructive read type semiconductor memory device and a driving method thereof.

[0002]

2. Description of the Related Art As a nondestructive read type semiconductor memory device having a ferroelectric capacitor, one having a circuit configuration shown in FIG. 6 is known.

That is, a conventional semiconductor memory device has a field effect transistor (hereinafter referred to as FET) 1 having a drain region 1a, a source region 1b and a gate electrode 1c.
And the first electrode 2a, the second electrode 2b and the ferroelectric film 2
and a ferroelectric capacitor 2 having c
The bit line BL is connected to the drain region 1a of T1 and the word line WL is connected to the first electrode 2a of the ferroelectric capacitor 2.

When writing data in this conventional semiconductor memory device, a write voltage is applied between the substrate 3 and the first electrode 2a of the ferroelectric capacitor 2 which serves as a control electrode. For example, when data is written by applying a positive voltage to the first electrode 2a with respect to the substrate 3, downward polarization occurs in the ferroelectric film 2c of the ferroelectric capacitor 2. After that, even if the first electrode 2a is grounded, a positive charge remains in the gate electrode 1c of the FET 1, so that the potential of the gate electrode 1c becomes positive.

If the potential of the gate electrode 1c exceeds the threshold voltage of the FET1, the FET1 is in the ON state. Therefore, if a potential difference is applied between the drain region 1a and the source region 1b, the drain region 1a and the source A current flows between the region 1b and the region. The logical state of such a ferroelectric memory is defined as "1", for example.

On the other hand, when a negative voltage with respect to the substrate 3 is applied to the first electrode 2a of the ferroelectric capacitor 2, upward polarization occurs in the ferroelectric film 2c of the ferroelectric capacitor 2. After that, even if the upper electrode 2a is grounded, the FET1
Since a negative charge remains on the gate electrode 1c, the potential of the gate electrode 1c becomes negative. In this case, since the potential of the gate electrode 1c is always smaller than the threshold voltage of the FET1, F
Since ET1 is in the off state, even if a potential difference is applied between the drain region 1a and the source region 1b, the drain region 1
No current flows between a and the source region 1b. The logical state of such a ferroelectric memory is defined as "0", for example.

Even if the power supply to the ferroelectric capacitor 2 is cut off, that is, even if the voltage is not applied to the first electrode 2a of the ferroelectric capacitor 2, the above-mentioned logic states are preserved. A nonvolatile semiconductor memory device is realized. That is, when the power supply is cut off for a certain period of time and then the power is supplied again to apply a voltage between the drain region 1a and the source region 1b, when the logic state is "1", the drain region 1a and the source region 1b are separated from each other. Since a current flows between them, data "1" can be read, but when the logic state is "0", no current flows between the drain region 1a and the source region 1b, so read data "0". You can

[0008]

However, a potential is generated in the gate electrode 1c of the FET 1 after writing the data, and the ability to hold the gate potential determines the retention characteristic. Due to the resistance component, the time constant until the ferroelectric capacitor is discharged is short, so that there is a problem that the data retention capacity is short, that is, the retention characteristic is not good.

Therefore, a semiconductor memory device as shown in FIG. 7 is considered. That is, a read FET 1 having a source region 1a, a drain region 1b and a gate electrode 1c,
A ferroelectric capacitor 2 having a first electrode 2a, a second electrode 2b and a ferroelectric film 2c, and a selection FET 4 having a source region 4a, a drain region 4b and a gate electrode 4c.
And a semiconductor memory device including. The second electrode 2b of the ferroelectric capacitor 2 is the gate electrode 1 of the read FET 1.
c and the source region 4a of the selection FET 4, the first electrode 2a of the ferroelectric capacitor 2 is connected to the source region 4a of the selection FET 4, and the first electrode 2a of the ferroelectric capacitor 2 is connected.
Electrode 2a is connected to the drain region 4b of the selection FET 4 and the word line WL, the drain region 1b of the read FET 1 is connected to the bit line BL, the source region 1a of the read FET 1 is connected to the plate line CP, and the selection FET
The gate electrode 4c of No. 4 is connected to the control line BS.
In FIG. 7, reference numeral 3 indicates a substrate on which the read FET 1 is formed.

The method of driving this semiconductor memory device is as follows.

First, when writing data, the gate potential and the substrate potential of the read FET 1 are set to the ground voltage, and then the word line WL, the bit line BL, and the plate line C.
P and the potential of all the signal lines of the control line BS are set to 0V,
Then, the word line WL is set to a positive or negative write voltage to cause downward polarization or upward polarization in the ferroelectric film 2c of the ferroelectric capacitor 2. Here, the state in which downward polarization occurs in the ferroelectric film 2 is defined as data “1”, and the state in which upward polarization occurs in the ferroelectric film 2 is defined as data “0”. .

When the data write operation is completed, the potential of the word line WL is set to 0V. This way,
When the data "1" (polarization is downward) is stored, the gate electrode 1c of the read FET 1 holds a positive potential, and the data "0" (polarization is upward) is stored. In this case, the gate electrode 1c of the read FET 1 holds a negative potential.

After that, the potential of the control line BS is set to the selection FET4.
The threshold voltage is raised above the threshold voltage and the select FET 4 is turned on. By doing so, both the first electrode 2a and the second electrode 2b of the ferroelectric capacitor 2 become 0V, so even if the potential of the control line BS is set to 0V and the selection FET 4 is turned off, Since there is no potential difference between the electrode 2a and the second electrode 2b, the magnitude of polarization of the ferroelectric film 2b is preserved.

Next, when reading data, a read voltage V _RD is applied to the word line WL. By doing so, a potential difference V _RD is generated between the word line WL and the substrate 3,
This potential difference is divided according to the capacitance value of the ferroelectric capacitor 2 and the gate capacitance value of the read FET 1. Then, the threshold voltage of the read FET 1 is set to the first voltage applied to the read FET 1 after the potential difference V _RD is capacitance-divided when the data “1” is written in the ferroelectric capacitor 2 and the ferroelectric voltage. When the data “0” is written in the body capacitor 2 and the potential difference V _RD is capacitance-divided and set to an intermediate value between the second voltage applied to the read FET 1, the data “1” is set. The read FET 1 is turned off when reading data, and the read FET 1 is turned on when reading data “0”. Therefore, when a potential difference is applied between the plate line CP and the bit line BL, no current flows through the read FET 1 when the data “1” is stored, while the current flows through the read FET 1 when the data “0” is stored. Since a current flows, it is possible to determine whether the stored data is "1" or "0".

Here, the capacitance value of the ferroelectric capacitor 2 and the gate capacitance value of the read FET 1 are adjusted so that when the read voltage V _RD is applied to the word line WL, it is applied to the ferroelectric capacitor 2. If the voltage is set to a value such that the polarization deviation (direction) of the ferroelectric film 2c of the ferroelectric capacitor 2 does not change, for example, a value that does not exceed the coercive voltage of the ferroelectric capacitor 2, the read operation is performed. At the time, when the voltage applied to the ferroelectric capacitor 2 is removed, the polarization deviation of the ferroelectric film 2c returns to the deviation before reading the data.

By the way, conventionally, in designing a peripheral circuit for controlling various signal lines of a semiconductor memory device, it is important to increase the operating speed of the device and prevent malfunction. That is, the operating speed is increased by shortening the rising and falling transition times of the cell selection signal or the read signal, etc., and the operation order is not changed due to the delay of the voltage transition of the signal line. Has been done. Therefore, the design is performed in consideration of reducing the load such as wiring resistance and increasing the driving capability of the signal line. Further, in order to prevent malfunction, the timing margin is optimized and the signal waveform is stabilized, and the control signal drive circuit is designed so that the waveform of the control signal does not overshoot.

However, in the nondestructive read type semiconductor memory device, there is a problem that the data is easily rewritten depending on the magnitude and direction of the voltage applied to the ferroelectric film at the time of reading the data. Especially when applying or removing the read voltage,
When the loads of the circuits connected to the two electrodes of the ferroelectric capacitor to which the read voltage is applied are different and, for example, the load on the opposite side of the drive circuit, that is, the side to which the read transistor 1 is connected is large, In some cases, the voltage transition on the side to which the read transistor 1 is connected is delayed, which may cause a voltage in the direction of destroying data to be applied to the ferroelectric film.

For this reason, the polarization amount of the ferroelectric capacitor decreases, so that there is a problem in that the data stored in the ferroelectric capacitor cannot be read when the read operation is repeated.

In a semiconductor memory device having a memory cell array structure, depending on the driving method, the ferroelectric capacitors of the unselected memory cells may be included in the memory capacitors when writing or reading data to or from other memory cell blocks. In some cases, a voltage in the direction of destroying data such as is applied. Therefore, there arises a problem that the data stored in the unselected memory cell cannot be read.

In view of the above, it is an object of the present invention to prevent a situation in which data stored in a ferroelectric capacitor cannot be read when a read operation is repeated in a nondestructive read type semiconductor memory device. And

[0021]

In order to achieve the above-mentioned object, a semiconductor memory device according to the present invention includes a ferroelectric capacitor for storing data by deviation of polarization of a ferroelectric film, and a ferroelectric capacitor. Data is read by detecting the voltage deviation of the ferroelectric film when a read voltage is applied to one of the pair of electrodes and a read voltage applied to the other electrode. The detection means and the voltage removal means for removing the read voltage applied to one electrode are provided, and when the read voltage is removed, the polarization deviation of the ferroelectric film reads the data when the read voltage is removed. Targeting a semiconductor memory device that is set to a size that returns to the previous deviation, when a read voltage is applied to one electrode, the ferroelectric film stores the ferroelectric film. And a control means for preventing the direction of the voltage to destroy over data is applied.

According to the semiconductor memory device of the present invention, when a read voltage is applied to one electrode of the ferroelectric capacitor, the ferroelectric film is stored in the ferroelectric film of the ferroelectric capacitor. Since the voltage that destroys the existing data is not applied, it is possible to prevent the situation in which the data stored in the ferroelectric capacitor cannot be read even if the read operation is repeated.

In the semiconductor memory device according to the present invention, the control means has means for reducing a potential difference generated between a pair of electrodes of the ferroelectric capacitor when a read voltage is applied to one electrode. Is preferred.

In this way, the potential difference generated between the pair of electrodes of the ferroelectric capacitor when a read voltage is applied to one electrode is reduced, so that the ferroelectric film is formed on the ferroelectric film. It is possible to reliably prevent a situation in which a voltage is applied in a direction that destroys the data stored in the memory.

In the semiconductor memory device according to the present invention, the read voltage is such that the data stored in the ferroelectric film is destroyed in the ferroelectric film when the read voltage is applied to one electrode. The size is preferably set so that no voltage is applied.

With this arrangement, when a read voltage is applied to one of the electrodes, a voltage that destroys the data stored in the ferroelectric film is not applied to the ferroelectric film. It is possible to reliably prevent a situation in which a voltage is applied to the body film in a direction that destroys the data stored in the ferroelectric film.

In the semiconductor memory device according to the present invention, the read voltage is such that when the read voltage is applied to one electrode, the change in voltage at one electrode is equal to or greater than the time constant at the other electrode of the pair of electrodes. The size is preferably set so as to have a transition time.

By so doing, it is possible to reliably prevent the situation where a voltage is applied to the ferroelectric film in the direction of destroying the data stored in the ferroelectric film.

In the semiconductor memory device according to the present invention, a plurality of ferroelectric capacitors are provided in an array,
The control means reads the data stored in the ferroelectric film of one of the plurality of ferroelectric capacitors when reading the data stored in the other ferroelectric capacitor of the plurality of ferroelectric capacitors. It is preferable to prevent a voltage in the direction of destroying the data stored in the ferroelectric film from being applied to the ferroelectric film of the body capacitor.

By doing so, in the semiconductor memory device in which the ferroelectric capacitors are arranged in an array, the ferroelectric film of another ferroelectric capacitor different from the ferroelectric capacitor to which the read voltage is applied, Since the voltage in the direction of destroying the data stored in the ferroelectric film is not applied, the data stored in the ferroelectric film of another ferroelectric capacitor is not destroyed.

In the method for driving a semiconductor memory device according to the present invention, a read voltage is applied to one electrode of a pair of electrodes of a ferroelectric capacitor that stores data by polarization deviation of the ferroelectric film, The data read step of reading data by detecting the polarization deviation of the ferroelectric film and the voltage removal step of removing the read voltage applied to one electrode are provided. The method of driving the semiconductor memory device is such that the deviation of the polarization of the ferroelectric film returns to the deviation before reading the data when the data is read. The method includes a step of preventing a voltage in the direction of destroying the data stored in the ferroelectric film from being applied to the body film.

According to the driving method of the semiconductor memory device of the present invention, when a read voltage is applied to one electrode of the ferroelectric capacitor, the ferroelectric film is formed on the ferroelectric film of the ferroelectric capacitor. Since the voltage in the direction of destroying the data stored in is no longer applied, it is possible to prevent the data stored in the ferroelectric capacitor from becoming unreadable even if the read operation is repeated.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A semiconductor memory device according to a first embodiment of the present invention will be described below with reference to FIG.
2 and FIG. 2.

The semiconductor memory device according to the first embodiment is
As shown in FIG. 1, a drive circuit 5 for applying a write voltage or a read voltage to the first electrode 2a is connected to the first electrode 2a of the ferroelectric capacitor 2, and
First electrode 2a and second electrode 2 of ferroelectric capacitor 2
Between b and b, a voltage outside the setting, for example, a voltage in the direction of destroying the data stored in the ferroelectric film 2c, is applied to the ferroelectric capacitor 2 except when data is being rewritten. A control circuit 6 for preventing this is connected.

FIG. 2 shows the control circuit 6 according to the first embodiment.
The control circuit 6 is composed of a pair of series circuits which are composed of a transistor 6a and a diode 6b which are connected in series, and which are in opposite directions to each other. This allows
When a read voltage is applied to the first electrode 2a during a data read operation, the first electrode 2a and the second electrode 2b
Since the potential difference between the first and second electrodes 2a and 2b of the ferroelectric capacitor 2 is reduced, the potential difference between the first and second electrodes 2a and 2b is prevented from being applied.

When the first embodiment is applied to a semiconductor memory device in which the ferroelectric capacitors 2 are arranged in an array, the read voltage is applied to one of the plurality of ferroelectric capacitors. When applied,
Since the situation in which the data stored in the other ferroelectric capacitor of the plurality of ferroelectric capacitors is destroyed can be avoided, even in a large-scale integrated non-destructive read type semiconductor memory device, It is possible to prevent the situation where the data stored in the dielectric capacitor cannot be read.

(Second Embodiment) A semiconductor memory device according to a second embodiment of the present invention will be described below with reference to FIG.

The semiconductor device according to the second embodiment is shown in FIG.
, The first electrode 2a of the ferroelectric capacitor 2 is
Is connected to a drive circuit 5 for applying a write voltage or a read voltage to the first electrode 2a, and between the drive circuit 5 and the second electrode 2b of the ferroelectric capacitor 2 is a strong circuit. The ferroelectric film 2 is applied to the dielectric capacitor 2 at a voltage other than the setting, for example, except when rewriting data.
A control circuit 7 is connected to prevent application of a voltage in a direction that destroys the data stored in c. By doing so, when a voltage outside the setting is applied to the ferroelectric capacitor 2, the voltage outside the setting is fed back to the drive circuit 5, so that the data stored in the ferroelectric film 2c is stored. The situation in which the car is destroyed is prevented.

(Third Embodiment) Hereinafter, a semiconductor memory device according to a third embodiment of the present invention will be described with reference to FIGS.
Will be described with reference to.

In the semiconductor device according to the third embodiment, the magnitude of the read voltage applied by the drive circuit 5 to the ferroelectric capacitor 2 is set within a predetermined range, and as a result,
The voltage change of the second electrode 2b to which the read voltage is not applied is controlled so as not to be delayed from the predetermined value with respect to the voltage change of the first electrode 2a to which the read voltage is applied. Specifically, the voltage change at the first electrode 2a is set to have a transition time that is equal to or longer than the time constant at the second electrode 2b.

The case where a read voltage that destroys the data in the ferroelectric capacitor 2 is applied except when the data is being rewritten will be described below.

By the way, as shown in FIG. 4, a first parasitic capacitance C ₁ of a circuit connected to the first electrode 2a is generated at the first electrode 2a of the ferroelectric capacitor 2, and
A second parasitic capacitance C ₂ of the circuit connected to the second electrode 2b is generated on the second electrode 2b of the ferroelectric capacitor 2.

The second parasitic capacitance C ₂ is the first parasitic capacitance C ₁
And a read voltage is applied to the first electrode 2a, the second electrode 2b receives a parasitic component due to the difference between the second parasitic capacitance C ₂ and the first parasitic capacitance C ₁ . Because of the influence, the voltage change of the second electrode 2b lags behind the voltage change of the first electrode 2a.

FIG. 5 shows the first electrode 2a and the second electrode 2
5 shows the state of voltage change in b, in FIG. 5, a shows the voltage of the first electrode 2a, b shows the voltage of the second electrode 2b when the data "1" is stored, c indicates the voltage of the second electrode 2b when the data "0" is stored.

As can be seen from the comparison of the changes in the voltages a, b, c, the voltage a of the first electrode 2a is steep, while the changes of the voltages b, c of the second electrode 2b are the second. Slow due to the presence of the parasitic capacitance C ₂ of the first electrode 2
The voltage a of a is considerably lower than the voltage b of the second electrode 2b and 1.

The voltage b of the second electrode 2b and the first electrode 2a
If the potential difference V ₁ with respect to the voltage a is positive, this positive potential difference acts in the direction of writing the data “0” in the ferroelectric capacitor 2, so that the data “1” is destroyed, that is, in the strong direction. It acts in a direction in which the amount of polarization of the dielectric film 2c decreases. Although the reduction of the polarization amount in one read operation is slight, the data amount is not rewritten in the non-destructive semiconductor memory device, so that the reduction of the polarization amount becomes large when the read operation is repeated. Finally, the data cannot be read.

Further, when the data "0" is stored, the read voltage a applied to the first electrode 2a.
Is set to 0 V, the potential difference V ₂ between the voltage c of the second electrode 2b and the voltage a of the first electrode 2a remains on the second electrode 2b.
This occurs because the polarization amount of the ferroelectric film 2c is slightly changed when the data "0" is written, and the data "0" is retained in the ferroelectric film 2c. Since the voltage in the direction of writing "0" acts, the problem of data destruction does not occur.

As can be seen from the above description, when the data "1" is stored, the second electrode 2b
When the potential difference V ₁ between the voltage b of the first electrode 2a and the voltage a of the first electrode 2a is positive, there is a problem that the voltage in the direction in which the data stored in the ferroelectric capacitor 2 is destroyed acts. .

Therefore, in the third embodiment, the data "1" is used.
Is stored, the potential difference V ₁ between the voltage b of the second electrode 2b and the voltage a of the first electrode 2a does not become positive, that is, the voltage of the first electrode 2a is d in FIG. The read voltage V _RD that changes as shown by is applied to the first electrode 2
It is characterized in that it is applied to a.

[0050]

According to the semiconductor memory device and the method of driving the same according to the present invention, when a read voltage is applied to one electrode of the ferroelectric capacitor, the ferroelectric film of the ferroelectric capacitor has the ferroelectric film. Since the voltage in the direction that destroys the data stored in the dielectric film is no longer applied, it is possible to prevent the data stored in the ferroelectric capacitor from becoming unreadable even if the read operation is repeated. it can.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of a control means in the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a schematic configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is an equivalent circuit for explaining a semiconductor memory device according to a third embodiment of the present invention.

FIG. 5 is a diagram illustrating a change in voltage of each electrode of a ferroelectric capacitor that constitutes a semiconductor memory device according to a third embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of a conventional semiconductor memory device.

FIG. 7 is an equivalent circuit diagram of a semiconductor memory device on which the present invention is based.

[Explanation of symbols]

1 readout transistor 2 Ferroelectric capacitor 2a First electrode 2b Second electrode 2c Ferroelectric film 5 drive circuit 6 control circuit 6a transistor 6b diode 7 control circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takehisa Kato             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd.

Claims (6)

[Claims] 1. A ferroelectric capacitor for storing data by deviation of polarization of a ferroelectric film, and a voltage applying means for applying a read voltage to one electrode of a pair of electrodes of the ferroelectric capacitor. A detection unit for reading the data by detecting a deviation of polarization of the ferroelectric film when a read voltage is applied to the one electrode, and the read voltage applied to the one electrode. A voltage removing means for removing the read voltage, and the read voltage has a magnitude such that when the read voltage is removed, the deviation of polarization of the ferroelectric film returns to the deviation before reading the data. In the semiconductor memory device set, when the read voltage is applied to the one electrode, the ferroelectric film has a direction of destroying data stored in the ferroelectric film. A semiconductor memory device comprising a control means for preventing a voltage from being applied. 2. The control means has means for reducing a potential difference generated between a pair of electrodes of the ferroelectric capacitor when the read voltage is applied to the one electrode. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. 3. The read voltage is applied to the ferroelectric film in a direction that destroys data stored in the ferroelectric film when the read voltage is applied to the one electrode. 2. The semiconductor memory device according to claim 1, wherein the size is set so as not to be set. 4. The read voltage has a transition time in which a change in the voltage of the one electrode when the read voltage is applied to the one electrode is equal to or longer than a time constant of the other electrode of the pair of electrodes. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a size such that 5. A plurality of the ferroelectric capacitors are provided in an array form, and the control means stores a ferroelectric film of one of the plurality of ferroelectric capacitors. When reading the stored data, a voltage in a direction that destroys the data stored in the ferroelectric film of the other ferroelectric capacitor of the plurality of ferroelectric capacitors. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is prevented from being applied. 6. A polarization deviation of the ferroelectric film by applying a read voltage to one of a pair of electrodes of a ferroelectric capacitor that stores data by polarization deviation of the ferroelectric film. And a voltage removal step of removing the read voltage applied to the one electrode, wherein the read voltage is set when the read voltage is removed. A driving method of a semiconductor memory device, wherein the deviation of polarization of the ferroelectric film is set to return to the deviation before reading the data, wherein the data reading step includes: A method of driving a semiconductor memory device, which comprises a step of preventing a voltage in a direction of destroying data stored in the ferroelectric film from being applied to the body film.