JP2003337693A - Fast processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a fast processor having high performance in processing which is not affected by the influence of latency. <P>SOLUTION: A sum-up device is constituted with a pipeline-type adder 202, a shift register 204 and a shit-step number control section 206. The output of the pipeline-type adder 202 is connected with the shift register 204, and the output of the shift register 204 is connected with an input of the pipeline-type adder 202. The number of the shift steps of the shift register 204 is controlled by the shift-step number control section 206. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed arithmetic unit. More specifically, the present invention relates to an arithmetic unit of a computer device and other electronic devices, and relates to a high-speed arithmetic unit that aims to increase the speed and efficiency of the arithmetic unit.

[0002]

2. Description of the Related Art Conventionally, in an arithmetic unit of a computer device and other electronic devices, a logic circuit constituting an arithmetic circuit of the arithmetic unit is finely divided by a register to form a pipeline so that a high operating clock can be obtained. A frequency, that is, a high calculation throughput is realized.

FIG. 3 is a block diagram showing an example of a conventional pipeline type arithmetic circuit. The multiplier 101 multiplies the data input from the input lines 102 and 103 and outputs the result to the output line 104. Adder 1
05 adds the data output from the output line 104 and the output line 107, and outputs the result to the output line 106. The register 108 is a register which receives data output from the output line 106 and outputs data to the output line 107.

The operation of the pipeline type arithmetic circuit shown in FIG. 3 will be described. Consider the case of calculating the inner product of two vectors A and B. It is assumed that the process from inputting the data output from the output line 104 and the output line 107 to the adder 105 to outputting the addition result to the output line 107 is completed in one clock. In that case, two vectors A and B
The above elements are input to the input line 102 and the input line 103 for each clock. Then, finally, the inner product result of the two vectors A and B is output to the output line 107.

Japanese Unexamined Patent Publication No. 9-325953 discloses a problem of "providing a processor capable of processing multiply-accumulate operations at high speed", "providing an instruction register for storing an instruction and a plurality of registers. According to the instruction stored in the instruction register, the register file in which data is read in parallel from two or more registers of the plurality of registers and the data read in parallel from the register in the register file are An arithmetic unit for performing a predetermined operation in accordance with the instruction stored in the instruction register and M (M is an integer of 2 or more) registers are provided, and the M number of units corresponding to the instruction stored in the instruction register are provided. A cumulative register file for reading data from one or more of the registers, data obtained as a result of calculation by the arithmetic unit, and a record of the cumulative register file. The data read out from the static,
An adder that adds according to the instruction stored in the instruction register, and the result data added by the adder is stored in the register of the cumulative register file according to the instruction stored in the instruction register. The technology of "processor characterized by being stored as" is disclosed.

Further, Japanese Unexamined Patent Publication No. 10-214261 discloses a problem that "in an accumulative parallel arithmetic processing unit, the aim is to improve the efficiency of the accumulating process, shorten the processing time, and increase the speed." , "The first continuous automatic address generator, the source data memory and the coefficient data memory, and the vector data of the source data memory and the coefficient data memory of the address output from the first continuous automatic address generator are stored. Stored in the first register, a pipeline arithmetic unit for calculating the vector data stored in the first register, a second register storing the calculation result of the pipeline arithmetic unit, and a second register stored in the second register. An accumulator for accumulating the arithmetic result, a third register for storing the accumulative result of the accumulator, a second continuous automatic address generator, A destination data memory for storing the accumulation result stored in the 3 register at the address output from the second continuous automatic address generator is configured in a pipeline, and the vector data is read, pipeline operation, accumulation is performed. Arithmetic processing and data transfer are performed in parallel for each tap to initialize the accumulator, first and second
A technique called "accumulation parallel arithmetic processing device characterized in that each address of the continuous automatic address generator is reset in parallel for every predetermined number of taps" is disclosed.

[0007]

The prior art has the following problems.

In the pipeline type arithmetic circuit shown in FIG. 3, the latency of the adder 105 greatly affects the product-sum processing performance. Latency
ncy) means the time from the start of requesting data until the data is returned. Therefore, the problem of latency influence is that it takes a long time to return the data and the processing speed is slow.

That is, since the adder 105 accumulates the added result in the register 108, the next addition cannot be performed until the addition result of the adder 105 is output to the output line 107. Therefore, the adder 105
When it takes m clocks (m> 1) from inputting the data output from the output lines 104 and 107 to outputting the addition result to the output line 107, the number of elements of the vectors A and B If n is n, it takes m * (n-1) clocks to calculate the inner product of the vectors A and B. That is, in the arithmetic processing such as the accumulation rate, the output of the arithmetic unit is fed back to the input, so that the problem of the latency of the arithmetic unit is exposed.

In the "processor and data processing device" of Japanese Unexamined Patent Publication No. 9-325953, "when an operation including a sum operation is individually performed a plurality of times, for example, for each operation performed individually, a register of a cumulative register file is registered. , And perform a partial operation of each of the above operations by the operation unit,
It is possible to use the calculation results by accumulating (cumulative addition) using assigned registers and adders. That is, the summation operation can be performed in parallel by not performing the summation operation collectively for each of the above-described computations but by accumulating in the order of the above-described computations and repeating it. Therefore, in this processor, it is possible to efficiently perform the calculation without the idle time of the calculation that has occurred in the conventional technique, and when the number of terms of the total calculation is small, the calculation should be performed in a shorter time than the conventional technique. However, there is still a problem of latency influence.

In Japanese Unexamined Patent Application Publication No. 10-214261, "accumulation parallel operation processing device and method", "conventional individual processing is incorporated into one pipeline processing to be parallel processing, so that accumulation of filter operations and the like can be performed. When performing arithmetic processing,
Although it has the advantageous effect of achieving a reduction in processing time, "there was a problem of latency impact as well.

The present invention has been made in view of the above problems in the prior art, and an object thereof is to provide an arithmetic circuit having a high processing performance without the problem of the influence of latency. .

[0013]

A high-speed arithmetic unit according to the first invention of the present application for solving the above-mentioned problems is to operate on an operation result belonging to the same set as one set of input data selected from a plurality of sets of input data. The present invention comprises: arithmetic means for performing arithmetic processing; storage means for classifying and retaining the arithmetic results of the arithmetic means for each set; and arithmetic result selection means for taking out and outputting the arithmetic results belonging to the designated set from the storage means. It is characterized by that.

Therefore, according to the high-speed arithmetic unit of the first invention of the present application, it is possible to realize an arithmetic circuit having high processing performance without the problem of latency influence.

A high-speed arithmetic unit according to the second invention of the present application for solving the above-mentioned problems is a high-speed arithmetic unit according to the first invention of the present application.
The arithmetic means is an arithmetic circuit for performing one or more logical operations among logical negation, logical product, logical sum, and exclusive logical sum.

Therefore, according to the above-described high-speed arithmetic unit of the second invention of the present application, one or more logical operations among logical negation, logical product, logical sum, and exclusive logical sum can be performed at high speed. It becomes possible to do it.

A high-speed arithmetic unit according to the third invention of the present application for solving the above-mentioned problems is a high-speed arithmetic unit according to the first invention of the present application.
The arithmetic means is an arithmetic circuit for performing four arithmetic operations on integers.

Therefore, according to the high-speed arithmetic unit of the third invention of the present application, the four arithmetic operations of integers can be performed at high speed.

A high-speed arithmetic unit according to a fourth invention of the present application for solving the above-mentioned problems is a high-speed arithmetic unit according to the first invention of the present application.
The arithmetic means is an arithmetic circuit for performing four arithmetic operations of floating point.

Therefore, according to the high-speed arithmetic unit of the fourth invention of the present application, it is possible to perform the four arithmetic operations of floating point at high speed.

A high-speed arithmetic unit according to the fifth invention of the present application for solving the above-mentioned problems is a high-speed arithmetic unit according to the first invention of the present application,
The arithmetic means is configured by combining a plurality of arithmetic circuits that perform logical operations and four arithmetic operations.

Therefore, according to the high speed operation device of the fifth invention of the present application, high speed operation is possible even if a plurality of logical operations and four arithmetic operations are combined.

A high-speed arithmetic unit according to a sixth invention of the present application for solving the above-mentioned problems is the high-speed arithmetic unit according to the first to fifth inventions of the present application, wherein the arithmetic means is pipelined. It is a feature.

Therefore, according to the high-speed arithmetic unit of the sixth invention of the present application, the instructions of the CPU or the like are divided into a plurality of procedures,
Since it is possible to process in a line work and the processing of the next instruction can be started before the processing of one instruction is completed, it is possible to realize an arithmetic circuit with high processing performance without the problem of latency influence.

The high-speed arithmetic unit according to the seventh invention of the present application for solving the above-mentioned problems is the high-speed arithmetic unit according to the first to sixth inventions of the present application, wherein the time required for the arithmetic unit to perform the arithmetic operation and the one set Of time required to input the input data, the time for which the calculation result is stored in the storage unit, and the calculation result selection unit selects the calculation result from the storage unit to reach the input of the calculation unit. It is characterized in that the number of clocks, which is the total of the time required for, and the number of sets are the same.

Therefore, according to the high-speed arithmetic unit of the seventh invention of the present application, it is possible to realize an arithmetic circuit having a high processing performance while keeping the operating rate of the arithmetic unit high and without the problem of latency.

The high-speed arithmetic unit according to the eighth invention of the present application for solving the above-mentioned problems is the high-speed arithmetic unit according to the first to sixth inventions of the present application, wherein the time required for the arithmetic operation by the arithmetic unit and the one set Of time required to input the input data, the time for which the calculation result is stored in the storage unit, and the calculation result selection unit selects the calculation result from the storage unit to reach the input of the calculation unit. It is characterized in that the number of sets is the same as a natural number times the number of clocks, which is the sum of the time required for.

Therefore, according to the high-speed arithmetic unit of the eighth invention of the present application, it is possible to keep the operating rate of the arithmetic unit high and to realize an arithmetic circuit with high processing performance without the problem of latency.

A high-speed arithmetic unit according to the ninth invention of the present application for solving the above-mentioned problems is the high-speed arithmetic unit according to the first, seventh and eighth inventions of the present application, wherein the storage means is a first-in first-out storage device. It is characterized by being used.

Therefore, according to the high-speed arithmetic unit of the ninth invention of the present application, the data such as the arithmetic result stored in the storage unit can be processed in the order in which they are stored. The time required for calculation, the time required for inputting the set of input data, the time for storing the calculation result in the storage means, and the calculation result selection means for selecting the calculation result from the storage means. The number of clocks, which is the sum of the time required to reach the input of the arithmetic means, and the number of sets are the same.

A high-speed arithmetic unit according to the tenth invention of the present application for solving the above-mentioned problems is the high-speed arithmetic unit according to the first, seventh and eighth inventions of the present application, wherein the storage means uses a shift register. It is characterized by being formed.

Therefore, according to the high-speed arithmetic unit of the tenth invention of the present application, it becomes possible to shift the stored information based on the given signal, and the time required for the arithmetic unit to perform the arithmetic operation, The time required for inputting the set of input data, the time for storing the calculation result in the storage means, the calculation result selecting means selecting the calculation result from the storage means, and inputting the calculation result It is possible to configure such that the number of clocks, which is the total of the time required to reach the above, and the number of sets are the same.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described.
The high-speed arithmetic unit of the present invention is of a pipeline type and is capable of simultaneously processing a plurality of sets of arithmetic operations.

The specific configuration is as follows. A high-speed arithmetic unit according to the present invention includes an arithmetic unit for performing arithmetic processing on an arithmetic result belonging to the same set as one set of input data selected from a plurality of sets of input data, and an arithmetic result of the arithmetic unit classified by set. And storage means for holding the calculation results, and calculation result selection means for extracting and outputting the calculation results belonging to the designated set from the storage means. This makes it possible to realize an arithmetic circuit with high processing performance without the problem of latency.

The arithmetic means is an arithmetic circuit for performing one or more logical operations among logical NOT, logical product, logical sum, and exclusive OR. Further, the arithmetic means is an arithmetic circuit that performs four arithmetic operations of integers and four arithmetic operations of floating point, and may be configured by combining a plurality of arithmetic circuits that perform logical operations and four arithmetic operations. As a result, at least one logical operation among logical negation, logical product, logical sum, and exclusive OR is performed at high speed, floating point arithmetic operations are performed at high speed, and integer arithmetic operations are performed. It is possible to perform the operation at high speed and to perform the high speed operation even if a plurality of logical operations and four arithmetic operations are combined.

The computing means is pipelined. This makes it possible to divide an instruction of the CPU or the like into a plurality of procedures and process them in an assembling manner, so that the processing of the next instruction can be started before the processing of one instruction is finished.
It is possible to realize an arithmetic circuit with high processing performance without the problem of latency effects.

The high-speed arithmetic unit includes a time required for the arithmetic unit to perform an arithmetic operation, a time required to input the set of input data, a time required to store the arithmetic result in the storage unit, and the arithmetic result. Since the number of clocks, which is the sum of the time required for the selection means to select the calculation result from the storage means and reach the input of the calculation means, is the same as the set number, the calculation is performed. It is possible to realize an arithmetic circuit with high processing performance, which keeps the operating rate of the device high and has no problem of the influence of latency.

The time required for the calculation by the calculation means,
The time required for inputting the set of input data, the time for storing the calculation result in the storage means, the calculation result selecting means selecting the calculation result from the storage means, and inputting the calculation result Can be configured so that the number of sets is the same as a natural number times the number of clocks, which is the sum of the time required to arrive at, and this also keeps the operating rate of the computing unit high and affects the latency. It is possible to realize an arithmetic circuit having high processing performance without the problem of.

The storage means is characterized by using a first-in first-out storage element. Therefore,
The data stored in the storage means, such as the calculation result, can be processed in the order in which they are stored, and the time required for the calculation by the calculation means and the time required for inputting the set of input data And the number of clocks that is the sum of the time required for the operation result to be stored in the storage means and the time required for the operation result selection means to select the operation result from the storage means and reach the input of the operation means. , And the number of sets is the same.

The storage means is composed of a shift register. This makes it possible to shift the stored information based on a given signal, the time required for the arithmetic means to perform the arithmetic operation, the time required to input the set of input data, and the The number of clocks, which is the sum of the time required to store the calculation result in the storage means and the time required for the calculation result selection means to select the calculation result from the storage means and reach the input of the calculation means, and the set It is possible to configure so that the numbers are the same.

By configuring as described above, the high-speed arithmetic unit according to the present invention performs arithmetic processing on a plurality of sets of input data. Even if a plurality of clocks are required for the operation, the next set of input data can be input to the arithmetic unit before the operation for one set of input data is completed. It is possible to maintain high operation rate and obtain high processing performance.

[0042]

1 is a block diagram of an embodiment of a high-speed arithmetic unit according to the present invention. The case where an accumulator is configured is shown. The accumulator includes a pipeline type adder 202, a shift register 204, and a shift stage number control unit 206. The output of the pipeline type adder 202 is sent to the shift register 204 and the output of the sist register 204 is sent to the pipeline. It is connected to one input of the type adder 202. Then, the shift register 20
The shift stage number control unit 206 can control the number of shift stages of four.

The operation means for performing operation processing on the operation result belonging to the same set as one set of input data selected from the above-mentioned plurality of sets of input data is the pipeline type adder 202 here, and the operation means The storage means for classifying and holding the operation results of each of the sets is the shift register 204 here, and the operation result selecting means for extracting and outputting the operation results belonging to the designated set from the storage means is the number of shift stages here. The control unit 206.

The pipeline type adder 202 is connected with the input line 201 to which the data to be accumulated is input and the output line 205 to which the accumulated intermediate result is fed back, as an input, and the addition to the output side. The output line 203 for outputting the result is connected.

The shift register 204 has an output line 203.
And the control line 20 output from the shift stage number control unit 206.
7 is connected as an input, and the output line 205 is connected to the output side.

The shift stage number control unit 206 uses the stage number input line 2
08 is connected as an input, and the control line 207 is connected to the output side.

Next, the operation of the circuit of FIG. 1 will be described with reference to FIG. The data to be accumulated is input from the input line 201. Here, it is assumed that the number of sets of data to be accumulated is k sets. This corresponds to, for example, the process of obtaining the sum of k vectors and obtaining k scalar values as a result. In this case, the number of stages of the shift register 204 is controlled so that the time until data is input from the input line 201 and the calculation result is output to the output line 205 is k clocks.

For example, when the latency of the pipeline type adder 202 is m clocks, the output line 203 and the output line 2
If the delay of 05 is sufficiently shorter than the period of 1 clock,
The number of stages of the shift register 204 is set to (km) stages. However, when the number of sets k is smaller than m, it means that the pipeline type arithmetic unit 202 itself cannot essentially provide performance, and is basically not a processing target. still,
In this configuration, it is also possible to avoid this problem by making k> m by performing calculation at once together with another data set.

According to the number k of data sets and the latency m of the pipeline type arithmetic unit 202, the shift register 204
It is the role of the shift stage number control unit 206 to set the stage number to (k−m). The value input from the stage number input line 208 and the latency m of the pipeline type adder 202
According to the control line 207, the shift register 204
Controls to set the number of shift stages.

The shift stage number control unit 206 controls the shift register 20 during the first k clocks of the accumulation rate process.
It also has a function of outputting a control signal to the control line 207 so that the output of 4 is fixed to zero. Further, since it is not necessary to put the result of the final addition of the accumulation rate process in the shift register 204, the shift stage number control unit 206 outputs a control signal to the control line 207 and outputs the output from the output line 203 to the output line 205. It is also possible to control the shift register 204 to bypass it directly.

A timing diagram showing the operation of the circuit of FIG. 1 is shown in FIG. FIG. 2 exemplifies a calculation for obtaining the sum total for each row of the matrix 301. The matrix 301 is a matrix with 4 rows and 4 columns. Therefore, there are four sets of processing for obtaining the four sums (that is, k = 4). If the latency m of the pipeline type arithmetic unit 202 is 2, the shift register 2
The number of shifts of 04 is km = 2. A timing diagram 302 shows the timing of the input line 201, the output line 203, and the output line 205 in that case.

Since each row of the matrix 301 is multiplexed and processed, data is input to the input line 201 in the order of the first column data of each row at the first 4 clocks and the second column data of each row at the next 4 clocks. To do. Since the number of rows in this case, that is, the number of shift stages is controlled in accordance with the number of sets k, each time data is input to the input line 201, the intermediate result accumulated up to that point is output line 205.
Come out to.

In this way, the pipeline type arithmetic unit 20
It becomes possible for 2 to continue the calculation without playing. Thereby, the accumulation rate process of the k sets of vectors is completed after (k * n + k-1) clocks, where n is the vector length. If the present invention is not used, it is necessary to wait (m + 1) clocks for each addition, and (m + 1) clocks in total.
+1) * n * k clocks are required.

In the embodiment of the present invention, k sets of accumulation rate processes are executed in parallel. Therefore, the latency of the arithmetic processing of the pipeline type adder 202 requires a plurality of clocks, data is input from the input line 201, and the calculation result is output to the output line 205 by k.
Even if a clock is required, another set of additions can be multiplexed and executed during that time, so that it is possible to keep the operating rate of the pipelined adder 202 high.

That is, like matrix-matrix multiplication,
When a plurality of sets of product-sum operations are required, application as an accumulator that constitutes the product-sum enables pipeline processing of a plurality of sets of product-sum efficiently.

[0056]

The high-speed arithmetic unit of the present invention comprises arithmetic means for performing arithmetic processing on arithmetic results belonging to the same set as one set of input data selected from a plurality of sets of input data, and the arithmetic operation of the arithmetic means. The pipeline arithmetic unit uses a plurality of clocks for calculation by providing the storage unit for classifying and holding the results by set and the calculation result selecting unit for fetching and outputting the calculation result belonging to the designated set from the storage unit. Even when data is fed back, the operation rate of the arithmetic unit can be kept high and high processing performance can be obtained, so that it is possible to realize an arithmetic circuit with high processing performance without the problem of latency.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment (accumulator) of a high-speed arithmetic unit according to the present invention.

2 is a timing diagram of the accumulator of FIG.

FIG. 3 is a block diagram of a conventional pipeline type arithmetic circuit.

[Explanation of symbols]

101 multiplier 102 input line 103 input line 104 output line 105 adder 106 output line 107 output line 108 registers 201 input line 202 Pipeline type adder 203 output line 204 shift register 205 output line 206 Shift stage number control unit 207 control line 208 steps number input line 301 matrix 302 Timing diagram

Claims (10)

[Claims] 1. An arithmetic means for performing arithmetic processing on an arithmetic result belonging to the same set as one set of input data selected from a plurality of sets of input data, and an arithmetic result of the arithmetic means is classified and retained for each set. A high-speed arithmetic unit comprising: a storage unit for storing the calculation result and a calculation result selection unit for outputting the calculation result belonging to the designated set from the storage unit. 2. The arithmetic means is an arithmetic circuit for performing one or more logical operations among logical NOT, logical product, logical sum, and exclusive OR. The high-speed arithmetic unit described in 1. 3. The high-speed arithmetic unit according to claim 1, wherein the arithmetic means is an arithmetic circuit for performing four arithmetic operations of integers. 4. The high-speed arithmetic unit according to claim 1, wherein said arithmetic means is an arithmetic circuit for performing four arithmetic operations of floating point. 5. The high-speed arithmetic unit according to claim 1, wherein the arithmetic means is configured by combining a plurality of arithmetic circuits for performing logical operations and four arithmetic operations. 6. A high-speed arithmetic unit according to claim 1, wherein said arithmetic unit is pipelined. 7. A time required for the calculation means to perform a calculation, and a time required for inputting the set of input data,
The number of clocks that is the sum of the time taken for the operation result to be stored in the storage means and the time required for the operation result selection means to select the operation result from the storage means and reach the input of the operation means; 7. The high-speed arithmetic unit according to claim 1, wherein the number of sets is the same as the number of sets. 8. A time required for the calculation means to perform a calculation and a time required for inputting the set of input data,
A natural number of clocks, which is the sum of the time required for the calculation result to be stored in the storage means and the time required for the calculation result selection means to select the calculation result from the storage means and reach the input of the calculation means. 7. The number of sets is the same as the number of sets.
The described high-speed computing unit. 9. The high-speed arithmetic unit according to claim 1, wherein said memory means comprises a first-in first-out memory device. 10. The high-speed arithmetic unit according to claim 1, wherein said storage means comprises a shift register.