JP2003332589A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

Info

Publication number
JP2003332589A
JP2003332589A JP2002134990A JP2002134990A JP2003332589A JP 2003332589 A JP2003332589 A JP 2003332589A JP 2002134990 A JP2002134990 A JP 2002134990A JP 2002134990 A JP2002134990 A JP 2002134990A JP 2003332589 A JP2003332589 A JP 2003332589A
Authority
JP
Japan
Prior art keywords
opening
light receiving
recess
semiconductor
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002134990A
Other languages
Japanese (ja)
Inventor
Kazuya Ota
和也 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2002134990A priority Critical patent/JP2003332589A/en
Publication of JP2003332589A publication Critical patent/JP2003332589A/en
Withdrawn legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Light Receiving Elements (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device in which a solid state image sensor can be contained in the same semiconductor package as that of an analog front end element and a timing generator element. <P>SOLUTION: In the recess 21 of a basic body 2, an AFE element 51 and a TG element 61 are fixed while connecting its pad electrodes 52 and 62 with wiring 3A formed inside the recess 21. The solid state image sensor 71 is also fixed on the upper surface of a heat spreader 11 passing the recess 21 while directing the light receiving face upward (to face a transparent seal glass 12). An electrode of the solid state image sensor 71 is connected with the wiring in the recess 21 of the basic body 2 through a thin gold wire. The recess 21 of the basic body 2 is internally sealed with transparent seal glass 11 and the interior is evacuated. The invention is applicable to a semiconductor package. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置および
製造方法に関し、特に、受光素子と、受光素子からの電
気信号を処理する半導体素子またはその信号処理のタイ
ミングを調整する半導体素子を1つのパッケージに収納
配置することができるようにした半導体装置および製造
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method, and more particularly, to a light-receiving element and a semiconductor element for processing an electric signal from the light-receiving element or a semiconductor element for adjusting the timing of signal processing. The present invention relates to a semiconductor device and a manufacturing method capable of being housed and arranged in a package.

【0002】[0002]

【従来の技術】ディジタルスチルカメラやディジタルビ
デオカメラには、レンズを介して入力された光信号を光
電変換により電気信号に変換する個体撮像素子Mc(例
えば、CMOS(Complementary Metal Oxide Semiconducto
r)センサ、CCD(Charged Coupled Device))、その個
体撮像素子Mcからの電気信号に対してA/D変換など
の信号処理を行うアナログフロントエンドとしての半導
体素子(以下、AFE素子と称する)Ma、および個体
撮像素子McとAFE素子Maとの間で、効率よく信号伝
達が行われるようにタイミングを調整するタイミングジ
ェネレータとしての半導体素子(以下、TG素子と称す
る)Mtが実装されている。
2. Description of the Related Art In a digital still camera or a digital video camera, a solid-state image pickup device Mc (for example, CMOS (Complementary Metal Oxide Semiconducto) that converts an optical signal input through a lens into an electric signal by photoelectric conversion is used.
r) Sensor, CCD (Charged Coupled Device), semiconductor element (hereinafter referred to as AFE element) as an analog front end that performs signal processing such as A / D conversion on electric signals from the individual image pickup element Mc Ma , And a semiconductor element (hereinafter referred to as a TG element) Mt as a timing generator that adjusts the timing so that signal transmission is efficiently performed between the solid-state image sensor Mc and the AFE element Ma.

【0003】[0003]

【発明が解決しようとする課題】ところで、個体撮像素
子Mcは、素子の温度が上昇すると、ノイズが発生する
特性があるので、通常、個体撮像素子Mcを、多くの熱
を発生するAFE素子MaやTG素子Mtと一緒に1つの
パッケージに組み込むことができず、例えば、図1に示
すように、それぞれ異なる半導体パッケージPc,Pa,
Pcに組み込まれて実装されている。なお、AFE素子
MaおよびTG素子Mtを1つの半導体パッケージにまと
めて組み込むこともできるが、結局、個体撮像素子Mc
は、別の半導体パッケージに組み込まれる。
By the way, since the solid-state image pickup device Mc has a characteristic that noise is generated when the temperature of the device rises, the solid-state image pickup device Mc is usually set to the AFE device Ma which generates a lot of heat. And the TG element Mt cannot be incorporated into one package. For example, as shown in FIG. 1, different semiconductor packages Pc, Pa,
It is built in and implemented in Pc. The AFE element Ma and the TG element Mt can be integrated into one semiconductor package, but in the end, the solid-state image pickup element Mc
Is incorporated into another semiconductor package.

【0004】冷却のためにペルチェ素子を利用して、個
体撮像素子Mc、AFE素子Ma、およびTG素子Mtを
1つのパッケージに組み込むことも試みられているが、
この場合、ペルチェ素子の特性から消費電力が高くな
り、また構成部品等が増えてしまうことから、特に、携
帯型のビデオカメラに利用することができなかった。
It has been attempted to use a Peltier device for cooling to incorporate the solid-state image pickup device Mc, the AFE device Ma, and the TG device Mt into one package.
In this case, the characteristics of the Peltier device increase power consumption and increase the number of components and the like, so that it cannot be used particularly for a portable video camera.

【0005】このように、従来においては、簡単な構成
で、個体撮像素子Mc、AFE素子Ma、およびTG素子
Mtを1つの半導体パッケージに組み込んで利用するこ
とができない課題があった。
As described above, conventionally, there is a problem that the solid-state image pickup device Mc, the AFE device Ma, and the TG device Mt cannot be incorporated and used in one semiconductor package with a simple structure.

【0006】本発明はこのような状況に鑑みてなされた
ものであり、簡単な構成で、個体撮像素子Mcと、AF
E素子MaおよびTG素子Mtを1つのパッケージに組み
込んで利用することができるようにするものである。
The present invention has been made in view of such a situation, and has a simple structure and a solid-state image pickup device Mc and an AF.
The E element Ma and the TG element Mt can be incorporated into one package for use.

【0007】[0007]

【課題を解決するための手段】本発明の半導体装置は、
放熱板が貫通するための第1の開口部および第2の開口
部、透明材で封止される第3の開口部、凹部を有するよ
うに形成された基体と、放熱板と、放熱板と第1の開口
部の隙間、および放熱板と第2の開口部の隙間を封止す
る樹脂と、第3の開口部を指向する放熱板の一方の面
に、受光面が第3の開口部を指向するように配置された
受光素子と、凹部の内側の面と、放熱板の他方の面で囲
まれた空間に配置された、受光素子からの、受光面に入
力された光信号を光電変換して得られた電気信号に対す
る信号処理を行う第1の半導体素子、または信号処理の
タイミングを調整する第2の半導体素子の少なくとも1
つと、基体の外側に形成された外部接続端子と、受光素
子、第1の半導体素子、第2の半導体素子、または外部
接続端子を電気的に接続する、凹部の内側に形成された
配線部と、透明材とを備えることを特徴とする。
The semiconductor device of the present invention comprises:
A first opening and a second opening through which the heat sink penetrates, a third opening sealed with a transparent material, a base formed to have a recess, a heat sink, and a heat sink The resin that seals the gap between the first opening and the gap between the heat dissipation plate and the second opening, and one surface of the heat dissipation plate that faces the third opening, the light receiving surface is the third opening. The optical signal input to the light-receiving surface from the light-receiving element, which is arranged in the space surrounded by the light-receiving element arranged so as to direct the light, the inner surface of the recess, and the other surface of the heat sink, is photoelectrically converted. At least one of a first semiconductor element that performs signal processing on an electric signal obtained by conversion or a second semiconductor element that adjusts the timing of signal processing.
And an external connection terminal formed on the outside of the base body and a wiring portion formed inside the recess for electrically connecting the light receiving element, the first semiconductor element, the second semiconductor element, or the external connection terminal. , And a transparent material.

【0008】半導体装置が、光信号を受光素子の受光面
に入射するレンズが格納された筐体に取り付けられる場
合において、放熱板に、筐体に設けられた位置決め部と
勘合する位置決め部を設けることができる。
When the semiconductor device is attached to the housing in which the lens that receives the optical signal on the light receiving surface of the light receiving element is stored, the heat dissipation plate is provided with the positioning portion that fits with the positioning portion provided in the housing. be able to.

【0009】本発明の半導体装置の製造方法は、放熱板
が貫通するための第1の開口部および第2の開口部、透
明材で封止される第3の開口部、並びに凹部を有するよ
うに基体を形成する行程と、受光素子からの電気信号に
対する信号処理を行う第1の半導体素子、および信号処
理のタイミングを調整する第2の半導体素子の少なくと
も一方を、凹部の内側に配置する行程と、第1の半導体
素子または第2の半導体素子を、受光素子または凹部の
外側に形成された外部接続端子と電気的に接続するため
に、凹部の内側に形成された配線部に接続する行程と、
貫通した放熱板と第1の開口部の隙間および放熱板と第
2の開口部の隙間を樹脂で封止することで、放熱板を固
定する行程と、放熱板の、第3の開口部を指向する面
に、受光素子を、受光面が第3の開口部を指向するよう
に配置する行程と、配線部と、受光素子を電気的に接続
する行程と、第3の開口部を、凹部の内部が真空になる
ように、透明材で封止する行程とを行うことを特徴とす
る。
The method for manufacturing a semiconductor device of the present invention has a first opening and a second opening through which a heat sink penetrates, a third opening sealed with a transparent material, and a recess. A step of forming a substrate on the substrate, a step of arranging at least one of a first semiconductor element for performing signal processing on an electric signal from a light receiving element and a second semiconductor element for adjusting timing of signal processing inside a concave portion. And a step of connecting the first semiconductor element or the second semiconductor element to a wiring portion formed inside the recess for electrically connecting the first semiconductor element or the second semiconductor element to an external connection terminal formed outside the light receiving element or the recess. When,
By sealing the gap between the radiating plate and the first opening that penetrates and the gap between the radiating plate and the second opening with resin, the process of fixing the radiating plate and the third opening of the radiating plate are performed. On the surface to be directed, a step of arranging the light receiving element so that the light receiving surface is directed to the third opening, a step of electrically connecting the wiring portion and the light receiving element, and a third opening are recessed. The step of sealing with a transparent material is performed so that the inside of the container becomes a vacuum.

【0010】本発明の半導体装置の製造方法において
は、放熱板が貫通するための第1の開口部および第2の
開口部、透明材で封止される第3の開口部、並びに凹部
を有するように基体が形成され、受光素子からの電気信
号に対する信号処理を行う第1の半導体素子、および信
号処理のタイミングを調整する第2の半導体素子の少な
くとも一方が、凹部の内側に配置され、第1の半導体素
子または第2の半導体素子が、受光素子または凹部の外
側に形成された外部接続端子と電気的に接続するため
に、凹部の内側に形成された配線部に接続され、貫通し
た放熱板と第1の開口部の隙間および放熱板と第2の開
口部の隙間を樹脂で封止することで、放熱板が固定さ
れ、放熱板の、第3の開口部を指向する面に、受光素子
が、受光面が第3の開口部を指向するように配置され、
配線部と、受光素子が電気的に接続され、第3の開口部
が、凹部の内部が真空になるように、透明材で封止され
る。
In the method for manufacturing a semiconductor device of the present invention, the semiconductor device has a first opening and a second opening through which the heat sink penetrates, a third opening sealed with a transparent material, and a recess. At least one of the first semiconductor element that performs signal processing on the electric signal from the light receiving element and the second semiconductor element that adjusts the timing of signal processing is disposed inside the recessed portion. The first semiconductor element or the second semiconductor element is connected to the wiring portion formed inside the concave portion to electrically connect to the light receiving element or the external connection terminal formed outside the concave portion, and the radiated heat is penetrated. By sealing the gap between the plate and the first opening and the gap between the heat dissipation plate and the second opening with a resin, the heat dissipation plate is fixed, and the surface of the heat dissipation plate facing the third opening is fixed. The light receiving element has a light receiving surface with a third opening It is arranged to direct,
The wiring portion and the light receiving element are electrically connected, and the third opening is sealed with a transparent material so that the inside of the recess is evacuated.

【0011】[0011]

【発明の実施の形態】図2は、本発明を適用した半導体
パッケージ1の斜め上方からの外観斜視図である。図3
は、真上から見た場合の半導体パッケージ1の外観を表
している。なお、半導体パッケージ1の上面には、透明
シールガラス12が取り付けられているので、図3に
は、その透明シールガラス12を介して見ることができ
る半導体パッケージ1の内部も表されている。
FIG. 2 is a perspective view of a semiconductor package 1 to which the present invention is applied, as seen from obliquely above. Figure 3
Represents the appearance of the semiconductor package 1 when viewed from directly above. Since the transparent seal glass 12 is attached to the upper surface of the semiconductor package 1, FIG. 3 also shows the inside of the semiconductor package 1 that can be seen through the transparent seal glass 12.

【0012】図4は、図2の半導体パッケージ1のX1
−X2線の断面図である。図5は、図2の半導体パッケ
ージ1のY1−Y2線の断面図である。
FIG. 4 shows X1 of the semiconductor package 1 of FIG.
It is a cross-sectional view taken along line X2-. FIG. 5 is a sectional view taken along line Y1-Y2 of the semiconductor package 1 of FIG.

【0013】半導体パッケージ1には、光学レンズを介
して入力された光信号を光電変換により電気信号に変換
する個体撮像素子71、個体撮像素子71からの電気信
号に対してA/D変換などの信号処理を行うアナログフ
ロントエンドとしての半導体素子(AFE素子)51、
および個体撮像素子71とAFE素子51との間で効率
よく信号伝達が行われるように信号伝達のタイミングを
調整するタイミングジェネレータとしての半導体素子
(TG素子)61が、図3乃至図5に示すように収納配
置されている。
The semiconductor package 1 includes a solid-state image pickup device 71 for converting an optical signal input via an optical lens into an electric signal by photoelectric conversion, and an A / D conversion or the like for the electric signal from the solid-state image pickup device 71. A semiconductor element (AFE element) 51 as an analog front end that performs signal processing,
Also, a semiconductor element (TG element) 61 as a timing generator that adjusts the signal transmission timing so that the signal transmission is efficiently performed between the solid-state image pickup element 71 and the AFE element 51 is as shown in FIGS. It is stored and arranged in.

【0014】半導体パッケージ1は、基本的に、基体
2、および互いに電気的に接続された、リードフレーム
で形成された配線部3Aと外部接続端子3Bから構成さ
れている。なお、配線部3Aを、グリーンシートに印刷
された導電ペーストを焼成することで形成し、リードフ
レームからなる外部接続端子3Bと接合することもでき
る。
The semiconductor package 1 is basically composed of a substrate 2, and a wiring portion 3A formed of a lead frame and electrically connected to each other and an external connection terminal 3B. The wiring portion 3A may be formed by firing a conductive paste printed on a green sheet and joined to the external connection terminal 3B made of a lead frame.

【0015】基体2は、プラスチックモールドやセラミ
ックなどのベース材料により、凹部21を有するように
形成されている。この凹部21には、放熱板11が貫通
するための開口部2A,2Bが側面に、透明シールガラ
ス12によりシーリングされる開口部2Cが上面にそれ
ぞれ設けられている。
The base 2 is formed of a base material such as plastic mold or ceramic so as to have a recess 21. The recess 21 is provided with openings 2A and 2B through which the heat dissipation plate 11 penetrates on its side surface and an opening 2C sealed by the transparent seal glass 12 on its upper surface.

【0016】基体2を貫通する放熱板11は、熱伝導性
の高い銅、窒化アルミニウム、または黒鉛などの材料で
作られている。透明シールガラス12は、可視光領域で
の透過特性に優れ、固体撮像素子71に悪影響を与える
放射線の発生を抑えることができる、ホウケイ酸ガラス
などの材料で作られている。
The heat dissipation plate 11 penetrating the base 2 is made of a material such as copper, aluminum nitride, or graphite having high heat conductivity. The transparent seal glass 12 is made of a material such as borosilicate glass that has excellent transmission characteristics in the visible light region and can suppress the generation of radiation that adversely affects the solid-state image sensor 71.

【0017】基体2の側面の開口部2A,2Bと放熱板
11の隙間は、樹脂13により封止されている。
The space between the openings 2A and 2B on the side surface of the base 2 and the heat dissipation plate 11 is sealed with resin 13.

【0018】基体2の凹部21には、AFE素子51お
よびTG素子61が、そのパット電極52およびパット
電極62(正確には、それらの上に形成されたバンプ
(突起電極))と、凹部21の内側に形成された配線部
3Aとが接続されて取り付けられている。
In the recess 21 of the substrate 2, the AFE element 51 and the TG element 61, the pad electrode 52 and the pad electrode 62 (to be exact, bumps (projection electrodes) formed thereon), and the recess 21 are formed. The wiring portion 3A formed inside is connected and attached.

【0019】凹部21にはまた、そこを通る放熱板11
の上面に、個体撮像素子71が、その受光面が上方を向
くように(透明シールガラス12を指向するように)取
り付けられている。
The recess 21 also has a heat sink 11 passing therethrough.
The solid-state image sensor 71 is attached to the upper surface of the so that the light receiving surface thereof faces upward (directing toward the transparent seal glass 12).

【0020】個体撮像素子71の電極72は、凹部21
の内側に形成された配線部3Aに、金細線81で電気的
に接続される。
The electrode 72 of the solid-state image pickup device 71 has a concave portion 21.
It is electrically connected to the wiring portion 3A formed on the inside by a thin gold wire 81.

【0021】グリット状に、半導体パッケージ1の裏面
に配置された外部接続端子3Bは、凹部21に収納配置
された固定撮像素子71、AFE素子51、またはTG
素子61と、配線部3Aを介して電気的に接続されてい
る。
The external connection terminals 3B arranged on the back surface of the semiconductor package 1 in the shape of a grid are fixed image pickup device 71, AFE device 51, or TG housed in the recess 21.
It is electrically connected to the element 61 via the wiring portion 3A.

【0022】半導体パッケージ1は、例えば、図6に示
すように、外部接続端子3Bが基板101に設けられた
スルーホール102に貫通されて半田付けされ、基板1
01上に半田付けされた他の半導体素子(AFE素子5
1からの電気信号を処理する素子)と電気的に接続され
る。なお、外部基板に設けられたランド(図示せず)に
半田付けすることもできる。
In the semiconductor package 1, for example, as shown in FIG. 6, the external connection terminals 3B are pierced through the through holes 102 provided in the substrate 101 and soldered, and the substrate 1
Other semiconductor element (AFE element 5
1) which electrically processes the electric signal from 1). It is also possible to solder to a land (not shown) provided on the external board.

【0023】なお、外部接続端子3Bは、この例の場
合、半導体パッケージ1の裏面にグリット状に配置され
ているが、半導体パッケージ1の枠に沿って配置するこ
ともできる。
Although the external connection terminals 3B are arranged in a grid shape on the back surface of the semiconductor package 1 in this example, they may be arranged along the frame of the semiconductor package 1.

【0024】半導体パッケージ1は、図7に示すよう
に、光学レンズが内部に取り付けられた筒状のレンズユ
ニット111に、その開口部112と、透明シールガラ
ス12の面が対面するように取り付けられる。放熱板1
1の両端には、レンズユニット111の開口部112の
付近に設けられた位置決め部113A,113Bと勘合
する位置決め部31A,31Bが設けられている。半導
体パッケージ1が、放熱板11の位置決め部31とレン
ズユニット111の位置決め部113により決定された
位置に取り付けられることにより、レンズユニット11
1の内部に取り付けられた光学レンズからの光信号が、
透明シールガラス12を介して半導体パッケージ1の内
部に収納配置された固定撮像素子71の受光面に適切に
入射させることができる。
As shown in FIG. 7, the semiconductor package 1 is attached to a cylindrical lens unit 111 in which an optical lens is attached so that its opening 112 and the surface of the transparent seal glass 12 face each other. . Heat sink 1
Positioning portions 31A and 31B that fit with positioning portions 113A and 113B provided near the opening 112 of the lens unit 111 are provided at both ends of the lens unit 1. By mounting the semiconductor package 1 at the position determined by the positioning portion 31 of the heat sink 11 and the positioning portion 113 of the lens unit 111, the lens unit 11
The optical signal from the optical lens attached inside 1
The light can be appropriately incident on the light receiving surface of the fixed image pickup device 71 housed and arranged inside the semiconductor package 1 through the transparent seal glass 12.

【0025】このような構成の半導体パッケージ1を製
造する方法について、図8を参照して説明する。
A method of manufacturing the semiconductor package 1 having such a structure will be described with reference to FIG.

【0026】はじめに、図8Aに示すように、AFE素
子51およびTG素子61が、フリップチップ実装法に
より凹部21の内側に実装される。具体的には、AFE
素子51のパット電極52、およびTG素子61のパッ
ト電極62が、基体2の凹部21の底面に形成された配
線部3Aに電気的に接続される。この場合、AFE素子
51およびTG素子61は、その回路形成面が下方を向
くように取り付けられる。
First, as shown in FIG. 8A, the AFE element 51 and the TG element 61 are mounted inside the recess 21 by the flip chip mounting method. Specifically, AFE
The pad electrode 52 of the element 51 and the pad electrode 62 of the TG element 61 are electrically connected to the wiring portion 3A formed on the bottom surface of the recess 21 of the base 2. In this case, the AFE element 51 and the TG element 61 are attached so that their circuit forming surfaces face downward.

【0027】なお、AFE素子51およびTG素子61
のパット電極52およびパット電極62と配線部3Aを
金細線などで接続するワイヤーボンド法で電気的に接続
することもできる。
The AFE element 51 and the TG element 61
It is also possible to electrically connect the pad electrode 52 and the pad electrode 62 to the wiring portion 3A by a wire bonding method using a gold wire or the like.

【0028】次に、図8Bに示すように、基体2の側面
に設けられた開口部2A,2Bに、放熱板11が、基体
2を貫通するようにして所定の位置まで挿入される。
Next, as shown in FIG. 8B, the heat radiating plate 11 is inserted into the openings 2A and 2B provided on the side surface of the base 2 to a predetermined position so as to penetrate the base 2.

【0029】次に、図8Cに示すように、基体2の側面
の開口部2A,2Bと放熱板11の隙間が樹脂13で封
止される。その結果、放熱板11を、基体2に固定する
ことができ、その隙間からの埃等の侵入を防止すること
ができる。
Next, as shown in FIG. 8C, the gap between the openings 2A, 2B on the side surface of the base 2 and the heat dissipation plate 11 is sealed with resin 13. As a result, the heat dissipation plate 11 can be fixed to the base body 2 and dust and the like can be prevented from entering through the gap.

【0030】次に、図8Dに示すように、放熱板11の
上面に、固定撮像素子71を、その受光面が上方を向く
ように、熱伝導性の良い銀ペーストなどの樹脂で固定さ
れる。そして固定撮像素子71の電極72と配線部3A
が金細線81で電気的に接続される。
Next, as shown in FIG. 8D, the fixed image pickup device 71 is fixed to the upper surface of the heat dissipation plate 11 with a resin such as silver paste having good heat conductivity so that its light receiving surface faces upward. . The electrode 72 of the fixed image pickup device 71 and the wiring portion 3A
Are electrically connected with a gold wire 81.

【0031】次に、図8Eに示すように、凹部21の内
部が真空にされた後、透明シールガラス12が装着され
る。
Next, as shown in FIG. 8E, after the inside of the recess 21 is evacuated, the transparent seal glass 12 is mounted.

【0032】以上のように凹部21の内部は真空であ
り、凹部21の内部での空気対流が行われないので、A
FE素子51またはTG素子61が発生した熱の固定撮
像素子71への伝導を抑制することができる。また、凹
部21の内部に発生した熱は、放熱板11を介して、凹
部21の外部に放出される。これらのことから、固定撮
像素子71の温度の上昇を防止することができ、温度上
昇によるノイズ発生を抑制することができるができるの
で、固定撮像素子71を、AFE素子51およびTG素
子61と同じ半導体パッケージ1内に組み込んで利用す
ることができる。
As described above, since the inside of the concave portion 21 is in a vacuum and air convection is not performed inside the concave portion 21, A
It is possible to suppress conduction of heat generated by the FE element 51 or the TG element 61 to the fixed image pickup element 71. Further, the heat generated inside the recess 21 is radiated to the outside of the recess 21 via the heat dissipation plate 11. From these things, it is possible to prevent the temperature rise of the fixed image sensor 71 and suppress the noise generation due to the temperature rise. Therefore, the fixed image sensor 71 is the same as the AFE element 51 and the TG element 61. It can be used by incorporating it in the semiconductor package 1.

【0033】なお、以上においては、半導体パッケージ
1には、個体撮像素子71、AFE素子51、およびT
G素子61が組み込まれていたが、個体撮像素子71
と、AFE素子51またはTG素子61のいずれか一方
の素子を、半導体パッケージ1に組み込むようにするこ
ともできる。
In the above description, the semiconductor package 1 includes the solid-state image pickup element 71, the AFE element 51, and the T element.
Although the G element 61 was incorporated, the solid-state image pickup element 71
Then, either one of the AFE element 51 and the TG element 61 can be incorporated into the semiconductor package 1.

【0034】また、図9に示すように、AFE素子51
(またはTG素子61)を、半導体パッケージ1の外側
に搭載することもできる。
Further, as shown in FIG.
(Or the TG element 61) can be mounted outside the semiconductor package 1.

【0035】[0035]

【発明の効果】本発明によれば、受光素子を、受光素子
からの電気信号を処理する第1の半導体素子または信号
処理のタイミングを調整する第2の半導体素子を、同じ
パッケージに収納配置することができる。
According to the present invention, the light receiving element is accommodated in the same package as the first semiconductor element for processing the electric signal from the light receiving element or the second semiconductor element for adjusting the timing of signal processing. be able to.

【図面の簡単な説明】[Brief description of drawings]

【図1】個体撮像素子、AFE素子、TG素子の半導体
パッケージを示す図である。
FIG. 1 is a diagram showing a semiconductor package of a solid-state image sensor, an AFE element, and a TG element.

【図2】本発明を適用した半導体パッケージの外観の構
成例を示す図である。
FIG. 2 is a diagram showing a configuration example of the appearance of a semiconductor package to which the present invention has been applied.

【図3】図2の半導体パッケージを真上から見た図であ
る。
3 is a view of the semiconductor package of FIG. 2 as viewed from directly above.

【図4】図2の半導体パッケージの断面図である。4 is a cross-sectional view of the semiconductor package of FIG.

【図5】図2の半導体パッケージの他の断面図である。5 is another cross-sectional view of the semiconductor package of FIG.

【図6】図2の半導体パッケージの実装方法を説明した
図である。
FIG. 6 is a diagram illustrating a method of mounting the semiconductor package of FIG.

【図7】図2の半導体パッケージを、レンズユニットに
取り付け方法を説明する図である。
FIG. 7 is a diagram illustrating a method of attaching the semiconductor package of FIG. 2 to a lens unit.

【図8】図2の半導体パッケージの製造方法を説明する
図である。
FIG. 8 is a diagram illustrating a method of manufacturing the semiconductor package of FIG.

【図9】図2の半導体パッケージの他の断面図である。9 is another cross-sectional view of the semiconductor package of FIG.

【符号の説明】[Explanation of symbols]

1 半導体パッケージ, 2 基体,2A 開口部,
2B 開口部, 2C開口部, 3A 配線部, 3B
外部接続端子, 11 透明リールガラス, 12
放熱板, 13 樹脂, 21 凹部, 31, 位置
決め部, 51 AFE素子, 52 パット電極,
61 TG素子, 62 パット電極, 71 固定撮
像素子, 72 電極, 81 金細線, 101 基
板,102 スルーホール, 111 レンズユニッ
ト, 112 開口部, 113 位置決め部
1 semiconductor package, 2 base, 2A opening,
2B opening, 2C opening, 3A wiring, 3B
External connection terminal, 11 Transparent reel glass, 12
Heat sink, 13 resin, 21 concave part, 31, positioning part, 51 AFE element, 52 pad electrode,
61 TG device, 62 pad electrode, 71 fixed image pickup device, 72 electrode, 81 gold wire, 101 substrate, 102 through hole, 111 lens unit, 112 opening part, 113 positioning part

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 放熱板が貫通するための第1の開口部お
よび第2の開口部、透明材で封止される第3の開口部、
凹部を有するように形成された基体と、 前記放熱板と、 前記放熱板と前記第1の開口部の隙間、および前記放熱
板と前記第2の開口部の隙間を封止する樹脂と、 前記第3の開口部を指向する前記放熱板の一方の面に、
受光面が前記第3の開口部を指向するように配置された
受光素子と、 前記凹部の内側の面と、前記放熱板の他方の面で囲まれ
た空間に配置された、前記受光素子からの、前記受光面
に入力された光信号を光電変換して得られた電気信号に
対する信号処理を行う第1の半導体素子、または前記信
号処理のタイミングを調整する前記第2の半導体素子の
少なくとも1つと、 前記基体の外側に形成された外部接続端子と、 前記受光素子、前記第1の半導体素子、前記第2の半導
体素子、または前記外部接続端子を電気的に接続する、
前記凹部の内側に形成された配線部と、 前記透明材とを備えることを特徴とする半導体装置。
1. A first opening and a second opening through which a heat sink penetrates, a third opening sealed with a transparent material,
A base formed to have a recess, the heat dissipation plate, a resin sealing the gap between the heat dissipation plate and the first opening, and the gap between the heat dissipation plate and the second opening, On one surface of the heat dissipation plate that points to the third opening,
From the light receiving element disposed in a space surrounded by a light receiving element whose light receiving surface is directed to the third opening, an inner surface of the recess, and the other surface of the heat dissipation plate. At least one of the first semiconductor element that performs signal processing on the electric signal obtained by photoelectrically converting the optical signal input to the light receiving surface, or the second semiconductor element that adjusts the timing of the signal processing. And an external connection terminal formed outside the base body, and electrically connecting the light receiving element, the first semiconductor element, the second semiconductor element, or the external connection terminal,
A semiconductor device comprising: a wiring portion formed inside the concave portion; and the transparent material.
【請求項2】 前記半導体装置が、前記光信号を前記受
光素子の前記受光面に入射するレンズが格納された筐体
に取り付けられる場合において、 前記放熱板には、前記筐体に設けられた位置決め部と勘
合する位置決め部が設けられていることを特徴とする請
求項1に記載の半導体装置。
2. In the case where the semiconductor device is attached to a housing in which a lens for making the optical signal incident on the light receiving surface of the light receiving element is housed, the heat dissipation plate is provided in the housing. The semiconductor device according to claim 1, further comprising a positioning portion that fits with the positioning portion.
【請求項3】 放熱板が貫通するための第1の開口部お
よび第2の開口部、透明材で封止される第3の開口部、
並びに凹部を有するように基体を形成する行程と、 受光素子からの電気信号に対する信号処理を行う第1の
半導体素子、および前記信号処理のタイミングを調整す
る第2の半導体素子の少なくとも一方を、前記凹部の内
側に配置する行程と、 前記第1の半導体素子または前記第2の半導体素子を、
前記受光素子または前記凹部の外側に形成された外部接
続端子と電気的に接続するために、前記凹部の内側に形
成された配線部に接続する行程と、 貫通した前記放熱板と前記第1の開口部の隙間および前
記放熱板と前記第2の開口部の隙間を樹脂で封止するこ
とで、前記放熱板を固定する行程と、 前記放熱板の、前記第3の開口部を指向する面に、前記
受光素子を、受光面が前記第3の開口部を指向するよう
に配置する行程と、 前記配線部と、前記受光素子を電気的に接続する行程
と、 前記第3の開口部を、前記凹部の内部が真空になるよう
に、前記透明材で封止する行程とを行うことを特徴とす
る半導体装置の製造方法。
3. A first opening and a second opening through which the heat sink penetrates, a third opening sealed with a transparent material,
And a step of forming a base body having a recess, at least one of a first semiconductor element that performs signal processing on an electric signal from a light receiving element, and a second semiconductor element that adjusts the timing of the signal processing, A step of arranging inside the recess, and the first semiconductor element or the second semiconductor element,
A step of connecting to a wiring portion formed inside the concave portion for electrically connecting to the light receiving element or an external connection terminal formed outside the concave portion; The process of fixing the heat sink by sealing the gap between the openings and the gap between the heat sink and the second opening with resin, and the surface of the heat sink facing the third opening. The step of arranging the light receiving element so that the light receiving surface is directed to the third opening, the step of electrically connecting the wiring portion and the light receiving element, and the third opening. And a step of sealing with the transparent material so that the inside of the recess is vacuumed.
JP2002134990A 2002-05-10 2002-05-10 Semiconductor device and its manufacturing method Withdrawn JP2003332589A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002134990A JP2003332589A (en) 2002-05-10 2002-05-10 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002134990A JP2003332589A (en) 2002-05-10 2002-05-10 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2003332589A true JP2003332589A (en) 2003-11-21

Family

ID=29697431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002134990A Withdrawn JP2003332589A (en) 2002-05-10 2002-05-10 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2003332589A (en)

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