JP2003332261A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a Ru thin film with a smooth surface and good film thickness uniformity on a semiconductor substrate when an MTM capacitor of a DRAM cell is formed. <P>SOLUTION: For forming an Ru initial layer 26 when the Ru thin film 27 is formed on the semiconductor substrate 11, a solution application method with which a stable thin film is difficult to form on surface projecting and recessing parts by the single method is used and the initial layer is used as a 'core'. Thus, a CVD method with which the smooth thin film is difficult to form by the single method is used and the Ru thin film is formed. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a metal thin film on a semiconductor substrate, which is used for manufacturing a DRAM, for example.

[0002]

2. Description of the Related Art As semiconductor devices become finer, for example, DRAM
In order to secure the cell capacity, for example, a MIM capacitor having a laminated structure of Ru (ruthenium) / TaO (tantalum oxide) / Ru is required, and the capacitor structure itself is more complicated and has a high aspect ratio. It has become to.

Although it is desirable to use a CVD technique for forming a film of Ru which will be an electrode of the above-mentioned capacitor, until now, CVD has been used.
With the technology alone, it was difficult to form a Ru film having excellent film quality including morphology and good adhesion to the underlying layer film. The main reason is that it is difficult to uniformly form the initial layer that becomes the nucleus of CVD-Ru on the underlying interlayer film.

Here, a case where an initial layer serving as a nucleus of CVD-Ru is formed by using the CVD method and a CVD-Ru film is formed thereon will be described in detail.

As shown in FIG. 5A, a contact plug 42 is formed on an interlayer insulating film 41 on a semiconductor substrate, an interlayer insulating film 43 is formed on the contact plug 42, and a contact hole 44 is formed. To form the initial layer 45. At this time, generally, the initial layer 45 first starts film formation in an isolated island shape, but it is not possible to increase the density of the island-shaped film formation portion 45 to some extent by adjusting the film formation conditions of the initial layer. It is possible.

However, as shown in FIG. 5B, when it is desired to finally form a thin Ru film 46 of about 20 nm by using the CVD method, an island-shaped initial layer 45 having a sufficient density cannot be obtained. Very difficult. For this reason, the final state of the CVD-Ru46 film becomes a film with surface irregularities.

In view of the above circumstances, FIGS. 6 (a) and 6 (b)
As shown in Fig. 3, a thin initial film 65, which becomes the nucleus of CVD-Ru, is formed by using the sputtering method, and Ru is formed on the initial film 65 by using the CVD method.
Methods for depositing the film 66 have been developed. In the figure, 41 is an interlayer insulating film, 42 is a contact plug, 43 is an interlayer insulating film, and 44 is a contact hole.

However, the sputtering method is inferior in step coverage and it is difficult to form a desired initial layer on the side surface of the hole bottom, for example. For this reason, as the capacitor structure becomes more complicated and has a high aspect ratio, it becomes impossible to sufficiently nucleate the bottom of the hole having a high aspect ratio by the sputtering method, and the hole is formed even when the CVD-Ru film 66 is deposited later. Stable film formation does not progress at the bottom, and CVD-Ru film is uniform as a whole
66 cannot be obtained, and the problem that morphology is significantly deteriorated is becoming more serious.

Further, in view of the above circumstances, FIG.
As shown in (b), consider the case where the Ru film is formed only by the solution coating method without using the CVD method. In the figure, 41 is an interlayer insulating film, 42 is a contact plug, 43 is an interlayer insulating film, 44 is a contact hole, 75 is a solution after coating, and 76 is a Ru film after baking (after film formation is completed).

However, the solution coating method is suitable for forming a uniform film on a flat semiconductor substrate surface or for filling a groove, but a thin Ru film of about 20 nm is formed on the side surface of the groove.
It is almost impossible to deposit 76, and as shown in FIG. 7B, an unnecessarily thick film is formed as it approaches the bottom of the hole, for example.

[0011]

As described above, when the Ru film is formed on the conventional semiconductor substrate, the initial layer is thinly formed on the underlying interlayer film by the sputtering method. However, there was a problem that sufficient nucleation became impossible, and the morphology was significantly deteriorated when the Ru film was subsequently deposited by the CVD method.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a metal thin film having a smooth surface and good thickness uniformity on a semiconductor substrate. And

[0013]

A first method of manufacturing a semiconductor device according to the present invention comprises a step of applying a solution containing a metal element on a semiconductor substrate to form a first thin film, and the first thin film. And a step of depositing a second thin film containing the metal element thereon.

A second method of manufacturing a semiconductor device according to the present invention is
A step of forming a first insulating film on a semiconductor substrate and burying a contact plug in a part thereof, and forming a second insulating film on the upper surface of the first insulating film and the contact plug, and forming a hole Alternatively, a step of forming a groove, a step of applying a solution containing a metal element to an upper surface of the second insulating film and an inner surface of the hole or groove to form a first thin film,
And a step of depositing a second thin film containing the metal element on the thin film.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a plan view schematically showing a part of an array of DRAM cells having MIM capacitors having a stack structure as an example of the memory cell array of the DRAM according to the embodiment.

This memory cell array has a memory cell array 1 for charge transfer.
DRAM cells, each of which is composed of an NMOS transistor and a capacitor having a stack structure for charge storage, are arranged in a matrix on a semiconductor substrate.

In FIG. 1, in the active region in the semiconductor substrate,
A drain region, a source region, and a channel region of the transistor are formed, and a word line WL including a gate electrode G is formed in a direction crossing over the channel region.

DC is a drain contact portion on the drain region, SC is a source contact portion on the source region,
BC is a bit line contact portion for connecting the bit line BL to a wiring portion connected to the drain contact portion DC at a position displaced from above the drain region.

On the source contact portion SC above the source region, there is provided a node contact portion for connecting a storage node to be a lower electrode of the MIM capacitor having a stack structure.

2 to 4 are views schematically showing a sectional structure of the wafer along the line AA 'in FIG. 1 in the manufacturing process of the memory cell array of FIG.

First, as shown in FIG. 2A, an element isolation region (STI) 12 having a trench structure, a gate insulating film 13 of a MOS transistor, and a gate electrode (FIG. 1) are formed on a semiconductor substrate 11 by using a conventional technique. A part of the word line WL) 14, a gate electrode protection film 15, a drain region D and a source region S are formed.
Further, the interlayer insulating film 16, for example, a contact plug 17 using polycrystalline silicon doped with P or As and a relay wiring continuous with the contact plug 17 are formed. After this, the interlayer insulating film 1
9. Form a bit line 21 indicated by a dotted line (located behind the cross section shown in the drawing).

Next, as shown in FIG. 2B, an interlayer insulating film 22 is deposited, and a storage node contact plug 23 made of, for example, titanium nitride TiN is formed.

Next, as shown in FIG. 2C, an interlayer insulating film 24 is deposited, and a hole or a groove, in this example, an opening portion 25 for forming a storage node is formed.

Next, as shown in FIG. 3A, a solution containing a Ru element (ruthenium-hydrochloric acid solution or the like) is applied and dried on the entire surface (the upper surface of the interlayer insulating film 24 and the inner surface of the opening 25). To do. As a result, a small amount of ruthenium chloride RuCl ₂ is adsorbed on the surface of the semiconductor substrate. Then, the ruthenium chloride is microcrystallized by annealing (baking) in an oxygen atmosphere to obtain the Ru initial layer 26.

Next, as shown in FIG. 3B, for example, Ru
A CVD-Ru film 27 is deposited by performing CVD using (EtCp) ₂ as a raw material. Next, as shown in FIG. 3C, the CVD-Ru film on the interlayer insulating film 24 is removed by, for example, the CMP method, and the CVD-Ru film 27 to be a storage node is left. Thereafter, a dielectric constant higher than normal silicon nitride film high dielectric film (e.g., Ta ₂ 0 _{5) 2}
Deposit 8.

Next, steps similar to those shown in FIGS. 3A to 3C are performed. That is, a solution containing ruthenium element (ruthenium-hydrochloric acid solution or the like) is applied and dried. As a result, a small amount of ruthenium chloride RuCl
₂ becomes adsorbed. After that, annealing is performed in an oxygen atmosphere to microcrystallize ruthenium chloride RuCl ₂ to obtain a Ru initial layer.

After that, CVD using Ru (EtCp) ₂ as a raw material is performed to deposit a CVD-Ru film as shown in FIG. 4 (a).
By processing by the RIE method, the CVD-Ru film 29 to be the plate electrode (upper electrode) of the capacitor is left.

Next, as shown in FIG. 4B, a multilayer wiring structure 30 is formed by using the conventional technique. Note that FIG. 4 (b)
Inside, 31, 33 and 35 are interlayer insulating films, and 32, 34 and 36 are wirings.

As described above, in the first embodiment, the insulating film 22 is formed on the semiconductor substrate 11, the contact plug 23 is embedded in a part of the insulating film 22, and the insulating film 22 and the insulating film 24 are formed on the upper surfaces of the contact plug 23. And a hole (or a groove may be used) 25 is formed in a part of the insulating film.

After that, a relatively uniform continuous ultra-thin film (<5 nm) is applied to the upper surface of the insulating film 24 and the inner surface of the hole (or groove) 25 by applying a solution containing Ru element. The Ru initial layer 26 is formed. At this time, the hole (or groove) 25
Although the film thickness of the Ru initial layer 26 becomes thicker at the bottom of the Ru initial layer 26, the film thickness of the Ru initial layer 26 at the bottom of the hole (or groove) 25 is set to about 5 nm on average. For example, it is easy to suppress the thickness to about 7 nm, and then the CVD-Ru film 27 can be uniformly deposited.

After that, the Ru initial layer 26 is used as a "nucleus" for CV.
The CVD-Ru film 27 is formed by the D method. At this time, the Ru initial layer 26
In addition, when a thin CVD-Ru film 27 having a thickness of, for example, about 20 nm is formed, the variation in the film thickness of the Ru initial layer 26 can be suppressed to about 10% at the most as a whole.

After that, the CVD-Ru film 27 is processed into a capacitor lower electrode, and a capacitor insulating film (high dielectric film) 28 is further formed, followed by the same process as the above-described process for forming the capacitor lower electrode 27. Thus, the capacitor upper electrode 29 is formed.

That is, in the first embodiment, the Ru thin films 27 and 29 which are promising as the electrode material of the MIM capacitor are formed on the semiconductor substrate.
To form the Ru initial layer, a solution coating method that is difficult to form a stable thin film on the surface irregularities alone is used to form the Ru initial layer. Ru using a CVD method that makes it difficult to form a thin film
Thin films 27 and 29 are formed.

As a result, the Ru thin films 27 and 29 having a smooth surface as a whole, good film thickness uniformity, excellent morphology, and stable film quality can be obtained, so that the capacitor characteristics can be improved. it can.

A plating method may be applied instead of the CVD method in the step shown in FIG. Generally, when forming the initial layer for plating, it was often the case that the groove was filled by using the sputtering method, but by using the solution coating method as in the above example, the Ru thin films 27 and 29 of about 20 nm were formed. It becomes possible to do.

<Second Embodiment> Since a new material such as Ru, which is rarely handled in the conventional Si process, has a problem of cross-contamination in the manufacturing process of a semiconductor device, especially in the wafer back surface or the wafer edge portion. It is desirable to remove it.

Even in the conventional sputtering method, it was possible to perform edge cutting to some extent by installing an edge cut ring or the like, but in the sprinkling method, it is necessary to prevent Ru atoms from wrapping around the edge cut ring. Was very difficult.

The DRAM manufacturing method according to the second embodiment is as follows.
The CVD-Ru film is prevented from adhering to the wafer edge portion or the back surface of the wafer. The step of depositing the ruthenium initial film is different from that of the DRAM manufacturing method according to the first embodiment described above. Are the same, and the steps corresponding to those of the first embodiment are the same as those of the first embodiment in the drawings.

First, as shown in FIGS. 2A to 2C, an opening 25 for forming a storage node is formed as in the first embodiment.

Next, as shown in FIG. 3A, a Ru-containing film is thinly deposited (for example, about 5 nm) by the sol-gel method using a highly viscous raw material containing Ru. At this time,
By rinsing the vicinity of the wafer edge of the Ru-containing film formed into a gel by wet etching or the same technique as rinsing the resist in the normal PEP process, a range of about 3 mm from the wafer edge is obtained. The Ru initial film should not be deposited on the inner region. When the raw material adheres to the back surface of the wafer, the back surface of the wafer is also rinsed so that the Ru initial film is not deposited.

Then, as shown in FIG. 3B, Ru
(EtCp) ₂ is used as a raw material for CVD, and CVD-
The Ru film 27 is deposited. At this time, the CVD-Ru film 2 is formed on the back surface of the wafer and the area about 3 mm from the edge of the wafer where the Ru initial film does not exist.
7 does not deposit.

Thereafter, as shown in FIGS. 3C to 4B, as in the first embodiment, the capacitor insulating film (dielectric film) 28, the capacitor upper electrode 29, and the multilayer wiring structure.
Forming 30.

According to the second embodiment described above, it becomes possible to peel off the wafer edge portion of the Ru-containing film formed in a gel state, and it is possible to more completely prevent the CVD-Ru film 27 from wrapping around. To the wafer edge and backside of the wafer
It becomes possible to prevent adhesion of the CVD-Ru film 27.

Therefore, in addition to the effects of the first embodiment, it is possible to avoid the cross contamination problem of the manufacturing line and improve the yield of semiconductor devices.

In each of the above-described embodiments, the DRAM using the Ru film as the electrode has been described, but the gist of the present invention is as described above.
The present invention is not limited to the Ru film and DRAM, and can be easily applied to metals other than Ru, metal compounds, and devices other than DRAM (ferroelectric memory, etc.).

[0047]

As described above, according to the method of manufacturing a semiconductor device of the present invention, a metal thin film having a smooth surface and good film thickness uniformity can be formed on a semiconductor substrate.
Further, it becomes possible to avoid the cross contamination problem in the manufacturing line and improve the manufacturing yield of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a part of an array of DRAM cells having MIM capacitors having a stack structure as an example of a memory cell array of DRAM according to a first embodiment of the present invention.

2 is a cross-sectional view schematically showing a cross-sectional structure of a wafer during a manufacturing process of the memory cell array in FIG.

FIG. 3 is a sectional view schematically showing the sectional structure of the wafer in the step following the step of FIG.

FIG. 4 is a sectional view schematically showing the sectional structure of the wafer in the step following the step of FIG.

[FIG. 5] In manufacturing a conventional DRAM memory cell, CVD-
Sectional drawing which shows roughly the cross-sectional structure of the wafer when a CVD method is used for film formation of the initial layer of Ru film, and a CVD-Ru film is formed on it by CVD method.

FIG. 6 is a schematic diagram illustrating a CVD-method for manufacturing a conventional DRAM memory cell.
Sectional drawing which shows roughly the cross-section of the wafer when a sputtering method is used for formation of the initial layer of Ru film, and a CVD-Ru film is formed on it by a CVD method.

FIG. 7 is a cross-sectional view schematically showing a cross-sectional structure of a wafer when a Ru film is formed only by a solution coating method in manufacturing a DRAM memory cell.

[Explanation of symbols]

11 ... Semiconductor substrate, 12 ... Element isolation region (STI), 13 ... MOS transistor gate insulating film, 14 ... Gate electrode (part of word line), 15 ... Gate electrode protective film, 16 ... Interlayer insulating film, 17 ... Contact plug, 19 ... Interlayer insulation film, 21 ... Bit line, 22 ... Interlayer insulation film, 23 ... Storage node / contact plug, 24 ... Interlayer insulation film, 25 ... Open hole part, 26 ... Ru initial layer, 27 ... CVD- Ru film (storage node, lower electrode of capacitor), 28 ... High dielectric film.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Daisuke Matsunaga             4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa             No. 1 within Fujitsu Limited F-term (reference) 4M104 BB04 DD45 DD51 GG16                 5F083 AD24 AD49 FR01 GA27 JA06                       JA38 JA39 JA40 MA06 MA17                       PR40

Claims (10)

[Claims] 1. A step of applying a solution containing a metal element onto a semiconductor substrate to form a first thin film, and a step of depositing a second thin film containing the metal element on the first thin film. A method for manufacturing a semiconductor device, comprising: 2. A first insulating film is formed on a semiconductor substrate,
A step of embedding a contact plug in a part thereof, and a second step on the upper surface of the first insulating film and the contact plug.
And forming a hole or groove in the insulating film in a part thereof, and applying a solution containing a metal element to the upper surface of the second insulating film and the inner surface of the hole or groove. And a step of depositing a second thin film containing the metal element on the first thin film, the method of manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of depositing the second thin film is a step different from the step of applying the solution. 4. The step of depositing the second thin film comprises CVD
4. The method for manufacturing a semiconductor device according to claim 3, wherein the method is a method. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the step of depositing the second thin film is a plating method. 6. The step of forming the first thin film is performed so that the first thin film does not exist on the end portion and / or the back surface of the semiconductor substrate. Item 1. A method of manufacturing a semiconductor device according to item 1. 7. The step of forming the first thin film is characterized in that after the solution containing the metal element is applied onto the semiconductor substrate, the solution is removed from the end and / or the back surface of the semiconductor substrate. Item 6. A method of manufacturing a semiconductor device according to any one of items 1 to 5. 8. The first thin film and the second thin film have substantially the same chemical composition.
8. A method of manufacturing a semiconductor device according to any one of items 7 to 7. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the first thin film and the second thin film are metal films. 10. The first thin film and the second thin film are
The method for manufacturing a semiconductor device according to claim 9, wherein the method is a ruthenium film.