JP2003332132A - Laminated chip component and its manufacturing method - Google Patents

Laminated chip component and its manufacturing method

Info

Publication number
JP2003332132A
JP2003332132A JP2002141599A JP2002141599A JP2003332132A JP 2003332132 A JP2003332132 A JP 2003332132A JP 2002141599 A JP2002141599 A JP 2002141599A JP 2002141599 A JP2002141599 A JP 2002141599A JP 2003332132 A JP2003332132 A JP 2003332132A
Authority
JP
Japan
Prior art keywords
conductor
insulating film
paste
conductive paste
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002141599A
Other languages
Japanese (ja)
Inventor
Yasuo Suzuki
靖生 鈴木
Yoshinari Oba
佳成 大場
Tatsuhiko Nawa
達彦 名和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FDK Corp
Original Assignee
FDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by FDK Corp filed Critical FDK Corp
Priority to JP2002141599A priority Critical patent/JP2003332132A/en
Publication of JP2003332132A publication Critical patent/JP2003332132A/en
Withdrawn legal-status Critical Current

Links

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated chip component for forming flat a correspond ing layer with a properly viscous insulating paste by excellently stably forming through-holes connecting the upper and lower layer conductor patterns, and to provide its manufacturing method. <P>SOLUTION: A laminated inductor 10 laminates insulating film layers 1 and conductor patterns 2 in an appropriate order, forms a chip body 3 incorporating a coil spirally connecting the conductor pattern 2 to the corresponding inside, and forms outside electrodes 4 and 4 on the two opposite faces. The insulating film layer 1 making each layer is formed so as to uniformly cover the whole region of the corresponding face with an appropriately viscous insulating paste. An interlayer conductor part 5 which is a through hole is provided on an interlayer insulating film layer 1, and mutually connects the upper and lower layer conductor patterns 2. In forming the interlayer conductor part 5, a small-piece like conductor base 50 is provided on a lower layer side by the high viscous conductive paste, the insulating film layer 1 is formed on the corresponding circumference to make a hole part 6, and then the hole part 6 is filled with a low viscous conductive paste 51. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、積層チップ部品及
びその製造方法に関するもので、より具体的には、チッ
プ本体内に導体パターンが層間で繋がった電極体を内蔵
する積層チップ部品の層間導体部分の改良に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated chip component and a method of manufacturing the same, and more specifically, to an interlayer conductor of a laminated chip component having an electrode body in which conductor patterns are connected between layers in a chip body. Regarding the improvement of the part.

【0002】[0002]

【発明の背景】周知のように、積層チップ部品と呼ばれ
る電子部品は、面実装に使用するためリード端子を廃し
て小片形状に小型化しており、その一つにインダクタン
ス素子である積層インダクタがある。
BACKGROUND OF THE INVENTION As is well known, electronic components called multilayer chip components are miniaturized into small pieces by eliminating lead terminals for use in surface mounting, and one of them is a multilayer inductor which is an inductance element. .

【0003】積層インダクタは、セラミック等の絶縁膜
と導体パターンを適宜な順に積層することで当該内部に
導体パターンが螺旋状に繋がったコイルを内蔵する矩形
状のチップ本体を形成し、さらにそのチップ本体の対向
2面に、内蔵コイルの両端とそれぞれ接続する外部電極
を設けた構成になっている。
In a laminated inductor, an insulating film such as ceramic and a conductor pattern are laminated in an appropriate order to form a rectangular chip body containing a coil in which the conductor pattern is spirally connected, and the chip is further formed. External electrodes that are connected to both ends of the built-in coil are provided on two opposing surfaces of the main body.

【0004】チップ本体(積層体)を形成する方法に
は、絶縁シートに導体パターンを形成して積み重ねてい
くシート積層法や、絶縁ペーストと導電ペーストとを交
互に塗り重ねていく印刷積層法などがあり、何れにして
も積層体の内部に、螺旋状に繋がったコイルパターン及
びそれの引き出しパターンを形成することになる。
As a method for forming the chip body (laminate), a sheet laminating method in which a conductor pattern is formed on an insulating sheet and stacking it, a printing laminating method in which an insulating paste and a conductive paste are alternately coated and stacked, etc. In any case, a coil pattern and a lead-out pattern thereof that are spirally connected are formed inside the laminated body.

【0005】上下層の導体パターンの接続には、当該面
をマスク層で部分的に覆って次層の導体パターンを引き
回す構成があるが、そのマスク層によって段差ができ、
積層がいびつになる問題がある。このため、各絶縁膜は
該当面の全域を均一に覆う形態とし、層間の絶縁膜層
に、いわゆるスルーホールを形成して、これにより上下
両パターンを電気的に接続する構成を採ることがある。
For connecting the conductor patterns of the upper and lower layers, there is a structure in which the surface is partially covered with a mask layer and the conductor pattern of the next layer is laid out.
There is a problem of stacking being distorted. Therefore, each insulating film may uniformly cover the entire area of the corresponding surface, and so-called through holes may be formed in the insulating film layers between the layers to electrically connect the upper and lower patterns. .

【0006】このスルーホールの形成は、シート積層法
によれば、絶縁シートにレーザや金型等により孔加工す
るので工程が複雑になり生産コストが高くなる問題があ
る。一方、印刷積層法では全ての工程がスクリーン版を
用いた単純な刷り出し塗り重ね作業でよく、簡単な工程
で生産が行えてコスト面で有利性がある。
According to the sheet laminating method, the through holes are formed in the insulating sheet by using a laser, a mold or the like, so that the process is complicated and the production cost is increased. On the other hand, in the printing and laminating method, all the steps may be simple print-out and recoating work using a screen plate, and production can be performed in simple steps, which is advantageous in terms of cost.

【0007】例えば、図1は印刷積層法によるスルーホ
ールの形成を説明する断面図であり、スルーホールの形
成には、導体パターン2を形成した下層に対して(図1
(a))、ホール位置となる島部を有するパターンのス
クリーン版を用いて絶縁ペーストを塗り、所定の厚みに
絶縁膜層1を形成し、ホール位置にはくぼんだ穴部6を
得る(図1(b))。
For example, FIG. 1 is a cross-sectional view for explaining the formation of a through hole by the printing and laminating method. For the formation of the through hole, the conductor pattern 2 is formed on the lower layer (FIG. 1).
(A)), an insulating paste is applied using a screen plate having a pattern having islands to be hole positions to form an insulating film layer 1 with a predetermined thickness, and recessed holes 6 are obtained at hole positions (Fig. 1 (b)).

【0008】この後、穴部6に導電ペースト7を充填
し、当該層を貫くスルーホール8を形成し(図1
(c))、スルーホール8上には、ファイン印刷により
次層の導体パターン2を形成する(図1(d))。
Thereafter, the hole portion 6 is filled with a conductive paste 7 to form a through hole 8 penetrating the layer (see FIG. 1).
(C)), the conductor pattern 2 of the next layer is formed on the through hole 8 by fine printing (FIG. 1 (d)).

【0009】ところが、スルーホールの形成に印刷積層
法を適用することには、絶縁ペーストがにじむ問題があ
る。すなわち、穴部6の形成において、そのサイズが小
径化しているために周縁の絶縁ペーストが当該ホール位
置に流れ込んでにじむ不良が起きやすく、サイズが小さ
いのでにじみ込みの影響が大きく、図1(e)に示すよ
うに、穴部6が埋まってしまう不良を起こすことから小
さなスルーホールを安定に形成することが難しいという
問題がある。
However, there is a problem that the insulating paste is bleeding when the printing lamination method is applied to the formation of the through holes. That is, in the formation of the hole portion 6, since the size of the hole portion is reduced in diameter, the peripheral insulating paste easily flows into the hole position to cause a bleeding defect, and since the size is small, the influence of bleeding is large. As shown in (), there is a problem that it is difficult to stably form a small through hole because a defect in which the hole 6 is filled occurs.

【0010】これは、絶縁ペーストが持つ流動性のため
に、スクリーン版から刷り出した形状はそのままには保
持できなく、若干のダレを生じることなので、絶縁ペー
ストを粘度の高いものにして保形性をよくする対策が考
えられる。しかし、粘度の高い絶縁ペーストでは、今度
は充填が不完全になることがあり、該当面の凹凸を埋め
て平坦面を得ることが困難になる不良を起こすため、絶
縁ペーストにはある程度の流動性が必要であって粘度を
むやみに高くはできない。
This is because the shape printed on the screen plate cannot be maintained as it is because of the fluidity of the insulating paste, and some sagging occurs. Measures to improve sex can be considered. However, if the insulating paste has a high viscosity, the filling may be incomplete, and it will be difficult to fill the irregularities on the relevant surface to obtain a flat surface. Is necessary and the viscosity cannot be unnecessarily increased.

【0011】本発明は、上記した背景に鑑みてなされた
もので、その目的とするところは、上記した問題を解決
し、上下層の導体パターンを接続するスルーホールを不
良なく安定に形成でき、適正な粘度の絶縁ペーストによ
り該当層を平坦に形成できる積層チップ部品及びその製
造方法を提供することにある。
The present invention has been made in view of the above background, and an object thereof is to solve the above problems and to stably form through holes for connecting upper and lower conductor patterns without defects. It is an object of the present invention to provide a laminated chip component capable of forming a corresponding layer flat with an insulating paste having an appropriate viscosity and a method for manufacturing the same.

【0012】[0012]

【課題を解決するための手段】上記した目的を達成する
ために、本発明に係る積層チップ部品では、セラミック
等の絶縁膜と導体パターンを適宜な順に積層することで
当該内部に前記導体パターンが層間で繋がった電極体を
内蔵するチップ本体を備えて、当該チップ本体の外面に
は前記電極体と接続する外部電極を設ける積層チップ部
品において、前記絶縁膜層に当該層を貫いて上下層の導
体パターンを接続する層間導体部を有し、前記層間導体
部は、下層側に小片状の導体ベースを設け、当該周囲に
絶縁膜層を形成して穴部とした後に、前記穴部に導電ペ
ーストを充填するように構成した(第1の発明)。
In order to achieve the above object, in a laminated chip component according to the present invention, an insulating film such as a ceramic and a conductor pattern are laminated in an appropriate order so that the conductor pattern is In a laminated chip component that includes a chip body containing an electrode body connected between layers, and an external electrode connected to the electrode body is provided on the outer surface of the chip body, the insulating film layer is penetrated through the layer to form upper and lower layers. An interlayer conductor portion for connecting a conductor pattern is provided, the interlayer conductor portion is provided with a small piece-shaped conductor base on a lower layer side, and an insulating film layer is formed around the periphery to form a hole portion, and then the hole portion is formed in the hole portion. It is configured to be filled with a conductive paste (first invention).

【0013】また、前記層間導体部の形成には、粘度の
高い導電ペーストにより下層側に小片状の導体ベースを
設け、当該周囲に絶縁膜層を形成して穴部とした後に、
前記穴部に粘度の低い導電ペーストを充填するとよい。
Further, in forming the interlayer conductor, a small piece-shaped conductor base is provided on the lower layer side with a conductive paste having a high viscosity, and an insulating film layer is formed around the conductor base to form a hole,
The hole may be filled with a conductive paste having a low viscosity.

【0014】また、前記絶縁膜層に当該層を貫いて上下
層の導体パターンを接続する層間導体部を有し、前記層
間導体部は、絶縁ペーストにより環状の枠部を設け、当
該枠部内に導電ペーストを充填するように構成しても良
い(第2の発明)。また、前記層間導体部の形成には、
粘度の高い絶縁ペーストにより環状の枠部を設け、当該
枠部内に導電ペーストを充填するとよい。上記した各構
成において、前記電極体は、前記チップ本体内で導体パ
ターンが螺旋状に繋がったコイルとすることができる。
In addition, the insulating film layer has an interlayer conductor portion that penetrates the layer and connects the conductor patterns of the upper and lower layers, and the interlayer conductor portion is provided with an annular frame portion with an insulating paste, and the frame portion is provided in the frame portion. You may comprise so that it may be filled with a conductive paste (2nd invention). Further, in forming the interlayer conductor portion,
It is preferable to provide an annular frame portion with an insulating paste having a high viscosity and fill the frame portion with the conductive paste. In each of the above-mentioned configurations, the electrode body may be a coil in which conductor patterns are spirally connected in the chip body.

【0015】したがって第1の発明では、スルーホール
となる層間導体部の形成において、小片状の導体ベース
を下層側にまず設けるので、当該周囲に絶縁膜層を形成
する際には下層側との接続が予め確保してあって、導体
ベースの高さを適切に設定することで穴部が埋まる不良
を防げる。このとき、導体ベースには粘度の高い導電ぺ
ーストを使用すればよく、形状を保持できる。また、穴
部に充填する導電ペーストは、粘度の低いものを使用す
ればよく、充填が不良になることを防止できる。そし
て、絶縁膜層を形成する絶縁ペーストは粘度の低い適正
なものを使用することができる。
Therefore, in the first aspect of the invention, since the small-piece-shaped conductor base is first provided on the lower layer side in the formation of the through-hole inter-layer conductor portion, the insulating film layer is formed on the lower layer side when forming the insulating film layer on the periphery. Connection is secured in advance, and by appropriately setting the height of the conductor base, it is possible to prevent a defect in which the hole is filled. At this time, a conductive paste having a high viscosity may be used for the conductor base, and the shape can be maintained. Further, the conductive paste with which the hole is filled may have a low viscosity, so that the filling can be prevented from being defective. Then, as the insulating paste forming the insulating film layer, an appropriate one having a low viscosity can be used.

【0016】また、第2の発明では、層間導体部の形成
において、絶縁ペーストにより環状の枠部を設けること
で、当該枠部が障壁になるので、絶縁膜層を形成する絶
縁ペーストが枠部内に流れ込むことはない。このとき、
枠部を形成する絶縁ペーストには粘度の高いものを使用
すればよく、形状を保持できる。また、枠部内に充填す
る導電ペーストは、粘度の低いものを使用すればよく、
充填が不良になることを防止できる。そして、絶縁膜層
を形成する絶縁ペーストは粘度の低い適正なものを使用
することができる。
In the second aspect of the invention, in forming the inter-layer conductor portion, by providing the annular frame portion with the insulating paste, the frame portion serves as a barrier, so that the insulating paste forming the insulating film layer is inside the frame portion. Does not flow into. At this time,
An insulating paste having a high viscosity may be used as the insulating paste for forming the frame, and the shape can be maintained. In addition, the conductive paste to be filled in the frame portion may have a low viscosity,
It is possible to prevent defective filling. Then, as the insulating paste forming the insulating film layer, an appropriate one having a low viscosity can be used.

【0017】[0017]

【発明の実施の形態】図2は、本発明の第1の実施の形
態を示している。本実施の形態では、積層チップ部品と
しての積層インダクタ10は、略矩形状に形成したチッ
プ本体3にコイルを内蔵するとともに、そのチップ本体
3の対向2面に、内蔵コイルの両端とそれぞれ接続する
外部電極4,4を設けた構成であり、外部電極4,4
は、内蔵コイルの軸線に沿う対向2面に形成し、いわゆ
る縦巻き型を採る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows a first embodiment of the present invention. In the present embodiment, a laminated inductor 10 as a laminated chip component has a coil built in a chip body 3 formed in a substantially rectangular shape, and two opposing faces of the chip body 3 are connected to both ends of the built-in coil. The external electrodes 4 and 4 are provided.
Is formed on two opposing surfaces along the axis of the built-in coil, and is a so-called vertical winding type.

【0018】チップ本体3は、セラミック等の絶縁膜か
らなる絶縁膜層1と導体パターン2を適宜な順に積層
し、これにより当該内部に導体パターン2が螺旋状に繋
がったコイルを形成し、積層を完了した後に所定温度で
焼結させる。
In the chip body 3, an insulating film layer 1 made of an insulating film such as ceramics and a conductor pattern 2 are laminated in an appropriate order, thereby forming a coil in which the conductor pattern 2 is spirally connected, and laminated. After completing the above, sintering is performed at a predetermined temperature.

【0019】外部電極4,4は、ディッピングにより形
成する。つまり銀等の導電ペーストの中にチップ本体3
の該当部分を浸けることで形成し、外部電極4,4とし
ては電極面に隣接する4面にも導電膜が所定に覆い被さ
る状態に成膜し、隣接4面に回り込む周縁部40を有す
る形態となる。このため、隣接4面の何れの面が下にな
っても面実装することができ、取り付け姿勢には基本的
には制限がないが、縦巻き型では横倒しにするとコイル
軸も倒れて横に向くので、磁場の向きに関して基板上で
制限がある実装には注意を要する。
The external electrodes 4 and 4 are formed by dipping. That is, the chip body 3 is placed in a conductive paste such as silver.
The external electrodes 4 and 4 are formed by immersing the corresponding portions of the above, and are formed so that the conductive films are also covered in a predetermined manner on the four surfaces adjacent to the electrode surfaces, and the peripheral electrodes 40 wrap around the adjacent four surfaces. Becomes Therefore, it can be surface-mounted regardless of which of the four adjacent surfaces is down, and there is basically no limit to the mounting posture. However, in the vertical winding type, the coil axis also collapses when it is laid sideways. Since it is facing, attention must be paid to mounting where there is a restriction on the substrate regarding the direction of the magnetic field.

【0020】各層をなす絶縁膜層1は、該当面の全域を
均一に覆う状態に形成し、従来のような該当面を部分的
に覆うマスク層は設けない。そして、上下層の導体パタ
ーン2の接続には、層間の絶縁膜層1に、いわゆるスル
ーホールである層間導体部5を設け、これにより上下両
パターンを電気的に接続する構成である。
The insulating film layer 1 forming each layer is formed so as to uniformly cover the entire area of the corresponding surface, and no conventional mask layer partially covering the surface is provided. For connecting the upper and lower conductor patterns 2, an interlayer conductor portion 5 which is a so-called through hole is provided in the interlayer insulating film layer 1 to electrically connect the upper and lower patterns.

【0021】つまり、層間導体部5は、下層側に小片状
の導体ベース50を設け、当該周囲に絶縁膜層1を形成
して穴部6とした後に、穴部6に粘度の低い導電ペース
ト51を充填することにより形成し、当該層を貫いて上
下層の導体パターン2を接続する。
That is, the inter-layer conductor portion 5 is provided with a small piece-shaped conductor base 50 on the lower layer side, the insulating film layer 1 is formed around the conductor base 50 to form the hole portion 6, and then the hole portion 6 is made of a conductive material having a low viscosity. It is formed by filling the paste 51, and the conductor patterns 2 in the upper and lower layers are connected to each other by penetrating the layer.

【0022】導体ベース50は、粘度の高い導電ペース
トにより形成し、形状,サイズは適宜に設定すればよい
が、高さは絶縁膜層1の厚さ設定や、これを形成する絶
縁ペーストの粘度等を考慮して設定し、当該層の形成時
に絶縁ペーストが導体ベース50上面に、いわゆるダレ
て流れ込まない設定にする。
The conductor base 50 is formed of a conductive paste having a high viscosity, and its shape and size may be set appropriately. The height is set by the thickness of the insulating film layer 1 and the viscosity of the insulating paste forming the same. In consideration of the above, the insulating paste is set so as not to soak and flow into the upper surface of the conductor base 50 when the layer is formed.

【0023】(製造方法)積層体であるチップ本体3の
形成は印刷積層法では、セラミック材料からなる絶縁ペ
ーストと、導電材料からなる導電ペーストとを交互にス
クリーン印刷していくもので、それらペーストは1回刷
り出す(塗る)と例えば10μm厚になり、これを塗っ
ては乾燥させて積み重ねていく。チップ部品の製造で
は、ワークとしては生産性の面からチップ部品複数枚分
の大きさのワーク積層体を製作し、そのワーク積層体を
十分に乾燥させた後に各単体に切断して焼成する。
(Manufacturing Method) In the formation of the chip body 3 which is a laminated body, in the printing lamination method, an insulating paste made of a ceramic material and a conductive paste made of a conductive material are alternately screen-printed. After being printed (painted) once, the thickness becomes, for example, 10 μm, and this is applied, dried, and stacked. In the production of chip components, a work laminate having a size of a plurality of chip components is manufactured from the viewpoint of productivity, and the work laminate is sufficiently dried and then cut into individual pieces and baked.

【0024】セラミック材料には、例えばガラスを添加
した低温焼結化した誘電体セラミックス(非磁性セラミ
ックス)を使用する。例えば、ホウケイ酸ガラスをアル
ミナに体積で70:30の比率に混合した誘電体材料を
使用し、これにビヒクルとしてエチルセルロースとテレ
ピネールと分散剤,可塑剤を混合したものを配合して混
練し、印刷用の絶縁ぺーストとすることができる。セラ
ミック材料としては、他にも例えばフェライト等の磁性
セラミックスを使用してもよい。また、バインダーもエ
チルセルロース以外でもよく、PVB,メチルセルロー
スやアクリル樹脂とすることができる。
As the ceramic material, for example, low temperature sintered dielectric ceramics (non-magnetic ceramics) to which glass is added is used. For example, a dielectric material prepared by mixing borosilicate glass with alumina in a volume ratio of 70:30 is used, and a mixture of ethyl cellulose, terpineol, a dispersant, and a plasticizer as a vehicle is mixed and kneaded, followed by printing. Can be an insulating paste for. In addition, magnetic ceramics such as ferrite may be used as the ceramic material. Further, the binder may be other than ethyl cellulose, and may be PVB, methyl cellulose or acrylic resin.

【0025】導電ペーストには銀ペーストを使用し、上
述したビヒクルに混合する。また、導電ペーストは銀パ
ラジウムでもよい。そして、分散剤や可塑剤は、印刷性
の向上や生産時の取り扱いを考慮して適宜に添加する。
A silver paste is used as the conductive paste and is mixed with the vehicle described above. The conductive paste may be silver palladium. Then, the dispersant and the plasticizer are appropriately added in consideration of improvement in printability and handling during production.

【0026】層間導体部5の形成は図3に示す工程手順
を採り、まず、所定パターンのスクリーン版を用いて粘
度の高い導電ペーストを塗って、下層の導体パターン2
上に導体ベース50を形成する(図3(a))。
To form the inter-layer conductor portion 5, the process procedure shown in FIG. 3 is adopted. First, a conductive paste having a high viscosity is applied using a screen plate having a predetermined pattern to form the lower conductor pattern 2.
A conductor base 50 is formed on the top (FIG. 3A).

【0027】次に、反転パターンのスクリーン版を用い
て絶縁ペーストを塗って導体ベース50の周りを埋め、
当該周囲に絶縁膜層1を形成し、導体ベース50の部分
にはくぼんだ穴部6を得る(図3(b))。
Next, using an inversion pattern screen plate, an insulating paste is applied to fill the periphery of the conductor base 50,
The insulating film layer 1 is formed around the periphery, and the recessed hole portion 6 is obtained in the portion of the conductor base 50 (FIG. 3B).

【0028】この後、穴部6に粘度の低い導電ペースト
51を充填し、当該層を貫く層間導体部5の形成を完了
する(図3(c))。そして、層間導体部5上には、フ
ァイン印刷により次層の導体パターン2を形成する(図
3(d))。
After that, the hole 6 is filled with the conductive paste 51 having a low viscosity, and the formation of the interlayer conductor 5 penetrating the layer is completed (FIG. 3C). Then, the conductor pattern 2 of the next layer is formed on the interlayer conductor portion 5 by fine printing (FIG. 3D).

【0029】なお、層間導体部5を多層に積み重ねる形
成も容易であり、図4に示すように、次層の導体ベース
50を形成し(図4(a))、導体ベース50の周りを
埋めて当該周囲に絶縁膜層1を形成し(図4(b))、
穴部6に粘度の低い導電ペースト51を充填して次層の
層間導体部5の形成を完了する(図4(c))。
It is also easy to stack the interlayer conductors 5 in multiple layers. As shown in FIG. 4, a conductor base 50 of the next layer is formed (FIG. 4A), and the periphery of the conductor base 50 is filled. To form an insulating film layer 1 around the periphery (FIG. 4B),
The hole portion 6 is filled with the conductive paste 51 having a low viscosity, and the formation of the interlayer conductor portion 5 of the next layer is completed (FIG. 4C).

【0030】このように、スルーホールとなる層間導体
部5の形成において、小片状の導体ベース50を下層側
にまず設けるので、当該周囲に絶縁膜層1を形成する際
には下層側との接続が予め確保してあって、導体ベース
50の高さを適切に設定するので穴部6が埋まる不良を
防げる。このとき、導体ベース50には粘度の高い導電
ぺーストを使用するので、形状を保持できる。また、穴
部6に充填する導電ペースト51は、粘度の低いものを
使用するので充填が不良になることを防止できる。した
がって、上下層の導体パターン2を接続するスルーホー
ルを不良なく安定に形成できる。
As described above, in the formation of the inter-layer conductor portion 5 to be the through hole, the small piece-shaped conductor base 50 is first provided on the lower layer side. Since the connection is secured in advance and the height of the conductor base 50 is set appropriately, the defect in which the hole 6 is filled can be prevented. At this time, since the conductive paste having a high viscosity is used for the conductor base 50, the shape can be maintained. Moreover, since the conductive paste 51 with which the hole 6 is filled has a low viscosity, it is possible to prevent the filling from becoming defective. Therefore, the through holes connecting the conductor patterns 2 in the upper and lower layers can be stably formed without any defect.

【0031】また、絶縁膜層1を形成する絶縁ペースト
は粘度の低い適正なものを使用することができ、このた
め該当層を平坦に形成できる。そして、導電ペースト
は、適用部分に対応した特性のものをそれぞれ使用する
ことになり、つまり粘度の高い導電ペーストにより導体
ベース50を形成し、穴部6には粘度の低い導電ペース
ト51を充填し、さらに上下層の導体パターン2はファ
イン印刷用の導電ペーストを用いて形成するので、それ
ぞれ最適な導体部分を形成することができる。その結
果、高品位の積層チップ部品が得られる。
Further, the insulating paste for forming the insulating film layer 1 can be an appropriate one having a low viscosity, so that the corresponding layer can be formed flat. Then, as the conductive paste, those having characteristics corresponding to the applied portion are used respectively, that is, the conductive base 50 is formed by the conductive paste having a high viscosity, and the conductive paste 51 having a low viscosity is filled in the hole portion 6. Further, since the upper and lower conductor patterns 2 are formed by using the conductive paste for fine printing, it is possible to form the optimum conductor portions. As a result, a high quality laminated chip component can be obtained.

【0032】図5は、本発明の第2の実施の形態を示し
ている。この第2の実施の形態では、層間導体部5の形
成について、周囲の絶縁膜層1をなす絶縁ペーストに注
目しており、層間導体部5は、粘度の高い絶縁ペースト
により環状の枠部9を設け、当該枠部9内に導電ペース
トを充填する構成とする。
FIG. 5 shows a second embodiment of the present invention. In the second embodiment, attention is paid to the insulating paste forming the surrounding insulating film layer 1 with respect to the formation of the inter-layer conductor portion 5, and the inter-layer conductor portion 5 is made of an insulating paste having a high viscosity to form an annular frame portion 9. Is provided and the frame portion 9 is filled with the conductive paste.

【0033】つまり本形態では、層間導体部5の形成は
図5に示す工程手順を採り、まず、所定パターンのスク
リーン版を用いて粘度の高い絶縁ペーストを塗って、下
層の導体パターン2上に環状の枠部9を形成する(図5
(a),(d))。
That is, in the present embodiment, the interlayer conductor portion 5 is formed by the process procedure shown in FIG. 5. First, a screen plate having a predetermined pattern is used to apply an insulating paste having a high viscosity, and the lower conductor pattern 2 is formed. An annular frame portion 9 is formed (see FIG. 5).
(A), (d)).

【0034】次に、反転パターンのスクリーン版を用い
て絶縁ペーストを塗って枠部9の周りを埋め、当該周囲
に絶縁膜層1を形成し、枠部9の部分にはくぼんだ穴部
6を得る(図5(b))。この後、穴部6に粘度の低い
導電ペースト51を充填し、当該層を貫く層間導体部5
の形成を完了する(図5(c),(e))。
Next, using an inversion pattern screen plate, an insulating paste is applied to fill the periphery of the frame portion 9, the insulating film layer 1 is formed around the periphery, and the recessed hole portion 6 is formed in the frame portion 9. Is obtained (FIG. 5 (b)). After that, the hole portion 6 is filled with a conductive paste 51 having a low viscosity, and the interlayer conductor portion 5 penetrating the layer.
Formation is completed (FIGS. 5C and 5E).

【0035】そして、層間導体部5上には、ファイン印
刷により次層の導体パターンを形成する。
Then, a conductor pattern of the next layer is formed on the interlayer conductor portion 5 by fine printing.

【0036】このように、粘度の高い絶縁ペーストによ
り環状の枠部9を設けるので、絶縁膜層1を形成する際
は当該枠部9が障壁になり、絶縁膜層1を形成する絶縁
ペーストが枠部9内に流れ込むことはない。このとき、
枠部9を形成する絶縁ペーストには粘度の高いものを使
用するので、形状を保持できる。また、枠部9内に充填
する導電ペースト51は、粘度の低いものを使用するの
で、充填が不良になることを防止できる。したがって第
1の実施の形態と同様に、上下層の導体パターン2を接
続するスルーホールを不良なく安定に形成できる。
As described above, since the annular frame portion 9 is provided with the insulating paste having high viscosity, the frame portion 9 serves as a barrier when the insulating film layer 1 is formed, and the insulating paste forming the insulating film layer 1 is It does not flow into the frame 9. At this time,
Since an insulating paste having a high viscosity is used for forming the frame portion 9, the shape can be maintained. Further, since the conductive paste 51 with which the frame portion 9 is filled has a low viscosity, it is possible to prevent defective filling. Therefore, similarly to the first embodiment, the through holes connecting the conductor patterns 2 in the upper and lower layers can be stably formed without any defect.

【0037】また、絶縁膜層1を形成する絶縁ペースト
は粘度の低い適正なものを使用することができ、このた
め該当層を平坦に形成できる。そして、導電ペースト
は、適用部分に対応した特性のものをそれぞれ使用する
ことになり、それぞれ最適な導体部分を形成することが
できる。その結果、高品位の積層チップ部品が得られ
る。
Further, the insulating paste for forming the insulating film layer 1 can be a proper one having a low viscosity, so that the corresponding layer can be formed flat. Then, as the conductive paste, the one having the characteristic corresponding to the applied portion is used, and the optimum conductor portion can be formed. As a result, a high quality laminated chip component can be obtained.

【0038】[0038]

【発明の効果】以上のように、本発明に係る積層チップ
部品では、スルーホールとなる層間導体部の形成におい
て、小片状の導体ベースを下層側にまず設けるので、当
該周囲に絶縁膜層を形成する際には下層側との接続が予
め確保してあって、導体ベースの高さを適切に設定する
ことで穴部が埋まる不良を防げる。このとき、導体ベー
スには粘度の高い導電ぺーストを使用するので形状を保
持でき、穴部に充填する導電ペーストは粘度の低いもの
を使用するので充填が不良になることを防止できる。
As described above, in the laminated chip component according to the present invention, the small-piece-shaped conductor base is first provided on the lower layer side in the formation of the interlayer conductor portion to be the through hole, so that the insulating film layer is formed around the conductor base. When forming the, the connection with the lower layer side is secured in advance, and by appropriately setting the height of the conductor base, it is possible to prevent a defect in which the hole is filled. At this time, since the conductive paste having a high viscosity is used for the conductor base, the shape can be maintained, and since the conductive paste having a low viscosity is used for filling the hole portion, it is possible to prevent the filling failure.

【0039】一方、粘度の高い絶縁ペーストにより環状
の枠部を設けるので、絶縁膜層を形成する際は当該枠部
が障壁になり、絶縁膜層を形成する絶縁ペーストが枠部
内に流れ込むことはない。このとき、枠部を形成する絶
縁ペーストには粘度の高いものを使用するので形状を保
持でき、枠部内に充填する導電ペーストは粘度の低いも
のを使用するので、充填が不良になることを防止でき
る。したがって、何れにしても上下層の導体パターンを
接続するスルーホールを不良なく安定に形成できる。
On the other hand, since the annular frame portion is provided by the insulating paste having high viscosity, the frame portion serves as a barrier when forming the insulating film layer, and the insulating paste forming the insulating film layer does not flow into the frame portion. Absent. At this time, since the insulating paste that forms the frame has a high viscosity, the shape can be maintained, and the conductive paste that fills the frame has a low viscosity, preventing the filling from becoming defective. it can. Therefore, in any case, the through holes connecting the upper and lower conductor patterns can be stably formed without any defect.

【0040】また、絶縁膜層を形成する絶縁ペーストは
粘度の低い適正なものを使用することができ、このため
該当層を平坦に形成できる。そして、導電ペーストは、
適用部分に対応した特性のものをそれぞれ使用すること
になり、それぞれ最適な導体部分を形成することができ
る。その結果、高品位の積層チップ部品が得られる。
Further, as the insulating paste for forming the insulating film layer, an appropriate one having a low viscosity can be used, so that the corresponding layer can be formed flat. And the conductive paste is
Since the ones having the characteristics corresponding to the applied portions are used, the optimum conductor portions can be formed. As a result, a high quality laminated chip component can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】積層チップ部品の従来例の要部であり、上下層
の導体パターンを接続するスルーホール部分の製造工程
を順に示す断面図である。
FIG. 1 is a cross-sectional view showing a main part of a conventional example of a layered chip component and showing in sequence a manufacturing process of a through hole portion for connecting conductor patterns of upper and lower layers.

【図2】第1の実施の形態を示す積層インダクタの側面
図である。
FIG. 2 is a side view of the laminated inductor showing the first embodiment.

【図3】上下層の導体パターンを接続する層間導体部の
製造工程を順に示す断面図である。
3A to 3D are cross-sectional views sequentially showing a manufacturing process of an interlayer conductor portion that connects conductor patterns of upper and lower layers.

【図4】層間導体部の製造工程を順に示す断面図であ
る。
4A to 4C are cross-sectional views sequentially showing a manufacturing process of an interlayer conductor portion.

【図5】層間導体部の他の形態を示し、その製造工程を
順に示す断面図(a)〜(c)及び平面図(d),
(e)である。
5A to 5C are cross-sectional views (a) to (c) and a plan view (d) showing another embodiment of the interlayer conductor part and showing the manufacturing process in order.
(E).

【符号の説明】[Explanation of symbols]

1 絶縁膜層 2 導体パターン 3 チップ本体 4 外部電極 5 層間導体部 6 穴部 7 導電ペースト 8 スルーホール 9 枠部 10 積層インダクタ 40 周縁部 50 導体ベース 51 導電ペースト 1 Insulating film layer 2 conductor pattern 3 chip body 4 external electrodes 5 Interlayer conductor 6 holes 7 Conductive paste 8 through holes 9 frame 10 Multilayer inductor 40 Edge 50 conductor base 51 Conductive paste

フロントページの続き (72)発明者 名和 達彦 東京都港区新橋5丁目36番11号 エフ・デ ィー・ケイ株式会社内 Fターム(参考) 5E062 DD04 5E070 AA01 AB02 CB13 CB17 Continued front page    (72) Inventor Tatsuhiko Nawa             F-de, 5-36-1 Shimbashi, Minato-ku, Tokyo             K.K Co., Ltd. F-term (reference) 5E062 DD04                 5E070 AA01 AB02 CB13 CB17

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 セラミック等の絶縁膜と導体パターンを
適宜な順に積層することで当該内部に前記導体パターン
が層間で繋がった電極体を内蔵するチップ本体を備え
て、当該チップ本体の外面には前記電極体と接続する外
部電極を設ける積層チップ部品において、 前記絶縁膜層に当該層を貫いて上下層の導体パターンを
接続する層間導体部を有し、 前記層間導体部は、下層側に小片状の導体ベースを設
け、当該周囲に絶縁膜層を形成して穴部とした後に、前
記穴部に導電ペーストを充填する構成としたことを特徴
とする積層チップ部品。
1. A chip body having an electrode body in which the conductor pattern is connected between layers is provided by laminating an insulating film such as ceramics and a conductor pattern in an appropriate order, and an outer surface of the chip body is provided. In a multilayer chip component provided with an external electrode connected to the electrode body, the insulating film layer has an interlayer conductor portion that connects the conductor patterns of upper and lower layers, and the interlayer conductor portion is small on the lower layer side. A laminated chip component having a configuration in which a strip-shaped conductor base is provided, an insulating film layer is formed around the strip-shaped conductor base to form a hole, and then the hole is filled with a conductive paste.
【請求項2】 セラミック等の絶縁膜と導体パターンを
適宜な順に積層することで当該内部に前記導体パターン
が層間で繋がった電極体を内蔵するチップ本体を備え
て、当該チップ本体の外面には前記電極体と接続する外
部電極を設ける積層チップ部品において、 前記絶縁膜層に当該層を貫いて上下層の導体パターンを
接続する層間導体部を有し、前記層間導体部は、絶縁ペ
ーストにより環状の枠部を設け、当該枠部内に導電ペー
ストを充填する構成としたことを特徴とする積層チップ
部品。
2. A chip body having an electrode body in which the conductor pattern is connected between layers is provided by laminating an insulating film such as ceramics and a conductor pattern in an appropriate order, and an outer surface of the chip body is provided. In a multilayer chip component provided with an external electrode connected to the electrode body, the insulating film layer has an interlayer conductor part that connects the conductor patterns of upper and lower layers, and the interlayer conductor part is formed of an insulating paste by a ring shape. 2. A layered chip component, wherein the frame portion is provided and the frame portion is filled with a conductive paste.
【請求項3】 前記層間導体部の形成には、粘度の高い
導電ペーストにより下層側に小片状の導体ベースを設
け、当該周囲に絶縁膜層を形成して穴部とした後に、前
記穴部に粘度の低い導電ペーストを充填することを特徴
とする請求項1に記載の積層チップ部品の製造方法。
3. The interlayer conductor is formed by forming a small piece-shaped conductor base on a lower layer side with a conductive paste having a high viscosity, forming an insulating film layer around the conductor base to form a hole, and then forming the hole. The method for manufacturing a layered chip component according to claim 1, wherein the part is filled with a conductive paste having a low viscosity.
【請求項4】 前記層間導体部の形成には、粘度の高い
絶縁ペーストにより環状の枠部を設け、当該枠部内に導
電ペーストを充填することを特徴とする請求項2に記載
の積層チップ部品の製造方法。
4. The multilayer chip component according to claim 2, wherein in forming the interlayer conductor portion, an annular frame portion is provided with an insulating paste having a high viscosity, and the conductive paste is filled in the frame portion. Manufacturing method.
【請求項5】 前記電極体は、前記チップ本体内で導体
パターンが螺旋状に繋がったコイルであることを特徴と
する請求項1から4のいずれか1項に記載の積層チップ
部品。
5. The layered chip component according to claim 1, wherein the electrode body is a coil in which conductor patterns are spirally connected in the chip body.
JP2002141599A 2002-05-16 2002-05-16 Laminated chip component and its manufacturing method Withdrawn JP2003332132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002141599A JP2003332132A (en) 2002-05-16 2002-05-16 Laminated chip component and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2003332132A true JP2003332132A (en) 2003-11-21

Family

ID=29702136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002141599A Withdrawn JP2003332132A (en) 2002-05-16 2002-05-16 Laminated chip component and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2003332132A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108630406A (en) * 2017-03-16 2018-10-09 三星电机株式会社 Coil electronic building brick and the method for manufacturing the coil electronic building brick
JP2019102755A (en) * 2017-12-07 2019-06-24 株式会社村田製作所 Coil component and method of manufacturing the same
JP2019102754A (en) * 2017-12-07 2019-06-24 株式会社村田製作所 Coil component and method of manufacturing the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108630406A (en) * 2017-03-16 2018-10-09 三星电机株式会社 Coil electronic building brick and the method for manufacturing the coil electronic building brick
CN108630406B (en) * 2017-03-16 2020-10-27 三星电机株式会社 Coil electronic component and method of manufacturing the same
JP2019102755A (en) * 2017-12-07 2019-06-24 株式会社村田製作所 Coil component and method of manufacturing the same
JP2019102754A (en) * 2017-12-07 2019-06-24 株式会社村田製作所 Coil component and method of manufacturing the same
US11562846B2 (en) 2017-12-07 2023-01-24 Murata Manufacturing Co., Ltd. Coil component and method for manufacturing the same
US11631527B2 (en) 2017-12-07 2023-04-18 Murata Manufacturing Co., Ltd. Coil component and method for manufacturing the same

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