JP2003330907A - Microcomputer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus operating method capable of easily changing a bus interface specification by increasing effective operation speeds of a bus, and a memory and peripheral function units connected to the bus, in a microcomputer system. <P>SOLUTION: An access operation through buses 113 and 114 with bus masters 101 and 102 connected is executed in a pipeline manner, and control of the pipeline execution is carried out by an exclusive bus controller 111. An access delaying the pipeline operation is executed by buses 123 and 124 of a lower tier connected through a buffer means 112, and by a bus controller 121 exclusively used for the lower tier. Therefore, the bus band for access is improved, and bus interfaces having various specifications, and buses allowing parallel execution can easily be structured. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer system having a bus master, a memory or peripheral function unit, and a bus connected to these units for transferring data.

[0002]

2. Description of the Related Art In a microcomputer system including a processor such as a microcomputer which is a bus master, a memory or peripheral function unit, and a bus, it is necessary to transfer data between the respective units.

On the other hand, in order to operate a logic circuit such as a microcomputer at a high speed, a first method for increasing the operating frequency to operate at a high speed as a whole and a pipeline method for effectively realizing a high speed operation are provided. There are two ways.

According to the first method, there are device limitations and generally an expensive system is often used. Therefore, usually, the first method and the second method are
It is used together in a range that is balanced from the viewpoint of both cost and performance.

On the other hand, as a microcomputer system, a CISC (Complex Insert
A truction set computer) system and a RISC (reduced instruction set computer) system for executing simple instructions at high speed are known.

In the RISC type microcomputer, many instructions are executed at high speed in one clock cycle by pipeline execution.

[0007]

However, in the RISC type microcomputer, the frequency of instruction fetches and data fetches is high, and the operating band of the bus means for exchanging data with the memory and peripheral function units affects the performance of the entire system. It will have a big impact. Therefore, RIS
In a system using a C-system microcomputer, high-speed bus transfer is required, and a memory and a peripheral function unit that operate at high speed are indispensable. However, in reality, not all the memories and peripheral function units connected to the bus can operate at the same speed as the microcomputer that is the bus master of the system. This is because the internal operation is pipelined especially in a high-speed microcomputer, and the time allowed for one pipeline stage is, in most cases, only one cycle of the basic clock of the system. Is.

As described above, when the microcomputer operates at the highest speed, the internal pipeline is executed in order without any disturbance, and the bus connected to this and all the memories and peripheral function units are connected. It is extremely difficult to operate all in one cycle of the basic clock of the system without delay. Therefore, it is necessary to provide an external interface inside the microcomputer together with the pipeline control means for controlling various access cycles and various access data sizes for performing various accesses on the bus of the system.

As described above, according to the above-mentioned conventional technique, the performance of the entire system is limited by the operating speed of the bus and the operating speed of the memory and peripheral function units accessed by the bus, that is, the access time for reading or writing data. There is a first problem that is caused.

In addition, according to the above-mentioned conventional technique, in order to control the bus by the external interface in accordance with the internal pipeline operation of the microcomputer, in addition to the basic external interface originally necessary, the bus is connected to the bus. There is a second problem in that it is necessary to provide an interface function that supports access to all possible memories and peripheral function units, which complicates the external interface and increases the logical scale.

Furthermore, when another system is constructed using the microcomputer, the third problem is that the bus interface specifications of the system are limited, and in a system having a plurality of bus masters, There is a fourth problem in that it is necessary to provide the external interface circuits corresponding to the pipeline operation inside the bus master as many as the number of bus masters.

Therefore, an object of the present invention is to increase the effective operating speed of the bus, the memory and the peripheral function unit, simplify the bus interface on the bus master side, and further improve the interface specifications of the memory and the peripheral function unit. It is an object of the present invention to provide a bus operation method for a microcomputer system that can be easily changed without changing the interface circuit on the bus master side.

[0013]

SUMMARY OF THE INVENTION The above object is to pipeline access to be performed via a bus and to hierarchically construct a bus for performing the access operation according to the operation speed of a device to be accessed. This is achieved by providing a bus controller capable of independently controlling each bus within a certain range.

That is, according to the basic technical idea of the present invention, a bus master, a first address bus to which an address from the bus master is transmitted, a first data bus to which data from the bus master is transmitted, and A high speed memory coupled to the first address bus and the first data bus,
A first bus buffer coupled to the first address bus and the first data bus, and the first address bus to the first bus buffer.
A second address bus coupled via one bus buffer,
A second data bus coupled to the first data bus via the first bus buffer, the second address bus and the second data bus.
2 A low speed device coupled to the data bus and the first device in response to an access request issued by the bus master.
Bus controller unit that grants the bus right between the first address data bus and the first data bus, and a second bus controller that controls the operation of the low-speed device when the access request of the bus master is the low-speed device A bus controller having a section, the bus master performs a pipeline operation including an address output stage and a data read / write stage to access the high speed memory or the low speed device, and the pipeline The operation is a first control signal indicating whether to grant the bus right to the first address bus and the first data bus, and a second control signal indicating whether to stop the pipeline operation. Controlled by the first control signal and the second control signal.
A control signal is output from the bus controller, the first control signal is asserted when permitting the bus right of the first address bus and the first data bus, the second control signal, Negated when stopping the pipeline operation, the bus master, when the first control signal and the second control signal is asserted,
The address output stage is performed, and the pipeline operation is stopped when the second control signal is negated in the previous period.

Further, the bus controller is the first controller.
It is preferable to monitor the access address output to the address bus 1 to determine whether the access is to the low speed device.

Furthermore, it is preferable that the pipeline operation further includes an arbitration stage.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.
This will be described in detail with reference to the drawings.

System Configuration FIG. 1 shows an example of the configuration of a microcomputer system using a pipeline control bus according to an embodiment of the present invention.

Bus masters 101 and 102 are processors such as microcomputers and DMAC (Direct Memory Access).
Controller) is a module that reads and writes data to memory and other peripheral function units in the system. This bus master 101,
The reference numeral 102 designates the address bus 1 when data is read from or written in the memories 115, 125 and other peripheral function units 126, 127 in the system.
Data is transmitted and received via a bus that can be classified into 13, 123 and data buses 114, 124.

The hierarchical bus bus is connected to each module accessible by the bus masters 101 and 102. Both the address bus and the data bus are 113, 114, 123 and 124.
Is roughly divided into two layers. This is to efficiently access a plurality of modules having different access times and access frequencies, and secondly to simplify the pipeline control of the entire bus interface by layering it. This is because.

The first level address bus 113 is connected to the IAB
(Internal Address Bus), first-tier data bus 11
4 is called IDB (Internal Data Bus).

The bus masters 101 and 102 in the high-speed memory chip directly drive the first-level address bus 113 and the first-level data bus 114, thereby driving the internal high-speed memory 115 connected to the first-level bus. High-speed continuous access is possible. Alternatively, in the case of discrete memory access, in many cases, it is possible to maintain high execution performance as the entire program by the instruction execution method by delayed load. Here, delayed loading means that when the bus master reads data from a storage device such as a memory,
This means executing a command or the like that does not affect the data by utilizing the gap until the desired data is read into the bus master.

The memory access operation in which the bus master 101 or 102 reads / writes data from / into the internal high-speed memory 115 via the IAB and IDB is pipelined, and the pipelined execution of this memory access is the first. It is controlled by the bus controller 111 of the hierarchy.

First-Level Bus Controller The first-level bus controller 111 directly controls the bus cycle involved in memory access in the circuit block 110 shown in FIG.
0 is a range directly connected by the first layer buses IAB and IDB. Details of the pipeline execution of memory access will be described later with reference to FIG.

Here, the memory access is activated by the bus masters 101 and 102, which are the subjects of the access operation.
In response to the memory access activation signal, the first-level bus controller 111 determines which bus master is granted the bus right for memory access when there are a plurality of bus masters, and the IAB, It controls the operation timing related to IDB data transfer. Therefore, the bus master, after activating the memory access, can execute another process until the bus controller instructs the next operation. Further, since the memory access itself is pipelined and its execution control is performed by the bus controller, not by the bus master, the pipeline configuration of the bus master does not necessarily match the pipeline configuration of the memory access itself. No need.

First layer bus buffer Further, the first layer buses IAB and IDB are transmitted through the first layer bus buffer 112 through the second layer bus means such as PAB (Peripheral Address Bus) 123 and PDB (. Pe
ripheral Data Bus) 124. Here, PAB is the address bus 123 of the second layer and PDB.
Is the data bus 124 of the second layer. The first layer bus buffer 112 is capable of unidirectionally transferring an address from the IAB 113 to the PAB 123 and bidirectionally transferring data between the IDB 114 and the PDB 124.

When the access request from the bus controller of the second layer delays the pipeline operation executed on the bus of the first layer, the bus controller 111 of the first layer controls execution of the access. To the second level bus controller 121. The buffer means 112 of the first layer transfers the address and data with a time lag at this time.
That is, the buses 123 and 124 of the second layer are connected to the low-speed memory 125 having a slow access speed, the peripheral function modules 126 and 127 having a low access frequency or a low access speed, and the bus means of a lower layer. Second-level bus buffer means 122 for
Etc., and the access operation thereof is controlled by the bus controller 121 of the second layer.

In this way, the second level bus controller 1
The range in which 21 controls the memory access operation is the circuit block 120, and the circuit block 120 is the range directly connected by the bus means PAB and PDB. That is, based on the information from the bus controller of the first layer, the bus means PAB and PDB of the second layer and the memory and peripheral function modules connected to the bus means are controlled to be executed in the first layer within a certain range. Can be controlled separately from.

Control of Bus Operation Therefore, access requests from the bus masters 101 and 102 are
First, it is supplied to the first bus controller, and whether the target of this access request is the range of the high-speed circuit block 110, the range of the low-speed circuit block 120, or the block of the lower speed and the lower speed of the first layer. It is determined by the bus controller 111 and the bus controller 121 of the second layer. That is, by including the information for identifying the access target in the access requests from the bus masters 101 and 102, the controller 11 can be identified from the identification information.
1, 121 can also perform the above determination. Further, the bus controllers 111 and 121 monitor access addresses from the bus masters 101 and 102 on the address bus, and determine whether the target of the access request is a high-speed circuit block range, a low-speed circuit block, or a lower-speed circuit block. A decision can be made. When the target of the access request is within the range of the high-speed circuit block 110, the bus buffers 112 and 122 are deactivated, and the data transfer between the bus master and the internal high-speed memory 115 is performed by the first-layer buses 113 and 114. Run through. If the target of the access request is within the range of the low-speed circuit block 120,
The bus buffer 112 is in an operating state, the bus buffer 122 is in a non-operating state, and data transfer between the bus master and the low speed memory 125 or the peripheral function units 126 and 127 is performed by the first layer buses 113 and 114 and the bus buffer 11.
2 is executed via the buses 123 and 124 of the second layer. If the target of the access request is within the range of the lower speed circuit block, the bus buffers 112 and 122 are in the operating state, and the data transfer between the bus master and the lower speed circuit is performed by the buses 113 and 114 of the first layer. Bus buffer 1
12, second layer buses 123 and 124, bus buffer 1
22 and is executed via the bus of the lower hierarchy.

Furthermore, in the system configuration example of FIG. 1, the effect of the present invention is effective even when there is only one bus master. Even when the bus hierarchy is only the first hierarchy, there are a plurality of sets for each hierarchy. However, even when a plurality of bus buffers are provided in parallel to construct each bus hierarchy, the effect of the present invention is effective.

Configuration of Memory Access Pipeline Next, the memory access pipeline execution and the control method of the pipeline execution will be described in detail with reference to FIG.

First, referring to FIG. 2, the contents of the memory access process will be analyzed step by step in the case of read access.

Bus master 101 for memory access
Calculates the address required for access. At this time,
If it is an ordinary general processor, a certain register 20
The value that is the source of the address is read from 1 and the arithmetic unit (A
U) 202 performs a desired address calculation and then stores it in the address buffer 203. Address buffer 203
The address stored in the memory 11 is output to the address bus 113 at an appropriate timing and is accessed on the memory 11 side.
A read / write signal indicating the type of access is normally given to 5.

On the side of the memory 115, the address bus 113
After receiving the address through, the address decoder 204 decodes the address. Then, the necessary memory element is selected based on the decode information, and the data read by the data buffer 206 on the memory side is output to the data bus 114 through the processing 205 for reading through the sense amplifier.

The bus master 101 of the access source fetches the read data on the data bus 114 into the data buffer 207 on the bus master side, and further, the desired register 2
It is stored in 08.

Among the above processing contents, the time weight is relatively large because of the address calculation in the bus master.
There are two locations from the memory element selection to the data reading after the address is loaded into the memory. Therefore, in general, it can be said that these two locations are particularly devised in terms of circuits and optimized.

On the other hand, the delays of the address bus and the data bus itself which connect the bus master to the memory and peripheral modules have become relatively non-negligible as the module performance has improved. Even if each module is optimized and operates at high speed, if the interfaces are not matched, the margin design that is unnecessary in terms of speed will be obliged and the overall performance will deteriorate. It will be.

In the present embodiment, the main focus is to realize a balanced pipeline operation as a whole from address calculation in the bus master to data fetching. FIG. 2 shows an example of pipeline stage allocation when the two-phase non-overlap clocks φ1 and φ2 are used as system clocks.

That is, data is read from the register 201 at the φ1 timing and sent to the arithmetic unit (AU) 202, and the calculated address is stored in the address buffer 203 at the φ2 timing and output to the address bus 113. Next, this address is temporarily latched before and after the address decoder 204 of the memory 115 at φ1 timing, and the read data is stored in the data buffer 206 at φ2 timing and output to the data bus 114. In addition, the read data on the data bus 114 is
The data is taken into the data buffer 207 on the bus master side at one timing and further stored in the desired register 208 at the φ2 timing.

High-speed memory 11 accessed in this way
The pipeline stage is assigned to No. 5, and the access time of the memory should be within the period from the rise of φ1 to the fall of φ2. Moreover, the access time in this case is a period purely from the selection of the memory element to the reading of the data excluding the address decoding and the bus driving, so that the operation can be performed at a higher speed than the conventional one.

That is, in the system of the pipeline control bus according to the present embodiment, it is possible to operate as if the delays caused by the address bus 113, the data bus 114 and the interface circuit thereof are canceled. By doing this, the bus bandwidth improves, but
In addition to the pipeline of the bus master itself, the total number of pipeline stages including memory access is increasing, so the number of combinations of control conditions increases and pipeline control becomes complicated for unified control. It is possible. In addition, there are many peripheral modules that are accessed infrequently or that do not require continuous access, and there is a risk that proper bus management will become difficult.

In order to solve these problems, in the present embodiment, the bus means are hierarchized as described with reference to FIG. 1, and the bus master corresponds only to the interface of the highest speed bus.
A bus controller is arranged for each descending hierarchy so that the bus master does not directly control the slower lower hierarchy bus.

Memory Access Pipeline Operation Next, using the operation timing chart of FIG.
Furthermore, the actual pipeline operation at the time of memory access will be described.

The access within the range 110 connected by the bus means of the first hierarchy in FIG. 1 is operated by four pipeline stages as shown in FIG. That is, the bus arbitration stage 301, the address output stage 302, and the write data stage 30
3 and 4 stages of the read data stage 304. Now, consider the case where the four-stage pipelines are all operating one cycle at a time without waiting time.

The bus arbitration stage 301 judges whether or not the bus request signal BUSREQ output from the bus master at the φ2 timing can be given to the bus master, and returns the bus acknowledge signal BUSACK to return the bus mastership signal. Manage.

When the bus right is granted by this bus arbitration, the address can be output to the address bus IAB from the φ2 timing of the next cycle. This is the address output stage 302.

In the next cycle, in the case of write access, the write data for the address output to the address bus IAB in the previous cycle is output to the data bus IDB from the φ2 timing. This is the write data stage 303, and in the case of read access, read data is output from the module accessed on the same timing.

In the case of a read access, the read data stage 304 of the next cycle is followed by the data bus I.
The read data output to DB is taken into the bus master at the timing of φ1. In the case of write access,
In the same read data stage 304, the write data output from the bus master to the data bus IDB is fetched into the data buffer on the accessed side at the φ1 timing.

In this pipeline control bus system, memory access within the range 110 connected by the bus means of the first layer directly accessed by the bus master operates in the four-stage pipeline described above, so that the memory etc. It is possible to increase the continuous access band of 2 to 3 times. In particular, by pipeline processing the bus arbitration, the time required to transfer the bus right between the bus masters is virtually invisible. Therefore, in a system in which the bus right is frequently transferred, the bus usage efficiency can be improved as compared with the conventional system.
Here, when there is one bus master in the system, the bus arbitration stage can be deleted from the pipeline stages described above.

Control of Pipeline Operation Next, an example of control of the pipeline operation described above will be described with reference to FIG.

The pipeline operation control example shown in FIG.
It is a control to advance or stop all four pipelines at the same time. To control this, one BUSRDY is used.
Signal is enough. BUSRDY signal is in every state φ
It is output at two timings and determines whether to advance the bus pipeline in the next state.

The BUSRDY signal is generated from the information about the memory access space such as the data size and the number of access cycles, the access state, and the information about the type of access target. The BUSRDY signal is generated by the bus controller and output to each bus master. Each bus master knows that the bus pipeline at that time has advanced by one stage when the BUSRDY signal is asserted when there is a bus cycle in the middle of access.

Next, the handling of the bus right in the pipeline operation will be described.

The transfer of the bus right in this embodiment is performed in the first stage of the pipeline. Therefore, the bus right request signal BUSREQ output from the bus master is valid only for one cycle period. That is, in the bus controller, every cycle, the bus acknowledge signal BUSAC is issued in response to the bus right request signal BUSREQ at that time.
The bus master in which K is generated and the BUSACK signal is asserted is given the right to use the bus pipeline for one access from the next cycle. However, since the pipeline cannot proceed unless the BUSRDY signal is asserted, the bus right is not actually granted unless the bus acknowledge signals BUSACK and BUSRDY signals are asserted at the same time. In this way, once the bus right is granted, the pipeline is sequentially executed according to the BUSRDY signal.

Cycle 40 of the basic clock shown in FIG.
In 1, the bus arbitration stage BAT for executing the bus cycle of access 1 is executed and the bus right is given to access 1. Therefore, in the next cycle 402, the address for executing the bus cycle of access 1 is executed. The output stage ADD is executed.

However, in cycle 402, BUSRDY
Since the signal is negated, the pipeline operation relating to the bus cycle of access 1 is the next cycle 403.
However, the address output stage remains as it is and the next pipeline operation cannot be started.

On the other hand, in the same cycle 402, access 2
The bus arbitration stage BAT for executing the bus cycle called
Since the Y signal is negated, the bus arbitration BAT becomes invalid and a new cycle 403
Then I will start the bus arbitration BAT again.

In cycles 403 and 404, BUSRDY
Signal is asserted and the following cycle 404, 40
5, the bus cycle of access 1 uses the data bus to transfer data, the bus cycle of access 2 uses the data bus after performing address transfer, and in cycle 404, access 3 acquires the bus right. Then, from cycle 405, access 4 starts executing the bus arbitration stage BAT.

In cycle 405, the BUSRDY signal is negated again, and in the subsequent cycle 406, the bus pipelines of access 2 and access 3 are put in the wait state, and access 4 acquires the bus right.

As described above, in this embodiment, a maximum of three access bus cycles are pipeline-executed at the same time. Further, in this method, since the bus arbitration is also assigned to one pipeline stage, this access may be executed by one bus master or three different bus masters. Therefore, in this method, apart from the bus arbitration, up to three bus masters can simultaneously use the bus resources and execute the respective access processes by pipeline.

Further, in the bus configuration according to the present invention, lower-level buses controlled by dedicated bus controllers can be hierarchically arranged under the pipeline control bus described above, and the peripheral modules to be connected can be connected. It is possible to freely construct a bus interface according to the above.

Pipeline Operation Control of Hierarchical Bus Next, an example of pipeline operation control of the hierarchical bus will be described with reference to FIG.

In FIG. 5, IAB and IDB are the first layer buses explained in FIG. 1, and the first layer address bus 11 is used.
3 and the data bus 114 of the first layer,
B and PDB are the second level bus described in FIG. 1, and are the second level address bus 123 and the second level data bus 124.
It corresponds to.

In FIG. 5, six access operations 531 to 536 are assumed as access cycles using the bus.
Access operations 531 and 535 are read cycles using the second hierarchy bus, access operations 534 are write cycles using the second hierarchy bus, and access operations 532 and 536.
Is a write cycle using the first hierarchy bus, and the access operation 533 is a read cycle using the first hierarchy bus. Also, apparent bus cycles corresponding to the access operations 531 to 536 are cycle periods 521 to 526 of the basic clock.

The signal controlling the pipeline operation of the bus is the BUSRDY signal, and the pipeline operation control by the BUSRDY signal is as described in FIG.

FIG. 5 shows an example of an interface with the pipeline operation executed by the first layer bus, where the number of memory cycles executed through the second layer bus is three.

The pipeline wait control by the access operation 531 corresponds to the BUSRDY signal negated in the basic clock cycles 503 and 504, and the pipeline wait control by the access operation 534 is negated in the basic clock cycles 508 and 509. In response to the BUSRDY signal that is present, pipeline control by the access operation 535 is performed in the basic clock cycle 5
This corresponds to the BUSRDY signal negated at 11, 512.

That is, in the wait control in the first access operation 531 which is a read cycle using the low speed second layer bus, the first layer bus buffer 112 is IAB
Since the above address is transferred to the PAB and held for three cycles of the basic clock, and bidirectional data transfer between the IDB and PDB is possible, during this time, from the device connected to the second layer bus The data is read out, the second layer bus, the first layer bus buffer, the first layer
It is read by the bus master via the hierarchical bus.

In the second access operation 532, which is a write cycle using the high-speed first hierarchy bus, under the influence of the two-cycle wait in the first access operation 531,
Although the address output stage ADD is extended by two cycles, the write operation is completed within one cycle of the basic clock after the end of the wait.

In the third access operation 533, which is a read cycle using the high-speed first hierarchy bus, under the influence of the two-cycle wait in the first access operation 531,
Although the bus arbitration BAT is extended by two cycles, the reading is completed within two cycles of the basic clock after the end of the wait.

In the wait control in the fourth access operation 534, which is a write cycle using the low-speed second hierarchy bus, the first hierarchy bus buffer 112 transfers the address on the IAB to the PAB and the three cycles of the basic clock. Since it can be held between the IDB and the PDB and the data can be transferred bidirectionally between the bus master and the device connected to the bus of the second layer, the bus of the first layer and the bus of the first layer can be held during this period. Data is transferred via the buffer and the bus of the second layer, and if the device is a memory, the data is read.

Although the embodiment of the present invention has been described in detail above, it is needless to say that the present invention is not limited to this embodiment and various modifications can be made within the scope of the technical idea thereof.

For example, SR is used as the internal high-speed memory 115.
Using AM, low-speed memory 125 as DRAM, EPR
It goes without saying that OM and others can be used.

In this embodiment, the number of wait cycles for accessing the low-speed second layer bus is two, but the number of wait cycles may be changed according to the speed of the second layer bus device. It is clear that the effect of is obtained.

The present invention incorporates a processor such as a microcomputer on a chip, and optimally designs a high-speed memory, a low-speed memory, a peripheral function unit, etc. in order to maximize the customer's target performance. Applica
It is particularly suitable for use in motion specific ICs).

The present invention has been described above.
The following effects can be obtained by applying the present invention.

First, by the bus of the first layer which executes pipeline access at high speed, the operating speed of the bus and the operating speed of the memory and peripheral function units accessed by the bus are effectively increased. The first problem that the performance of the entire system is limited by the access time for reading or writing data can be solved.

Further, by controlling the pipeline execution of the memory access by the bus of the first layer by the dedicated first layer bus controller, the bus master which is the subject of the access can control the bus controller of the first layer. It suffices to include a bus instruction for activating a memory access operation and means for executing address output and data input / output in accordance with a control signal from the first layer bus controller.
In other words, by separating the pipeline operation control inside the bus master of a microcomputer or the like from the memory access pipeline operation control, the bus master itself has only to realize a simple interface. In particular, the memory access operation is pipelined. In this case, the number of control conditions that occur in various combinations with the pipeline execution state inside the bus master can be reduced. This can reduce the control logic scale for executing the memory access as a whole, and can solve the second problem that the logic scale increases.

Further, there is provided a bus controller capable of hierarchizing the buses for executing the access operation according to the operation speed of the device to be accessed and further independently controlling the buses of the respective hierarchies within a certain fixed range. Thus, it is possible to obtain the same effect as in the case where the memory access operation control is separated between the first layer bus controller and the bus master.

When another system is constructed by using the bus master module such as a microcomputer corresponding to the bus interface according to the present invention, the bus interface circuit of the bus master module is not changed and the bus controller of the first layer is used. , Or even by changing the functional specifications of the bus controller in the lower hierarchy, it becomes possible to deal with it, and when constructing another system,
The third problem that the bus interface specification of the system is limited can be solved.

Further, as another effect by separating the pipeline operation control inside the bus master such as a microcomputer from the memory access operation control, in a system having a plurality of bus masters, each bus master performs the same function. It is not necessary to have a complicated bus interface, each bus master only has a simple bus interface, and it is sufficient to have one bus controller for controlling memory access execution as a whole, and an external bus with all memory access functions. It is possible to solve the fourth problem that it is necessary to provide the interface circuits by the number of bus masters. In addition, this means that even if the specifications of the internal pipeline operations of the respective bus masters are different, as long as the above-mentioned simple bus interface means is provided, the high-speed operation of the first hierarchy according to the present invention is achieved. It means that it is possible to connect to bus means.

As described above, the effective operating speed of the bus and the memories and peripheral function units connected to the bus are increased, the bus interface on the bus master side is simplified, and the memories and peripherals connected to the bus are also improved. A bus operation method in which the interface specifications on the functional unit side can be easily changed without changing the interface circuit on the bus master side, and an operation control method for the bus and a memory or peripheral function unit connected to the bus , And a microcomputer capable of operating according to the operating system of the bus, and a system including these units.

[0083]

According to the present invention, it is possible to provide a microcomputer system capable of operating at high speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a microcomputer system using a pipeline control bus according to an embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating a pipeline operation of memory reading according to the embodiment of FIG.

FIG. 3 is a diagram illustrating pipeline operation control of memory access according to the embodiment of FIG.

FIG. 4 is a diagram illustrating pipeline operation control of memory access according to the embodiment of FIG.

5 is a diagram illustrating an example of pipeline operation control of the hierarchical structure bus of the embodiment of FIG.

[Explanation of symbols]

101 ... First bus master, 102 ... Second bus master, 1
Reference numeral 10 ... High-speed circuit block connected by a first layer bus, 111 ... First layer bus controller, 112 ... First layer bus buffer, 113 ... First layer address bus, 114 ... First layer data Bus, 115 ... Internal high-speed memory, 120 ... Low-speed circuit block connected by second-tier bus, 121 ... Second-tier bus controller,
122 ... Second layer bus buffer, 123 ... Second layer address bus, 124 ... Second layer data bus, 125
... Low speed memory, 126, 127 ... Peripheral function unit, 2
01 ... Register, 202 ... Address arithmetic unit (AU), 2
03 ... address buffer, 204 ... address decoder,
205 ... Storage element selecting / reading means, 206 ... Read data buffer, 207 ... Data buffer, 208 ...
Register, 301 ... Bus arbitration stage,
302 ... Address output stage, 303 ... Write data stage, 304 ... Read data stage, 401-4
07 ... Basic clock cycles, 501-515 ... Basic clock cycles, 521-526 ... Apparent access bus cycles, 531-536 ... Access operations.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shigeki Masumura             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Hideo Nakamura             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Takaki Noguchi             1-280, Higashi Koikekubo, Kokubunji, Tokyo             Central Research Laboratory, Hitachi, Ltd. (72) Inventor Shunpei Kawasaki             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Kaoru Fukada             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Yasushi Akao             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group F term (reference) 5B062 DD10 JJ10                 5B077 BA02 MM02

Claims (6)

[Claims] 1. A bus master, a first address bus to which an address from the bus master is transmitted, a first data bus to which data from the bus master is transmitted, the first address bus and the first data bus. A high-speed memory coupled to the first address bus, a first bus buffer coupled to the first address bus and the first data bus, a second bus coupled to the first address bus via the first bus buffer An address bus, a second data bus coupled to the first data bus via the first bus buffer, a low speed device coupled to the second address bus and the second data bus, and from the bus master In response to the issued access request, the access request from the first bus controller unit that grants the bus right to the first address bus and the first data bus In the case of a low speed device, a bus controller having a second bus controller unit for controlling the operation of the low speed device is provided, and the bus master outputs an address to access the high speed memory or the low speed device. A pipeline operation including a cascade stage and a data read / write stage is performed, and the pipeline operation is a first indicating whether or not to grant the bus right of the first address bus and the first data bus. Control signal, controlled by a second control signal indicating whether to stop the pipeline operation, the first control signal and the second control signal is output from the bus controller, the first control signal, The first address bus and the first
Is asserted when permitting a bus right with the data bus of, the second control signal is negated when stopping the pipeline operation, the bus master, the first control signal and the second control signal The microcomputer system, wherein the address output stage is performed when asserted, and the pipeline operation is stopped when the second control signal is negated in the previous period. 2. The microcomputer system according to claim 1, wherein the bus controller monitors an access address output to the first address bus to determine whether the access is to the low speed device. . 3. The microcomputer system according to claim 1, wherein the pipeline operation further includes an arbitration stage. 4. The bus master according to claim 1, wherein a plurality of bus masters are provided, and a plurality of the first control signals are output corresponding to each of the plurality of bus masters. Microcomputer system. 5. The microcomputer system according to claim 1, wherein the bus master is built in one chip together with the high speed memory and the low speed device. 6. A microcomputer system, wherein memory access from a bus master is pipelined hierarchically.