JP2003329736A - Test circuit for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that it is impossible to perform specification of nonconformity spots which aims at failure analysis or test development, and observation of its information by a limited number of terminals, in a test circuit which inputs an expected value to a semiconductor integrated circuit and performs comparison inside. <P>SOLUTION: An output data signal A of a test object circuit 1 and an expected value signal B from an expected value input terminal 2 are compared by a comparing means 3, and the comparison result signal C is held in a nonconformity holding means M1 when the signal C represents nonconformity. When a decision signal D outputted by the holding means M1 represents nonconformity, an output data locking means M2 holds the logic value of the output signal A of the circuit 1. When a delayed decision signal F as a delayed signal of the decision signal D by a decision delay means 11 is in a state of representing nonconformity, and output buffer 12 is brought into a conducting state, and a defective information signal E is outputted to the outside from an input/output terminal 2A for inputting the expected value signal B. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit of a semiconductor integrated circuit suitable for selection of non-defective products and defective products, failure analysis, and test development.

[0002]

2. Description of the Related Art A conventional test circuit for a semiconductor integrated circuit is shown in FIG. 11 and will be described below (see Japanese Patent Application Laid-Open No. 3-25382).

In FIG. 11, reference numeral 60 denotes a test target circuit which is a semiconductor integrated circuit as a test target. A test pattern is periodically input to the test target circuit 60 from an LSI tester (not shown) in synchronization with a clock CLK ₀ . The first and second output data signals A1 and A2 are output from the output terminal of the test target circuit 60 at a predetermined cycle. 61,
Reference numeral 62 is an expected value input terminal for inputting the expected value signals B1 and B2, and 63 and 64 are comparing means for comparing the output data signals A1 and A2 with the expected value signals B1 and B2, respectively, which are constituted by exclusive OR gates. Has been done. The exclusive OR gate outputs "0" when the two inputs match and outputs "1" when they do not match. 65 is a comparison means 63, 64
Is a logical sum gate that logically sums the outputs of the output signals C1 and C2 from Reference numeral 66 is a flip-flop that latches the output signal C3 from the OR gate 65 in synchronization with the rising edge of the clock CLK ₀ . Reference numeral 67 is a determination signal output terminal for outputting a determination signal D which is the result of internal comparison.

Here, when the circuit under test 60 is operating normally and the output data signals A1 and A2 match the expected value signals B1 and B2, respectively, the comparing means 6
When the output signals C1 and C2 of 3 and 64 are both “0”, the OR gate 6 is generated at the rising timing of the clock CLK _0.
When the output signal C3 of 5 is "0", the determination signal D which is the output of the flip-flop 66 outputs "0".

However, when the circuit under test 60 causes an abnormal operation and the output data signal A1 does not match the expected value signal B1 or the output data signal A2 does not match the expected value signal B2, or both of them. When at least one of the output signals C1 and C2 of the comparison means 63 and 64 becomes "1", the clock CLK
_When the output signal C3 of the OR gate 65 is "1" at the rising timing of ₀ , the determination signal D which is the output of the flip-flop 66 outputs "1". The judgment signal D externally output from the judgment signal output terminal 67 is judged by the LSI tester. This allows you to test all expected values without making an external comparison.

[0006]

However, in the case of the prior art having the above-mentioned configuration, the determination signal D output externally outputs "0" and "1" while the operation of the circuit under test 60 does not enter the abnormal sequence. When it is repeated, it is difficult to accurately determine the abnormal operation due to the output delay and the terminal skew generated by the board capacity of the LSI tester. Therefore, a high-precision and high-cost LSI tester has to be used.

Further, as the debug information of the failure analysis or the test pattern creation error, information whether the output data signal of the test target circuit 60 is logically "0" or "1" in the abnormal operation cycle, or the corresponding information. In order to output the defective time information signal indicating when the cycle was, a terminal dedicated to the output must be specially provided.

Further, there is a problem that even if the defective time information signal is output, the LSI tester cannot accurately determine it in the case of high-speed operation due to a problem such as the board capacity of the LSI tester.

Further, the timing of inputting the expected value signal does not coincide with the output data signal due to delay variation inside the LSI, and there is a possibility that it may be determined as a defective product although it is a good product. In order to avoid this inconvenience, it is sufficient to constantly change the input timing and repeat the test a plurality of times for one test target circuit, but this causes a problem that the inspection time becomes long.

Further, even if a defect is determined, the internal clock cannot be stopped at the timing of the mismatch, so that the switching operation of the mounted transistors is continuously performed, and the defective portion is detected while maintaining the state where the mismatch occurs in the test. There was a problem that it could not be specified.

[0011]

The present invention solves the above problems by taking the following means.

As a first solution, a test circuit for a semiconductor integrated circuit according to the present invention comprises an expected value input terminal for inputting an expected value signal, an output data signal of a circuit under test and the expectation value from the expected value input terminal. Comparing means for comparing with the value signal, disagreement holding means for holding the disagreement state when the comparison result signal from the comparing means indicates disagreement, and a determination signal for externally outputting the determination signal output by the inconsistency holding means An output terminal, an output data lock unit that holds an output data signal from the test target circuit when the determination signal output from the mismatch hold unit indicates a mismatch state, and an output signal of the output data lock unit is externally output. And a defect information output terminal for

According to this structure, the comparison means compares the output data signal with the expected value signal, and when the result of the comparison shows a mismatch, the mismatch holding means holds the mismatch state and then outputs the determination signal to the outside. At the same time, the output data locking means locks the output data signal output from the circuit under test at the timing when the mismatch occurs, and then outputs the signal externally. That is, while performing internal comparison between the output data signal and the expected value signal, defect information (the output data signal is logically "0" at the abnormal operation timing,
It is possible to hold information used for failure analysis which is "1". Since this defect information is retained even after the mismatch detection, it can be externally observed even during the high speed test without being affected by the board capacity.

As a second solving means, a test circuit for a semiconductor integrated circuit according to the present invention is the same as the first solving means, wherein the defect information output terminal is omitted, and further,
The following components have been added. That is, the determination delay means for delaying the determination signal output from the mismatch holding means by a predetermined period, and the expected value input terminal are connected,
The output buffer outputs a high impedance when the delay determination signal from the determination delay means indicates a match, and outputs the output signal from the output data locking means when the delay determination signal indicates a mismatch.

This makes it possible to omit the defect information output terminal. That is, the expected value input terminal is also used as the output terminal of the defect information signal (this input terminal is also used as the input / output terminal 2 in the description of the embodiments described later).
Equivalent to A). The determination signal output by the mismatch holding means is delayed by the determination delay means. This is the delay determination signal. When the delay determination signals indicate coincidence, the output buffer outputs high impedance, so the output of the output data lock means and the expected value input terminal are electrically separated. Therefore, there is no problem in inputting the expected value signal. When the output data signal and the expected value signal do not match, the determination signal of the inconsistency holding means becomes active, and as a result, the output data signal of the circuit under test is locked by the output data locking means. The determination signal is delayed, and the delayed determination signal becomes active. Input of the expected value signal is stopped within this delay time. Then, the activated delay determination signal brings the output buffer into a conducting state, and the defect information signal from the output data lock means is externally output from the expected value input terminal.
Since the expected value input terminal is also used as the output terminal of the failure information signal, it is possible to eliminate the need for a dedicated output terminal for outputting the failure information signal, as compared with the case of the first solution.

As a third solving means, a test circuit for a semiconductor integrated circuit according to the present invention is obtained by adding the following constituent elements to the above first solving means. That is, a determination delay unit that delays the determination signal output by the mismatch holding unit by a predetermined period, and a clock are measured,
A clock measuring unit that holds the number of measurement clocks at the timing when the judgment signal output from the mismatch holding unit changes to mismatch, and the held measurement clock when the delay judgment signal output from the judgment delay unit indicates a mismatch When the measurement clock number output means for serially outputting a number at a predetermined interval and the delay judgment signal output by the judgment delay means indicate a match, the output of the output data lock means is selected, and when they do not match, the measurement is performed. Selecting means for selecting the output of the clock number output means and outputting it to the defect information output terminal.

This is in addition to the defect information indicating whether the output data signal of the test target circuit is logically "0" or "1" at the time of abnormal operation, and at what timing the abnormal operation occurs. The defect time information is externally output. Further, the defect information and the defect time information are externally output from the same output terminal (defect information output terminal). The clock measuring means is reset together with the mismatch holding means at the start of the test operation. When the determination signal output from the non-coincidence holding unit changes to non-coincidence, the clock measuring unit stops the time counting operation and holds the number of measurement clocks measured until then. On the other hand, the failure information signal held by the output data lock means is externally output from the failure information output terminal via the selection means. When the delayed determination signal obtained by delaying the determination signal by the determination delay means becomes active, the measurement clock number output means is activated and the output of the selection means is switched to the measurement clock number output means side. The measurement clock number output means performs parallel / serial conversion of the measurement clock number data (multivalue) held by the clock measurement means. The serial data of the number of measurement clocks is sequentially output from the defect information output terminal to the outside through the selecting means. The data of the number of measurement clocks is not 1 bit but multivalued, and parallel / serial conversion is performed in order to output this from one defect information output terminal. Further, in order to output the defect information signal and the defect time information signal from the same defect information output terminal, an output form in a time division state is adopted, and therefore a selecting means is provided. According to the present invention, not only the defect information but also the defect time information can be obtained, and the defect information output terminal for outputting the defect information signal is also used as an external output of the defect time information signal. Simplification can proceed.

As a fourth solving means, a test circuit for a semiconductor integrated circuit according to the present invention is the same as the above first solving means, except that the defect information output terminal is omitted.
The following components have been added. That is, first determination delay means for delaying the determination signal output from the mismatch holding means by a predetermined cycle, and second determination delay means for delaying the delay determination signal from the first determination delay means by a predetermined cycle. A clock measuring unit that measures a clock and holds the number of measurement clocks at the timing when the determination signal output from the inconsistency holding unit changes to inconsistent; and a second delay determination output from the second determination delay unit. When the measured clock number output means that serially outputs the held measured clock number at a predetermined interval when the signals indicate a mismatch and the second delay determination signal output by the second determination delay means indicate a match Selects the output of the output data lock means, and when there is a mismatch, selects the output of the measurement clock number output means and outputs it, and the expected value input terminal When the first delay determination signal output from the first determination delay means indicates a match, a high impedance is output, and when the first delay determination signal indicates a mismatch, the output signal of the selection means. And an output buffer for outputting.

The relationship of the fourth solving means to the third solving means is similar to the relationship of the second solving means to the first solving means. In the third solving means, it is possible to omit the defect information output terminal. That is, the expected value input terminal is also used as the output terminal of the defect information and the defect information signal. For this purpose, the number of judgment delay means is increased and an output buffer is added.

The following can be given as a fifth means for solving the problems. That is, in the third solving means or the fourth solving means, the selecting means outputs the failure information signal from the output data locking means and the failure time information signal from the measurement clock number output means. In this order, the defect information signal is arranged first and the defect time information signal is arranged later. The output order may be reversed, and the basic operation is the same.

As a sixth solution, a test circuit for a semiconductor integrated circuit according to the present invention is the test circuit according to any one of the above first to fifth solutions, in which the following constituent elements are further added. That is, an expected value delay means for delaying the expected value signal from the expected value input terminal, and a delay system comparison means for comparing the output data signal of the circuit under test and the delayed expected value signal by the expected value delay means. A delay system mismatch holding means for holding the mismatched state when the comparison result signals from the delay system comparing means indicate a mismatch, and is inserted between the mismatch holding means and the determination signal output terminal. A logical product means for outputting the logical product of the output signal of the mismatch holding means and the output signal of the delay system mismatch holding means to the judgment signal output terminal as the judgment signal.

This corresponds to the variation in the internal delay of the semiconductor integrated circuit. The comparison means compares the output data signal from the test target circuit and the expected value signal, but it is important that the timings of both are matched with high accuracy. However, the input timing of the expected value signal may not match the output data signal due to variations in the internal delay of the semiconductor integrated circuit. If it is left as it is, there is a possibility that a non-defective product may be erroneously determined as a defective product. Therefore, the expected value delay means, the delay system comparison means, and the delay system disagreement holding means are added. Further, a logical product means is added. With this configuration, when comparing the output data signal and the expected value signal, the timing can be slightly shifted and the comparison can be performed. Therefore, the accuracy of the match or mismatch judgment is high. As a result, it is possible to perform parallel comparison while absorbing variations in internal delay. Therefore, it is possible to eliminate the need to repeat the test for the same test target circuit in a state where the input timing is changed, and it is possible to shorten the inspection time.

As a seventh solving means, a test circuit for a semiconductor integrated circuit according to the present invention is the same as the sixth solving means, wherein the defect information output terminal is omitted.
The following components have been added. That is, when the judgment delay means for delaying the judgment signal output from the logical product means by a predetermined cycle and the expected value input terminal are connected, and the delay judgment signal from the judgment delay means indicates a match, a high impedance is output. The output buffer outputs the output signal from the output data lock means when the delay determination signals indicate a mismatch.

This makes it possible to omit the defect information output terminal, as described above. That is, the expected value input terminal is also used as the output terminal of the failure information signal. Since the expected value input terminal is also used as the output terminal of the failure information signal, a special output terminal for outputting the failure information signal is unnecessary.

As an eighth solution, a test circuit for a semiconductor integrated circuit according to the present invention is the same as the sixth solution, with the addition of the following components. That is, the first determination delay means for delaying the determination signal output from the AND means by a predetermined cycle and the second determination delay means for delaying the delay determination signal from the first determination delay means by a predetermined cycle.
Determination delay means, a clock measuring means for measuring a clock and holding the number of measurement clocks at the timing when the determination signal output from the mismatch holding means changes to mismatch, and the second determination delay means output. Measurement clock number output means for serially outputting the held measurement clock number at a predetermined interval when the second delay determination signal indicates a mismatch, and the second delay determination signal output by the second determination delay means. Are connected to the expected value input terminal, and selection means for selecting and outputting the output of the measurement clock number output means when they do not match, and Output a high impedance when the first delay determination signal output from the determination delay means of 1 indicates a match, and select the above when the first delay determination signal indicates a mismatch. Is an output buffer for outputting an output signal of the stage.

This is similar to the above, in addition to the defect information indicating whether the output data signal of the test target circuit is logically "0" or "1" at the time of the abnormal operation, the timing at which the abnormal operation occurs. Is output to the outside. Further, the defect information and the defect time information are externally output from the same output terminal. Not only the failure information but also the failure time information can be obtained, and the failure information output terminal for outputting the failure information signal is also used for the external output of the failure time information signal, which simplifies the circuit configuration. it can.

As a ninth solving means, a test circuit for a semiconductor integrated circuit according to the present invention is the above sixth to eighth solving means, wherein the expected value delay means, the delay system comparing means and the delay system do not match. A plurality of sets of holding means are provided, and the logical product means is configured to take a logical product of the mismatch holding means and the plurality of sets of delay system mismatch holding means.

This is because there are a plurality of sets of judgment delay means, delay system comparison means, and delay system disagreement holding means.
In other words, it is described from the comparison that there are three or more systems that hold disagreement. In contrast to the eighth solving means, it is described from the comparison that there are two systems for holding the mismatch. It is clarified that the number of lines need not be limited to two. The larger the number of systems, the greater the effect of absorbing the variation in internal delay, and the more accurate the test based on the comparison judgment becomes.

As a tenth solving means, a test circuit for a semiconductor integrated circuit according to the present invention is characterized in that, in the above first to ninth solving means, respective output signals of the mismatch holding means and the delay system mismatch holding means are outputted. It is provided with an output terminal group for individually outputting to the outside.

In this case, determination signals of a plurality of phases can be acquired from the output terminal group and can be used as an index for timing adjustment. Then, it can be adjusted so that the non-defective product can be determined regardless of whether the input timing of the expected value signal is earlier or later.

As an eleventh solving means, in the test circuit for a semiconductor integrated circuit according to the present invention, in addition to the above first to tenth solving means, the judgment signals output to the judgment signal output terminals show a mismatch. At this time, the clock control means for stopping the supply clock to the circuit under test is provided.

According to this, at the timing when the output data signal does not match the expected value signal, the clock supply to the circuit under test can be stopped, and the switching operation of the mounted transistor can be internally stopped forcibly. Therefore, it is not necessary to cut off the clock supply by observing the timing of the mismatch by an external operation, and the defective portion can be specified while maintaining the state where the mismatch occurs in the test. For example, a defective portion can be analyzed by using a light emission phenomenon corresponding to the amount of current using a test pattern.

As a twelfth solving means, a test circuit for a semiconductor integrated circuit according to the present invention is the same as the above first to eleventh solving means, further configured as follows. That is, the test target circuit outputs the output data signal in a plurality of bits, and the expected value input terminal, the comparing means, the mismatch holding means, the determination signal output terminal, the output data locking means, and the failure information. A plurality of sets of output terminals are provided according to the number of bits of the output data signal, and the logical sum of the outputs of the plurality of mismatch holding means is used as the determination signal.

According to this, for a plurality of multi-bit output data signals of the circuit under test, the multi-bit failure information at the time of failure is held while internally comparing the output data signal and the expected value signal. Therefore, the failure analysis can be advantageously developed.

[0035]

(First Embodiment) FIG. 1 is a circuit diagram showing a structure of a test circuit of a semiconductor integrated circuit according to a first embodiment of the present invention.

Output data signal A from the circuit under test 1
And the expected value signal B from the expected value input terminal 2 are inputted to the comparison means 3 which is an exclusive OR gate. The comparison means 3 compares the output data signal A output from the test target circuit 1 with the corresponding expected value signal B, and outputs “0” as the comparison result signal C when they match and when they do not match. "1" is output as the comparison result signal C. The comparison result signal C from the comparison means 3 is input to the mismatch holding means M1. The mismatch holding means M1 is composed of an OR gate 4 and a flip-flop 5 with reset. The output of the comparator 3 and the output of the flip-flop 5 are input to the input side of the OR gate 4, and the output of the OR gate 4 is connected to the data input (D) of the flip-flop. The flip-flop 5 receives the data from the OR gate 4 every cycle of the test pattern, that is, the clock CLK.
_It is updated and stored for each rising edge of ₀ , and
When the comparison result signal C is "1" that does not match, once the "1" is held, it has a function of holding it until it is reset. The determination signal D output from the mismatch holding means M1 is output to the determination signal output terminal 6 and is also supplied to the output data locking means M2. The determination signal D indicates whether the test target circuit 1 is a good product or a defective product.

Output data signal A from the circuit under test 1
Is also supplied to the output data lock means M2. The output data lock means M2 is composed of an AND gate 7 and a flip-flop 8. The determination signal D output from the mismatch holding means M1 is logically inverted and input to one input of the AND gate 7. The output data signal A from the test target circuit 1 is the data input (D) of the flip-flop 8.
, And the data output (Q) is connected to the defect information output terminal 9. The AND gate 7 connected to the clock input (CLK) of the flip-flop 8 opens the gate when the decision signal D is “0”, that is, when the output data signal A of the test target circuit 1 matches the expected value signal B. In this state, the output data signal A is output in synchronization with the clock CLK ₀ . Further, when the determination signal D is "1", that is, when the output data signal A of the test target circuit 1 does not match the expected value signal B, the output data signal becomes non-conductive, and the output data signal at the timing when the mismatched state occurs. Hold A,
After that, the defect information signal E indicating the defect is output.

The operation of the test circuit of the semiconductor integrated circuit of the present embodiment configured as above will be described below. The clock CLK ₀ is the circuit under test (semiconductor integrated circuit)
1 and the test circuit concerned are commonly supplied.

When the circuit under test 1 is reset, the flip-flop 5 of the mismatch holding means M1 receives a reset signal (not shown) at its reset terminal and is initialized to logic "0". The output data signal A output from the test target circuit 1 and the expected value signal B input from the expected value input terminal 2 are compared by the comparison means 3, and the comparison result signal C is input to the OR gate 4. The comparison result signal C of the comparison means 3 and the output of the flip-flop 5 are input to the logical sum gate 4 and logically summed. The logical sum output of the logical sum gate 4 is input to the flip-flop 5. The flip-flop 5 stores the output of the OR gate 4 at the rising timing of the clock CLK ₀ .

<In the case of non-defective product> The output data signal A output from the circuit under test 1 is normal in all cycles of the test pattern, and the output data signal A is the expected value signal B input from the expected value input terminal 2. When they match, the comparison result signal C by the comparison means 3 is logic "0", and the determination signal D which is the output of the flip-flop 5 of the mismatch holding means M1 remains logic "0". When the output data signal A continues to be in the normal state, the judgment signal output terminal 6 continues to output the judgment signal D of logic "0" until the end of the test. External L
The SI tester observes the output of the logic "0" from the determination signal output terminal 6 and determines that it is a good product. When the determination signal D is "0", the AND gate 7 of the output data locking means M2 for inputting "1" of the logical inversion is the gate to open in synchronization normal output data signal A to the clock CLK ₀ The defect information output terminal 9 sequentially outputs to the outside.

<< In case of defective product >> The output data signal A is defective at a certain cycle of the test pattern, and the comparing means 3
When the output data signal A and the expected value signal B show a mismatch, the comparison result signal C of the comparison means 3 switches from "0" to "1". Flip-flop 5 of the mismatch holding means M1
Represents the logic "1" from the OR gate 4 as the clock CLK ₀
Hold in sync with the rising edge of. Flip flop 5
Since the output of is fed back to the input of OR gate 4,
Once the flip-flop 5 holds "1", it keeps holding and outputting "1" even if the comparison result signal C becomes "0" thereafter. It lasts until it is reset.

Flip-flop 5 of the mismatch holding means M1
When the decision signal D output by the switch is switched to "1", the output data lock means M for inputting "0" of its logical inversion
The AND gate 7 of 2 switches to the gate closed state, the flip-flop 8 holds the output data signal A at the time when the defect occurs, and thereafter, the defect information signal E indicating the defect is transmitted to the defect information output terminal 9 Output from. An external LSI tester observes the judgment signal D of logic "1" from the judgment signal output terminal 6 to judge that it is a defective product, and at the same time, uses the failure information signal E output from the failure information output terminal 9 as failure analysis information. use. The failure information signal E output when the determination signal D is "1" indicates the logic ("0" or "1") when the test target circuit 1 causes a failure. In addition, when the flip-flop 5 is reset,
The AND gate 7 restarts the gate opening.

As described above, according to the present embodiment, the test target circuit 1 at the timing when the abnormal operation occurs
Of the output data signal A of "0" at that time
It is possible to store and externally output the defect information indicating whether it is "1" or "1" while internally comparing the output data signal and the expected value signal. Since the information used for this failure analysis is retained after the mismatch, it can be externally observed even during the high speed test without being affected by the board capacitance.

(Second Embodiment) FIG. 2 is a circuit diagram showing a structure of a test circuit of a semiconductor integrated circuit according to a second embodiment of the present invention. The same components as those in FIG. 1 in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

The test target circuit 1 outputs 2-bit output data signals A1 and A2. Correspondingly, two comparators 3a and 3b are provided, two OR gates 4a and 4b in the mismatch holding means M1 and two reset flip-flops 5a and 5b are provided, respectively. Has been.
Further, two AND gates 7a and 7b are provided as the AND gate 7 in the output data lock means M2, and the flip-flop 8
Are provided respectively as 8a and 8b.

The comparison means 3a in which the 2-bit output data signals A1 and A2 from the test target circuit 1 and the 2-bit expected value signals B1 and B1 from the expected value input terminals 2a and 2b are exclusive OR gates, respectively. , 3b. The comparing means 3a compares the output data signal A1 of the first bit output from the circuit under test 1 with the expected value signal B1 corresponding to the output data signal A1, and when they match, the comparison result signal C1.
"0" is output as the comparison result signal C
"1" is output as 1. The comparison means 3b outputs the output data signal A2 of the second bit and the expected value signal B corresponding thereto.
2 is compared, and when they match, "0" is output as the comparison result signal C2, and when they do not match, "1" is output as the comparison result signal C2. The comparison result signals C1 and C2 from the comparing means 3a and 3b are input to the mismatch holding means M1, respectively.

The mismatch holding means M1 is a combination of an OR gate 4a and a flip-flop 5a with reset, and a combination of an OR gate 4b and a flip-flop 5b with reset, which have the same relationship as in FIG. 1 in the first embodiment. , And an OR gate 10. The OR gate 10 includes both flip-flops 5a and 5b.
Output the output signals D1 and D2, and outputs the logical sum as the determination signal D to the determination signal output terminal 6 and the output data lock means M2.

The output data locking means M2 is composed of a combination of a logical product gate 7a and a flip-flop 8a and a combination of a logical product gate 7b and a flip-flop 8b which have the same relationship as in FIG. 1 in the first embodiment. ing. The 2-bit output data signals A1 and A2 from the circuit under test 1 are flip-flops 8 respectively.
a and 8b are connected to the data inputs (D), and the respective data outputs (Q) are connected to the defect information output terminals 9a and 9b. The AND gates 7a and 7b connected to the clock inputs (CLK) of the flip-flops 8a and 8b have the expected data signals A1 and A2 output from the test target circuit 1 when the decision signal D is "0". When the state coincides with B1, the gate is open, and at this time, the flip-flops 8a and 8b respectively output the output data signal A.
1 and A2 are output in synchronization with the clock CLK ₀ . Further, when the determination signal D is "1", that is, when at least one of the output data signals A1 and A2 of the test target circuit 1 does not match the expected value signals B1 and B1, the AND gates 7a and 7b are in the non-conducting states. It becomes conductive, and the flip-flops 8a and 8b hold the output data signals A1 and A2 at the time when the mismatched state occurs, and thereafter output the failure information signals E1 and E2 indicating the failure.

The operation of the test circuit of the semiconductor integrated circuit of the present embodiment configured as above will be described below.

<< Good Product >> Both the 2-bit output data signals A1 and A2 output from the test target circuit 1 are normal, and the output data signals A1 and A2 are input from the expected value input terminals 2a and 2b, respectively. Expected value signal B1, B2
If they match, the comparison result signals C1 and C2 by the comparison means 3a and 3b are both logic "0", and the output signals D1 and D2 of the flip-flops 5a and 5b are also logic "0". As a result, the decision signal D output from the OR gate 10 remains the logic "0". When the output data signals A1 and A2 continue to be in the normal state, the determination signal output terminal 6 continues to output the determination signal D of logic "0" until the end of the test. An external LSI tester observes the output of the logic "0" from the determination signal output terminal 6 and determines that it is a good product. When the decision signal D is "0", the AND gates 7a and 7b of the output data lock means M2 which inputs "1" of its logical inversion are gate open, and the normal output data signals A1 and A2 are supplied to the clock CLK _0. The defect information output terminal 9
It is sequentially output from a and 9b.

<< In case of defective product >> Output data signals A1, A
If at least one of the two 2 is defective and at least one of the flip-flops 5a and 5b outputs the logic "1", the determination signal D output from the OR gate 10 changes from the logic "0" to the logic "0". Invert to "1". That is, the judgment signal output terminal 6 continues to output the judgment signal D of logic "1" until the test ends after either of the two flip-flops 5a and 5b first holds the mismatch. When the determination signal D is switched to "1", the AND gates 7a and 7b of the output data lock means M2 which inputs "0" of its logical inversion are switched to the gate closed state, and the defect is generated. Output data signal A
1 and A2 are held, and thereafter, defect information signals E1 and E2 indicating the defect are output to the defect information output terminals 9a and 9b, respectively.
Output from. An external LSI tester observes the judgment signal D of logic "1" from the judgment signal output terminal 6 to judge that it is a defective product, and at the same time, judges the defect information signals E1 and E2 output from the defect information output terminals 9a and 9b to be defective. Used as information for analysis. When the flip-flops 5a and 5b are reset, the AND gates 7a and 7b restart the gate opening.

In the above, the output of the circuit under test 1 is set to 2 bits, but it can be applied to the case of 3 bits or more. In that case, the number of the comparison means 3, the OR gate 4 and the flip-flop 5 which constitute the mismatch holding means M1.
, And the number of AND gates 7 and flip-flops 8 forming the output data lock means M2 are set to a number corresponding to the number of output bits of the circuit under test 1.

(Embodiment 3) Embodiment 3 of the present invention
Omits a dedicated output terminal for external output of the defect information signal. That is, the input terminal of the expected value signal is also used as the output terminal of the defect information signal.
Defect information output terminal 9 in FIG. 1 in the case of the first embodiment
However, the defect information signal E is externally output from the expected value input terminal 2 in FIG. The dual-purpose terminal is the input / output terminal 2A for outputting expected value input failure information.

FIG. 3 is a circuit diagram showing the structure of the test circuit of the semiconductor integrated circuit according to the third embodiment of the present invention. The same components as those in FIG. 1 in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. In FIG. 3, reference numeral 11 is a judgment delay means for delaying the judgment signal D output from the flip-flop 5 in the mismatch holding means M1 by a predetermined cycle (here, four cycles) and outputting it as a delay judgment signal F. 2A
Is an input / output terminal for inputting the expected value signal B and outputting the defect information signal E for outputting the expected value input defect information. 1
Reference numeral 2 is an output buffer configured as a tri-state buffer, the input terminal of which is connected to the defect information signal E from the flip-flop 8 in the output data lock means M2, and the output terminal of which is the expected value input defect information output. The input / output terminal 2A is connected, and the delay determination signal F from the determination delay means 11 is input to its control terminal.

The function of the output buffer 12 is as follows. When the output data signal A continues to match the expected value signal B, the decision signal D is logic "0", and as a result, the delay decision signal F is "0", the output buffer Reference numeral 12 outputs a high impedance and blocks the defect information signal E from the output data lock means M2 to the input / output terminal 2A. The output data signal A and the expected value signal B indicate disagreement, the judgment signal D is switched from "0" to "1", the state continues to some extent, and the delay judgment signal F is also switched from "0" to "1". Then, the output buffer 12 becomes conductive and outputs the defect information signal E from the output data lock means M2 to the input / output terminal 2A. At the input / output terminal 2A, the output data signal A and the expected value signal B
The input of the expected value signal B is stopped during the period from the time when and indicate that they do not match until the delay time in the determination delay means 11 elapses. This is done by an instruction from the LSI tester. The judgment delay means 11 is composed of four flip-flops and has a delay time of four clocks of the clock CLK ₀ . Since other configurations are similar to those of the first embodiment shown in FIG. 1, the same parts are allotted with the same reference numerals and the description thereof will be omitted.

The operation of the test circuit of the semiconductor integrated circuit of the present embodiment configured as described above will be described below.

<In the case of non-defective product> The output data signal A output from the circuit under test 1 is normal in all cycles of the test pattern, and the expected value signal input from the input / output terminal 2A of the expected value input failure information output. B and the output data signal A match. In this case, the comparison result signal C by the comparison means 3 is logic "0", and the determination signal D which is the output of the flip-flop 5 of the mismatch holding means M1 is logic "0".
It remains. When the output data signal A continues to be in the normal state, the judgment signal output terminal 6 continues to output the judgment signal D of logic "0" until the end of the test. An external LSI tester observes the output of the logic "0" from the determination signal output terminal 6 and determines that it is a good product. When the judgment signal D is "0", the logical product gate 7 of the output data lock means M2 for inputting the logically inverted "1" is gate open, and the normal output data signal A
Are sequentially output in synchronization with the clock CLK ₀ . Also,
When the output data signal A continues to be in the normal state, the delay judgment signal F outputted from the judgment delay means 11 continues to output logic "0", the output buffer 12 always outputs high impedance, and the output data lock means M2 The output terminal of the flip-flop 8 is separated from the input / output terminal 2A, and the input of the expected value signal B to the input / output terminal 2A is not disturbed.

<< In case of defective product >> The output data signal A is defective at a certain cycle of the test pattern, and the comparing means 3
When the output data signal A and the expected value signal B show a mismatch, the comparison result signal C of the comparison means 3 switches from "0" to "1". Flip-flop 5 of the mismatch holding means M1
Is switched to “1” in synchronization with the rising edge of the clock CLK ₀ and holds “1”. That is, the determination signal D is inverted from the logic "0" to the logic "1". Judgment signal D
Is switched to "1", the logical product gate 7 of the output data lock means M2 which inputs "0" of its logical inversion is switched to the gate closed state, and the flip-flop 8 outputs the output data at the time when the defect occurs. The signal A is held. The data holding state in the flip-flop 8 continues until the flip-flop 5 with reset in the mismatch holding means M1 is reset.

The external LSI tester observing the state of the judgment signal output terminal 6 judges the defective product by switching from the logic "0" to the logic "1" and expects from the input / output terminal 2A. The input of the value signal B is stopped.

The decision delay means 11 outputs a decision signal D of "0".
The delay determination signal F is inverted from the logic "0" to the logic "1" with a delay of four cycles from the time when the switch from "1" to "1". When the delay judgment signal F is inverted to "1", the output buffer 12 is switched from the high impedance state to the conduction state, and the defect information signal from the flip-flop 8 of the output data lock means M2 which has been already in the output lock state. E is output from the input / output terminal 2A through the output buffer 12. At this time, the input of the expected value signal B has already been stopped at the input / output terminal 2A, and there is no hindrance to the external output of the defect information signal E from the input / output terminal 2A.

As described above, in the external LSI tester, the judgment signal D of logic "1" from the judgment signal output terminal 6 is outputted.
I / O terminal 2A
The failure information signal E output from is used as information for failure analysis. The failure information signal E output when the determination signal D is “1” is the logic (“0” or “1”) of the output data signal A of the test target circuit 1 when the test target circuit 1 causes a failure. ) Is shown.

In the present embodiment, the judgment delay means 1
Although 1 is delayed by 4 cycles, the delay time may be set appropriately according to the conditions. The external LSI tester may require a larger number of clocks depending on the accuracy.

As described above, according to the present embodiment, the terminal for inputting the expected value signal B is also used as the terminal for outputting the defect information signal E after the judgment signal D outputs the defective state. . It is the output buffer 12 and the judgment delay means 11 that realize this dual use. Due to this dual use, a dedicated output terminal for outputting the defect information signal E (corresponding to the defect information output terminal 9 in FIG. 1 in the case of the first embodiment) can be omitted.

(Fourth Embodiment) FIG. 4 is a circuit diagram showing a structure of a test circuit of a semiconductor integrated circuit according to a fourth embodiment of the present invention. The same components as those in FIG. 3 in the case of the third embodiment are assigned the same reference numerals and explanations thereof will be omitted. The present embodiment not only externally outputs a failure information signal indicating whether the output data signal of the test target circuit is logically "0" or "1" at the time of abnormal operation, but also which abnormal operation has occurred. The defective time information signal indicating the timing is also externally output. Then, the defect information signal and the defect time information signal are time-divided and externally output from the expected value signal input terminal (input / output terminal 2A).

In FIG. 4, reference numeral 21 has the same structure as the judgment delay means 11 in FIG. 3 in the third embodiment, and the flip-flop 5 in the mismatch holding means M1.
The first delay determination signal F is obtained by delaying the determination signal D output by the first delay determination signal D by a predetermined cycle (here, four cycles).
The second determination delay means 22 further delays the first delay determination signal F output from the first determination delay means 21 by a predetermined period (here, four cycles) and outputs it as the second delay determination signal G. Is a determination delay means.

M3 is a clock measuring means for measuring the clock CLK ₀ and holding the number N (D1) of measured clocks when the determination signal D output from the non-coincidence holding means M1 is switched to "1" for non-coincidence. It is composed of a logical product gate 23, a flip-flop with reset 24, and an incrementer 25. A clock CL is applied to the AND gate 23.
The logic inversion of the determination signal D is input as well as K ₀ is input. The output of the AND gate 23 is connected to the clock input (CLK) of the flip-flop 24.
The data output terminal (Q) of the flip-flop 24 is connected to the input terminal of the incrementer 25, and the output terminal of the incrementer 25 is connected to the data input terminal (D) of the flip-flop 24. The flip-flop 24 outputs multivalued measurement clock count data Hp.

M4 is a measurement clock number output means. The data output terminal (Q) of the flip-flop 24 in the clock measuring means M3 is connected to the input terminal of the measurement clock number output means M4, and the multivalued measurement clock number data Hp is input. The measurement clock number output means M4 inputs the measurement clock number data Hp, the clock CLK _0, and the second delay determination signal G from the second determination delay means 22, and the second delay determination signal G becomes “1”. When switched, the multi-valued measured clock count data Hp is converted into parallel / serial in synchronization with the clock CLK ₀ .
The converted serial measurement clock number signal Hs is output.
Specifically, the measurement clock number output means M4 divides the clock CLK ₀ by four and divides the n-bit data (n is 32, for example) into 1 by using the output of the quarter circuit as a clock.
It is composed of two PS conversion circuits that perform parallel / serial conversion into bit data.

Reference numeral 26 receives the defect information signal E output from the output data lock means M2 and the serial measurement clock number signal Hs output from the measurement clock number output means M4, and the second determination delay means 22 outputs the second signal. It is a selection unit such as a multiplexer that selects and outputs one of them according to the logical value of the delay determination signal G of 2. Specifically, when the second delay judgment signal G is logic "0", the defect information signal E is selected, and when it is logic "1", the serial measurement clock number signal Hs is selected.

The operation of the test circuit of the semiconductor integrated circuit of the present embodiment configured as described above will be described below.

When the circuit under test 1 is reset, the flip-flop 5 in the mismatch holding means M1 is initialized to logic "0", and at the same time, the clock measuring means M3.
The flip-flop 24 in is also initialized, and counting of the n-bit measurement clock number data Hp from "0" is started.

The operation in the case of a non-defective product is the same as in the case of the third embodiment, and the description thereof will be omitted.

<< In case of defective product >> The output data signal A is defective in a certain cycle of the test pattern, and the comparing means 3
When the output data signal A and the expected value signal B show a mismatch, the comparison result signal C of the comparison means 3 switches from "0" to "1". Flip-flop 5 of the mismatch holding means M1
Is inverted from logic "0" to logic "1", and this decision signal D is output to the first decision delay means 21, output data lock means M2, and clock measurement means M3. As a result, the logical product gate 7 of the output data lock means M2 for inputting "0" of the logical inversion of the determination signal D is switched to the gate closed state, and the flip-flop 8 outputs the output data signal A at the time when the defect occurs. Hold. Further, the AND gate 23 of the clock measuring means M3 is also switched to the gate closed state, the flip-flop 24 stops counting the number of clocks from the start of the test to the time of occurrence of the defect, and the count value at that time, that is, n-bit measurement The value of the clock number data Hp is held. The data holding states of these flip-flops 8 and 24 are the same as those of the flip-flop 5 with reset in the mismatch holding means M1.
Continues until is reset.

The external LSI tester observing the state of the determination signal output terminal 6 determines that it is a defective product by switching from the logic "0" to the logic "1" and expects from the input / output terminal 2A. The input of the value signal B is stopped.

The first judgment delay means 21 delays the first delay judgment signal F from the logic "0" to the logic 4 cycles after the judgment signal D is switched from "0" to "1". It is inverted to "1" and output to the control terminal of the output buffer 12 and the second determination delay means 22. When the first delay determination signal F is inverted to "1", the output buffer 12 is switched from the high impedance state to the conductive state. At this time, since the second delay judgment signal G given to the control terminal of the selection means 26 by the second judgment delay means 22 is still logic "0", the selection means 26 is defective from the output data lock means M2. In this state, the information signal E is selected. The defect information signal E passes through the output buffer 12 and the input / output terminal 2
It is output from A. At this time, the input of the expected value signal B has already been stopped at the input / output terminal 2A,
There is no problem with the external output of the defect information signal E from A.

Next, when the time corresponding to four cycles which is the delay time of the second judgment delay means 22 has elapsed, the second judgment delay means 22 outputs the second delay judgment signal G output by the second judgment delay means 22 to the logic "0". From "" to logic "1". Along with this, the measurement clock number output means M4 is activated and the operation of parallel / serial conversion of the multivalued measurement clock number data Hp already locked by the clock measurement means M3 into the serial measurement clock number signal Hs is started. To do. Further, the selection means 26 is switched to a state of selecting the serial measurement clock number signal Hs from the measurement clock number output means M4, and the serial measurement clock number signal Hs is output from the input / output terminal 2A through the output buffer 12. To be done.

That is, when a mismatch between the output data signal A and the expected value signal B is detected, the logical value of the output data signal A at that time point is locked by the output data locking means M2 and the time information at that time point is obtained. Is locked in the clock measuring means M3, the input of the expected value signal B from the input / output terminal 2A is stopped, and after a lapse of a predetermined time, the defect information signal E is externally output from the input / output terminal 2A, and further the lapse of a predetermined time. After that, the serial measurement clock number signal Hs is externally output from the input / output terminal 2A.

Measured clock count data Hp from LSB to M
In the case of n = 32, conversion to the serial measurement clock number signal Hs up to SB requires a total of 128 (32 × 4) clocks in a cycle of 4 clocks of the clock CLK ₀ . The serial measurement clock number signal Hs is externally output from the input / output terminal 2A over this time.

That is, 4 after the decision signal D is logically inverted.
The output buffer 12 is enabled after the clock, and at the same time, the failure information signal E is output from the input / output terminal 2A, and four clocks later, the serial measurement clock number indicating the cycle causing the failure from the measurement clock number output means M4 at four clock intervals. The signal Hs is output serially. In addition,
In the present embodiment, the configuration is such that the output is performed at 4 clock intervals, but the cycle is not limited to this.

As described above, in the external LSI tester, the judgment signal D of logic "1" from the judgment signal output terminal 6 is outputted.
I / O terminal 2A
The failure information signal E output from is used as information for failure analysis. The failure information signal E output when the determination signal D is "1" indicates the logic ("0" or "1") when the test target circuit 1 causes a failure.

In the present embodiment, the judgment delay means 1
Although 1 is delayed by 4 cycles, the delay time may be set appropriately according to the conditions. The external LSI tester may require a larger number of clocks depending on the accuracy.

As described above, according to the present embodiment, the test target circuit 1 at the timing when the abnormal operation occurs
Of the output data signal A of “0” or “1”, and the defect time information of when the corresponding cycle is when can be output in a time division manner, so that the defect analysis can be performed more effectively. And test patterns can be debugged.

Contrary to the above description, the selecting means 26 selects the serial measurement clock number signal Hs when the second delay judgment signal G is logic "0", and when it is logic "1". The defect information signal E may be selected. In this case, the serial measurement clock number signal Hs is first output from the input / output terminal 2A, and then the defect information signal E is output.

(Embodiment 5) Embodiment 5 of the present invention
Is to absorb the time variation of the expected value signal.

FIG. 5 is a circuit diagram showing the structure of the test circuit of the semiconductor integrated circuit according to the fifth embodiment of the present invention. The same components as those in FIG. 1 in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 5, 27a is a first expected value delay means for delaying the expected value signal B from the input / output terminal 2A,
27b is a second expected value delay means for further delaying the _first expected value delay signal B ₁ by the first expected value delay means 27a. The first expected value delay means 27a and the second expected value delay means 27b have the same configuration. Therefore, the respective delay times τ1 and τ2 are the same. These can be configured by connecting a predetermined number of buffers in series, for example. Further, for example, a configuration may be used in which a flip-flop that inputs the clock CLK ₀ to the clock input (CLK) delays for one cycle. However, τ1 ≠ τ2 does not matter.

28a is the output data from the circuit under test 1.
Signal A and first expected value delayed signal B ₁First to compare with
Of the delay system of FIG.
Output data signal A and second expected value delayed signal B₂Compare with
This is a second delay system comparison means.

M5a is a first delay system disagreement holding means for holding the disagreement state when the first comparison result signal C ₁ from the first delay system comparison means 28a is "1" indicating a disagreement, M5b is a second delay based mismatch holding means for holding the mismatch state when the second comparison result signal C ₂ of from comparison means 28b of the second delay system indicating the disagreement "1".

The structure of the mismatch holding means M5a, M5b of the first and second delay systems is the same as that of the mismatch holding means M1. 29a and 29b are OR gates, 30
Reference numerals a and 30b are flip-flops with reset. The output terminals of the mismatch holding means M1 and the mismatch holding means M5a, M5b of the first and second delay systems are connected to the input terminal of the AND gate (logical product means) 31. Although the determination signal D is output from the output terminal of the AND gate 31,
The output terminal of the AND gate 31 is the judgment signal output terminal 6
And is supplied to the output data lock means M2 and the judgment delay means 11.

In comparison between the output data signal A output from the circuit under test 1 and the expected value signal B, if the expected value signal has a temporal variation (jitter), the decision signal D becomes inaccurate. In the present embodiment, the comparison means 3 not only compares the expected value signal B input from the input / output terminal 2A with the output data signal A, but also the first and second expected value delay means 27a and 27b perform one step. And the output data signal A is compared with each of the first and second expected value delayed signals B ₁ and B ₂ delayed in two stages, and the decision signal D is generated by the sum of these three comparison results. ing.

That is, when the comparison result signal C is inverted to "1", the output signal D ₀ of the mismatch holding means M1 is "1".
Is held in reverse. Further, when the first comparison result signal C ₁ is inverted to "1", the output signal D ₁ of the first delay system mismatch holding means M5a is inverted and held to "1". When the second comparison result signal C ₂ is inverted to "1", the output signal D ₂ of the second delay system mismatch holding means M5b is inverted and held at "1". These three comparison result signals C, C ₁ , C ₂ are all inverted from “0” to “1”, and as a result, the three output signals D ₀ , D ₁ , D ₂ are all “1”. Only occasionally, the decision signal D output from the AND gate 31 is inverted to "1". At other times, the determination signal D remains "0".

The operation of the test circuit of the semiconductor integrated circuit of the present embodiment having the above configuration will be described below.

<< In the case of non-defective product >> The output data signal A output from the test target circuit 1 is 3 of the comparing means 3 and the comparing means 28a of the first delay system and the comparing means 28b of the second delay system.
Where the expected value signal B, the first expected value delayed signal B ₁ and the second
Are compared by the expected delay signal B ₂ . If the circuit under test 1 is normal, even if there is timing variation in the expected value signal B that is input, it will match at least at one location. That is, at least one of the comparison result signal C, the first comparison result signal C ₁ , and the second comparison result signal C ₂ maintains “0”. As a result, the mismatch holding means M
1 output signal D ₀ , first delay system mismatch holding means M5
a output signal D ₁ of the second delay system disagreement holding means M5
Any one of the output signals D ₂ of b maintains "0".
Therefore, the decision signal D which is the output of the AND gate 31
Keeps "0", and this outputs the judgment signal D indicating normality from the judgment signal output terminal 6 to the external LSI tester.

<< In Case of Defective Product >> If an abnormality has occurred in the test target circuit 1, and if there is timing variation in the expected value signal B to be input, there will be a mismatch at all three comparison points. That is, all of the comparison result signal C, the first comparison result signal C ₁ , and the second comparison result signal C ₂ are inverted to “1”. As a result, the output signal D ₀ mismatch holding means M1, the output signal D ₁ of the mismatch holding means M5a of the first delay system, none of the output signal D ₂ mismatches holding means M5b of the second delay system "1 "And the AND gate 3
The determination signal D, which is the output of 1, is also inverted to "1". The determination signal output terminal 6 outputs a determination signal D indicating an abnormality to an external LSI tester.

In the external LSI tester, the logic "1" of the determination signal D output from the determination signal output terminal 6 determines that the product is defective, and the input of the expected value signal B from the input / output terminal 2A is stopped. Further, the determination signal D is "1"
The logic value of the output data signal A is held in the output data lock means M2 at the timing of switching to the defect information signal E.
Is output as. Then, when the delay judgment signal F output from the judgment delay means 11 switches to "1" after a predetermined time delay, the output buffer 12 switches from the high impedance state to the conducting state, and the held defect information signal E is held.
Is output from the input / output terminal 2A to the external LSI tester through the output buffer 12.

In this embodiment, two delay system blocks for absorbing the delay variation of the expected value signal B are used, but the number may be one or three or more.

As described above, according to the present embodiment, the output data signal of the test target circuit 1 is composed of the input expected value signal and one or more expected value signals delayed by a specified time interval. Since A can be compared in parallel, an appropriate test can be performed without being affected by variations in the internal delay of the test target circuit 1, and the inspection time can be shortened as compared with the conventional technique.

(Modified Embodiment) (1) As shown in FIG. 6, output terminals of the mismatch holding means M1, the first delay system mismatch holding means M5a, and the second delay system mismatch holding means M5b, respectively. External output terminal 32
It may be configured to connect a, 32b, and 32c and used as an index for timing adjustment. With this configuration, with respect to the timing of inputting the expected value signal B from the input / output terminal 2A using the non-defective sample, the comparison means 2 of the first delay system
8a and the first delay system non-coincidence holding means M5a can be adjusted to a timing at which a non-defective product is determined. That is, it is possible to perform adjustment so that the non-defective product can be determined regardless of whether the timing is earlier or later.

(2) As shown in FIG. 7, the system for supplying the clock CLK ₀ to the circuit under test 1 may be arranged to interpose the clock control means M6 for stopping the clock supply at the time of mismatch. Specifically, the AND gate 33 is interposed, and the AND gate 33 is controlled by the logical inversion of the determination signal D. That is, when a mismatch occurs between the output data signal A and the expected value signal B and the determination signal D is inverted to “1”, the supply of the clock CLK ₀ to the test target circuit 1 is stopped. When they do not match, the switching operation of the mounted transistor is stopped, and the defective portion can be analyzed by using the light emission phenomenon according to the current amount using the test pattern.

Although FIG. 7 corresponds to the case of the first embodiment with the addition of the clock control means M6 to FIG. 1, the same thing may be applied to other embodiments.

(3) The second embodiment shown in FIG. 2 is based on the fact that the test target circuit 1 outputs the output data signal A of a plurality of bits. This concept is the same as the third embodiment shown in FIG. 4 may be applied to the fourth embodiment shown in FIG. 4, the fifth embodiment shown in FIG. 5, and further modified embodiments thereof.

(4) The fourth embodiment shown in FIG. 4 is different from the third embodiment shown in FIG. 3 in clock measuring means M.
3 and measurement clock number output means M4 is added to output the defective time information to the outside, but ignoring that the serial measurement clock number signal Hs is output from the input / output terminal 2A, The concept may be applied to other embodiments. In that case, the measurement clock number output means M4 may be omitted and a plurality of terminals for outputting the measurement clock number data Hp may be provided. Further, the output data lock means M2 and the selection means 26 may be omitted and a terminal for externally outputting the serial measurement clock number signal Hs may be provided. Embodiments of these modifications are shown in FIGS. 8 and 9. In FIG. 8, 34 is an external output terminal for externally outputting the serial measurement clock number signal Hs from the measurement clock number output means M4, and in FIG. 9, 35 is the defect information signal E from the selection means 26 or the serial measurement clock number. Signal H
It is an external output terminal for externally outputting s. Although not shown, the failure information signal E may be output from the input / output terminal 2A via the output buffer 12, while the serial measurement clock number signal Hs may be output from a dedicated external output terminal. On the contrary, the serial measurement clock number signal Hs is output via the output buffer 12 to the input / output terminal 2A.
Alternatively, the defect information signal E may be output from a dedicated external output terminal.

(5) As a modification of the fifth embodiment shown in FIG. 5, a defect information output terminal 9 dedicated to external output of the defect information signal E may be provided as shown in FIG. In this case, the decision delay means 11 and the output buffer 12 in FIG. 5 are omitted, and the input terminal of the expected value signal B becomes the expected value input terminal 2 for input only. Although not shown, the configuration including the delay system comparing means and the mismatch holding means shown in FIG. 5 may be applied to a mode having the clock measuring means M3 and the measured clock number output means M4 as shown in FIG.

[0103]

As described above, according to the present invention, the following effects are exhibited.

(1) The failure information used for failure analysis of whether the output data signal of the test target circuit is logically "0" or "1" in the abnormal operation cycle is held while internally comparing the expected value. be able to. Since the defect information is retained once the abnormal operation is detected, it can be externally observed even during the high speed test without being affected by the board capacity.

(2) Further, if the judgment delay means and the output buffer are provided so that the defect information signal is output from the terminal for inputting the expected value signal, a dedicated terminal for externally outputting the defect information signal is provided. Since it is not necessary to provide the device, it contributes to downsizing and cost reduction of the semiconductor integrated circuit.

(3) Further, in addition to the defect information at the time of abnormal operation, when the defect time information indicating at which timing the abnormal operation occurs is output to the outside, more detailed defect analysis can be performed.

Particularly, if the defect information and the defect time information are externally output from the same output terminal, the circuit structure can be simplified.

Further, if the first and second judgment delay means and the output buffer are added, the defect information and the defect time information can be output from the expected value input terminal to the outside in a time division manner, and the number of terminals is limited. You can get more information at. That is, defect analysis and test development can be performed more effectively.

(4) If the expected value delay means for delaying the expected value signal by a predetermined unit time, the mismatch holding means of the delay system and the logical product means are added, the timing is positively changed and the output data signal is compared in parallel. Therefore, the test can be performed without being affected by the variation in the internal delay of the semiconductor integrated circuit, and the repetitive test can be omitted to shorten the inspection time.

(5) Further, when the judgment signal from the mismatch holding means indicates a mismatch, if the clock supply to the circuit under test is stopped based on the judgment signal, the switching operation of the mounted transistor is internally forced. It can be stopped. Therefore, it is not necessary to cut off the clock supply by observing the timing of mismatch by an external operation,
It is possible to specify the defective portion while maintaining the state in which the mismatch occurs in the test.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a test circuit of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a test circuit of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a test circuit of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a test circuit of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a test circuit of a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a test circuit of the semiconductor integrated circuit according to another embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a test circuit of the present semiconductor integrated circuit in still another embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a test circuit of the present semiconductor integrated circuit according to still another embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of a test circuit of the present semiconductor integrated circuit in still another embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of a test circuit of the present semiconductor integrated circuit according to still another embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of a test circuit of a conventional semiconductor integrated circuit.

[Explanation of symbols]

1 test target circuit (semiconductor integrated circuit) 2, 2a, 2b expected value input terminal 2A expected value input failure information output input / output terminal 3, 3a, 3b comparison means (exclusive OR gate) 4, 4a, 4b logical OR Gates 5, 5a, 5b Flip-flop with reset 6 Judgment signal output terminals 7, 7a, 7b AND gates 8, 8a, 8b Flip-flops 9, 9a, 9b Failure information output terminal 10 Logical sum gate (logical sum means) 11 Judgment Delay means 12 Output buffer 21 First judgment delay means 22 Second judgment delay means 23 AND gate 24 Flip-flop 25 Incrementer 26 Selection means 27a First expected value delay means 27b Second expected value delay means 28a 1 delay system comparing means 28b Second delay system comparing means 29a, 29b OR gates 30a, 30b Flip flow 31 AND gates 32a, 32b, 32c External output terminal 33 AND gates 34, 35 External output terminals A, A1, A2 Output data signals B, B1, B2 Expected value signal B ₁ First expected value delayed signal B ₂ Second expected value delay signal C, C1, C2 Comparison result signal C ₁ First comparison result signal C ₂ Second comparison result signal D Judgment signals E, E1, E2 Failure information signal F First delay judgment signal G second delay determination signal CLK ₀ clock M1 mismatch holding means M2 output data lock means M3 clock measuring means M4 measurement clock number output means M5a first delay system mismatch holding means M5b second delay system mismatch holding means M6 Clock control means

Claims (12)

[Claims] 1. An expected value input terminal for inputting an expected value signal, a comparing means for comparing an output data signal of a circuit under test and the expected value signal from the expected value input terminal, and a comparison from the comparing means. When the result signals show a mismatch, the mismatch holding means for holding the mismatch status, the determination signal output terminal for externally outputting the determination signal output by the mismatch holding means, and the determination signal output by the mismatch holding means do not match. A test circuit for a semiconductor integrated circuit, comprising: output data lock means for holding an output data signal from the circuit under test when indicating a state; and a failure information output terminal for externally outputting an output signal of the output data lock means. 2. The defect information output terminal according to claim 1, further comprising: a determination delay means for delaying the determination signal output by the mismatch holding means by a predetermined cycle, and the expected value input terminal. And an output buffer that is connected and outputs high impedance when the delay determination signal from the determination delay means indicates a match and outputs the output signal from the output data locking means when the delay determination signal indicates a mismatch. A semiconductor integrated circuit test circuit provided. 3. The determination delay unit according to claim 1, further comprising: a determination delay unit that delays the determination signal output by the inconsistency holding unit by a predetermined cycle; and the determination signal output by the inconsistency holding unit does not match. A clock measurement unit that holds the number of measurement clocks at a changed timing, and a measurement clock number output that serially outputs the held number of measurement clocks at predetermined intervals when the delay determination signal output from the determination delay unit indicates a mismatch. Means, the output of the output data lock means is selected when the delay judgment signal output by the judgment delay means indicates coincidence,
A test circuit for a semiconductor integrated circuit, comprising: a selection means for selecting the output of the measurement clock number output means when there is a mismatch and outputting the output to the defect information output terminal. 4. The first determination delay unit according to claim 1, wherein the defect information output terminal is omitted, and further, the first determination delay unit delays the determination signal output from the mismatch holding unit by a predetermined period, and the first determination delay unit. Second determination delay means for delaying the delay determination signal from the determination delay means of a predetermined cycle, and clock count, and the number of measurement clocks at the timing when the determination signal output from the mismatch holding means changes to mismatch. A clock measuring unit that holds the measured clock number output unit that serially outputs the held measured clock number at a predetermined interval when the second delay determination signal output from the second determination delay unit indicates disagreement; When the second delay judgment signal output from the second judgment delay means indicates a match, the output of the output data lock means is selected, and when they do not match the measurement clock. Selection means for selecting and outputting the output of the clock number output means, and a high impedance when the first delay judgment signal output from the first judgment delay means connected to the expected value input terminal indicates a match. A test circuit for a semiconductor integrated circuit, comprising: an output buffer which outputs and outputs an output signal of the selecting means when the first delay determination signal indicates a mismatch. 5. The order according to claim 3 or 4, wherein the selecting means outputs the defective information signal from the output data locking means and the defective time information signal from the measurement clock number outputting means. The test circuit of the semiconductor integrated circuit is configured so that the failure information signal comes first and the failure time information signal comes later. 6. The expected value delay means for delaying the expected value signal from the expected value input terminal, the output data signal of the circuit under test, and the expectation according to claim 1. A delay system comparing means for comparing the delayed expected value signal by the value delay means, and a delay system mismatch holding means for holding the mismatch state when the comparison result signals from the delay system comparing means indicate mismatch. It is inserted between the mismatch holding means and the judgment signal output terminal, and the logical product of the output signal of the mismatch holding means and the output signal of the delay system mismatch holding means is output to the judgment signal output terminal as the judgment signal. A test circuit for a semiconductor integrated circuit, comprising: a logical product means for outputting. 7. The defect information output terminal according to claim 6, further comprising: a determination delay unit that delays the determination signal output from the AND unit by a predetermined cycle, and the expected value input terminal. And an output buffer that is connected and outputs high impedance when the delay determination signal from the determination delay means indicates a match and outputs the output signal from the output data locking means when the delay determination signal indicates a mismatch. A semiconductor integrated circuit test circuit provided. 8. The method according to claim 6, further comprising: a first determination delay unit that delays the determination signal output from the AND circuit by a predetermined cycle; and a delay determination signal from the first determination delay unit that is predetermined. A second judgment delay means for delaying the cycle; a clock measuring means for measuring a clock and holding the number of measurement clocks at the timing when the judgment signal output from the non-coincidence holding means changes to non-coincidence; A measurement clock number output means for serially outputting the held measurement clock number at a predetermined interval when the second delay determination signal output by the delay means indicates a mismatch, and the first determination clock output by the second determination delay means. The output of the output data lock means is selected when the delay determination signals of 2 indicate a match, and the output of the measurement clock number output means is selected and output when a mismatch occurs. And the first delay determination signal connected to the expected value input terminal and the first delay determination signal output from the first determination delay means indicates a match, a high impedance is output, and the first delay determination signal indicates a mismatch. A test circuit for a semiconductor integrated circuit, comprising: an output buffer that outputs the output signal of the selecting means when indicated. 9. The method according to claim 6, wherein a plurality of sets of the expected value delay means, the delay system comparison means, and the delay system disagreement holding means are provided, and the logical product is provided. A means is a test circuit of a semiconductor integrated circuit, which performs a logical product of the mismatch holding means and the plurality of sets of delay system mismatch holding means. 10. The semiconductor integrated circuit according to claim 6, further comprising an output terminal group for individually outputting the output signals of the mismatch holding means and the delay system mismatch holding means, respectively. Test circuit. 11. The clock control means according to claim 1, wherein when the judgment signal output to the judgment signal output terminal indicates a mismatch, the clock supplied to the circuit under test is stopped. A semiconductor integrated circuit test circuit provided. 12. The test target circuit according to claim 1, wherein the test target circuit outputs a plurality of bits of the output data signal, and the expected value input terminal,
A plurality of sets of the comparison means, the mismatch holding means, the determination signal output terminal, the output data locking means, and the defect information output terminal are provided according to the number of bits of the output data signal, and the plurality of mismatch holding means. A test circuit for a semiconductor integrated circuit, wherein the logical sum of the outputs of the above is used as the determination signal.