JP2003318843A - Reception electric field intensity detection circuit - Google Patents

Reception electric field intensity detection circuit

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Publication number
JP2003318843A
JP2003318843A JP2002126787A JP2002126787A JP2003318843A JP 2003318843 A JP2003318843 A JP 2003318843A JP 2002126787 A JP2002126787 A JP 2002126787A JP 2002126787 A JP2002126787 A JP 2002126787A JP 2003318843 A JP2003318843 A JP 2003318843A
Authority
JP
Japan
Prior art keywords
signal
gain control
electric field
circuit
gain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002126787A
Other languages
Japanese (ja)
Inventor
Mamoru Arayashiki
護 荒屋敷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002126787A priority Critical patent/JP2003318843A/en
Publication of JP2003318843A publication Critical patent/JP2003318843A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reception electric field intensity detection circuit for shortening transient response time of a reception electric field intensity signal. <P>SOLUTION: The reception electric field intensity detection circuit is provided with gain control amplifier circuits 10a, 10b that amplify an intermediate frequency signal inputted with a gain adjusted by internal control, limiter amplifier circuits 23, 24 that amplify an inputted signal with fixed gain, a wave detection circuit 26 that detects waves of the intermediate frequency signal inputted in the gain control amplifier circuit 10a, a wave detection circuit 29 that detects waves of the input signal in the limiter amplifier circuit 24, a signal addition circuit 30 that generates the reception electric field intensity signal by adding an output signal of the wave detection circuit 26, gain control signals to be outputted from the gain control amplifier circuits 10a, 10b respectively and an output signal of the wave detection circuit 29 together and a low-pass filter circuit 31 that restrict bands of a signal outputted from the signal addition circuit 30 and outputs the reception electric field intensity signal. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、受信電界強度信号
の過渡応答時間が短い受信電界強度検出回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a received electric field strength detection circuit having a short transient response time of a received electric field strength signal.

【0002】[0002]

【従来の技術】移動体通信機器などの受信装置で用いら
れる受信回路として、高周波の受信信号を中間周波帯に
変換してから復調するスーパーヘテロダイン方式の受信
回路がある。中間周波帯の信号(中間周波信号)を増幅
するためにリミッタ増幅方式を採用する従来の受信回路
では、多段構成のリミッタ増幅回路の各段から中間周波
信号を取り出して受信電界強度信号を得ることにより受
信電界強度を検出する方法が知られている。
2. Description of the Related Art As a receiver circuit used in a receiver such as a mobile communication device, there is a super-heterodyne receiver circuit that converts a high-frequency received signal into an intermediate frequency band and then demodulates it. In a conventional receiver circuit that adopts a limiter amplification method to amplify an intermediate frequency band signal (intermediate frequency signal), an intermediate frequency signal is extracted from each stage of a limiter amplifier circuit having a multi-stage configuration to obtain a received electric field strength signal. A method of detecting the received electric field strength is known.

【0003】このような受信回路の受信電界強度の検出
に係る構成の一例を図4に示す。同図に示すように、従
来の受信回路は、端子20より入力された中間周波信号
を増幅するリミッタ増幅回路21〜24と、リミッタ増
幅回路21〜24の各段の入力信号を検波する検波回路
26〜29と、各検波回路26〜29の出力信号を加算
して受信電界強度信号を生成する信号加算回路30と、
信号加算回路30の出力信号を帯域制限する低域通過フ
ィルタ回路31とを備えて構成されている。なお、検波
回路26〜29は、入力信号を二乗検波し、入力信号に
対して擬似対数の関係となる出力信号を出力する回路で
ある。
FIG. 4 shows an example of a configuration related to detection of the received electric field strength of such a receiving circuit. As shown in the figure, the conventional receiving circuit includes a limiter amplifier circuit 21 to 24 that amplifies the intermediate frequency signal input from the terminal 20, and a detection circuit that detects the input signal of each stage of the limiter amplifier circuits 21 to 24. 26-29, and a signal addition circuit 30 for adding the output signals of the detection circuits 26-29 to generate a reception electric field strength signal,
A low pass filter circuit 31 for band limiting the output signal of the signal addition circuit 30 is provided. The detection circuits 26 to 29 are circuits that square-law detect an input signal and output an output signal having a pseudo-logarithmic relationship with the input signal.

【0004】なお、リミッタ増幅回路の24の出力信号
は端子25から取り出され、後段の回路、例えば復調回
路に出力される。また、低域通過フィルタ回路31を通
過した受信電界強度信号は端子32から取り出され、後
段の回路、例えば信号処理回路に出力される。
The output signal of 24 of the limiter amplifier circuit is taken out from the terminal 25 and output to a circuit in the subsequent stage, for example, a demodulation circuit. Further, the received electric field strength signal that has passed through the low-pass filter circuit 31 is taken out from the terminal 32 and output to a circuit in the subsequent stage, for example, a signal processing circuit.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記従
来の受信回路にあっては、受信電界強度信号に含まれる
中間周波信号の包絡線信号成分の減衰量を大きくしよう
とすると、受信電界強度信号の過渡応答時間が長くなっ
てしまうという問題点があった。すなわち、中間周波信
号の包絡線信号成分は低域通過フィルタ21のカットオ
フ周波数を低くするかフィルタ次数を高くすることで減
衰量を大きくすることでできるが、この場合、中間周波
信号のステップ状のレベル変化に対して受信電界強度信
号の過渡応答時間は長くなってしまう。
However, in the above conventional receiving circuit, if the attenuation amount of the envelope signal component of the intermediate frequency signal included in the received electric field strength signal is increased, the received electric field strength signal There is a problem that the transient response time becomes long. That is, the envelope signal component of the intermediate frequency signal can be increased by decreasing the cutoff frequency of the low-pass filter 21 or increasing the filter order, but in this case, the step shape of the intermediate frequency signal is increased. Therefore, the transient response time of the received electric field strength signal becomes long with respect to the level change.

【0006】また、従来の移動体通信機器には、2系統
のアンテナを備え、当該機器の受信回路が各アンテナで
受信された信号の受信電界強度を比較し、受信電界強度
が強い方の受信信号を利用することによって通信品質を
良好に保つという、いわゆるダイバーシチ受信方式を採
用するものがある。1系統の受信回路に対して2系統の
アンテナを切り換えて受信を行うアンテナ切り換えダイ
バーシチ方式においては、アンテナ切り換え時の信号レ
ベルのステップ変化に対する受信電界強度信号の過渡応
答時間が短いほど、アンテナの選択にかかる時間が短く
なるため好ましい。
Further, the conventional mobile communication device is provided with two systems of antennas, and the receiving circuit of the device compares the received electric field strengths of the signals received by the respective antennas, and the reception electric field strength of the stronger one is received. There is one that employs a so-called diversity reception system in which communication quality is kept good by using a signal. In the antenna switching diversity method in which two systems of antennas are switched for reception with respect to one system of receiving circuit, the shorter the transient response time of the received electric field strength signal with respect to the step change of the signal level at the time of antenna switching, the more the antenna selection becomes. This is preferable because the time required for

【0007】但し、包絡線変動を伴うベースバンド変調
成分を含んだ受信信号の場合、2系統のアンテナでそれ
ぞれ受信した信号のキャリア信号成分の電界強度を適切
に検出するためには、受信電界強度信号に現れるベース
バンド変調信号の包絡線変動分を所望の値まで減衰させ
る必要がある。ベースバンド変調信号の包絡線変動分の
減衰量が十分でないと、包絡線変動分がキャリア信号成
分に重畳され、キャリア信号成分の電界強度が正しく検
出されなくなってしまうからである。
However, in the case of a received signal including a baseband modulation component accompanied by envelope fluctuation, in order to properly detect the electric field intensity of the carrier signal component of the signals respectively received by the two antennas, the received electric field intensity It is necessary to attenuate the envelope variation of the baseband modulation signal appearing in the signal to a desired value. This is because if the amount of attenuation of the envelope variation of the baseband modulated signal is not sufficient, the amount of envelope variation is superimposed on the carrier signal component, and the electric field strength of the carrier signal component cannot be detected correctly.

【0008】しかしながら、上述のように、低域通過フ
ィルタ21の減衰量と過渡応答時間はトレードオフの関
係にあり、減衰量を大きく取ろうとすると過渡応答時間
が長くなってしまうため、アンテナ切り換えダイバーシ
チ方式を採用する従来の受信回路にあっては、所望の過
渡応答時間内では中間周波信号の包絡線信号成分におい
て十分な減衰量が得られない場合があるという問題点も
あった。
However, as described above, the attenuation amount of the low-pass filter 21 and the transient response time are in a trade-off relationship, and the transient response time becomes long if the attenuation amount is set to a large value, so that the antenna switching diversity. In the conventional receiving circuit adopting the method, there is also a problem that sufficient attenuation may not be obtained in the envelope signal component of the intermediate frequency signal within the desired transient response time.

【0009】本発明は、上記従来の問題点に鑑みてなさ
れたものであって、受信電界強度信号の過渡応答時間を
短くすることのできる受信電界強度検出回路を提供する
ことを目的としている。
The present invention has been made in view of the above conventional problems, and an object of the present invention is to provide a received electric field strength detection circuit capable of shortening the transient response time of a received electric field strength signal.

【0010】[0010]

【課題を解決するための手段】上記目的を達成するため
に、本発明に係る受信電界強度検出回路は、内部で生成
された利得制御信号によって出力信号が入力信号に対し
線形動作するよう利得を調整し、当該調整された利得で
入力信号を増幅する利得制御増幅手段と、前記利得制御
増幅手段の入力信号を検波する第1の検波手段と、前記
第1の検波手段の出力信号と前記利得制御増幅手段の利
得制御信号とを加算して帯域制限することにより受信電
界強度信号を生成する受信電界強度信号生成手段と、を
備えている。
In order to achieve the above object, a received electric field strength detection circuit according to the present invention provides a gain control signal internally generated with a gain so that an output signal linearly operates with respect to an input signal. Gain control amplification means for adjusting and amplifying an input signal with the adjusted gain; first detection means for detecting an input signal of the gain control amplification means; output signal of the first detection means and the gain Reception electric field strength signal generation means for generating a reception electric field strength signal by adding the gain control signal of the control amplification means and band limiting.

【0011】また、本発明に係る受信電界強度検出回路
は、前記利得制御増幅手段は、前記利得制御信号によっ
て利得が調整される、入力信号を増幅する可変利得増幅
手段と、前記可変利得増幅手段の出力信号を検波する第
2の検波手段と、前記第2の検波手段の出力を積分して
利得制御信号を出力する積分手段と、を有し、前記利得
制御信号によって出力信号の振幅が所定値以上とならな
いよう前記可変利得増幅手段の利得が制御される。
Further, in the received electric field strength detection circuit according to the present invention, the gain control amplification means has a variable gain amplification means for amplifying an input signal whose gain is adjusted by the gain control signal, and the variable gain amplification means. Second detection means for detecting the output signal of the second detection means, and integration means for outputting the gain control signal by integrating the output of the second detection means, and the amplitude of the output signal is predetermined by the gain control signal. The gain of the variable gain amplifying means is controlled so as not to exceed the value.

【0012】可変利得増幅手段は利得制御信号に対して
利得が指数関数的に変化するよう設計されているため、
結果的に、利得制御信号の等価的な時定数は小さくな
り、このため過渡応答時間は短くなる。このような利得
制御信号が受信電界強度信号生成手段で加算される信号
に含まれているため、過渡応答時間の短い受信電界強度
信号を生成することができる。また、受信電界強度信号
の減衰量に関しては、帯域制限による時定数だけでなく
積分手段の時定数も調整することができるため、過渡応
答時間を短くしたまま減衰量を大きくすることができ
る。
Since the variable gain amplifying means is designed so that the gain changes exponentially with respect to the gain control signal,
As a result, the equivalent time constant of the gain control signal is small, which shortens the transient response time. Since such a gain control signal is included in the signals added by the reception electric field strength signal generating means, it is possible to generate a reception electric field strength signal having a short transient response time. Regarding the attenuation amount of the received electric field intensity signal, not only the time constant due to band limitation but also the time constant of the integrating means can be adjusted, so that the attenuation amount can be increased while keeping the transient response time short.

【0013】また、本発明に係る受信電界強度検出回路
は、前記利得制御増幅手段の出力信号を増幅する複数段
構成の増幅手段群と、最前段の増幅手段の入力信号を除
く各増幅手段の入力信号を検波する第3の検波回路群
と、を備え、前記受信電界強度信号生成手段は、前記第
1の検波手段の出力信号および前記利得制御増幅手段の
利得制御信号に加え、前記第3の検波回路群の各出力信
号も加算する。
Further, the received electric field strength detection circuit according to the present invention includes a plurality of amplifying means groups for amplifying the output signal of the gain control amplifying means, and each amplifying means excluding the input signal of the frontmost amplifying means. A third detection circuit group for detecting an input signal, wherein the reception electric field strength signal generation means adds the output signal of the first detection means and the gain control signal of the gain control amplification means to the third detection circuit. Each output signal of the detection circuit group of is also added.

【0014】また、本発明に係る受信電界強度検出回路
は、前記受信電界強度生成手段は、前記第1の検波手段
の出力信号と前記利得制御増幅手段の利得制御信号とを
加算する信号加算手段と、前記信号加算手段で加算され
た信号を帯域制限する帯域制限手段と、を有する。
In the received electric field strength detection circuit according to the present invention, the received electric field strength generating means adds the output signal of the first detecting means and the gain control signal of the gain control amplifying means. And band limiting means for band limiting the signals added by the signal adding means.

【0015】さらに、本発明に係る移動体通信装置は、
請求項1、2、3または4記載の受信電界強度検出回路
を備えている。
Further, the mobile communication device according to the present invention is
The reception electric field strength detection circuit according to claim 1, 2, 3 or 4 is provided.

【0016】[0016]

【発明の実施の形態】以下、本発明に係る受信電界強度
検出回路の実施の形態について、図面を参照して詳細に
説明する。本実施形態の受信電界強度検出回路は、スー
パーヘテロダイン方式の受信回路に設けられており、多
段構成の増幅回路の各段から中間周波信号を取り出して
受信電界強度を得ることにより受信電界強度を検出する
ものである。当該受信電界強度検出回路を有する受信回
路は、携帯電話やPDA等の移動体通信機器に設けられ
ている。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a received electric field strength detection circuit according to the present invention will be described below in detail with reference to the drawings. The reception electric field strength detection circuit of the present embodiment is provided in a superheterodyne type reception circuit, and detects the reception electric field strength by extracting the intermediate frequency signal from each stage of the multistage amplifier circuit to obtain the reception electric field strength. To do. A reception circuit having the reception electric field strength detection circuit is provided in mobile communication devices such as mobile phones and PDAs.

【0017】図1は、本発明に係る一実施形態の受信電
界強度検出回路を示すブロック図である。同図におい
て、図4(従来技術)と重複する部分には同一の符号を
付す。図1に示すように、本実施形態の受信電界強度検
出回路は、特許請求の範囲の利得制御増幅手段に該当す
る利得制御増幅回路10a,10bと、増幅手段群に該
当するリミッタ増幅回路23,24と、第1の検波手段
に該当する検波回路26と、第3の検波手段群に該当す
る検波回路29と、信号加算手段に該当する信号加算回
路30と、帯域制限手段に該当する低域通過フィルタ回
路31とを備えて構成されている。なお、信号加算回路
30および低域通過フィルタ回路31は、併せて、特許
請求の範囲の受信電界強度信号生成手段に該当する。
FIG. 1 is a block diagram showing a received electric field strength detection circuit according to an embodiment of the present invention. In the figure, the same parts as those in FIG. 4 (prior art) are designated by the same reference numerals. As shown in FIG. 1, the received electric field strength detection circuit of the present embodiment includes gain control amplification circuits 10a and 10b corresponding to the gain control amplification means of the claims and a limiter amplification circuit 23 corresponding to the amplification means group. 24, a detection circuit 26 corresponding to the first detection means, a detection circuit 29 corresponding to the third detection means group, a signal addition circuit 30 corresponding to the signal addition means, and a low band corresponding to the band limiting means. It is provided with a pass filter circuit 31. The signal addition circuit 30 and the low-pass filter circuit 31 together correspond to the received electric field strength signal generating means in the claims.

【0018】以下、本実施形態の受信電界強度検出回路
が有する各構成要素について説明する。まず、利得制御
増幅回路10(10a,10b)は、内部制御によって
調整された利得で入力信号を増幅するものであり、特許
請求の範囲の可変利得増幅手段に該当する可変利得増幅
回路101と、第2の検波手段に該当する両波検波回路
103と、積分手段に該当する積分回路105とから構
成されている。当該利得制御増幅回路10では、出力信
号の振幅が一定値以上とならないように、即ち、入力信
号に対して線形動作するように利得制御のための帰還を
行っている。
The respective constituent elements of the received electric field strength detection circuit of this embodiment will be described below. First, the gain control amplification circuit 10 (10a, 10b) amplifies an input signal with a gain adjusted by internal control, and includes a variable gain amplification circuit 101 corresponding to the variable gain amplification means in the claims. It is composed of a double wave detection circuit 103 corresponding to the second detection means and an integration circuit 105 corresponding to the integration means. The gain control amplifier circuit 10 performs feedback for gain control so that the amplitude of the output signal does not exceed a certain value, that is, it operates linearly with respect to the input signal.

【0019】以下、利得制御増幅回路10が有する各構
成要素について説明する。まず、可変利得増幅回路10
1は、中間周波信号を増幅するものであり、その利得は
積分回路105から出力される利得制御信号(後述)に
よって制御される。また、両波検波回路103は、可変
利得増幅回路101の出力信号を検波するものである。
また、積分回路105は、両波検波回路103の出力を
積分して利得制御信号を出力するものであり、当該利得
制御信号は可変利得増幅回路101と信号加算回路30
の双方に入力される。
The components of the gain control amplifier circuit 10 will be described below. First, the variable gain amplifier circuit 10
1 is for amplifying the intermediate frequency signal, and its gain is controlled by a gain control signal (described later) output from the integrating circuit 105. The double-wave detection circuit 103 detects the output signal of the variable gain amplification circuit 101.
The integrating circuit 105 integrates the outputs of the both-wave detecting circuit 103 and outputs a gain control signal. The gain control signal is the variable gain amplifying circuit 101 and the signal adding circuit 30.
Is input to both.

【0020】また、リミッタ増幅回路23,24は、入
力された中間周波信号を一定の利得で増幅するものであ
る。また、検波回路26は、前段の利得制御増幅回路1
0aの入力信号を検波するものである。また、検波回路
29は、後段のリミッタ増幅回路24の入力信号を検波
するものである。また、信号加算回路30は、検波回路
26,29の各出力信号と利得制御増幅回路10a,1
0bが有する積分回路105a,105bから出力され
た利得制御信号とを加算するものである。また、低域通
過フィルタ回路31は、信号加算回路30から出力され
た信号を帯域制限するものである。低域通過フィルタ回
路31から出力される信号を受信電界強度信号という。
The limiter amplifier circuits 23 and 24 amplify the input intermediate frequency signal with a constant gain. Further, the detection circuit 26 is the gain control amplifier circuit 1 of the preceding stage.
The input signal of 0a is detected. The detector circuit 29 detects the input signal of the limiter amplifier circuit 24 in the subsequent stage. Further, the signal addition circuit 30 includes the output signals of the detection circuits 26 and 29 and the gain control amplification circuits 10a and 1a.
The gain control signals output from the integrating circuits 105a and 105b included in 0b are added. The low-pass filter circuit 31 limits the band of the signal output from the signal addition circuit 30. The signal output from the low pass filter circuit 31 is called a received electric field strength signal.

【0021】利得制御増幅回路10を除く以上説明した
構成要素、すなわち、リミッタ増幅回路23,24、検
波回路26,29、信号加算回路30および低域通過フ
ィルタ回路31は、従来と同様である。本実施形態の受
信電界強度検出回路において、アンテナ(図示せず)で
受信した高周波信号を周波数変換して得られた中間周波
信号が端子20から入力されると、利得制御増幅回路1
0a,10bおよびリミッタ増幅回路23,24を経て
端子25から取り出され、後段の回路、例えば復調回路
(図示せず)に出力される。また、低域通過フィルタ回
路31を通過した受信電界強度信号は端子32から取り
出され、後段の回路、例えば信号処理回路に出力され
る。
The constituent elements described above except the gain control amplifier circuit 10, that is, the limiter amplifier circuits 23 and 24, the detector circuits 26 and 29, the signal adder circuit 30, and the low-pass filter circuit 31, are the same as those in the prior art. In the received electric field strength detection circuit of the present embodiment, when the intermediate frequency signal obtained by frequency-converting the high frequency signal received by the antenna (not shown) is input from the terminal 20, the gain control amplifier circuit 1
It is taken out from the terminal 25 through the 0a and 10b and the limiter amplifier circuits 23 and 24, and is output to a circuit in the subsequent stage, for example, a demodulation circuit (not shown). Further, the received electric field strength signal that has passed through the low-pass filter circuit 31 is taken out from the terminal 32 and output to a circuit in the subsequent stage, for example, a signal processing circuit.

【0022】以下、利得制御増幅回路10の過渡的な動
作について、図2および図3を参照して説明する。図2
は中間周波信号の入力レベルに対する受信電界強度信号
の特性を示す説明図である。横軸は中間周波信号の入力
レベルをデシベル(dB)で表し、縦軸は受信電界強度
信号の出力レベルをリニアで表している。同図に示す破
線は、左から検波回路29の出力信号のレベル、利得制
御増幅回路10aから出力された利得制御信号のレベ
ル、利得制御増幅回路10bから出力された利得制御信
号のレベル、検波回路26の出力信号のレベルを表して
おり、実線はこれらを信号加算回路30で加算して低域
通過フィルタ回路31で帯域制限した信号(受信電界強
度信号)の出力レベルを表しており、それぞれ入力のデ
シベル変化に対する出力のリニアな変化特性を示してい
る。
The transient operation of the gain control amplifier circuit 10 will be described below with reference to FIGS. 2 and 3. Figure 2
FIG. 4 is an explanatory diagram showing characteristics of a received electric field strength signal with respect to an input level of an intermediate frequency signal. The horizontal axis represents the input level of the intermediate frequency signal in decibels (dB), and the vertical axis represents the output level of the received electric field strength signal in linear form. The broken line shown in the figure indicates from the left the level of the output signal of the detection circuit 29, the level of the gain control signal output from the gain control amplification circuit 10a, the level of the gain control signal output from the gain control amplification circuit 10b, and the detection circuit. 26, the solid line represents the output level of a signal (received electric field strength signal) that has been band-limited by the low-pass filter circuit 31 by adding them in the signal addition circuit 30. It shows the linear change characteristic of the output with respect to the change of decibel.

【0023】利得制御増幅回路10において、可変利得
増幅回路101の出力信号のレベルをVo(t)とし、
当該出力信号のキャリア成分の角周波数をωcとする
と、出力信号のレベルVo(t)は式(1)によって表
される。 Vo(t)=Ao(t)cos(ωct) …(1) 但し、Ao(t)は出力信号の振幅である。
In the gain control amplifier circuit 10, the level of the output signal of the variable gain amplifier circuit 101 is Vo (t),
When the angular frequency of the carrier component of the output signal is ωc, the level Vo (t) of the output signal is represented by Expression (1). Vo (t) = Ao (t) cos (ωct) (1) where Ao (t) is the amplitude of the output signal.

【0024】可変利得増幅回路101の出力信号は、両
波検波回路103に入力される。両波検波回路103の
出力信号レベルVd(t)は、式(2)に示すように入
出力の関係が線形である。 Vd(t)=KAo(t) …(2)
The output signal of the variable gain amplifier circuit 101 is input to the double wave detection circuit 103. The output signal level Vd (t) of the double-wave detection circuit 103 has a linear input / output relationship as shown in Expression (2). Vd (t) = KAo (t) (2)

【0025】両波検波回路103の出力信号は、周波数
特性がF(ω)の積分回路105に入力される。積分回
路105は包絡線変動成分(すなわちAo(t)の変
動)を減衰し、その出力信号である利得制御信号は可変
利得増幅回路101の利得を制御する。積分回路105
がコンデンサCと抵抗Rとから成る回路とすると、積分
回路の出力信号、すなわち利得制御信号の電圧レベルV
g(t)は式(3)によって表される。 Vg(t)=(1/τ)∫[Vd(t)−Vg(t)]dt …(3) 但し、τ=CRである。
The output signal of the double wave detection circuit 103 is input to the integration circuit 105 having a frequency characteristic of F (ω). The integrating circuit 105 attenuates the envelope fluctuation component (that is, fluctuation of Ao (t)), and the gain control signal which is its output signal controls the gain of the variable gain amplifying circuit 101. Integrating circuit 105
Is a circuit including a capacitor C and a resistor R, the voltage level V of the output signal of the integrating circuit, that is, the gain control signal.
g (t) is represented by Formula (3). Vg (t) = (1 / τ) ∫ [Vd (t) −Vg (t)] dt (3) However, τ = CR.

【0026】上記式(1)〜(3)から、利得制御信号
の電圧レベルVg(t)の変化を示す微分方程式は、式
(4)によって表される。 dVg(t)/dt=(1/τ)[KAo(t)−Vg(t)] …(4) 当該式(4)より、等価的な時定数τeは式(5)によ
って示される。 τe=τ/[KAo(t)−Vg(t)] …(5)
From the above equations (1) to (3), the differential equation showing the change in the voltage level Vg (t) of the gain control signal is represented by the equation (4). dVg (t) / dt = (1 / τ) [KAo (t) -Vg (t)] (4) From the equation (4), the equivalent time constant τe is represented by the equation (5). τe = τ / [KAo (t) -Vg (t)] (5)

【0027】可変利得増幅回路101は、一般に、利得
制御信号の電圧に対して利得が指数関数的に変化するよ
う設計される。したがって、本実施形態では、可変利得
増幅回路101の利得G(t)が利得制御信号の電圧レ
ベルVg(t)に対して式(6)のように変化すると仮
定する。 G(t)=Go×exp[−αVg(t)] …(6) 式(6)より、利得制御信号の電圧レベルVg(t)が
小さいと可変利得増幅回路101の利得G(t)は高く
なり、利得制御信号の電圧レベルVg(t)が大きいと
利得G(t)は低くなる。
The variable gain amplifier circuit 101 is generally designed so that the gain changes exponentially with respect to the voltage of the gain control signal. Therefore, in the present embodiment, it is assumed that the gain G (t) of the variable gain amplifier circuit 101 changes as shown in equation (6) with respect to the voltage level Vg (t) of the gain control signal. G (t) = Go × exp [−αVg (t)] (6) From equation (6), when the voltage level Vg (t) of the gain control signal is small, the gain G (t) of the variable gain amplifier circuit 101 is As the voltage level Vg (t) of the gain control signal increases, the gain G (t) decreases.

【0028】初期状態において、利得制御増幅回路10
の入力信号レベルが小さい状態(利得が高い状態)から
大きい状態にステップ状に変化した時(立ち上がり過渡
応答)、式(5)からKAo(t)>Vg(t)となる
ので、等価的な時定数τeは小さくなる。また、初期状
態において、利得制御増幅回路10の入力信号レベルが
大きい状態(利得が低い状態)から小さい状態にステッ
プ状に変化した時(立ち下がり過渡応答)、式(5)か
らKAo(t)<Vg(t)となるので、等価的な時定
数τeは小さくなる。このように、等価的な時定数τe
が小さくなるため収束時間は短くなる。
In the initial state, the gain control amplifier circuit 10
When the input signal level of is changed stepwise from a small state (high gain state) to a large state (rising transient response), KAo (t)> Vg (t) is obtained from the equation (5). The time constant τe becomes smaller. Further, in the initial state, when the input signal level of the gain control amplifier circuit 10 changes stepwise from a high state (low gain state) to a low state (falling transient response), KAo (t) is calculated from the equation (5). Since <Vg (t), the equivalent time constant τe becomes small. Thus, the equivalent time constant τe
Is smaller, the convergence time is shorter.

【0029】この関係を図3に示す。図3は、利得制御
信号の過渡応答特性を示す説明図である。横軸は時間を
表し、縦軸は利得制御信号のレベルをリニアで表してい
る。同図に示す一点破線は、積分回路105がコンデン
サCと抵抗Rとから成る場合における利得制御信号の電
圧レベルがステップ状の過渡応答を示しており、その時
定数はτ(=CR)となる。また、同図に示す破線は、
利得制御増幅回路10の初期状態における時定数をτ/
[KAo(t)−Vg(t)]とした場合の延長線を示
している。また、同図に示す実線は、初期状態における
時定数がτ/[KAo(t)−Vg(t)]の状態から
利得制御と共に一点破線で示す特性へと遷移していく場
合について示している。図3の実線に示すように、本実
施形態によれば等価的な時定数が小さくなるため収束時
間は短くなる。
This relationship is shown in FIG. FIG. 3 is an explanatory diagram showing the transient response characteristic of the gain control signal. The horizontal axis represents time, and the vertical axis represents the level of the gain control signal linearly. The dashed-dotted line shown in the figure shows a step-like transient response of the voltage level of the gain control signal in the case where the integrating circuit 105 includes the capacitor C and the resistor R, and the time constant thereof is τ (= CR). In addition, the broken line shown in FIG.
The time constant in the initial state of the gain control amplifier circuit 10 is τ /
An extension line in the case of [KAo (t) -Vg (t)] is shown. Further, the solid line shown in the figure shows the case where the time constant in the initial state changes from τ / [KAo (t) -Vg (t)] to the characteristic indicated by the dashed line with gain control. . As shown by the solid line in FIG. 3, according to the present embodiment, the equivalent time constant becomes smaller, so the convergence time becomes shorter.

【0030】したがって、利得制御増幅回路10a,1
0bからの利得制御信号に基づく受信電界強度信号にあ
っては、積分回路105a,105bと低域通過フィル
タ回路31の各時定数を調整することにより、低域通過
フィルタ回路31のみで減衰量を大きくする場合と比較
して過渡応答時間を短くすることができる。また、同様
に、低域通過フィルタ回路31のみで過渡応答時間を短
くする場合と比較して減衰量を大きくすることができ
る。
Therefore, the gain control amplifier circuits 10a, 1
In the received electric field strength signal based on the gain control signal from 0b, by adjusting the time constants of the integrating circuits 105a and 105b and the low-pass filter circuit 31, the attenuation amount can be reduced only by the low-pass filter circuit 31. The transient response time can be shortened as compared with the case of increasing it. Similarly, the attenuation amount can be increased as compared with the case where the transient response time is shortened only by the low pass filter circuit 31.

【0031】以上説明したように、本実施形態の受信電
界強度検出回路によれば、信号加算回路30で加算され
る信号に過渡応答時間が短く減衰量の大きな利得制御信
号が含まれているため、過渡応答時間の短い受信電界強
度信号を生成することができる。これらの効果を奏する
本実施形態の受信電界強度検出回路を受信回路に組み込
むことにより、受信電界強度検出回路の過渡応答時間を
短縮しつつ、包絡線変動分の変動を小さくすることがで
きる。また、受信電界強度検出回路の過渡応答時間を短
縮しつつ、より短い時間で基地局を切り換えることがで
きる。さらに、受信電界強度検出回路の包絡線変動成分
の変動を小さくしつつ、より正確な受信電界強度で基地
局を切り換えることができる。
As described above, according to the received electric field strength detection circuit of the present embodiment, the signal added by the signal addition circuit 30 includes the gain control signal having a short transient response time and a large attenuation amount. It is possible to generate a received electric field strength signal having a short transient response time. By incorporating the reception electric field strength detection circuit of the present embodiment having these effects into the reception circuit, it is possible to shorten the transient response time of the reception electric field strength detection circuit and reduce the fluctuation of the envelope fluctuation amount. Further, the base station can be switched in a shorter time while shortening the transient response time of the reception electric field strength detection circuit. Further, it is possible to switch the base station with more accurate received electric field strength while reducing the fluctuation of the envelope fluctuation component of the received electric field strength detection circuit.

【0032】なお、利得制御増幅回路の段数、リミッタ
増幅回路の段数および検波回路の段数は、本実施形態の
構成に限定されるものではなく、異なる段数としても良
い。また、図2に示した受信電界強度信号出力の特性図
においては、破線で示された各検波回路の出力特性およ
び各利得制御増幅回路の利得制御信号の出力特性が全て
同一であるが、各々の出力が受け持つ入力信号レベルの
範囲とその傾きが個々に異なる場合においては、信号加
算回路30にて各検波回路の出力および各利得制御信号
の出力を加算する前に減衰または増幅を行うことで信号
レベルを調整して、加算結果の出力特性が直線になるよ
う調整しても良い。
The number of stages of the gain control amplifier circuit, the number of stages of the limiter amplifier circuit, and the number of stages of the detection circuit are not limited to those of the present embodiment, but may be different numbers of stages. Further, in the characteristic diagram of the received electric field strength signal output shown in FIG. 2, the output characteristics of each detection circuit and the output characteristics of the gain control signal of each gain control amplifier circuit, which are indicated by broken lines, are all the same. In the case where the range of the input signal level and the slope of the input signal are different from each other, the signal adding circuit 30 performs attenuation or amplification before adding the output of each detection circuit and the output of each gain control signal. The signal level may be adjusted so that the output characteristic of the addition result becomes linear.

【0033】[0033]

【発明の効果】以上説明したように、本発明に係る受信
電界強度検出回路によれば、可変利得増幅手段は利得制
御信号に対して利得が指数関数的に変化するよう設計さ
れているため、結果的に、利得制御信号の等価的な時定
数は小さくなり、このため過渡応答時間は短くなる。こ
のような利得制御信号が受信電界強度信号生成手段で加
算される信号に含まれているため、過渡応答時間の短い
受信電界強度信号を生成することができる。また、受信
電界強度信号の減衰量に関しては、帯域制限による時定
数だけでなく積分手段の時定数も調整することができる
ため、過渡応答時間を短くしたまま減衰量を大きくする
ことができる。
As described above, according to the received electric field strength detection circuit of the present invention, the variable gain amplification means is designed so that the gain changes exponentially with respect to the gain control signal. As a result, the equivalent time constant of the gain control signal is small, which shortens the transient response time. Since such a gain control signal is included in the signals added by the reception electric field strength signal generating means, it is possible to generate a reception electric field strength signal having a short transient response time. Regarding the attenuation amount of the received electric field intensity signal, not only the time constant due to band limitation but also the time constant of the integrating means can be adjusted, so that the attenuation amount can be increased while keeping the transient response time short.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の形態を示す図、FIG. 1 is a diagram showing an embodiment of the present invention,

【図2】図1の動作特性を示す図FIG. 2 is a diagram showing the operating characteristics of FIG.

【図3】図1の動作特性を示す図FIG. 3 is a diagram showing operating characteristics of FIG.

【図4】従来の受信回路の受信電界強度の検出に係る構
成の一例を示すブロック図
FIG. 4 is a block diagram showing an example of a configuration related to detection of a received electric field strength of a conventional receiving circuit.

【符号の説明】[Explanation of symbols]

10a,10b 利得制御増幅回路 101a,101b 可変利得増幅回路 103a,103b 両波検波回路 105a,105b 積分回路 23,24 リミッタ増幅回路 26,29 検波回路 30 信号加算回路 31 低域通過フィルタ回路 10a, 10b Gain control amplifier circuit 101a, 101b Variable gain amplifier circuit 103a, 103b double wave detection circuit 105a, 105b integrating circuit 23,24 limiter amplifier circuit 26,29 Detection circuit 30 signal addition circuit 31 Low-pass filter circuit

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 内部で生成された利得制御信号によって
出力信号が入力信号に対し線形動作するよう利得を調整
し、当該調整された利得で入力信号を増幅する利得制御
増幅手段と、 前記利得制御増幅手段の入力信号を検波する第1の検波
手段と、 前記第1の検波手段の出力信号と前記利得制御増幅手段
の利得制御信号とを加算して帯域制限することにより受
信電界強度信号を生成する受信電界強度信号生成手段
と、を備えたことを特徴とする受信電界強度検出回路。
1. A gain control amplification means for adjusting a gain by an internally generated gain control signal so that an output signal linearly operates with respect to an input signal, and amplifying the input signal with the adjusted gain, and the gain control. A first detection means for detecting an input signal of the amplification means, and an output signal of the first detection means and a gain control signal of the gain control amplification means are added to perform band limitation to generate a reception electric field strength signal. A received electric field strength detection circuit, comprising:
【請求項2】 前記利得制御増幅手段は、 前記利得制御信号によって利得が調整される、入力信号
を増幅する可変利得増幅手段と、 前記可変利得増幅手段の出力信号を検波する第2の検波
手段と、 前記第2の検波手段の出力を積分して利得制御信号を出
力する積分手段と、を有し、 前記利得制御信号によって出力信号の振幅が所定値以上
とならないよう前記可変利得増幅手段の利得が制御され
ることを特徴とする請求項1記載の受信電界強度検出回
路。
2. The gain control amplification means includes a variable gain amplification means for amplifying an input signal, the gain of which is adjusted by the gain control signal, and a second detection means for detecting an output signal of the variable gain amplification means. And an integrating means for integrating the output of the second detecting means and outputting a gain control signal, wherein the gain control signal prevents the amplitude of the output signal from exceeding a predetermined value. The received electric field strength detection circuit according to claim 1, wherein the gain is controlled.
【請求項3】 前記利得制御増幅手段の出力信号を増幅
する複数段構成の増幅手段群と、 最前段の増幅手段の入力信号を除く各増幅手段の入力信
号を検波する第3の検波回路群と、を備え、 前記受信電界強度信号生成手段は、前記第1の検波手段
の出力信号および前記利得制御増幅手段の利得制御信号
に加え、前記第3の検波回路群の各出力信号も加算する
ことを特徴とする請求項1または2記載の受信電界強度
検出回路。
3. An amplifying means group having a plurality of stages for amplifying an output signal of the gain control amplifying means, and a third detecting circuit group for detecting an input signal of each amplifying means except an input signal of the amplifying means of the front stage. And the reception electric field intensity signal generation means adds each output signal of the third detection circuit group in addition to the output signal of the first detection means and the gain control signal of the gain control amplification means. 3. The received electric field strength detection circuit according to claim 1 or 2.
【請求項4】 前記受信電界強度生成手段は、 前記第1の検波手段の出力信号と前記利得制御増幅手段
の利得制御信号とを加算する信号加算手段と、 前記信号加算手段で加算された信号を帯域制限する帯域
制限手段と、を有することを特徴とする請求項1、2ま
たは3記載の受信電界強度検出回路。
4. The reception electric field strength generation means includes a signal addition means for adding an output signal of the first detection means and a gain control signal of the gain control amplification means, and a signal added by the signal addition means. 4. The received electric field strength detection circuit according to claim 1, 2 or 3, further comprising: band limiting means for band limiting.
【請求項5】 請求項1、2、3または4記載の受信電
界強度検出回路を備えたことを特徴とする移動体通信装
置。
5. A mobile communication device comprising the received electric field strength detection circuit according to claim 1, 2, 3, or 4.
JP2002126787A 2002-04-26 2002-04-26 Reception electric field intensity detection circuit Pending JP2003318843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002126787A JP2003318843A (en) 2002-04-26 2002-04-26 Reception electric field intensity detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002126787A JP2003318843A (en) 2002-04-26 2002-04-26 Reception electric field intensity detection circuit

Publications (1)

Publication Number Publication Date
JP2003318843A true JP2003318843A (en) 2003-11-07

Family

ID=29541104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002126787A Pending JP2003318843A (en) 2002-04-26 2002-04-26 Reception electric field intensity detection circuit

Country Status (1)

Country Link
JP (1) JP2003318843A (en)

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