JP2003316846A - Verification device for image display logic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a verification device for an image display logic circuit capable of efficiently performing the logic verification of a designed image display logic circuit. <P>SOLUTION: Based on circuit connection data of a circuit connection data storage part 11 and input test pattern data of an input pattern signal storage part 12, a logic simulation is executed in a logic simulation execution part 13, and during the execution, various signals of image display are extracted in a logic simulation result extraction part 15. The coordinate value, page number (display position) and RGB value of a drawing pixel are calculated in a pixel drawing coordinate value calculation part 15 and a pixel drawing RGB value calculation part 16 based on the extracted various signals. The calculated display position and RGB value are associated with the pixel drawing RGB value in a coordinate value storage part 18, and the RGB value (numerical value) is displayed on a pixel drawing RGB value display part 21 every red, green or blue through an image display part 17, a coordinate value input part 19, and a pixel drawing RGB value extraction part 20. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for verifying a designed image display logic circuit model or image display logic circuit element.

[0002]

2. Description of the Related Art In a conventional method for verifying an image display logic circuit, data of an input test pattern is applied to an image display logic circuit (model) for which a logic simulation is performed to perform a simulation. Output image signal (RGB signal, luminance signal, transmission (Bl
ank) signal, horizontal sync signal, vertical sync signal, and other signals that are output to the display device) are displayed graphically on a monitor (CRT, etc.) to visually check whether the expected character or image data is output. I was confirming it.

[0003]

According to the conventional verification method,
An image signal output from the image display logic circuit model causes a pixel (picture element) at an arbitrary coordinate to be displayed.
When verifying whether or not t) is correctly colored, the color of the monitor was visually confirmed and checked, but the design image display logic circuit model when the number of simultaneous colors increases and the color depth increases Then, there is a problem that it is difficult to visually check the color development state.

The present invention has been made in order to solve the above problems, and determines whether or not a pixel at an arbitrary coordinate is correctly colored by an image signal output from a designed image display logic circuit. An object of the present invention is to provide a verification device for an image display logic circuit, which can easily grasp the color development state during verification and can efficiently perform logic verification.

[0005]

A verification device for an image display logic circuit according to the present invention includes a circuit connection data storage section for storing circuit connection data defining a connection relation of an image display logic circuit, and the above-mentioned image display logic circuit. An input pattern signal storage unit that stores input test pattern data to be applied to the input unit of the logic circuit, a logic simulation execution unit that executes a logic simulation of the image display logic circuit based on the circuit connection data and the input test pattern data, A logic simulation result extraction unit that extracts a logic signal value change of an image signal during execution of the logic simulation execution unit, and a pixel to be drawn based on the clock signal, horizontal synchronization signal, and vertical synchronization signal extracted by the logic simulation result extraction unit Pixel drawing coordinate value calculation unit that calculates the coordinate value and page number of RGB signal, luminance signal logic simulation result extraction unit has extracted the transmission signal, based on,
Pixel drawing R for calculating the RGB value of the pixel to be drawn
GB value calculating unit, pixel drawing RGB value that stores the coordinate value corresponding to the pixel to be drawn, page number and RGB value in association with each other, coordinate value storage unit, pixel drawing R
Based on the RGB value calculated by the GB value calculation unit, the coordinate value calculated by the pixel drawing coordinate value calculation unit, and the page number,
An image display unit that draws each pixel and displays the image, the coordinates of any pixel on the image displayed by the image display unit,
When the user designates, the coordinate value input unit that extracts the designated coordinate value and page number, the RGB value of the pixel specified by the coordinate value and the page number extracted by the coordinate value input unit, and the pixel drawing RGB Value, the pixel drawing RGB value extraction unit extracted from the coordinate value storage unit, and the RGB values extracted by the pixel drawing RGB value extraction unit in red, green,
A pixel drawing RGB value display unit for displaying numerical values for each blue color is provided.

Further, a circuit connection data storage section storing circuit connection data defining a connection relation of the image display logic circuit, and an input pattern signal storing input test pattern data applied to the input section of the image display logic circuit. A storage unit, a logic simulation execution unit that executes a logic simulation of the image display logic circuit based on the circuit connection data and the input test pattern data, and extracts a logic signal value change of an image signal during execution of the logic simulation execution unit. A logical simulation result extraction unit, a pixel drawing coordinate value calculation unit that calculates a coordinate value of a pixel to be drawn and a page number based on the clock signal, the horizontal synchronization signal, and the vertical synchronization signal extracted by the logical simulation result extraction unit, RGB signals extracted by the logic simulation result extraction unit, Degree signal, transmission signal, based on,
Pixel drawing R for calculating the RGB value of the pixel to be drawn
It is determined whether or not any one of the RGB signal, the luminance signal, the transparent signal, the clock signal, the horizontal synchronizing signal, and the vertical synchronizing signal extracted by the GB value calculating unit and the logic simulation result extracting unit has an indefinite value. If an indeterminate value is generated in any of the clock signal, the horizontal synchronizing signal, and the vertical synchronizing signal, the indeterminate value generating signal name and the indeterminate value generating simulation extracted from the logic simulation result extracting unit are determined. The time and the pixel drawing coordinate value extracted from the pixel drawing coordinate value calculation unit are output to the indefinite value generation message display unit that displays the pixel drawing coordinates one clock before, and are output to any of the clock signal, horizontal synchronization signal, and vertical synchronization signal. If an indeterminate value does not occur and any of the RGB signals, luminance signals, and transmission signals has an indeterminate value, then The indeterminate value generation pixel drawing coordinates calculated by the xcel drawing coordinate value calculation unit, and the indeterminate value generation signal name and the indeterminate value generation simulation time extracted from the logic simulation result extraction unit are output to the indeterminate value generation message display unit. Section, an image display section for drawing and displaying an image of each pixel based on the RGB value calculated by the pixel drawing RGB value calculating section, the coordinate value calculated by the pixel drawing coordinate value calculating section, and the page number.

Further, the pixel drawing RGB value for storing the coordinate value corresponding to the pixel to be drawn, the page number and the RGB value in association with each other, the coordinate value storage unit, and the coordinates of an arbitrary pixel on the image displayed by the image display unit. , The coordinate value input section for extracting the specified coordinate value and page number specified by the user, the RGB value of the pixel specified by the coordinate value and page number extracted by the coordinate value input section, and the pixel drawing A pixel drawing RGB value extraction unit for extracting RGB values and coordinate value storage unit, and a pixel drawing RGB value display unit for displaying the RGB values extracted by the pixel drawing RGB value extraction unit as numerical values for each of red, green, and blue Is.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. Embodiment 1. FIG. 1 is a configuration diagram showing a first embodiment of a verification device for an image display logic circuit according to the present invention. In the figure, reference numeral 11 denotes a circuit connection data storage unit for giving circuit connection data that defines the connection relationship of image display logic circuits, 1
Reference numeral 2 is an input pattern signal storage unit that applies a test pattern to the input unit of the image display logic circuit, 13 is a logic simulation execution unit that performs logic simulation based on the test pattern data applied from the input pattern signal storage unit, and 14 is a logic A logic simulation result extraction unit that extracts logic signal value change information of an image signal necessary for image display during execution of simulation, 15 is based on the clock signal, horizontal synchronization signal, and vertical synchronization signal extracted by the logic simulation result extraction unit 14. , A pixel drawing coordinate value calculation unit for calculating the coordinate value of the pixel to be drawn and the page number (vertical synchronization number), 16 is a pixel to be drawn based on the RGB signal, the luminance signal, and the transmission signal extracted by the logic simulation result extraction unit 14. Pixel drawing RGB value calculation unit for calculating RGB values of 18 over the entire simulation time, the pixels are stored in association with the RGB values and the coordinate values and a page number corresponding to the pixel to be drawn drawing RG
A B value / coordinate value storage unit 17 draws each pixel based on the pixel drawing RGB value calculated by the pixel drawing RGB value calculation unit 16, the coordinate value calculated by the pixel drawing coordinate value calculation unit 15, and the page number An image display unit for displaying an image on the display device 19, and a user designates the coordinates of an arbitrary point (pixel) on an arbitrary page image displayed by the image display unit 18 by the user using a pointing device or the like.
A coordinate value input section for extracting the coordinate value and page number, 20
Is the drawing RGB value of the pixel specified by the coordinate value specified by the coordinate input unit 19 and the page number.
Pixel drawing RGB extracted from the value / coordinate value storage unit 18
A value extraction unit 21 is a pixel drawing RGB value display unit that displays the pixel drawing RGB values extracted by the pixel drawing RGB value extraction unit 20 as numerical values by dividing them into red, green, and blue.

Here, the image display logic circuit to be verified may be an element such as an LSI or a virtual model that can be used on a computer.

Next, with reference to FIG. 1 and FIG.
~ It demonstrates according to the flowchart of FIG. 2 is a flow chart of the logic simulation execution unit, FIG. 3 is a flow chart of the logic simulation result extraction unit, FIG. 4 is a flow chart of the pixel drawing coordinate value calculation unit, and FIG.
6 is a flowchart of a pixel drawing RGB value calculation unit, FIG.
Is a flowchart of the image display unit, and FIG. 7 is a pixel drawing R
FIG. 8 is a flowchart of the pixel drawing RGB value extraction unit, and FIG. 9 is a flowchart of the pixel drawing RGB value display unit.

First, the circuit connection data storage unit 11 is provided with circuit connection data to be verified (netlist data defining connection relationships between various operation models forming an image display logic circuit), and then a test pattern. Data storage 1
Input test pattern data to be input to the image display logic circuit to be verified is added to 2.

Next, according to the flowchart shown in FIG. 2, when the logic simulation execution unit 13 starts the logic simulation (Start), the input test pattern data is added to the circuit connection data provided in the circuit connection data storage unit 11. 0 is applied to the coordinate values (Px, Py) and page number (Pz) of the applied pixel to be drawn.
Is input, circuit operation (Event) is extracted, signal values output from all terminals of the elements (transistors, gates) connected to the signal line where the event occurs are extracted, and logical processing of the elements is performed. And the delay information t, the output signal value is scheduled to be output after t time.

During execution of the logic simulation, the logic simulation result extraction unit 14 extracts the horizontal synchronizing signal according to A → B of the flow chart shown in FIG. 3, and the pixel drawing coordinate value calculation unit 15 is shown in FIG. According to B → C of the flowchart shown, it is judged whether or not the horizontal synchronizing signal value has changed from the logical value 0 to the logical value 1, and when the logical value has not changed (the coordinate P _{x as it is} ,
P _y ) and the logical value has changed (the drawing coordinate P _x in the X direction is reset to 0 and 1 is added to the drawing coordinate P _y in the Y direction), and the logical simulation is performed. The result extraction unit 14 extracts the vertical synchronization signal value at the drawing coordinate value according to C → D in the flowchart shown in FIG.

Further, the pixel drawing coordinate value calculation unit 15
According to D → E of the flowchart shown in FIG.
The vertical sync signal value changed from logical value 0 to logical value 1.
It is judged whether the logical value of the vertical sync signal value has changed.
If not (page P as it is) _z) And vertical sync signal
If the logical value of the value has changed (clear the drawing area,
Page break and reset drawing position in Y direction to 0)
Page number P_zTo extract the logical simulation result
The section 14 is E → F in the flowchart shown in FIG.
The image signal is extracted according to E → G.

The logic simulation result extraction unit 14 is
The clock signal value is extracted, it is determined whether the clock signal value has changed from the logical value 0 to the logical value 1, and when the logical value of the clock signal value has changed, E → G in the flowchart shown in FIG. Therefore, 1 is added to P _x , and the image signal values (red signal value P _r , green signal value P _g , blue signal value P
_b ), background color value (BGr, BGg, BGb), semi-transmissive signal value (Blank), luminance signal value (Brightness)
s) is extracted.

Next, the pixel drawing RGB value calculation unit 16
Determines whether the semi-transmissive signal value (Blank) extracted by the logic simulation result extraction unit 14 is a logical value 1 according to the flow chart of G → H shown in FIG. The RGB value (red signal value P _r , green signal value P _g , blue signal value P _b ) is calculated by calculating the arithmetic mean of the signal and the background color value and further adding the luminance signal value to the arithmetic mean value. However, if the logical value is not 1, the image signal values (red signal value P _r , green signal value P _g , blue signal value P _b ) extracted by the logical simulation result extraction unit 14 are obtained.
The RGB value (red signal value P _r , green signal value P _g , blue signal value P _b ) is calculated by adding the luminance signal to. The RGB values (red signal value P _r , green signal value P _g , blue signal value P _b ) calculated here are signal values at the coordinates (P _x , P _y ) of the page of a certain page number P _z .

Next, the image display unit 17 displays the flow chart of FIG.
Chart drawing RGB values as shown in H → I
RGB values calculated by the calculator 16 (red signal value P_r, Green
Color signal value P_g, Blue signal value P_b) Is the page number P_zso
Coordinates of a page (P_x, P _y).

Further, as shown by I → F in the flowchart of FIG. 7, the RGB values (red signal value P _r , green signal value P _g , blue signal value P _b calculated by the pixel drawing RGB value calculation unit 16 are shown. ) Is the page number and coordinate values (P _x , P _y ,
_Pz ) and the pixel drawing RGB values are stored in the table Ptable of the coordinate value storage unit 18.

After this, the logic simulation execution unit 13
In the above, it is judged whether or not all the events at the current time have been extracted and evaluated. If not extracted and evaluated for all the events, a new event is extracted, a logical simulation is executed, and the same as above. Repeat the process.

When all the events at the current time are extracted and evaluated, it is judged whether or not the simulation is the end time, and if it is not the end time, the simulation time is advanced to the time when the next event occurs, and a new event is generated. Extraction is performed, logic simulation is executed, and the same processing as above is repeated.

If it is the end time, the user can
When the coordinates of an arbitrary pixel whose RGB value is to be confirmed are specified on the screen of No. 7 using a pointing device such as a mouse, the coordinate input unit 19 causes the coordinate value and page number (P
_x , P _y , P _z ) to obtain the pixel drawing RGB value extraction unit 2
0 is the pixel drawing RGB value of the RGB value of the coordinate input from the coordinate input unit 19 according to J → K in the flowchart shown in FIG.
pixel drawing RGB value display unit 21
According to K → END of the flowchart shown in FIG. 9, RGB values are divided into red, green, and blue and displayed as numerical values.

Further, in the flow chart shown in FIG. 3, when the clock signal value extracted by the logic simulation result extracting unit 14 has not changed from the logic value 0 to the logic value 1 (in the case of E → F), the logic The simulation execution unit 13 determines whether or not all the events at the current time have been extracted and evaluated. If all the events have not been extracted and evaluated, a new event is extracted and the same logic simulation as above is performed. To execute.

After this, all the events at the current time are extracted,
When the simulation is finished and the simulation end time comes, the coordinate input unit 19 causes the user to specify the coordinates of any pixel for which the RGB value is to be confirmed on the screen of the image display unit 17 using a pointing device such as a mouse. The coordinate value and page number (P _x , P _y , P _z ) are obtained, and the pixel drawing RGB value extraction unit 20 follows the J → K of the flowchart shown in FIG. 8 and inputs the coordinate input from the coordinate input unit 19. Of the pixel drawing RGB value and the coordinate value storage unit 18 from the table Ptable, and the pixel drawing RGB value display unit 21 follows the K → END of the flowchart shown in FIG. It is divided into blue and displayed as a numerical value.

As described above, according to the present embodiment, in order to verify whether or not the pixel at an arbitrary coordinate is correctly colored by the image signal output from the designed image display logic circuit, the image display is performed. Since it is possible to grasp the light emission state of the on-screen pixels by a numerical value, it is possible to accurately and efficiently verify the image display logic circuit.

Embodiment 2. FIG. 10 is a configuration diagram showing a second embodiment of the image display logic circuit verification device according to the present invention. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding portions.

In this embodiment, the indeterminate value discriminating unit 22 and the indefinite value generating message display unit for displaying the indefinite value generating signal name output by the indefinite value discriminating unit 22, the indefinite value generating simulation time, and the indefinite value generating pixel drawing coordinates. 23 is provided. The indefinite value is a case where the logical values 1 and 0 are not specified in the logical simulation, and usually un
The known signal is displayed.

The indefinite value discriminating unit 22 determines that any one of the RGB signal, the luminance signal, the transparent signal, the clock signal, the horizontal synchronizing signal, and the vertical synchronizing signal extracted by the logic simulation result extracting unit 14 becomes an indefinite value. If the indeterminate value signal is generated in any of the clock signal, the horizontal synchronizing signal, and the vertical synchronizing signal, the indeterminate value generating signal name and the indeterminate value extracted from the logic simulation result extracting unit 14 are determined. The generation simulation time and the pixel drawing coordinate immediately before (one clock before) extracted from the pixel drawing coordinate calculation unit 15 are output to the indefinite value generation message display unit 23, and the clock signal, the horizontal synchronizing signal, and the vertical synchronizing signal are output. Also when an indefinite value does not occur, and R
When an indeterminate value occurs in any of the GB signal, the brightness signal, and the transmission signal, the indeterminate value generation pixel drawing coordinate which is the calculation result of the pixel drawing coordinate calculation unit 15 and the undefined value extracted from the logic simulation result extraction unit 14 The generated signal name and the indeterminate value occurrence simulation time are output to the indeterminate value occurrence message display unit 23.

The operation of this embodiment will be described below. 11 is a flowchart of the logic simulation result extraction unit, FIG. 12 is a flowchart of the image display unit, and FIG. 13 is a flowchart of the indefinite value determination unit.

First, circuit connection data to be verified (netlist data defining connection relationships of various operation models forming an image display logic circuit) is added to the circuit connection data storage unit 11, and then a test pattern is added. Data storage 1
Input test pattern data to be input to the image display logic circuit to be verified is added to 2.

Next, as shown in the flow chart of FIG. 2, when the logic simulation execution unit 13 starts the logic simulation (Start), the input test pattern data is added to the circuit connection data provided in the circuit connection data storage unit 11. Is applied, 0 is input to the coordinate values (P _x , P _y ) of the pixel to be drawn and the page number (P _z ) respectively, circuit operation (Event (event)) extraction is performed, and on the signal line where the event has occurred. Signal values output from all terminals of the elements (transistors, gates) connected to are extracted, and the output signal values are scheduled to be output after t time based on the logical processing of the elements and the delay information t.

During execution of the logic simulation, the logic system
The simulation result extraction unit 14 uses the flow shown in FIG.
-Extract horizontal sync signal according to A → B on the chart
Then, the pixel drawing coordinate value calculation unit 15 causes the pixel drawing coordinate value calculation unit 15 shown in FIG.
According to B → C of the row chart, the horizontal sync signal value
Determine whether the logical value changed from logical 0 to logical 1
If the theoretical value has not changed (coordinate P as it is)_x,
P_y) And the logical value has changed (drawing in the X direction
Coordinate P_xIs reset to 0 and the drawing coordinate P in the Y direction is set. _yTo
Add 1) to calculate the drawing coordinate value
The result extraction unit 14 uses the drawing coordinate values shown in FIG.
Vertical synchronization according to C → D of the flowchart shown in
Extract the signal value.

Further, the pixel drawing coordinate value calculation unit 15
According to D → E of the flowchart shown in FIG.
The vertical sync signal value changed from logical value 0 to logical value 1.
It is judged whether the logical value of the vertical sync signal value has changed.
If not (page P as it is) _z) And vertical sync signal
If the logical value of the value has changed (clear the drawing area,
Page break and reset drawing position in Y direction to 0)
Page number P_zIs calculated and the flowchart shown in FIG.
Follow E → L.

The logic simulation result extraction unit 14
The clock signal value is extracted, and according to L → M or L → F in the flowchart shown in FIG.

According to the flow chart shown in FIG. 13, the indeterminate value discriminating unit 22 discriminates whether or not an indefinite value signal value is generated in any of the clock signal, the horizontal synchronizing signal, and the vertical synchronizing signal, and determines the indefinite value. When the signal value is generated, the indefinite value generation signal name and the indefinite value generation simulation time extracted from the logic simulation result extraction unit 14 and immediately before the extraction from the pixel drawing coordinate calculation unit 15 (1
Pixel drawing coordinates ( _Px , _Py , _Pz ) before clock)
According to F → J or F → A shown in the flowchart of FIG. 2,
The logic simulation execution unit 13 determines whether or not all the events at the current time have been extracted and evaluated. If all the events have not been extracted and evaluated, a new event is extracted and the logic simulation is executed. The same process as above is repeated.

When all the events at the current time are extracted and evaluated, it is judged whether or not the simulation end time is reached, and if it is not the end time, the simulation time is advanced to the time when the next event occurs, and a new event is generated. Extraction is performed, logic simulation is executed, and the same processing as above is repeated.

If it is the end time, the process is ended.

Further, when an indefinite value signal value is not generated in any of the clock signal, the horizontal synchronizing signal, and the vertical synchronizing signal, the clock is changed according to M → F or M → N shown in the flowchart of FIG. When it is determined whether the signal value has changed from the logical value 0 to the logical value 1 and the logical value of the clock signal value has changed, 1 is set to P _{x according} to M → N in the flowchart shown in FIG. adding to the image signal values (red signal value _{P r,} the green signal value _{P g,} blue signal value _P b), the background color value (BGR, BGG, BGb), semitransparent signal value (Blank), the luminance signal value (Brightne
After extracting (ss), N → G or N → H of the flowchart shown in FIG. 13 is followed.

In the flow chart shown in FIG.
When an indeterminate value occurs in any of the RGB signal, the luminance signal, and the transmission signal, the indeterminate value generation pixel drawing coordinate which is the calculation result of the pixel drawing coordinate calculation unit 15 and the undefined value extracted from the logic simulation result extraction unit 14 The generated signal name and the indeterminate value occurrence simulation time are output to the indeterminate value occurrence message display unit 23, and the R of the pixel for drawing the warning color (W _r , W _g , W _b ) given by the user as a constant value.
Substituting into the GB values (P _r , P _g , P _b ) and according to H → F shown in the flowchart of FIG. 12, the coordinates (P _x , P _y ) of the page of page number P _z are displayed on the image display unit 17. RGB
Draw the values (P _r , P _g , P _b ).

When an indeterminate value does not occur in any of the RGB signal, the luminance signal, and the transmission signal, pixel drawing R is performed according to the flow chart of G → H shown in FIG.
The GB value calculation unit 16 determines whether the semi-transmissive signal value (Blank) extracted by the logic simulation result extraction unit 14 is a logical value 1, and when the logical value is 1, the phase between the image signal and the background color value is determined. The RGB value (red signal value P _r , green signal value P _g , blue signal value P _b ) obtained by calculating the arithmetic mean and adding the luminance signal value to the arithmetic mean value is obtained. , The luminance signal is added to the image signal values (red signal value P _r , green signal value P _g , blue signal value P _b ) extracted by the logic simulation result extraction unit 14 to obtain RGB values (red signal value P _r , green color). The signal value P _g and the blue signal value P _b ) are calculated. The RGB values (red signal value P _r , green signal value P _g , blue signal value P _b ) calculated here are for a certain page number P _z.
Values at the page coordinates (P _x , P _y ).

As shown in H → F in the flowchart of FIG. 12, the image display unit 17 displays the RGB values (red signal value P _r , green signal value P _g , blue color) calculated by the pixel drawing RGB value calculation unit 16. The signal value P _b ) is drawn at the coordinates (P _x , P _y ) of the page with the page number P _z , and according to F → J or F → A shown in the flowchart of FIG. , It is judged whether or not all the events at the current time have been extracted and evaluated, and if all the events have not been extracted and evaluated, a new event is extracted, a logical simulation is executed, and the same processing as above is performed. repeat.

When all the events at the current time are extracted and evaluated, it is judged whether or not it is the simulation end time, and if it is not the end time, the simulation time is advanced to the time when the next event occurs, and a new event is generated. Extraction is performed, logic simulation is executed, and the same processing as above is repeated.

If it is the end time, the process is ended.

As described above, according to the present embodiment, when various image signals are not normally output and have logical indefinite values, the coordinates and signal names where the indefinite values occur during drawing are displayed to the user. Therefore, the debug efficiency of the logic design of the image display logic circuit is improved.

Embodiment 3. In the present embodiment, the pixel rendering RGB value, coordinate value storage unit, pixel rendering RGB value extraction unit, coordinate value input unit and pixel rendering RGB value display unit in the second embodiment are similar to those in the first embodiment. Be prepared.

In this embodiment, the pixel drawing R
RGB value (red signal value P_r, Green signal value
P_g, Blue signal value P_b) Is calculated, the
Before determining an indeterminate value, page number and coordinate value (P_x,
P_y, P_z), Pixel drawing RGB values, coordinates
RGB values calculated in the table Ptable in the standard value storage unit
(Red signal value P_r, Green signal value P_g, Blue signal value P_b)
Save the image and draw it in the image display area.
Calculated RGB value (red signal value P_r, Green signal value
P_g, Blue signal value P_b) Is the page number P_zWhich is
The coordinates of P (P_x, P _y), Then from the coordinate input section
Pixel drawing RGB values by specifying pixels in the image display area
Pixel drawing RG for the RGB values of the coordinates specified by the extraction unit
Extracted from table Ptable of B value and coordinate value storage
Then, the pixel drawing RGB value display section displays the RGB value in red,
The values are displayed separately for green and blue.

According to the present embodiment, the above-mentioned first embodiment
Similarly, since it is possible to grasp the light emission state of the pixels on the screen on which the image is displayed, it is possible to accurately and efficiently verify the image display logic circuit.

FIG. 2 in the first to third embodiments described above.
~ By recording the steps shown in the flowcharts of Fig. 9 and Fig. 11 to Fig. 13 on a recording medium and using them in a computer, it is possible to easily modify the program for the occurrence of indefinite values and the like.

[0048]

According to the image display logic circuit verification device of the present invention, the circuit connection data storage unit storing the circuit connection data defining the connection relation of the image display logic circuit, and the image display logic circuit. An input pattern signal storage unit that stores input test pattern data to be applied to the input unit, a logic simulation execution unit that executes a logic simulation of the image display logic circuit based on the circuit connection data and the input test pattern data, and the logic A logic simulation result extraction unit that extracts a logic signal value change of an image signal during execution of the simulation execution unit, and coordinates of pixels to be drawn based on the clock signal, horizontal synchronization signal, and vertical synchronization signal extracted by the logic simulation result extraction unit A pixel drawing coordinate value calculation unit that calculates the value and the page number, and the logical system A pixel drawing RGB value calculation unit that calculates the RGB value of the pixel to be drawn based on the RGB signal, the luminance signal, and the transmission signal extracted by the simulation result extraction unit, the coordinate value corresponding to the pixel to be drawn, the page number, and the RGB value. Each pixel is drawn based on the pixel drawing RGB value, the coordinate value storage unit, the RGB value calculated by the pixel drawing RGB value calculation unit, the coordinate value calculated by the pixel drawing coordinate value calculation unit, and the page number. The image display section for displaying the image, the coordinate value input section for extracting the specified coordinate value and the page number by the user specifying the coordinate of any pixel on the image displayed by the image display section, and the coordinate The RGB value of the pixel specified by the coordinate value extracted by the value input section and the page number is converted into the pixel drawing RGB value, coordinate Pixel draw RGB value extraction unit for extracting from the storage unit, the pixel draw RG
It is equipped with a pixel drawing RGB value display unit that displays the RGB values extracted by the B value extraction unit numerically for each of red, green, and blue. However, the verification of the image display logic circuit can be performed accurately and efficiently.

Further, a circuit connection data storage section storing circuit connection data defining the connection relationship of the image display logic circuit, and an input pattern signal storing input test pattern data applied to the input section of the image display logic circuit. A storage unit, a logic simulation execution unit that executes a logic simulation of the image display logic circuit based on the circuit connection data and the input test pattern data, and extracts a logic signal value change of an image signal during execution of the logic simulation execution unit. A logical simulation result extraction unit, a pixel drawing coordinate value calculation unit that calculates a coordinate value of a pixel to be drawn and a page number based on the clock signal, the horizontal synchronization signal, and the vertical synchronization signal extracted by the logical simulation result extraction unit, RGB signals extracted by the logic simulation result extraction unit, Degree signal, transmission signal, based on,
Pixel drawing R for calculating the RGB value of the pixel to be drawn
It is determined whether or not any one of the RGB signal, the luminance signal, the transparent signal, the clock signal, the horizontal synchronizing signal, and the vertical synchronizing signal extracted by the GB value calculating unit and the logic simulation result extracting unit has an indefinite value. If an indeterminate value is generated in any of the clock signal, the horizontal synchronizing signal, and the vertical synchronizing signal, the indeterminate value generating signal name and the indeterminate value generating simulation extracted from the logic simulation result extracting unit are determined. The time and the pixel drawing coordinate value extracted from the pixel drawing coordinate value calculation unit are output to the indefinite value generation message display unit that displays the pixel drawing coordinates one clock before, and are output to any of the clock signal, horizontal synchronization signal, and vertical synchronization signal. If an indeterminate value does not occur and any of the RGB signals, luminance signals, and transmission signals has an indeterminate value, then The indeterminate value generation pixel drawing coordinates calculated by the xcel drawing coordinate value calculation unit, and the indeterminate value generation signal name and the indeterminate value generation simulation time extracted from the logic simulation result extraction unit are output to the indeterminate value generation message display unit. Section, an image display section for drawing and displaying an image of each pixel based on the RGB value calculated by the pixel drawing RGB value calculating section, the coordinate value calculated by the pixel drawing coordinate value calculating section, and the page number. , When the various image signals are not output normally and become the logic indeterminate value, the coordinates and signal name where the indeterminate value occurs during drawing are displayed to the user, which improves the debug efficiency of the logic design of the image display logic circuit. improves.

Further, the pixel drawing RGB value which stores the coordinate value corresponding to the pixel to be drawn, the page number and the RGB value in association with each other, the coordinate value storage unit, and the coordinates of an arbitrary pixel on the image displayed by the image display unit. , The coordinate value input section for extracting the specified coordinate value and page number specified by the user, the RGB value of the pixel specified by the coordinate value and page number extracted by the coordinate value input section, and the pixel drawing A pixel drawing RGB value extraction unit for extracting RGB values and coordinate value storage unit, and a pixel drawing RGB value display unit for displaying the RGB values extracted by the pixel drawing RGB value extraction unit as numerical values for each of red, green, and blue Therefore, the light emission state of the pixels on the screen where the image is displayed is grasped numerically, and the verification of the image display logic circuit is accurately performed.
And can be done efficiently.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of an image display logic circuit verification device according to the present invention.

FIG. 2 is a flowchart of a logic simulation execution unit according to the first embodiment.

FIG. 3 is a flowchart of a logic simulation result extraction unit according to the first embodiment.

FIG. 4 is a flowchart of a pixel drawing coordinate value calculation unit in the first embodiment.

FIG. 5 is a flowchart of a pixel drawing RGB value calculation unit in the first embodiment.

FIG. 6 is a flowchart of the image display unit according to the first embodiment.

FIG. 7 is a pixel drawing RGB according to the first embodiment.
6 is a flowchart of a value / coordinate value storage unit.

FIG. 8 is a flowchart of a pixel drawing RGB value extraction unit according to the first embodiment.

FIG. 9 is a flowchart of a pixel drawing RGB value display unit in the first embodiment.

FIG. 10 is a configuration diagram showing a second embodiment of the image display logic circuit verification device according to the present invention.

FIG. 11 is a flowchart of a logic simulation result extraction unit according to the second embodiment.

FIG. 12 is a flowchart of an image display unit according to the second embodiment.

FIG. 13 is a flowchart of an indefinite value determination unit according to the second embodiment.

[Explanation of symbols]

11 circuit connection data storage unit, 12 test pattern data storage unit, 13 logic simulation execution unit, 14
Logical simulation result extraction unit, 15 pixel drawing coordinate value calculation unit, 16 pixel drawing RGB value calculation unit,
17 image display section, 18 pixel drawing RGB value, coordinate value storage section, 19 coordinate value input section, 20 pixel drawing R
GB value extraction unit, 21 pixel drawing RGB value display unit, 2
2 indeterminate value discriminating section, 23 indeterminate value occurrence message display section.

Claims (3)

[Claims] 1. A circuit connection data storage unit storing circuit connection data defining a connection relation of an image display logic circuit, and an input pattern signal storing input test pattern data applied to an input unit of the image display logic circuit. A storage section, a logic simulation execution section that executes a logic simulation of the image display logic circuit based on the circuit connection data and the input test pattern data, and a logic signal value change of an image signal is extracted during execution of the logic simulation execution section. A logic simulation result extraction unit, a pixel drawing coordinate value calculation unit that calculates a coordinate value and a page number of a pixel to be drawn based on the clock signal, the horizontal synchronization signal, and the vertical synchronization signal extracted by the logic simulation result extraction unit, RGB extracted by the logic simulation result extraction unit
A pixel drawing RGB value calculation unit that calculates the RGB value of a pixel to be drawn based on a signal, a luminance signal, and a transmission signal, and a pixel drawing RGB that stores the coordinate value corresponding to the pixel to be drawn, the page number, and the RGB value in association with each other.
A value, a coordinate value storage unit, an image display unit that draws each pixel and displays an image based on the RGB value calculated by the pixel drawing RGB value calculation unit, the coordinate value calculated by the pixel drawing coordinate value calculation unit, and the page number, A coordinate value input unit that extracts the designated coordinate value and page number by the user designating the coordinates of an arbitrary pixel on the image displayed by the image display unit, and the coordinates extracted by the coordinate value input unit. The RGB value of the pixel specified by the value and the page number is the pixel drawing R
Pixel drawing RGB extracted from GB value and coordinate value storage
A value extraction unit, a pixel drawing RGB that displays the RGB values extracted by the pixel drawing RGB value extraction unit as numerical values for each of red, green, and blue
An apparatus for verifying a logic circuit for image display, comprising a value display unit. 2. A circuit connection data storage unit that stores circuit connection data that defines the connection relationship of the image display logic circuit, and an input pattern signal that stores input test pattern data applied to the input unit of the image display logic circuit. A storage section, a logic simulation execution section that executes a logic simulation of the image display logic circuit based on the circuit connection data and the input test pattern data, and a logic signal value change of an image signal is extracted during execution of the logic simulation execution section. A logic simulation result extraction unit, a pixel drawing coordinate value calculation unit that calculates a coordinate value and a page number of a pixel to be drawn based on the clock signal, the horizontal synchronization signal, and the vertical synchronization signal extracted by the logic simulation result extraction unit, RGB extracted by the logic simulation result extraction unit
A pixel drawing RGB value calculation unit that calculates the RGB value of the pixel to be drawn based on the signal, the luminance signal, and the transmission signal, and the RGB extracted by the logic simulation result extraction unit.
Signal, luminance signal, transparent signal, clock signal, horizontal synchronizing signal, vertical synchronizing signal is discriminated whether or not the signal has an indefinite value, the clock signal, horizontal synchronizing signal, vertical synchronizing signal of the above If an indefinite value occurs in any of the above, the indefinite value generation signal name and the indefinite value generation simulation time extracted from the logic simulation result extraction unit and one clock extracted from the pixel drawing coordinate value calculation unit Output to the indefinite value generation message display section that displays the previous pixel drawing coordinates, and the clock signal,
When an indeterminate value does not occur in any of the horizontal synchronizing signal and the vertical synchronizing signal, and when an indeterminate value occurs in any of the RGB signal, the luminance signal and the transmission signal, the pixel An indeterminate value determination unit that outputs the indeterminate value generation pixel drawing coordinates calculated by the drawing coordinate value calculation unit, the indeterminate value generation signal name and the indeterminate value generation simulation time extracted from the logic simulation result extraction unit to the indeterminate value generation message display unit An image display unit for drawing and displaying each pixel based on the RGB value calculated by the pixel drawing RGB value calculation unit, the coordinate value calculated by the pixel drawing coordinate value calculation unit, and the page number is provided. Image display logic circuit verification device. 3. A pixel drawing RGB value that stores a coordinate value corresponding to a pixel to be drawn, a page number, and an RGB value in association with each other, a coordinate value storage unit, and a coordinate of an arbitrary pixel on an image displayed by the image display unit. A coordinate value input section for extracting a designated coordinate value and a page number specified by the user; an RGB value of a pixel specified by the coordinate value and the page number extracted by the coordinate value input section; RG
Pixel drawing RGB value extraction unit that extracts from the B value and coordinate value storage unit, and pixel drawing RGB that displays the RGB values extracted by the pixel drawing RGB value extraction unit as numerical values for each of red, green, and blue
3. The image display logic circuit verification device according to claim 2, further comprising a value display unit.