JP2003316612A - Device for automatically preparing reduction program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prepare a reduction program capable of the performance evaluation of the same level as a benchmark program while keeping the characteristics of the benchmark program regarding a device for automatically preparing the reduction program. <P>SOLUTION: The device is provided with a highly frequently processed part extraction part, a repetition number-of-times control part and a data amount reduction control part. The file forms of input, output and the output of respective processing parts are equalized, it is made possible to interrupt a processing in the respective processing parts and it is made possible to continue the processing from the processing part in the middle. An outermost loop part including a highly frequently processed function is detected in the highly frequently processed part extraction part and the program part is extracted. In the repetition number-of-times control part, the change of the processing by the number of times of repetition is checked from a counter value inside hardware, the number of times of the repetition is reduced to one in the case that there is no change, and the number of times of the repetition is reduced to one by making the processings before and after the change coexist even in the case that the number of times of the repetition can not be simply reduced to one for the processing in the middle of the repetition. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

The present invention relates to a processor (CP
(U, MPU, etc.) When designing (U, MPU, etc.), the present invention relates to a reduced program automatic creation apparatus for automatically creating a reduced program obtained by reducing an allocation program for performance evaluation by a logic simulator.

In recent years, processor performance has been remarkably improved due to technological advances. In conjunction with this, a group of application programs that evaluate the performance of the processor (this is called a "benchmark program") also has a large number of instructions and a large amount of data, which is complicated.

It takes several months to operate this application program by a logic simulator that operates at tens of thousands of the actual speed, and the entire execution is executed by the logic simulator to verify the logic circuit of the developed processor. It is impossible to estimate performance or performance in a realistic time.

However, there is a demand for evaluation using a logic simulator in an early stage of processor design and feedback to the processor for development. For this reason,
It is necessary to reduce the number of instructions that can be executed in a realistic time by the logic simulator while maintaining the characteristics of the original program.

[0005]

2. Description of the Related Art A conventional example will be described below.

The conventional verification and performance evaluation on the logic simulator at the time of processor design have been performed using a test program or a small application program having a relatively small number of instructions. However, since these small program groups are not generally large-sized benchmark programs used for processor performance evaluation, they cannot be compared with the performance of processors developed by other companies early in processor design during logic circuit verification. Also, because of the huge number of instructions, it takes several months to execute a benchmark program with a logic simulator.

[0007]

SUMMARY OF THE INVENTION The above-mentioned conventional device has the following problems.

Conventionally, the verification and performance evaluation of a benchmark program by a logic simulator cannot be executed in a realistic time, and the processor design at the time of logic circuit verification cannot be compared with the performance of a processor developed by another company at an early stage. It was

The present invention solves such a conventional problem, and automatically maintains a reduced program capable of performance evaluation at the same level as that of the benchmark program while maintaining the characteristics of the benchmark program (reduction target application program). The purpose is to create.

[0010]

In order to achieve the above object, the present invention has the following constitution.

(1): A reduced program automatic creation apparatus for reducing the number of instructions while retaining the characteristics of the application program, which is a high frequency processing part for extracting a high frequency processing part from the application program to be reduced. An extraction unit, a repetition number control unit that controls the number of repetitions, and a data amount reduction control unit that performs data amount reduction control are provided, and the file formats of the input and output and the output of each processing unit are made equal to each other. With the function that enables the processing to be interrupted at, and the processing can be continued from an intermediate processing unit, and the high-frequency processing part extraction unit detects the outermost loop location including the high-frequency processing function and extracts the program location. With the function and the repeat count control unit, the change in processing due to the repeat count is investigated from the counter value inside the hardware. Even if it is not possible to reduce the number of iterations to one once in the middle of the iteration, it is possible to reduce the number of iterations to one by mixing the processing before and after the change. A reduction program automatic creation device characterized in that

(2): In the reduction program automatic creation apparatus of the above (1), the data reduction control unit includes control means for recognizing an access pattern of a variable and selecting a variable that can be reduced. To do.

(3): In the reduction program automatic creation apparatus of (1), the data amount reduction control unit is provided with deciding means for recognizing the cache capacity and determining the reduction amount of the data amount. Characterize.

(4): In the reduction program automatic creation apparatus of (1) above, the data amount reduction control unit is provided with control means for changing the address of the access variable to reproduce the cache capacity miss. It is characterized by

(5): The reduced program automatic creation apparatus of the above (1) is characterized in that it has a function of judging the similarity between the original program and the reduced program by the cache miss rate.

(Operation) The operation of the present invention based on the above configuration will be described.

(A): In the above (1), the high-frequency processing part extraction section extracts the high-frequency processing section from the application program to be reduced, and the repetition number control section controls the repetition number to obtain the data amount. The reduction control unit performs a data amount reduction process, thereby performing a process of reducing the number of instructions while maintaining the characteristics of the reduction target application program.

In this case, the file formats of the input and output and the output of each processing unit are made equal, the processing can be interrupted in each processing unit, and the processing can be continued from the processing unit in the middle. Further, the high-frequency processing portion extraction unit detects the outermost loop location including the high-frequency processing function and extracts the program location.

Further, the repeat count control unit investigates the change in the process depending on the repeat count from the counter value in the hardware, reduces the repeat count to one when there is no change, and simply repeats the process in the middle of the repeat. Even if the number of times cannot be reduced to once, the number of repetitions can be reduced to one by mixing the processes before and after the change.

With this configuration, the intermediate files output by the three types of processing units (the high-frequency processing portion extraction unit, the repetition number control unit, and the data amount reduction control unit) are the input reduction target program and the execution module. Since the file formats are the same, the processing can be interrupted halfway and saved as an intermediate file, and the processing can be continued from the middle of each processing unit using the intermediate file as an input. That is, since it is possible to easily end the process in the middle of the process and start the process in the middle of the process, the operator or the like can freely use the time and the work efficiency is extremely good.

Furthermore, it is possible to evaluate the performance at the same level as the benchmark program while maintaining the characteristics of the benchmark program (reduction target application program). By executing the reduced program created by the reduced program automatic generator with a logic simulator, the performance of the benchmark program can be predicted and verified in a realistic time, which contributes to shortening the period of design and development of the development processor and retuning. There is a lot to do.

(B): In the above (2), the control process of the data reduction control unit recognizes the access pattern of the variable and selects the variable that can be reduced.

In this way, performance evaluation at the same level as the benchmark program can be performed while maintaining the characteristics of the benchmark program. By executing the reduced program created by the reduced program automatic generator with a logic simulator, the performance of the benchmark program can be predicted and verified in a realistic time, which contributes to shortening the period of design and development of the development processor and retuning. There is a lot to do.

(C): In the above (3), the determining means of the data amount reduction control unit recognizes the capacity of the cache and determines the reduction size of the data amount. This makes it possible to perform performance evaluation at the same level as the benchmark program while maintaining the characteristics of the benchmark program. By executing the reduced program created by the reduced program automatic generator with a logic simulator, the performance of the benchmark program can be predicted and verified in a realistic time, which contributes to shortening the period of design and development of the development processor and retuning. There is a lot to do.

(D): In the above (4), the control means of the data amount reduction control unit reproduces the cache variable miss by changing the address of the access variable.

In this way, the cache miss rate can be made equal even if the data amount is reduced. In addition, it is possible to perform performance evaluation at the same level as the benchmark program while maintaining the characteristics of the benchmark program. By executing the reduced program created by the reduced program automatic generator with a logic simulator, the performance of the benchmark program can be predicted and verified in a realistic time, which contributes to shortening the period of design and development of the development processor and retuning. There is a lot to do.

(E): In the above (5), the reduced program automatic creation apparatus judges the similarity between the original program and the reduced program based on the cache miss rate. This makes it possible to perform performance evaluation at the same level as the benchmark program while maintaining the characteristics of the benchmark program. By executing the reduced program created by the reduced program automatic generator with a logic simulator, the performance of the benchmark program can be predicted and verified in a realistic time, which contributes to shortening the period of design and development of the development processor and retuning. There is a lot to do.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

§1: Description of the entire reduction program automatic creation apparatus FIG. 1 is an explanatory diagram of the reduction program automatic creation apparatus. As shown in FIG. 1, the high-frequency processing part extraction unit 1 receives a benchmark program (application program to be reduced) and an execution module as an input, and intermediates the program and the execution module from which the high-frequency processing part is extracted. It is to be newly created as a file.

The repeat count control unit 2 receives the program and execution module created by the high frequency processing part extraction unit 1 and newly creates a program and its execution module with a reduced repeat count as an intermediate file. The data amount reduction control unit 3 inputs the program and the execution module created by the repetition number control unit 2 and creates a program and an execution module with a reduced data amount.

As described above, the reduced program automatic creation apparatus includes three types of processing units, which are the high frequency processing portion extraction unit 1, the repetition number control unit 2, and the data amount reduction control unit 3. The intermediate file output by each processing unit has the same file format as the input reduction target program or execution module, so processing is interrupted and saved as an intermediate file, and the intermediate file is input from the middle of each processing unit. It is possible to continue processing.

As described above, since the processing can be ended in the middle of the processing or the processing can be continued from the middle of the processing, the time is free and the work efficiency is good. Moreover, since the reduction program and the execution module are stored as a set as an intermediate file, the processing can be ended once and the reduction program creation processing can be started halfway.

§2: Detailed Explanation of High Frequency Processing Part Extraction Unit FIG. 2 is an explanatory diagram of the high frequency processing part extraction unit. As shown in FIG. 2, the high frequency processing part extraction unit 1 operates by inputting a benchmark program and an execution module to be reduced. Further, in the high-frequency processing portion extraction unit 1, the profiler 14 outputs the main function in the program and its processing time ratio (profiler information).

The outermost loop detection unit 11 in FIG. 2 receives profile information and a threshold value α for high-frequency processing, recognizes a function equal to or more than that value as a high-frequency processing function, and detects the outermost loop location of the function. . The program generation unit 12 extracts the outermost loop location from the program and creates a high-frequency processing extraction program as a new intermediate file.

The execution module generation unit 13 compiles the high frequency process extraction program by the compiler 15 to create a high frequency process extraction execution module as an intermediate execution module. It should be noted that the threshold value α used is one that the operator has previously input. The profiler 14 refers to a tool for analyzing the operation of a program.

§3: Detailed Description of Repeat Count Control Section (See FIGS. 3 and 4) FIG. 3 is an explanatory diagram of the repeat count control section. Also, FIG.
Is a diagram for explaining the behavior change in the loop rotation speed reduction unit. In FIG. A, the behavior does not change. → It is possible to reduce the number of repetitions to 1 time. In Fig. B, the behavior changes. → It is simply reduced to 1 repetition number. Yes, FIG. C shows an explanatory diagram of the program generation unit by reducing the number of repetitions. Further, in FIG. 4C, C-1 is the original program code, C-2
Indicates loop reduction program code.

The repetition number control unit 2 operates with the intermediate file and the execution module output from the high frequency processing part extraction unit 1 as inputs. Behavior investigation part 2 by the number of loops
1 starts the hardware counter 26 (counter inside the CPU), and every time the loop count (the loop count of the program) ends once, the number of instructions M (M:
It outputs the mega step) and the secondary cache miss rate (%).

The loop rotation speed reduction unit 22 detects a behavior change of the loop from the output result of the behavior investigation unit 21 according to the number of loops. Behavior changes are changes in the number of loops and instructions,
It is performed by changing the number of loops and the secondary cache miss rate.

For example, as shown in FIG. 4A, if the number of loops is proportional to the number of instructions and the secondary cache miss rate is constant even if the number of loops changes, the behavior does not change between the loops. That is, the behavior of one loop is considered to reflect the behavior of all loops, and the loop rotation speed can be reduced to one loop.

The program generator 24 newly generates a program code having a loop rotation speed of 1.
On the other hand, as shown in FIG. 4B, when the number of loops and the number of instructions are not proportional and the secondary cache miss rate changes as the number of loops changes, the behavior of one loop is It cannot be said that the behavior is reflected, and it cannot simply be reduced to one loop. Therefore, the behavior change point investigation unit 23 detects and investigates a portion where the behavior changes between the loops.

In C-1 of FIG. 4C, the function funcA ()
Is processed 250 times, and the function funcB () becomes (4000-2
Since it is processed 50 times, the behavior is different before and after the loop processing. The number of times the processing behavior changes between loops and the changed loop number (250 in this example) are detected.

The behavior change point investigation unit 23 detects one change count because the process changes in the 250th loop out of 4000 total loop counts, and changes loop number 2
Detect 50. The program generation unit 24 receives the information of the behavior change point investigation unit 23 and creates a program for reducing one loop.

C-2 in FIG. 4C shows a program code for one-loop extraction which is automatically generated by the program generating section 24. The number of loops is reduced to one, and a program code is newly generated in which the processing ratios of the respective functions funcA () and funcB () are determined by the ratio of the loop rotation speed.

As described above, the repeat count control unit 2 investigates the change in the process depending on the repeat count from the internal counter value of the hardware. If there is no change, the repeat count is reduced to one and the process is repeated. Even if it is impossible to simply reduce the number of repetitions to one, it is possible to reduce the number of repetitions to one by mixing the processes before and after the change.

After that, the execution module generation unit 25 compiles the program automatically generated by the program generation unit 24, and repeatedly creates a reduction execution module as an intermediate execution module.

§4: Detailed description of data amount reduction control unit (see FIGS. 5, 6, and 7) FIG. 5 is an explanatory diagram of the data amount reduction control unit. In addition, FIG.
Is a variable access analysis diagram in the reduced variable selection unit and an explanatory diagram of a program generation unit in data amount reduction,
The figure is a variable access analysis diagram in the reduced variable selection unit, and the diagram B is an explanatory diagram of the program generation unit in the data amount reduction. Further, in FIG. 6A, (a) shows a variable that can be reduced and (b) shows a variable that cannot be reduced. Further, in FIG. 6B, (a) shows the original program code and (b) shows the data reduction program code.

FIG. 7 is an explanatory diagram of a method of reproducing the cache miss rate in reducing the amount of data. (A) is the original program code, (b) is the code in which no cache miss occurs, and (c) is the cache. Indicates the code that makes the mistake.

The data amount reduction control unit 3 operates with the intermediate file and the execution module output from the repeat count control unit 2 as inputs. The reduced variable selection unit 31 decodes the variable access pattern and selects a variable that can be reduced.

In FIG. 6, (a) in FIG. 6A is a variable in which the width of the access stride does not change by reducing the data size. For example, double a [100] [10
[0] array data is accessed sequentially from the first dimension, the second dimension accessed later can be reduced. This is because the access to the cache line does not change even if the reference area is reduced.

In FIG. 6, (b) of FIG. 6A is a variable in which the width of the access stride changes by reducing the data size. For example, double b [100] [100]
If the array data is accessed stride from the second dimension, the stride width of the variable access will be different from the original access if the first dimension accessed after processing is reduced, and the cache to be accessed Since the line positions are also different, the cache miss rate of the original program cannot be reproduced.

Therefore, the reduced variable selection unit 31 decodes the variable access pattern and selects a variable that has not been stride-accessed.

The reduced size determination unit 32 inputs the secondary cache size of the processor (for example, CPU) to be developed, and determines the reduced size of the variable. The original program has a large variable size, so a large amount of data is referenced and the data is frequently flushed from the cache, resulting in a high cache miss rate.

On the other hand, if the size of the variable is reduced too much, the area to be referred to will be reduced, so that the data will remain in the cache, it will be difficult to flush the data from the cache, and the cache miss rate will be low. Therefore, the size to be reduced must be a size at which flushing from the cache occurs, and the size to be reduced is determined to be equal to or larger than the size of the secondary cache.

Variables to be reduced are selected from those having a large size. For example, if the size of the secondary cache is 8 Kbytes, the size of the one-dimensional array double a [] is 8 Kbytes.
The array size of the array a is determined and reduced as described above. If the array a of the original program is smaller than the cache size, the array size is not reduced.

The program generator 33 generates a program code with a reduced variable size, and accordingly generates a program code with a reduced loop rotation speed that governs the reduced variable. For example, (b) of FIG. 6B shows an example in which the size of the array a is reduced from 10,000 to 500, and the number of rotations of the loop is also reduced from 10,000 to 500.

The execution module generation unit 34 compiles the program automatically generated by the program generation unit 33 by the compiler to generate a data amount reduction execution module as an intermediate execution module. In this execution module, the cache miss rate examining unit 35 measures the cache miss rate by a cache simulator 38 having a cache configuration of a development processor (for example, CPU). If this error rate is substantially the same as the error rate of the original program, the created reduction program and execution module are output as the final reduction execution module.

On the other hand, if the cache miss rate of the original program is clearly different, the generated reduced program and execution module are not certified as reduced. The cause of this is that the influence of the program code change of FIG. 6B, (b), occurred at a processing location other than that of FIG. 6B, (b).

FIG. 7A shows the original program code, and since the areas referred to by both processes C and D are sufficiently large, a cache miss occurs. In FIG. 7B, a cache miss occurs because the size of the array data is reduced and the program code is changed so that a cache miss occurs in the process C. However, in the process D, the array data a referred to is the process C. It remains in the cache, and since the data is referenced in the process D, no cache miss occurs.

In the cache behavior reproducing unit 36, the program code and the execution module are reproduced to cope with this. In FIG. 7C, the reference address of the process D is set to the process C.
The miss rate is reproduced by changing the address of the access variable so that it is different from the address that was not used and using the address that is not left in the cache.

For the change in the program, a program code in which the index of the array data is changed is generated. This code becomes an execution module again by the compiler, is compared with the miss rate of the original program by the cache miss rate examining unit 35, and if they are almost the same, it is output as a reduced program and an execution module.

The execution modules created by the repeat count control unit 2 and the data amount reduction control unit 3 shown in FIG. 1 define the equivalence between the original program and the reduced program by the degree of similarity of the secondary cache miss rate. The secondary cache miss rate has a large latency because it causes access to the main memory and greatly affects the performance of the processor (for example, CPU). Therefore, the secondary cache miss rate is made equal and used for performance evaluation of the reduced program. To do.

§5: Description of Specific Device Example and Recording Medium FIG. 8 shows a specific device example. The reduction program automatic creation apparatus shown in FIG. 1 can be realized by, for example, the apparatus shown in FIG. This device example is a device realized by an arbitrary computer such as a personal computer or a workstation, and includes a computer main body 41,
The computer main body 41 includes a display device 42, an input device 43 such as a keyboard and a mouse, a removable disk drive (RDD) 44, and a magnetic disk device (MDD) 45.

Then, in the computer main body 41, a CPU (central processing unit) 4 for performing various controls inside the apparatus, etc.
6. R for storing data such as various parameters
An OM (nonvolatile memory) 47, a memory 48 used by the CPU 46 for work, an interface control unit 49 for performing interface control with an external I / O device, a communication control unit 50 for performing communication control with the outside, and the like are provided. There is.

The processing performed by the apparatus shown in FIG. 1 is performed in advance, for example, on a hard disk drive (HDD) 45.
The program stored (recorded or stored) in the magnetic disk of the above is read under the control of the CPU 46, and the C
This is performed by executing the program read by the PU 46.

However, the present invention is not limited to such an example, and for example, a program is stored in the magnetic disk of the hard disk device 45 as follows, and the CPU 46 executes this program to perform the above processing. It is also possible.

Read by a removable disk drive 44 a program (program data created by another device) stored in a removable disk created by another device (floppy disk, CD-ROM, other optical disk, etc.). , On the recording medium (magnetic disk) of the hard disk device 45.

Data such as a program transmitted from another device via a communication line such as a LAN or the Internet is received via the communication control unit 50, and the data is recorded on the recording medium (magnetic disk) of the hard disk device 45. To store.

(Supplementary Note) The following configuration is supplementary to the above description.

(Supplementary Note 1) An apparatus for automatically creating a reduced program for reducing the number of instructions while retaining the characteristics of the application program, which is a high-frequency processing portion for extracting a high-frequency processing portion from the application program to be reduced. An extraction unit, a repetition number control unit that controls the number of repetitions, and a data amount reduction control unit that performs data amount reduction control are provided, and the file formats of the input and output and the output of each processing unit are made equal to each other. A function that enables the processing to be interrupted by the processing unit and that the processing can be continued from the processing unit in the middle, and a function that the outermost loop portion including the high-frequency processing function is detected by the high-frequency processing portion extraction unit and the program portion is extracted. Then, the repeat count control unit checks the change in processing depending on the repeat count from the counter value inside the hardware, and if there is no change, repeat count Even if it is not possible to reduce the number of iterations to one once in the middle of the iteration, it is possible to reduce the number of iterations to one by mixing the processing before and after the change. A reduction program automatic creation device characterized in that

(Supplementary Note 2) The data reduction control unit includes control means for recognizing an access pattern of a variable and selecting a variable that can be reduced. apparatus.

(Supplementary Note 3) The data amount reduction control unit is provided with a determining means for recognizing the capacity of the cache and determining a reduction amount of the data amount (Supplementary Note 1).
Automatic reduction program creation device described.

(Supplementary Note 4) The data amount reduction control unit is provided with control means for reproducing by changing the address of the access variable in order to reproduce the cache capacity miss (Supplementary Note 1). Automatic reduction program creation device.

(Supplementary note 5) The reduced program automatic creation apparatus according to (Supplementary note 1), which is provided with a function of determining the similarity between the original program and the reduced program based on the cache miss rate.

(Supplementary Note 6) A function of making the input and output and the output of each processing unit have the same file format in the computer so that the processing can be interrupted in each processing unit and the processing can be continued from an intermediate processing unit, The high-frequency processing part extraction unit detects the outermost loop location containing the high-frequency processing function and extracts the program location, and the repeat count control unit investigates the change in processing due to the number of repeats from the internal counter value of the hardware. However, if there is no change, reduce the number of repetitions to one,
Even if it is not possible to reduce the number of repetitions to one in the middle of the repetition, record the program to realize the function that can reduce the number of repetitions to one by mixing the processing before and after the change. Computer readable recording medium.

(Supplementary Note 7) A function of making the input and output and the output of each processing unit have the same file format in the computer so that the processing can be interrupted in each processing unit and the processing can be continued from an intermediate processing unit, The high-frequency processing part extraction unit detects the outermost loop location containing the high-frequency processing function and extracts the program location, and the repeat count control unit investigates the change in processing due to the number of repeats from the internal counter value of the hardware. However, if there is no change, reduce the number of repetitions to one,
A program that realizes a function that can reduce the number of repetitions to one by mixing the processing before and after the change even if the number of repetitions cannot be reduced to one during the repetition.

[0076]

As described above, the present invention has the following effects.

(1): In claim 1, the high-frequency processing part extraction unit extracts the high-frequency processing part from the application program to be reduced, and the repetition number control unit controls the repetition number to reduce the data amount. The control unit performs a data amount reduction process, thereby performing a process of reducing the number of instructions while retaining the characteristics of the reduction target application program.

In this case, the file formats of the input and output and the output of each processing unit are made equal, the processing can be interrupted in each processing unit, and the processing can be continued from the processing unit in the middle. Further, the high-frequency processing portion extraction unit detects the outermost loop location including the high-frequency processing function and extracts the program location.

Further, the repeat count control unit investigates the change in the process depending on the repeat count from the internal counter value of the hardware, reduces the repeat count to one when there is no change, and simply repeats the process in the middle of the repeat. Even if the number of times cannot be reduced to once, the number of repetitions can be reduced to one by mixing the processes before and after the change.

In this way, the intermediate files output by the three types of processing units (the high-frequency processing portion extraction unit, the repeat count control unit, and the data amount reduction control unit) are the same as the input reduction target program and execution module. Since the file formats are the same, the processing can be interrupted halfway and saved as an intermediate file, and the processing can be continued from the middle of each processing unit using the intermediate file as an input. That is, since it is possible to easily end the process in the middle of the process and start the process in the middle of the process, the operator or the like can freely use the time and the work efficiency is extremely good.

Further, it is possible to evaluate the performance at the same level as the benchmark program while maintaining the characteristics of the benchmark program (reduction target application program). By executing the reduced program created by the reduced program automatic generator with a logic simulator, the performance of the benchmark program can be predicted and verified in a realistic time, which contributes to shortening the period of design and development of the development processor and retuning. There is a lot to do.

(2): In claim 2, the control process of the data reduction control unit recognizes the access pattern of the variable and selects the variable that can be reduced.

In this way, it is possible to evaluate the performance at the same level as the benchmark program while maintaining the characteristics of the benchmark program. By executing the reduced program created by the reduced program automatic generator with a logic simulator, the performance of the benchmark program can be predicted and verified in a realistic time, which contributes to shortening the period of design and development of the development processor and retuning. There is a lot to do.

(3): In claim 3, the determining means of the data amount reduction control unit recognizes the capacity of the cache and determines the reduction size of the data amount. This makes it possible to perform performance evaluation at the same level as the benchmark program while maintaining the characteristics of the benchmark program. By executing the reduced program created by the reduced program automatic generator with a logic simulator, the performance of the benchmark program can be predicted and verified in a realistic time, which contributes to shortening the period of design and development of the development processor and retuning. There is a lot to do.

(4): In claim 4, the control means of the data amount reduction control unit reproduces the cache capacity miss by changing the address of the access variable.

By doing so, the cache miss rate can be made equal even if the data amount is reduced. In addition, it is possible to perform performance evaluation at the same level as the benchmark program while maintaining the characteristics of the benchmark program. By executing the reduced program created by the reduced program automatic generator with a logic simulator, the performance of the benchmark program can be predicted and verified in a realistic time, which contributes to shortening the period of design and development of the development processor and retuning. There is a lot to do.

(5): In claim 5, the reduced program automatic creation apparatus judges the degree of similarity between the original program and the reduced program (feature retention) by the cache miss rate.
This makes it possible to perform performance evaluation at the same level as the benchmark program while maintaining the characteristics of the benchmark program. By executing the reduced program created by the reduced program automatic generator with a logic simulator, the performance of the benchmark program can be predicted and verified in a realistic time, which contributes to shortening the period of design and development of the development processor and retuning. There is a lot to do.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a reduction program automatic creation device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a high frequency processing part extraction unit according to the embodiment of the present invention.

FIG. 3 is an explanatory diagram of a repeat count control unit according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram of behavior change in the loop rotation speed reduction unit according to the embodiment of the present invention, in which FIG. A does not change the behavior (the number of repetitions can be reduced to 1), and FIG. B changes the behavior. (It is simply impossible to reduce the number of iterations to one), and FIG. C is an explanatory diagram of the program generation unit by reducing the number of iterations (C-1: original program code, C
2: Loop reduction program code).

FIG. 5 is an explanatory diagram of a data amount reduction control unit according to the embodiment of the present invention.

6A and 6B are a variable access analysis diagram in the reduced variable selection unit and an explanatory diagram of the program generation unit in the data amount reduction according to the embodiment of the present invention. FIG. 6A is a variable access analysis diagram in the reduced variable selection unit, and FIG. It is explanatory drawing ((a): original program code, (b): data reduction program code) of the program generation part in data amount reduction.

7A and 7B are explanatory diagrams of a cache miss rate reproduction method in data amount reduction according to the embodiment of the present invention, where FIG. 7A is an original program code, FIG. 7B is a code in which no cache miss occurs, and FIG. Indicates the code that makes the mistake.

FIG. 8 is a diagram showing a specific device example in the embodiment of the present invention.

[Explanation of symbols]

1 High frequency processing part extraction unit 2 Repeat count controller 3 Data amount reduction control unit 11 Outermost loop detector 12, 24, 33 Program generator 13 Execution module generator 14 Profiler 15, 27, 37 compiler 21 Behavior Research Department based on the number of loops 22 Loop speed reduction unit 23 Behavior change point investigation department 25 Execution module generator 26 Hardware Counter 31 Reduced variable selection section 32 Reduced size determination unit 34 Execution module generation unit 35 Cash Miss Rate Research Department 36 Cache Behavior Replay Unit 38 Cash Simulator 41 computer 42 display device 43 Input device 44 Removable Disk Drive (RDD) 45 Hard Disk Drive (HDD) 46 CPU (central processing unit) 47 ROM (Read Only Memory) 48 memory 49 Interface control unit (I / F control unit) 50 Communication control unit

Claims (5)

[Claims] 1. A reduced program automatic creation apparatus for reducing the number of instructions while retaining the characteristics of an application program, wherein a high frequency processed portion extraction unit extracts a high frequency processed portion from an application program to be reduced. It also has a repeat count control unit that controls the number of repeats and a data amount reduction control unit that controls the amount of data, and makes the file formats of input and output equal to the output of each processing unit, and processes each processing unit. And a function that allows processing to be continued from an intermediate processing unit, a function that detects the outermost loop location including the high-frequency processing function in the high-frequency processing portion extraction unit, and extracts the program location, The repeat count control unit investigates the change in processing depending on the repeat count from the counter value inside the hardware, and if there is no change, the repeat count is once. Even if it is not possible to reduce the number of iterations to one in the middle of the iterations by reducing the number of iterations, it is possible to reduce the number of iterations to one by mixing the processing before and after the change. Automatic reduction program creation device characterized by. 2. The reduction program automatic creation apparatus according to claim 1, wherein the data reduction control unit includes control means for recognizing an access pattern of a variable and selecting a variable that can be reduced. 3. The reduction program automatic creation apparatus according to claim 1, wherein the data amount reduction control unit includes a determination unit that recognizes a cache capacity and determines a reduction amount of the data amount. 4. The reduction program according to claim 1, wherein the data amount reduction control unit includes a control unit that reproduces a cache capacity miss by changing an address of an access variable. Automatic creation device. 5. The reduced program automatic creation apparatus according to claim 1, further comprising a function of determining a similarity between the original program and the reduced program based on a cache miss rate.