JP2003315427A - Test-signal generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test-signal generation circuit for a semiconductor integrated circuit which is protected surely so as to prevent a test-mode operation from being performed without increasing the number of pins of an IC, when a test-mode signal is generated mistakenly in an ordinary operation. <P>SOLUTION: Prescribed data is written in such a way that a low-level signal is input to an output terminal OUT as an N-channel open drain terminal in the semiconductor integrated circuit, and that a high-level signal Sr is output to a register 23 for a test mode. Only when a low-level control signal Sc is output from a control circuit 12, a high-level test signal St used to instruct the test-mode operation is generated. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test signal generation circuit in a semiconductor integrated circuit, and more particularly to a test signal generation circuit provided in a semiconductor integrated circuit formed of CMOS.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit formed of CMOS, a semiconductor chip is tested before shipping. Therefore, a test circuit is incorporated in the semiconductor integrated circuit in addition to a normally used circuit. ing. The test circuit operates differently from the normally used function, and such a test circuit must be disabled after shipment. Therefore, the semiconductor integrated circuit needs a test signal for switching between the normal operation mode and the test mode.

Conventionally, as a method of obtaining such a test signal, a method of directly inputting a test signal from the outside as shown in FIG. 5 or a test mode shown in a predetermined register as shown in FIG. A method of using a circuit that generates a predetermined test signal by writing data has been mainly used. According to the method shown in FIG. 5, when a test is performed at the time of manufacturing, it is possible to generate a test signal St by inputting a predetermined signal to the test signal input terminal TE and test the semiconductor integrated circuit 100. it can. After the shipment, when the semiconductor integrated circuit 100 is used, the test signal input terminal TE is connected to the ground voltage so that the semiconductor integrated circuit 100 is protected from being operated in the test mode.

On the other hand, in the method shown in FIG. 6, predetermined data is stored in the test mode register 110 from an external circuit (not shown) such as a CPU via the interface terminal I / F.
For example, the test signal St is generated by writing high-level data. At this time, the same high level data is also written in the protect signal generation register 111. Test mode register 1
The high-level test signal St is output to the internal circuit 112 only when the high-level signal is output from each of the 10 and the protect signal generation register 111, and the internal circuit 112 operates in a predetermined test mode. By using the protect signal generation register 111 in this way, the protection is strengthened.

[0005]

However, in the method as shown in FIG. 5, a dedicated pin for inputting a test signal is required in the IC, and the number of pins used during normal operation is insufficient or the miniaturization of the IC is hindered. There was a problem of becoming a cause. In the method of FIG. 6, the interface terminal I / F
External circuit such as CPU that outputs data to
Wrong data is written in the test mode register 110 and the protect signal generation register 111,
There is a problem that the internal circuit 112 may erroneously perform the test mode operation.

The present invention has been made in order to solve the above problems, and a test mode signal is erroneously generated during normal operation without increasing the number of pins of the IC to perform the test mode operation. An object of the present invention is to obtain a test signal generation circuit for a semiconductor integrated circuit, which can be surely protected so as not to have it.

[0007]

A test signal generating circuit according to the present invention has an N-channel open drain output terminal for generating a test signal for causing a semiconductor integrated circuit to perform a predetermined test mode operation. In a test signal generation circuit provided in the semiconductor integrated circuit having,
A test mode data storage unit that stores predetermined data input from the outside during the test mode operation and outputs a signal according to the stored data, and a predetermined signal is output from the test mode data storage unit A protect circuit section for outputting a binary signal corresponding to the signal input from the output terminal, a control circuit section for controlling the operation of the transistor forming the N-channel open drain, and the test mode data storage section. And a signal generation circuit section for generating and outputting the predetermined test signal according to each signal output from the protection circuit section and the control circuit section.

A power supply voltage supply circuit unit is provided for outputting a power supply voltage to the output terminal when the test mode data storage unit and the control circuit unit output signals to be output in the test mode, respectively. Good.

Specifically, the power supply voltage supply circuit section is
A first MOS transistor in which a parasitic diode is formed in a direction in which a current flows from the power supply voltage to the output terminal, and a second MOS transistor in which a parasitic diode is formed in a direction in which a current flows from the output terminal to the power supply voltage And a circuit in which are connected in series, and a power supply voltage is supplied to the output terminal via the circuit.

In this case, the sum of the respective ON resistances of the first and second MOS transistors is such that the output terminal becomes a predetermined voltage when the voltage connected to the pull-up resistance becomes the ground voltage. Is set to.

On the other hand, the protection circuit section switches according to a signal output from the test mode data storage section and an inverter circuit that outputs the signal input from the output terminal to the signal generation circuit section. A first switching element for controlling the power supply to the inverter circuit and a switching circuit according to a signal output from the test mode data storage unit to control the connection of the output terminal of the inverter circuit to a predetermined voltage. A second switching element, and when a predetermined signal is output from the test mode data storage section in the test mode,
The switching element supplies power to the inverter circuit, and the second switching element cuts off connection to a predetermined voltage at the output terminal of the inverter circuit, and a predetermined signal is output from the test mode data storage unit during normal operation. May be output, the first switching element may cut off the power supply to the inverter circuit and the second switching element may connect the output terminal of the inverter circuit to a predetermined voltage.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Next, the present invention will be described in detail based on the embodiments shown in the drawings. First embodiment. FIG. 1 is a circuit diagram showing an example of a test signal generation circuit according to the first embodiment of the present invention. In FIG. 1, the test signal generation circuit 1 is configured to cause the internal circuit 10 to perform a predetermined test mode operation.
A signal generation circuit unit 2 that generates a predetermined test signal St and outputs it to the internal circuit 10, and an output terminal OU in the test mode.
The power supply voltage supply circuit unit 3 supplies the power supply voltage VDD1 to the output terminal OUT so that T does not become open.

Further, the signal generation circuit section 2 has a 3-input AN.
Protecting the D circuit 21 and the signal level from the output terminal OUT to the corresponding input terminal of the AND circuit 21 in the normal operation mode to prevent the AND circuit 21 from erroneously outputting the high-level test signal St. Circuit 22
It has and. Furthermore, the signal generation circuit unit 2 is configured to transfer a predetermined interface terminal I / F from an external circuit (not shown) such as a CPU when shifting from the normal operation mode to the test mode.
It is provided with a test mode register 23 to which predetermined data is written via. The test mode register 23 serves as a test mode data storage unit.

On the other hand, the protect circuit 22 comprises P-channel type MOS transistors (hereinafter referred to as PMOS transistors) 31, 32, N-channel type MOS transistors (hereinafter referred to as NMOS transistors) 33 and 34, and an inverter 35. Between the voltage VDD1 and the ground voltage, PMOS transistors 31, 32 and NMOS
The transistor 33 is connected in series, and the NMOS transistor 34 is connected in parallel with the NMOS transistor 33. The PMOS transistor 31 is the first
The switching element of the NMOS transistor 34
Form a second switching element.

The gates of the PMOS transistor 32 and the NMOS transistor 33 are connected to each other and to the output terminal OUT, and the PMOS transistor 32 and the NM are connected.
The connection portion with the OS transistor 33 is connected to the corresponding input terminal of the AND circuit 21. Thus, the PMOS
The transistor 32 and the NMOS transistor 33 form an inverter circuit. In addition, each gate of the PMOS transistor 31 and the NMOS transistor 34 has
The output signal Sr of the test mode register 23 is input via the inverter 35.

Next, the power supply voltage supply circuit section 3 includes a PMOS.
It is formed by the transistors 41 and 42 and the OR circuit 43, and PM is provided between the power supply voltage VDD1 and the output terminal OUT.
The OS transistors 41 and 42 are connected in series. The substrate gate (back gate) of the PMOS transistor 41 is connected to the drain of the PMOS transistor 41, and the substrate gate of the PMOS transistor 42 is connected to the source of the PMOS transistor 42. PMOS transistors 41 and 42
Of the OR circuit 4 are connected to respective gates of the OR circuit 4 and
3 output terminals are connected. In the OR circuit 43,
The output signal Sr of the test mode register 23 is input to the inverting input terminal. The PMOS transistor 41 serves as a first MOS transistor, and the PMOS transistor 42 serves as a second MOS transistor.

Here, the output terminal OUT forms an N-channel open drain terminal as shown in FIG. 2, the NMOS transistor 11 is connected between the output terminal OUT and the ground voltage, and the gate of the NMOS transistor 11 is connected. Is supplied with the control signal Sc of the control circuit 12. NM
When the OS transistor 11 is turned off and cut off, the output terminal OUT is opened, and when the NMOS transistor 11 is turned on, the output terminal OUT is low level. The control signal Sc output from the control circuit 12 is supplied to the inverting input terminal of the AND circuit 21 and the OR circuit 4
3 is input to each of the non-inverting input terminals. The output terminal OUT may be pulled up by the pull-up resistor 51, and the pull-up resistor 51 is connected to the power supply voltage V
It may be connected to a power supply voltage VDD2 different from DD1.

In such a structure, in the normal operation mode, the test mode register 2 is set so that the low level signal Sr is output from the test mode register 23.
3 is written into the test mode register 23. In the test mode, the data is written into the test mode register 23 so that the test mode register 23 outputs the high-level signal Sr. For example, during normal operation, the output terminal O
When the UT is used in an open state, the voltage level of the output terminal OUT may become indefinite.

Even in such a case, a signal obtained by inverting the signal level of the output signal Sr of the test mode register 23 is output from the inverter 35 to the PMOS transistor 31.
, And the respective gates of the NMOS transistor 34. Therefore, during normal operation, the NMOS transistor 34 is turned on, and the signal Sp input to the corresponding input terminal of the AND circuit 21 is fixed at a low level.
It is possible to prevent the internal circuit 10 from erroneously performing the test mode operation by outputting the high-level test signal St from the ND circuit 21. At this time, since the PMOS transistor 31 is turned off and is in the cutoff state, PM
The reactive current can be prevented from flowing through the series circuit of the OS transistor 32 and the NMOS transistor 33.

On the other hand, in the test mode, the output terminal OU
By connecting T to the ground voltage, a low level signal is input to the output terminal OUT. In test mode,
High-level signal Sr from the test mode register 23
Is output, the PMOS transistor 31 is turned on, and the PMOS transistor 32 and the NMOS transistor 33 cause the high-level signal Sp to go to the AND circuit 2.
1 is output to the corresponding input terminal. Further, in the test mode, the control signal Sc from the control circuit 12 is at a low level, so that the NMOS transistor 11 is turned off to be in a cutoff state. In this way, since the signals Sr and Sp input to the AND circuit 21 become the high level and the control signal Sc becomes the low level, the AND circuit 21 outputs the high-level test signal St and the internal circuit 1
0 operates in a predetermined test mode.

Here, during normal operation, the output terminal O
Power supply voltage VDD2 higher than power supply voltage VDD1 to UT
When the pull-up resistor 51 is connected to the power supply voltage VDD
There may be a case where a current flows backward from 2 to the power supply voltage VDD1. The power supply voltage supply circuit section 3 has a function of preventing such a reverse current flow. Power voltage supply circuit section 3
In the normal operation, the low-level signal Sr is input to the inverting input terminal of the OR circuit 43, and the OR circuit 43 outputs the high-level signal regardless of the signal level of the control signal Sc. Therefore, the PMOS transistors 41 and 42
Both turn off and enter the cutoff state.

Since the substrate gate is connected to the drain of the PMOS transistor 41, the parasitic diode is formed so that the direction from the power supply voltage VDD1 to the output terminal OUT is the forward direction. On the other hand, in the PMOS transistor 42, since the substrate gate is connected to the source, the parasitic diode is formed so that the direction from the output terminal OUT to the power supply voltage VDD1 is the forward direction. For this reason, the power supply voltage supply circuit section 3 can prevent the backflow of current from the power supply voltage VDD2 to the power supply voltage VDD1.

In the normal operation mode, the control signal Sc becomes low level, the NMOS transistor 11 is turned off, and the output terminal OUT is opened.
The output terminal OUT may go low. The power supply voltage supply circuit unit 3 sets the output terminal OUT to the high level so that the test signal St does not become the high level when the signal Sr accidentally becomes the high level in such a state. In the normal operation mode, when the NMOS transistor 11 is turned off, both the PMOS transistors 41 and 42 are turned on, and a high level signal is output to each gate of the PMOS transistor 32 and the NMOS transistor 33. In this way, the power supply voltage supply circuit unit 3
Can prevent the output terminal OUT from being opened when the NMOS transistor 11 is turned off in the normal operation mode, and can prevent the test signal St from accidentally becoming high level.

3 and 4 are diagrams showing the relationship among the signal Sr, the control signal Sc, the output terminal OUT and the test signal St. FIG. 3 shows the case where the output terminal OUT is connected to the ground voltage. FIG. 4 shows a case where the output terminal OUT is opened and a case where the output terminal OUT is pulled up by the pull-up resistor 51. In FIG. 3, since the output terminal OUT is connected to the ground voltage, the output terminal O
UT is always low. Therefore, when the signal Sr is at the high level and the control signal Sc is at the low level, the test signal St is at the high level, and the internal circuit 10 operates in the test mode.

Next, in FIG. 4, there is no combination in which the output terminal OUT is in the open state and the test signal St becomes high level, and the internal circuit 10 does not operate in the test mode. Further, even when the output terminal OUT is pulled up by the pull-up resistor 51, there is no combination in which the test signal St becomes high level. However, when the signal Sr is at the high level and the control signal Sc is at the low level, and the power supply voltage VDD2 to which the resistor 51 pulling up the output terminal OUT is connected becomes 0V, the output terminal OUT becomes the low level. The test signal S
There is a problem that t becomes high level and the internal circuit 10 performs the test mode operation.

In order to prevent the occurrence of such a problem,
The resistance value of the resistor 51 that pulls up the output terminal OUT is
The sum of the on resistances of the PMOS transistors 41 and 42 is made sufficiently large. By doing so, the power supply voltage V to which the pull-up resistor 51 is connected is
When DD2 becomes 0V, the voltage of the output terminal OUT becomes
The value can be set to a value sufficient to turn on the NMOS transistor 33, and it is possible to prevent the test signal St from accidentally becoming high level. As can be seen from FIG. 4, the test signal St is erroneously set to the high level during the normal operation, and the test mode operation is not performed.

As described above, the test signal generation circuit according to the first embodiment outputs a low level signal to the output terminal OUT which is an N-channel open drain terminal in the semiconductor integrated circuit, and outputs the low level signal to the test mode register 23. The high-level test signal St for instructing the test mode operation is generated only when the predetermined data is written so as to output the high-level signal Sr and the low-level control signal Sc is output from the control circuit 12. I chose Therefore, the internal circuit 10 can be operated in the test mode without providing a dedicated pin for inputting a predetermined test signal from the outside, and the test mode signal is erroneously generated during the normal operation. Secure protection can be applied to prevent test mode operation.

[0028]

As is apparent from the above description, according to the test signal generating circuit of the present invention, a predetermined signal is input to the output terminal which is the N-channel open drain terminal in the semiconductor integrated circuit, and the test mode is used. The predetermined test signal is generated and output according to each signal output from the data storage unit, the protect circuit unit, and the control circuit unit. From this, it is possible to allow the internal circuit to perform the test mode operation without providing a dedicated pin for inputting a predetermined test signal from the outside, and the test mode signal is erroneously generated during the normal operation. Secure protection can be applied to prevent mode operation.

Further, by providing the power supply voltage supply circuit section, it is possible to prevent the output terminal from being opened in the normal operation mode, and when the output terminal is opened, a predetermined test signal is erroneously output. It is possible to reliably prevent the test mode operation from being generated.

Specifically, in the first MOS transistor of the power supply voltage supply circuit section, since the parasitic diode is formed in the direction in which the current flows from the power supply voltage to the output terminal, the pull-up resistor is connected to the output terminal. It is possible to prevent a current from flowing back to the power supply voltage via the pull-up resistor when is connected.

The first and second power supply voltage supply circuit sections are also provided.
The sum of the on-resistances of the MOS transistors is set so that the output terminal has a predetermined voltage when the voltage connected to the pull-up resistor becomes the ground voltage. From this, it is possible to prevent a predetermined test signal from being erroneously generated and a test mode operation being performed when the voltage to which the pull-up resistor is connected becomes the ground voltage.

On the other hand, in the protect circuit section, when a predetermined signal is output from the test mode data storage section in the test mode, power is supplied to the inverter circuit and a predetermined voltage at the output terminal of the inverter circuit is supplied. When the predetermined signal is output from the test mode data storage section during normal operation,
The power supply to the inverter circuit is cut off, and the output terminal of the inverter circuit is connected to a predetermined voltage. Therefore, it is possible to surely prevent a predetermined test signal from being erroneously generated during the normal operation to perform the test mode operation, and it is possible to prevent a reactive current from flowing through the inverter circuit during the normal operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a test signal generation circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of an output circuit connected to an output terminal OUT.

FIG. 3 is a diagram showing a relationship among a signal Sr, a control signal Sc, an output terminal OUT and a test signal St when the output terminal OUT is connected to a ground voltage.

FIG. 4 shows a signal Sr when the output terminal OUT is opened and when the output terminal OUT is pulled up,
It is a figure showing the relation of control signal Sc, output terminal OUT, and test signal St.

FIG. 5 is a diagram showing an example of a conventional test signal generation circuit.

FIG. 6 is a diagram showing another example of a conventional test signal generation circuit.

[Explanation of symbols]

1 Test signal generation circuit 2 Signal generation circuit section 3 Power supply voltage supply circuit section 10 Internal circuit 11 NMOS transistor 12 Control circuit 21 3-input AND circuit 22 Protect circuit 23 Test Mode Register 51 Pull-up resistor

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2G132 AE22 AE26 AE27 AG01 AK07                       AK13 AL11 AL31                 5F038 BE05 BE08 DF10 DT02 DT09                       EZ20

Claims (5)

[Claims] 1. A test signal generating circuit provided in a semiconductor integrated circuit having an N-channel open drain output terminal for generating a test signal for causing a semiconductor integrated circuit to perform a predetermined test mode operation. A test mode data storage section for storing predetermined data input from the outside during the test mode operation and outputting a signal corresponding to the stored data; and a predetermined signal output from the test mode data storage section Then, a protection circuit unit that outputs a binary signal corresponding to the signal input from the output terminal, a control circuit unit that controls the operation of the transistor that forms the N-channel open drain, and the test mode data Generating the predetermined test signal according to each signal output from the storage unit, the protection circuit unit, and the control circuit unit Test signal generating circuit, characterized in that it comprises a signal generation circuit for outputting Te. 2. A power supply voltage supply circuit unit for outputting a power supply voltage to the output terminal when a signal output in the test mode is output from each of the test mode data storage unit and the control circuit unit. Claim 1
The described test signal generation circuit. 3. The power supply voltage supply circuit section includes a first MOS transistor having a parasitic diode formed in a direction in which a current flows from the power supply voltage to the output terminal, and a current flows from the output terminal to the power supply voltage. 3. The test signal according to claim 2, further comprising a circuit in which a second MOS transistor having a parasitic diode formed in a direction is connected in series, and a power supply voltage is supplied to the output terminal via the circuit. Generation circuit. 4. The sum of the respective ON resistances of the first and second MOS transistors is such that the output terminal becomes a predetermined voltage when the voltage connected to the pull-up resistance becomes the ground voltage. The test signal generation circuit according to claim 3, wherein the test signal generation circuit is set. 5. The protect circuit unit outputs an signal input from the output terminal to the signal generation circuit unit, and switches according to a signal output from the test mode data storage unit. A first switching element that controls power supply to the inverter circuit, and performs switching control according to a signal output from the test mode data storage unit to control connection of the output terminal of the inverter circuit to a predetermined voltage. A second switching element, wherein the first switching element supplies power to the inverter circuit when a predetermined signal is output from the test mode data storage section in the test mode.
Switching element cuts off the connection to a predetermined voltage at the output terminal of the inverter circuit, and when a predetermined signal is output from the test mode data storage section during normal operation, the first switching element operates as the inverter circuit. The test signal generating circuit according to claim 1, 2, 3 or 4, wherein the second switching element connects the output terminal of the inverter circuit to a predetermined voltage while shutting off the power supply to the.