JP2003309296A - Integrated circuit device and its manufacturing method, piezoelectric oscillator and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve significant reduction in size at the time of configuring a computer or the like, while reducing the generation of a electromagnetic wave and accelerating the reduction of power. <P>SOLUTION: An integrated circuit comprises a crystal unit 31, a clock generating circuit connected with the crystal unit 31 generating a clock signal, and a CPU operating based on the clock signal. A chip 1 has such a structure that the integrated circuit is mounted on a chip substrate 41 and they are integrated including the crystal unit 31 into a one chip device. Connection pads 76 and 77 of the crystal unit 31 are connected electrically and mechanically with specified wiring layers 57 and 58 formed on the chip substrate 41 through bumps 61 and 62, respectively. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device and a method of manufacturing the same, a piezoelectric vibrator that can be used in the integrated circuit device and the like, and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the rapid spread of mobile communication and an increase in the amount of processed data such as images, the demand for high-speed processing of a CPU (central processing unit) that performs arithmetic processing has increased more than ever. ing. In order to meet the demand, the clock frequency for operating the CPU has been further increased.

As is well known, a computer using a CPU has a piezoelectric oscillator such as a crystal oscillator, a clock generation circuit connected to the piezoelectric oscillator to generate a clock signal, and a CPU that operates based on the clock signal. , A system controller, a memory, an input / output interface, and various buses connecting them.

When constructing such a computer,
In order to reduce the size and facilitate manufacturing, the CPU, the system controller, the input / output interface, and the like, excluding the piezoelectric vibrator and the clock generation circuit, are integrated into a single chip and constructed as a microprocessor chip. What accommodates this microprocessor chip in a predetermined package is provided as a microprocessor. This conventional microprocessor has a ROM
A memory such as a RAM or RAM does not have to be built into a single chip in the microprocessor chip, but is premised on the external attachment of the memory, and a memory such as ROM or RAM is also called a one-chip microcomputer in a single chip in the microprocessor chip. and so on. In the past, the piezoelectric vibrator and the clock generation circuit were each housed in a package different from the package of the microprocessor chip and configured as separate discrete parts.

However, if the microprocessor chip, the piezoelectric vibrator, and the like are housed in separate packages in this way, the mounting space for them and the steps for fixing each package, etc., increase and the size is reduced. It is not always sufficient in terms of manufacturing ease.

Therefore, in order to improve this, a microprocessor chip, a piezoelectric vibrator, and a clock generating circuit are
It has a structure in which they are electrically connected to each other using a wiring board for connection (which is much larger than a microprocessor chip) prepared separately from these, and then housed in the same package. A microprocessor with a built-in oscillator is provided (for example, JP-A-60-134455). According to this oscillator-embedded microprocessor, since it is made into one package (not made into one chip), it is possible to reduce the size and facilitate the manufacturing.

Further, conventionally, a through hole that is slightly smaller than the vibrating crystal plate is formed in the semiconductor substrate on which the oscillation circuit is formed, and the vibrating crystal plate is arranged so as to straddle this through hole. Provided is a crystal oscillator (for convenience of description, referred to as “oscillation circuit built-in type crystal oscillator”) having a structure in which a peripheral portion of a diaphragm is fixed to a peripheral portion of the through hole in a semiconductor substrate by direct bonding. (For example, Japanese Patent Laid-Open No. 7-38333). In this crystal oscillator with a built-in oscillation circuit, since the oscillation circuit and the piezoelectric vibrator are integrated, it is possible to reduce the size and facilitate the manufacturing of this portion. When a computer is constructed using this crystal oscillator with a built-in oscillation circuit, a microprocessor in which only the microprocessor chip described above is housed is used together.

[0008]

However, in the case of constructing a computer, there is an increasing demand for miniaturization and facilitation of manufacturing, and the above-described conventional oscillator-embedded microprocessor and conventional oscillator-embedded circuit are incorporated. It is not always possible to sufficiently meet the demand by using a crystal oscillator of the type.

Further, when the above-mentioned conventional microprocessor with built-in oscillator or crystal oscillator with built-in oscillator circuit is used, the electromagnetic wave generated by the clock generation is inevitably relatively large, which causes electromagnetic interference ( EMI (Electr
It has been difficult to take measures to reduce (o-Mgnetic-Interfarence)) (hereinafter referred to as "EMI measures").

That is, since a signal corresponding to the clock flows in the wiring between the piezoelectric vibrator and the clock generation circuit and the wiring between the clock generation circuit and the CPU, these wirings serve as an antenna for generating electromagnetic waves. To work. However, in the case of the conventional oscillator-embedded microprocessor, the wiring between the piezoelectric vibrator and the clock generation circuit and the wiring between the clock generation circuit and the CPU have to be relatively long. The antenna action of these wirings becomes large, relatively large electromagnetic waves are generated, and it is extremely difficult to completely shield these wiring portions from electromagnetic waves. When the conventional crystal oscillator with a built-in oscillation circuit is used, a clock generation circuit (oscillation circuit) and a C
Since the wiring to PU has to be relatively long,
The antenna action of this wiring becomes large, a relatively large electromagnetic wave is generated, and it is extremely difficult to completely shield the wiring portion from electromagnetic waves. Therefore, it is difficult to take measures against EMI in any of the above-mentioned conventional techniques. In particular, when the clock frequency is increased, the generated electromagnetic waves increase, and the problem becomes more serious.

Further, in any of the above-mentioned conventional techniques,
As described above, since each wiring has to be relatively long, the power consumption due to the resistance component of the wiring cannot be ignored,
It was a hindrance to low power consumption.

The present invention has been made in view of such circumstances, and in comparison with the above-mentioned prior art, when constructing a computer or the like, it is possible to greatly reduce the size and to generate an electromagnetic wave. (EN) An integrated circuit device that can reduce power consumption and further promote low power consumption, a manufacturing method thereof, a piezoelectric vibrator that can be used in this integrated circuit device, and a manufacturing method thereof. To aim.

[0013]

The inventor of the present invention was caught by the conventional fixed idea that the CPU and the piezoelectric vibrator should naturally exist as separate parts until the present invention is reached. It is inevitable to break away from the level of the prior art described above, and it was completely inconceivable to integrate the piezoelectric vibrator, the clock generation circuit, and the CPU into one chip.

As described above, it has been extremely difficult not only for the present inventor to obtain the idea that the piezoelectric vibrator, the clock generation circuit and the CPU are integrated into one chip by being caught by the conventional fixed idea. It was similar to those skilled in the art. This means that by combining the three elements of the piezoelectric vibrator, the clock generating circuit, and the CPU into one chip, a great merit can be obtained as will be described later, but no particular demerit occurs. If one could easily conceive it, it is obvious that such a three-party implementation on one chip has already been realized, or at least had already been proposed, but it was not. Is.

Now, the merits of integrating the three elements of the piezoelectric vibrator, the clock generating circuit and the CPU into one chip will be described. First, when constructing a computer or the like, it is possible to make the size significantly smaller than the above-described conventional technique. It is not necessary to interpose a wiring board or the like between the piezoelectric vibrator and the clock generating circuit and between the clock generating circuit and the CPU, and these are integrated together, so that the size can be remarkably reduced. Secondly, the generation of electromagnetic waves is significantly suppressed, and EMI countermeasures are facilitated. The wiring between the piezoelectric vibrator and the clock generation circuit is significantly shortened, and the wiring between the clock generation circuit and the CPU is significantly shortened, so that the antenna action of those wirings is significantly reduced.
The generation of electromagnetic waves accompanying the clock generation is greatly suppressed. Thirdly, lower power consumption can be promoted. The wiring between the piezoelectric vibrator and the clock generation circuit is significantly shortened, and the wiring between the clock generation circuit and the CPU is also significantly shortened, so that the resistance component of these wirings is reduced, which reduces power consumption. It is reduced.

The present invention is based on the idea that the present inventor is not limited to the conventional fixed idea and that the three elements of the piezoelectric vibrator, the clock generating circuit and the CPU are integrated into one chip.
It was made. Further, the present invention has been made by implementing various ideas described later when embodying such an idea.

That is, the integrated circuit device according to the first aspect of the present invention includes a piezoelectric vibrator, a clock generation circuit connected to the piezoelectric vibrator to generate a clock signal, and a CPU that operates based on the clock signal. An integrated circuit including
An integrated circuit device mounted on a chip substrate, wherein the integrated circuit including the piezoelectric vibrator is integrally integrated into one chip.

An integrated circuit device according to a second aspect of the present invention is the integrated circuit device according to the first aspect, wherein the piezoelectric vibrator has two connection pads, and at least one of the two connection pads is connected. The wiring board is electrically and mechanically connected to a predetermined wiring layer formed on the chip substrate via bumps. The bumps include, in addition to metal bumps, bumps made of a conductive adhesive or the like. This also applies to each of the modes described later.

An integrated circuit device according to a third aspect of the present invention is the integrated circuit device according to the first aspect, wherein: (a) the piezoelectric vibrator is formed on a piezoelectric element plate and a surface of the piezoelectric element plate on the chip substrate side. And a second excitation electrode formed on the second surface of the piezoelectric element plate opposite to the chip substrate, and formed on the surface of the piezoelectric element plate on the chip substrate side. A first connection pad electrically connected to the first excitation electrode, and a second connection pad electrically connected to the second excitation electrode formed on a surface of the piezoelectric element plate on the chip substrate side. And (b) the first and second connection pads are electrically and mechanically connected to predetermined wiring layers formed on the chip substrate through bumps, respectively. It is a thing.

An integrated circuit device according to a fourth aspect of the present invention is the integrated circuit device according to the third aspect, wherein the piezoelectric element plate has a through hole, and the second connection pad has a conductive property existing in the through hole. It is electrically connected to the second excitation electrode through a substance.

An integrated circuit device according to a fifth aspect of the present invention is the integrated circuit device according to the fourth aspect, wherein the through hole is formed at a position substantially deviating from a predetermined vibration region of the piezoelectric element plate. is there.

An integrated circuit device according to a sixth aspect of the present invention is the integrated circuit device according to any one of the first to fifth aspects, wherein a predetermined element is formed in a region of the chip substrate facing the piezoelectric vibrator. Is.

An integrated circuit device according to a seventh aspect of the present invention is the integrated circuit device according to any one of the first to sixth aspects, further comprising a storage chamber in which the piezoelectric vibrator is stored and closed.

An integrated circuit device according to an eighth aspect of the present invention is the integrated circuit device according to the seventh aspect, wherein the accommodating chamber has a recess formed in at least one of the chip substrate and a laminated portion on the chip substrate. It is formed by a lid that closes the opening side of the recess.

An integrated circuit device according to a ninth aspect of the present invention is the integrated circuit device according to the eighth aspect, wherein the lid is a conductive plate for electromagnetic shielding, or the lid has a conductive film for electromagnetic shielding. It was formed.

An integrated circuit device according to a tenth aspect of the present invention is the integrated circuit device according to any one of the seventh to eighth aspects, wherein the space in the storage chamber is substantially evacuated.

An integrated circuit device according to an eleventh aspect of the present invention is the integrated circuit device according to any one of the first to tenth aspects, wherein the piezoelectric element plate of the piezoelectric vibrator is disposed on a side opposite to the chip substrate. And a reinforcing plate that supports a portion of the piezoelectric element plate that is substantially deviated from a predetermined vibration region.

An integrated circuit device according to a twelfth aspect of the present invention is the integrated circuit device according to the eleventh aspect, wherein the reinforcing plate is a conductive plate for electromagnetic shield, or the reinforcing plate has a conductive layer for electromagnetic shield. It was formed.

An integrated circuit device according to a thirteenth aspect of the present invention is the integrated circuit device according to any one of the first to twelfth aspects, wherein the chip substrate side and the piezoelectric element plate side of the piezoelectric vibrator are adhered to each other. The agent is provided so as to hermetically seal the space where the predetermined vibration region of the piezoelectric element plate is located.

An integrated circuit device according to a fourteenth aspect of the present invention is the integrated circuit device according to any one of the first to thirteenth aspects, wherein a conductive layer for electromagnetic shielding is formed on the element forming region on the chip substrate. It is a thing.

An integrated circuit device according to a fifteenth aspect of the present invention is the integrated circuit device according to any one of the first to fourteenth aspects, wherein the integrated circuit formed into one chip is housed in a hermetically sealed package. It is a thing.

An integrated circuit device according to a sixteenth aspect of the present invention is the integrated circuit device according to the fifteenth aspect, wherein the space inside the package is substantially evacuated.

An integrated circuit device manufacturing method according to a seventeenth aspect of the present invention is a manufacturing method for manufacturing the integrated circuit device according to the first aspect, wherein a portion of the integrated circuit excluding the piezoelectric vibrator is used. And a step of preparing the piezoelectric vibrator, and a step of electrically and mechanically integrating the piezoelectric vibrator with the chip substrate.

In the method of manufacturing an integrated circuit device according to an eighteenth aspect of the present invention, in the seventeenth aspect, the step of integrating includes a step of forming a predetermined wiring layer formed on the chip substrate and the piezoelectric vibrator. The step of electrically and mechanically connecting to the connection pad via the bump is included.

A method for manufacturing an integrated circuit device according to a nineteenth aspect of the present invention is the method according to the seventeenth or eighteenth aspect,
The chip substrate on which a portion of the integrated circuit excluding the piezoelectric vibrator is formed has a recess at a predetermined position, and the step of integrating is performed by disposing the piezoelectric vibrator in the recess. After the step of integrating, the step of closing the opening side of the recess with a lid is provided.

According to a twentieth aspect of the present invention, in the method for manufacturing an integrated circuit device according to any one of the seventeenth to nineteenth aspects, the step of preparing the piezoelectric vibrator is the first step of forming the piezoelectric element plate. A first step of forming a first conductive film in an island shape on the surface, and a second step of forming a sacrificial layer on a predetermined area or the entire area of the first surface of the piezoelectric element plate after the first step And after the second step, the piezoelectric element plate and the reinforcing plate,
The third step of joining so that the sacrificial layer is on the side of the reinforcing plate, and the second surface side of the piezoelectric element plate opposite to the first surface is removed after the third step. And a fourth step of thinning the piezoelectric element plate, and after the fourth step, forming a through hole in the piezoelectric element plate so that a part of the first conductive film faces the second surface side. A fifth step of forming, a sixth step of forming a second conductive film in an island shape in the through hole and on the second surface of the piezoelectric element plate, and the sacrifice after the sixth step. A seventh step of removing the layer.

In the manufacturing method of the integrated circuit device according to the twenty-first aspect of the present invention, in the twentieth aspect, in the third step, the piezoelectric element plate and the reinforcing plate are provided, and the sacrifice in the piezoelectric element plate is performed. An adhesive disposed on at least a part of the region where the layer is not formed, and including a bonding step.

A method for manufacturing an integrated circuit device according to the twenty-second aspect of the present invention is the method according to the twentieth or twenty-first aspect.
In the step of preparing the piezoelectric vibrator, after the sixth step and before the seventh step, the piezoelectric element plate is arranged so that a part of the sacrificial layer faces the second surface side. It includes the step of forming an opening.

In the integrated circuit device manufacturing method according to the twenty-third aspect of the present invention, in any one of the twentieth to twenty-second aspects, the fourth step includes a step of etching the piezoelectric element plate.

A piezoelectric vibrator according to a twenty-fourth aspect of the present invention is a piezoelectric element plate, a first excitation electrode formed on a first surface of the piezoelectric element plate, and the first element of the piezoelectric element plate. A second excitation electrode formed on a second surface opposite to the first surface, and a first excitation electrode formed on the first surface of the piezoelectric element plate and electrically connected to the first excitation electrode. The piezoelectric element plate has a through-hole, and a connection pad and a second connection pad formed on the first surface of the piezoelectric element plate and electrically connected to the second excitation electrode. , The second connection pad, through the conductive material present in the through hole,
It is electrically connected to the second excitation electrode.

In the method of manufacturing a piezoelectric vibrator according to a twenty-fifth aspect of the present invention, a first step of forming a first conductive film in an island shape on a first surface of a piezoelectric element plate, and the first step. After the second step of forming a sacrificial layer in a predetermined area or the entire area of the first surface of the piezoelectric element plate afterwards, and after the second step, the piezoelectric element plate and the reinforcing plate are sacrificed. The third step of joining so that the layer is on the side of the reinforcing plate, and, after the third step, removing the second surface side of the piezoelectric element plate opposite to the first surface. A fourth step of thinning the piezoelectric element plate;
After the step of, the fifth step of forming a through hole in the piezoelectric element plate so that a part of the first conductive film faces the second surface side, and the inside of the through hole and the piezoelectric element plate. A sixth step of forming a second conductive film in an island shape on the second surface, and a seventh step of removing the sacrificial layer after the sixth step.
And the stages of.

A method for manufacturing a piezoelectric vibrator according to a twenty-sixth aspect of the present invention is the method according to the twenty-fifth aspect, wherein in the third step, the piezoelectric element plate and the reinforcing plate are provided in the piezoelectric element plate. An adhesive disposed on at least a part of the region where the sacrificial layer is not formed includes a step of joining.

According to a twenty-seventh aspect of the present invention, in the method of manufacturing a piezoelectric vibrator according to the twenty-fifth or twenty-sixth aspect, the step of preparing the piezoelectric vibrator is the step after the sixth step. Before the step of 7, the step of forming an opening in the piezoelectric element plate so that a part of the sacrificial layer faces the second surface side is included.

In the method of manufacturing a piezoelectric vibrator according to a twenty-eighth aspect of the present invention, in any one of the twenty-fifth to twenty-seventh aspects, the fourth step includes a step of etching the piezoelectric element plate. .

In the first to twenty-seventh aspects, the piezoelectric vibrator may be, for example, a ceramic vibrator, but from the viewpoint of frequency stability, it is preferably a crystal vibrator. In the case of a crystal oscillator, a crystal blank is the piezoelectric blank.

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An integrated circuit device and a method of manufacturing the same, a piezoelectric vibrator and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

[First Embodiment]

FIG. 1 is a schematic sectional view schematically showing an integrated circuit device according to the first embodiment of the present invention. Figure 2
FIG. 2 is a block diagram showing an example of an integrated circuit that is integrally integrated with the chip 1 in FIG. 1 to form a single chip. Figure 3
FIG. 3 is a schematic cross-sectional view schematically showing a part of the chip 1.
FIG. 4 is a view taken along the line AA ′ in FIG. 3 in which only the crystal unit 31 is viewed. FIG. 4 is a BB ′ arrow view in FIG. 3 in which only the crystal unit 31 is viewed.

The device according to the present embodiment comprises a chip 1,
The package 2 that accommodates the chip 1 in a substantially vacuum state is provided.

In this embodiment, as the package 2,
The package disclosed in JP-A-7-161860 is used. The package 2 has a package body 11 made of an insulating material such as ceramic. The package body 11 has a stepped recess formed inside thereof. The wiring pattern forming portion 1 is provided in the recessed portion.
2 and a chip mounting part 14 for mounting the chip 1.
Is set. Around the package body 11, a lead pin group 15 which is an external terminal of the chip 1 is provided. The lead pin group 15 includes the wiring pattern forming portion 12
Is connected to a wiring pattern (not shown) formed on the. The wiring pattern is electrically connected to an external connection electrode (not shown) of the chip 1 via the bonding wire 16.

The package body 11 is provided with a ventilation structure 17 corresponding to the mounting portion 14 and made of a porous insulator or the like. The ventilation structure 17 includes the package body 11
It is formed from the chip mounting surface to the lower surface of the package body 11.

The chip 1 is fixed on the chip mounting surface of the ventilation structure 17 via an adhesive layer 18 made of a thermosetting adhesive. As the thermosetting adhesive, for example, a paste in which epoxy is mixed with silver is used. A lid 20 is fixed to the surface of the ventilation structure 17 opposite to the chip mounting surface (hereinafter referred to as the back surface) with an adhesive layer 19 made of a thermosetting adhesive. The lid 10 is made of a metal such as copper or aluminum so as to have an electromagnetic shield function, and blocks the ventilation of the ventilation structure 17. Further, for the adhesive layer 19, for example, a paste in which silver is mixed with epoxy is used, but an adhesive having a high hermetic sealing property is more preferable.

An upper lid 21 is fixed to the upper surface of the package 1 with a brazing material or the like. The chip 3 is hermetically sealed and accommodated in the package 1 by the lid 10 and the upper lid 21. The upper lid 21 is preferably a conductive plate such as a metal plate for electromagnetic shielding or a conductive layer such as a metal layer for electromagnetic shielding formed in order to prevent EMI.

If such a structure is adopted as the package 2, as described in Japanese Patent Application Laid-Open No. 7-161860, the package 2 is manufactured by a predetermined manufacturing method so that the inside of the package 2 is highly airtight. Can be kept in vacuum. However, instead of the package 2, a package 2 having another structure capable of housing the chip 1 in a substantially vacuum state may be adopted. In the present embodiment, it is preferable that the chip 1 is housed in the package in a vacuum state, but it is not always necessary to house the chip 1 in a vacuum state. , For convenience of explanation, it is referred to as a "normal package".

In the present embodiment, the integrated circuit shown in FIG. 2 is integrated on the chip 1. This integrated circuit includes a crystal oscillator 31 as a piezoelectric oscillator, a clock generation circuit 32 that is connected to the crystal oscillator 31 and generates a clock signal,
The CPU 33, the system controller 34, the memory 35, the input / output interface 36, the data bus 37, and the system data bus 3 which operate based on the clock signal.
8, an address bus 39, etc., and also includes a crystal oscillator 31 and a clock generation circuit 32 in addition to the circuit configuration mounted on the conventional one-chip microcomputer. In the present invention, the circuit configuration of the integrated circuit integrated on the chip 1 is not limited to the configuration shown in FIG. 2, and may be various circuits including a crystal oscillator, a clock generation circuit and a CPU. . For example, the integrated circuit integrated on the chip 1 may adopt a configuration based on the assumption that a memory such as a ROM or a RAM is externally attached. Further, in the present invention, instead of the crystal oscillator 31, it is possible to use another piezoelectric oscillator such as a ceramic oscillator.

As shown in FIG. 3, the chip 1 has a structure in which the integrated circuit shown in FIG. 2 is mounted on a chip substrate 41,
The integrated circuit shown in FIG. 2, including the crystal unit 31, is integrated into one chip.

FIG. 3 shows the parts near the crystal oscillator 31, the P-channel MOSFET 42, and the N-channel MOSFETs 43 and 44 among the constituent elements of the integrated circuit. On the chip substrate 41, a portion of the integrated circuit shown in FIG. 2 other than the crystal oscillator 31 is formed.
In FIG. 3, as a representative of them, MOSFETs 42, 4
3,44 are shown. A pair of P-channel MOSFETs
And the N-channel MOSFET form one CMOS that is a component of a logic circuit or the like. In this embodiment, an N-type silicon substrate is used as the chip substrate 41. In FIG. 3, 45 is an N-type silicon epitaxial layer, 46 is a P-type well layer, 47 is a P-type impurity layer, 4
8 is an N-type impurity layer, 49 is an element isolation impurity layer, 50,
51 is a silicon oxide film, 50 is a thin portion of the silicon oxide film, 51 is a thick portion of the silicon oxide film for element isolation, 52 is a source or drain electrode made of Al or the like, and 53 is made of polysilicon. Becomes a gate electrode,
54 is an interlayer insulating film, 55 is a metal layer for electromagnetic shielding, 56
Is a surface protection film, and 57 and 58 are metal wiring layers connected to the clock generation circuit 32 (see FIG. 2) formed on the chip substrate 41. The electromagnetic shield metal layer 55 is formed over almost the entire element formation region on the chip substrate 41. The electromagnetic shield metal layer 55 is connected to the outside to apply a constant potential to take a bias. A wiring layer, another element, another interlayer insulating film, or the like is formed between the interlayer insulating film 54 and the electromagnetic shielding metal layer 55, if necessary, but they are omitted in FIG.

The wiring layers 57 and 58 connected to the clock generation circuit 32 are electrically and mechanically connected to the two connection pads 76 and 77 of the crystal oscillator 31, which will be described later, via the bumps 61 and 62, respectively. Has been done. As a result, the crystal unit 31 is integrated with the chip substrate 41, and the crystal unit 31 and the clock generation circuit 32 are integrated.
An electrical connection between is realized. Bump 61,
In addition to metal bumps or the like, 62 may be a protrusion such as a conductive adhesive (for example, a polyimide-based, epoxy-based, or silicon-based adhesive to which a conductive material is added). Below the vibrating region 71a of the crystal unit 31, a space required for vibration is secured by the height of the bumps 61 and 62.

In the example shown in FIG. 3, the crystal oscillator 31
Although only one MOSFET 44 is formed below, a plurality of elements may actually be formed. It is not always necessary to form an element below the crystal unit 31, but if an element is formed in a region facing the crystal unit 31 as in the present embodiment, higher integration can be achieved at a higher density. Is possible and preferable. Further, the arrangement of the crystal unit 31 in the surface direction of the substrate 41 is not limited to the position on the MOSFET, and it can be arranged at any position. However, it is preferable to arrange it at a position close to the clock generation circuit 32. This is because the wiring layers 57 and 58 through which the signal corresponding to the clock flows becomes shorter, and the electromagnetic waves generated from the wiring layers 57 and 58 are further reduced.

In the present embodiment, as shown in FIGS. 3 to 5, the crystal unit 31 is a crystal element plate having the same thin thickness (for example, several μm to several tens of μm) over the entire region. Has 71. The crystal blank plate 71 has two cutout portions 72 and 73 formed in a rectangular shape in a plan view, so that the central vibration region 71a is located outside the vibration region 71a, and both sides are connected regions 71b. , 71c and a frame-shaped region 71d connected to the vibration region 71a. The diameter of the vibrating region 71a is, for example, several hundred μm.
It is assumed to be a thousand to several hundreds of μm. The excitation electrode 74 is formed in the center of the surface of the vibration region 71a on the chip substrate 41 side (hereinafter, this surface is referred to as the lower surface, and the opposite surface is referred to as the upper surface).
An excitation electrode 75 is formed in the center of the upper surface of the vibration area 71a. One of the excitation electrodes 74 and 75 has a vibration region 71a.
You may form over the whole of.

As shown in FIG. 4, the two connection pads 76 and 77 are formed on both sides of the lower surface of the frame-shaped region 71d. On the lower surface of the vibration region 71a, the connection pad 76 and the excitation electrode 74 are electrically connected by the lead 78,
These are composed of one continuous metal film. A lead 79 connected to the excitation electrode 75 is formed on the upper surface of the vibrating region 71a, and the lead 79 is composed of one continuous metal film. The lead 79 is electrically connected to the connection pad 77 via the through hole 80 formed in the frame-shaped region 71d. In the present embodiment, the lead 79 and the connection pad 77 are electrically connected by the metal film forming the connection pad 77 entering the through hole 80 and coming into contact with the metal film forming the lead 79. .

The through hole 80 has a vibrating region 71.
Although it is possible to dispose it in a, it is possible to form it in a region outside the vibrating region 71a in the quartz crystal plate 71 as in the present embodiment so as not to affect the vibration characteristics.
preferable.

Next, an example of a method of manufacturing the integrated circuit device according to this embodiment will be described with reference to FIGS. 6 and 7. 6 and 7 are schematic cross-sectional views schematically showing each step of the manufacturing method and correspond to FIG. 6 and 7, the same elements as those in FIG. 3 are designated by the same reference numerals.

First, a portion of the integrated circuit shown in FIG. 2 excluding the crystal oscillator 31 is subjected to a normal semiconductor manufacturing process such as growth of an epitaxial layer, implantation / diffusion of impurities, film formation, and patterning by photolithography. A chip substrate 41 on which is formed is prepared (FIG. 6). At this time, openings 63 and 64 are formed in the protective layer 56 and the interlayer insulating film 54 to expose the connection portions of the wiring layers 57 and 58 with the bumps 61 and 62. At this stage, the chip substrate 41 is in a state in which a plurality of chips are formed on one wafer, as in the normal semiconductor manufacturing process.

On the other hand, a plurality of the above-mentioned crystal oscillators 31 are prepared for each chip 1. The crystal unit 31 can be manufactured, for example, by the following method. That is, first, a relatively thick crystal blank is prepared, thinned to the above-mentioned thickness by machining, mechanical polishing, etc., and has the above-mentioned shape. Next, a metal film to be the excitation electrode 75 and the lead 79 is formed on the upper surface of the thinned quartz crystal plate by vapor deposition or the like, and is patterned into those shapes by the photolithography etching method or the like. Then, through holes 80 are formed in the quartz crystal plate by a photolithographic etching method or the like. After that, the excitation electrode 74 and the lead 7 are formed on the lower surface of the crystal blank.
8 and the connection pads 76, 77 are formed with a metal film, and patterned by photolithography or the like. Thereby, the crystal unit 31 can be manufactured. However, the manufacturing method of the crystal unit 31 is not limited to such a manufacturing method. For example, it is possible to employ a manufacturing method which is a modification of the manufacturing method shown in FIGS. The manufacturing method will be described later.

Next, as shown in FIG. 7, bumps 61 and 62 are formed at the openings 63 and 64 of the chip substrate 41 in the state shown in FIG. 6, and then the connection pads 76 of the crystal unit 31 are formed. , 77 are bumps 61, 6 respectively
Join to 2.

After that, the wafer in which the crystal unit 31 is integrated is separated into individual chips 1 by dicing or the like. As a result, the chip 1 is completed.

Finally, the chip 1 is housed in the package 2 in a vacuum state. As a result, the integrated circuit device according to this embodiment is completed.

In the integrated circuit device according to the present embodiment, an integrated circuit including the crystal unit 1, the clock generation circuit 31, and the CPU 33 is mounted on the chip substrate 41 and integrated together with the crystal unit 31. It is a one-chip chip. Therefore, according to the present embodiment,
The following advantages are obtained.

First, it is not necessary to interpose a wiring board or the like between the crystal oscillator 31 and the clock generating circuit 31 and between the clock generating circuit 31 and the CPU 33, and these are integrated together. The size can be remarkably reduced.

Secondly, the wiring between the crystal oscillator 31 and the clock generating circuit 32 is remarkably shortened, and the wiring between the clock generating circuit 32 and the CPU 33 is remarkably shortened. Is significantly reduced, and the generation of electromagnetic waves associated with clock generation is greatly suppressed. Moreover, in the present embodiment, since the electromagnetic shield metal layer 55 is formed over almost the entire element forming region, the generated electromagnetic wave is shielded and EMI is substantially not generated. In the present embodiment, there is no magnetic shield that covers the crystal unit 31 in the chip 1,
By using a conductive plate as the upper lid 21 of the package 2, this portion is also electromagnetically shielded. As described above, in the present embodiment, not only the generation of electromagnetic waves due to clock generation is greatly suppressed, but also EMI countermeasures are sufficiently taken. However, in the present embodiment, since the electromagnetic wave itself generated by the clock generation is reduced, it is not always necessary to form the electromagnetic shield metal layer 55,
The upper lid 21 of the package 2 does not necessarily have to have an electromagnetic shield function.

Thirdly, since the wiring between the crystal oscillator 31 and the clock generating circuit 32 becomes remarkably short and the wiring between the clock generating circuit 32 and the CPU 33 becomes remarkably short, the resistance components of these wirings are reduced. Becomes smaller, which reduces power consumption.

Further, according to the present embodiment, in addition to the main advantages described above, the following various advantages can be obtained.

That is, in the present embodiment, the excitation electrode 7
Since both of the two connection pads 76 and 77 electrically connected to the crystal oscillators 4 and 75 are formed on the lower surface of the crystal oscillator 31, the crystal oscillator 3 is formed only by the bumps 61 and 62.
1 can be electrically connected. Therefore,
The crystal oscillator 31 can be easily integrated with the chip substrate 41.

Further, in the present embodiment, the crystal oscillator 31
At the excitation electrode 7 formed on the upper surface of the quartz crystal plate 71.
5 and the connection pad 77 formed on the lower surface are connected via the conductive material (the metal forming the connection pad 77 in the present embodiment) present in the through hole 80, the excitation electrode 74, The crystal unit 31 having two connection pads 76 and 77 electrically connected to 75,
It can be easily manufactured. By forming such through holes 80, for example, FIG.
It is possible to adopt a manufacturing method which is a modification of the manufacturing method shown in FIG. In the field of crystal oscillators, there have been no cases or proposals for forming through holes for electrical connection on the front and back sides of the crystal element plate 71, and such an idea has never existed.

Further, according to the present embodiment, as described above, since the element (the MOSFET 44 in the example of FIG. 3) is formed in the region facing the crystal unit 31, it is possible to achieve high density and high integration. Can be converted.

By the way, in the present embodiment, instead of the crystal unit 31, the crystal unit 13 shown in FIGS. 8 and 9 is used.
1 may be used. FIG. 8 is a schematic plan view showing the crystal unit 131 viewed from the side opposite to the chip substrate, and corresponds to FIG. FIG. 9 is a schematic plan view showing the crystal unit 131 viewed from the chip substrate side, and corresponds to FIG.
8 and 9, elements that are the same as or correspond to the elements in FIGS. 4 and 5 are assigned the same reference numerals, and overlapping descriptions thereof will be omitted. The crystal resonator 131 shown in FIGS. 8 and 9 is different from the crystal resonator 31 shown in FIGS. 4 and 5 in that in the crystal resonator 131, the frame-shaped region 71d of the crystal resonator 31 is
The only difference is that the portions around the connection pads 76 and 77 are formed and are removed.

Further, in the present embodiment, instead of the crystal unit 31, the crystal unit 23 shown in FIGS. 10 and 11 is used.
1 may be used. FIG. 10 is a schematic plan view showing the crystal unit 231 viewed from the side opposite to the chip substrate, and corresponds to FIG. FIG. 11 is a schematic plan view showing the crystal unit 231 viewed from the chip substrate side, and corresponds to FIG. 8 and 9, elements that are the same as or correspond to the elements in FIGS. 4 and 5 are assigned the same reference numerals, and overlapping descriptions thereof will be omitted. Crystal unit 2 shown in FIGS. 10 and 11.
31 differs from the crystal unit 31 shown in FIGS. 4 and 5 in that in the crystal unit 231, the cutouts 72 and 73 formed in the crystal unit plate 71 in the crystal unit 31 are not formed. The only difference is that the crystal blank 71 is rectangular. Also in the crystal unit 131, the region outside the vibrating region 71a of the crystal element plate 71 is a region that does not substantially vibrate. It will be similar. The crystal unit 231 also has the same thin thickness as the crystal unit 31 over the entire crystal element plate 71.

The crystal units 131 and 231 are also
It can be manufactured by the same manufacturing method as the crystal unit 31.

[Second Embodiment]

FIG. 12 is a schematic sectional view schematically showing a part of the chip 101 used in the integrated circuit device according to the second embodiment of the present invention, and corresponds to FIG. Figure 1
In FIG. 2, the same or corresponding elements as those in FIG. 3 are designated by the same reference numerals, and the duplicate description thereof will be omitted.

The difference between the integrated circuit device according to the present embodiment and the integrated circuit device according to the first embodiment is that FIG.
12 is replaced with a chip 101 shown in FIG.
However, the only difference is that it is housed in the package 2 in FIG.

The chip 101 shown in FIG. 12 is different from the chip 1 shown in FIG. 3 only in the points described below.

In the chip 101, instead of the crystal unit 31 shown in FIGS. 4 and 5, a crystal unit having the same structure as the crystal unit 31 and having the frame-shaped region 71d of the crystal unit plate 71 expanded outward. 331 is used. Crystal oscillator 33
One frame-shaped region 71d is joined to the reinforcing plate 91 with the adhesive 90 and is reinforced by the reinforcing plate 91. Adhesive 90
Is a vibration region 71a of the crystal blank 71 of the crystal unit 331.
However, the thickness of the adhesive 90 ensures a vibration space above the vibration region 71a of the quartz crystal plate 71. The material of the reinforcing plate 91 is not particularly limited, but a metal plate or the like is used as the reinforcing plate 91 so that the reinforcing plate 91 acts as an electromagnetic shield, or
It is preferable to form a metal layer or the like for electromagnetic shielding on the upper surface or the lower surface of the reinforcing plate 91. When the reinforcing plate 91 has an electromagnetic shield function, it is not necessary to give the package 2 an electromagnetic shield function.

Further, in the chip 101, since the bonded body of the crystal oscillator 331 in which the frame-shaped region 71d of the crystal element plate 71 is expanded and the reinforcing plate 91 is stably integrated with the chip substrate 41 side, the crystal is formed. Expanded frame-shaped region 71d of the base plate 71
Are bonded to the protective layer 56 with an adhesive 92 at a plurality of scattered points. As the adhesive 92, for example,
A polyimide-based, epoxy-based, or silicon-based adhesive can be used. The adhesive 92 may be insulative or conductive.

The bonded body of the crystal unit 331 and the reinforcing plate 91 may have a size that covers almost the entire area of the chip substrate 41, or a size that covers a local area of the chip substrate 41. You may have. Even in the former case, the size of the bonded body of the crystal unit 331 and the reinforcing plate 91 is as shown in FIG.
Chip substrate 4 to which the bonding wire 16 therein is connected
The size is set so as not to cover the external connection electrode (not shown) on the first electrode 1.

Next, an example of a method of manufacturing the integrated circuit device according to this embodiment will be described with reference to FIGS. FIG. 13 is a schematic cross-sectional view schematically showing the step of the manufacturing method, and corresponds to FIG. 14
[Fig. 4] is a schematic plan view schematically showing another step of the manufacturing method. Also, refer to FIG. 6 again.

First, according to a normal semiconductor manufacturing process,
A chip substrate 41 on which a portion of the integrated circuit shown in FIG. 2 excluding the crystal oscillator 31 is formed is prepared (FIG. 6). At this time, the wiring layer 5 is formed on the protective layer 56 and the interlayer insulating film 54.
Openings 63 and 64 for exposing the connection portions of the bumps 61 and 62 with the bumps 7 and 58 are formed in advance. At this stage, as in the normal semiconductor manufacturing process, the chip substrate 41 is formed by forming a plurality of chips on one wafer as shown in FIG. In FIG. 14, 41
a indicates an area for one chip. Further, although the alignment mark 95 is formed on the wafer 41 in FIG. 14, this is not always necessary in this manufacturing method.

On the other hand, a plurality of bonded bodies of the above-described crystal oscillator 331 and the reinforcing plate 91 are prepared for each chip 101. This bonded body is, for example, a crystal oscillator 331 for one chip manufactured by a manufacturing method similar to that of the crystal oscillator 31 described in relation to the first embodiment, and a reinforcing plate for one chip. It can be manufactured by bonding 91 with an adhesive 90. In addition, this bonded body has, for example, one crystal element plate having regions for a plurality of chips, the removal regions 72, 73 for the plurality of chips 101, and the excitation electrode 7.
4, 75, leads 78, 79, connection pads 76, 77, and through holes 80 are formed, and then a reinforcing plate 91 having regions for a plurality of chips is joined with an adhesive 90 to form a joined body for the plurality of chips. Individual chip 1 by dicing
It can also be manufactured by separating into those corresponding to.

Next, as shown in FIG. 13, bumps 61 and 62 are formed at the openings 63 and 64 of the chip substrate 41 in the state shown in FIG. 6 and are adhered to the protective film 56 at predetermined locations. After the agent 92 is formed, the connection pads 76 and 77 of the crystal unit 331 are connected to the bumps 6 respectively.
1, 62, and the lower surface of the expanded region of the crystal element plate 71 of the crystal unit 331 is bonded to the adhesive agent 92.

Thereafter, the wafer in which the bonded body of the crystal oscillator 331 and the reinforcing plate 91 is integrated is separated into individual chips 1 by dicing or the like. As a result, the chip 101 is completed.

Finally, the chip 101 is housed in the package 2 in a vacuum state. As a result, the integrated circuit device according to this embodiment is completed.

In the manufacturing method described above, the crystal unit 331 is used.
When the joined body of the reinforcing plate 91 and the reinforcing plate 91 was joined onto the chip substrate 41, the joined body was separated into one chip. However, for example, if the following manufacturing method is adopted, batch processing can be performed on the joined body, and mass productivity can be further improved.

In this manufacturing method, similarly to the manufacturing method described above, the chip substrate 41 on which the portion of the integrated circuit shown in FIG. 2 excluding the crystal oscillator 31 is formed is prepared (FIGS. 6 and 14). At this time, as shown in FIG. 14, alignment marks 95 made of a metal film or the like are formed on the wafer that constitutes the chip substrate 41.

On the other hand, a bonded body of the crystal resonator 331 including a plurality of chip regions and the reinforcing plate 91 is formed, for example, as shown in FIG.
It is prepared by the manufacturing method shown in FIGS. 16 to 20 are schematic cross-sectional views schematically showing each step of the method for manufacturing the joined body. For convenience of drawing notation, FIG.
6 to 20 show areas for three chips.

First, a comparatively thick crystal element plate 150 including a plurality of chip regions (the crystal element plate 150 will eventually become the crystal element plate 71 in FIG. 12) is prepared, and this crystal element is prepared. On the plate 150, a metal film 151 to be the excitation electrode 75 and the leads 79 is formed in an island shape (FIG. 16). This formation is performed by depositing a metal film 15 on the entire surface of the crystal blank 150.
After formation of No. 1, it can be performed by patterning by a photolithographic etching method or the like.

Next, the crystal blank 150 in the state shown in FIG.
Above, the vibrating region 71a of the crystal blank 71 in FIG.
A resist 152 serving as a sacrificial layer is formed in an island shape at a place to be an upper vibration space. Then, on the crystal blank 150, in the region where the vibration region 71a is not formed,
An adhesive 153 corresponding to the adhesive 90 in FIG. 12 is arranged, and the reinforcing plate 154 corresponding to the reinforcing plate 91 is joined by this adhesive 153 (FIG. 17).

Next, the crystal blank 15 in the state shown in FIG.
The lower surface side of 0 is removed to thin the quartz crystal plate 150 to a desired thickness. This can be performed by any one of mechanical polishing, chemical mechanical polishing, and etching, or a combination of two or more, for example. In the case of etching, wet etching, dry etching, or a combination of both may be used. NH ₄ HF ₂ or HF, for example, can be used as an etching solution when performing wet etching. Also,
When dry etching is performed, for example, reactive ion etching using CF ₄ as a gas can be used. After that, a through hole 155 corresponding to the through hole 80 in FIG. 12 is formed by the photolithography etching method or the like (FIG. 18).

Next, the crystal blank 150 in the state shown in FIG.
A metal film 156 to be the excitation electrode 74, the lead 78, and the connection pads 76 and 77 is formed in an island shape on the lower surface of the substrate (FIG. 19). This formation can be performed by vapor deposition of the metal film 156 and patterning by the photolithographic etching method.

After that, the crystal blank 15 in the state shown in FIG.
After forming openings 157 corresponding to the cutouts 72 and 73 in FIGS. 4 and 5 by photolithography or the like, the resist 152 is removed by ashing or the like (FIG. 20). As a result, a bonded body (bonded body shown in FIG. 20) of the crystal unit 331 including the regions for a plurality of chips and the reinforcing plate 91 is completed.

A view taken along the line CC 'in FIG. 20 is shown in FIG. In FIG. 20, the metal layer 156 is omitted. Figure 20
In the figure, reference numeral 150a indicates an area for one chip.
Note that, for convenience of drawing notation, the position of the opening 157 is not accurately shown in FIG. As shown in FIG.
An alignment mark 159 is formed on the crystal blank plate 150 of this bonded body. This alignment mark 1
59 can be formed simultaneously with the metal film 156, for example. This alignment mark 159 is shown in FIG.
It is used together with the alignment mark 95 therein to align the bonded body with the wafer shown in FIG.

After the wafer shown in FIG. 14 and the bonded body shown in FIG. 15 are prepared as described above, the bumps 61 and 62 in FIG. 12 and the bumps corresponding to the adhesive 92 in FIG. 12 are formed on the wafer shown in FIG. Adhesives 92 are respectively formed, the wafer and the bonded body are aligned using the alignment marks 95 and 159, and both are bonded. Looking at each individual chip, it becomes similar to the case of FIG. After that, the individual chips 101 are separated by dicing or the like. If the crystal unit may be damaged by dicing, the entire surface of the crystal element plate 150 may be protected by resist or wax and removed after dicing, or the crystal element plate 150 and the wafer shown in FIG. 14 may be removed in advance. You may cut it in half. As a result, the chip 101 is completed.

Finally, the chip 101 is housed in the package 2 in a vacuum state. As a result, the integrated circuit device according to this embodiment is completed.

If the manufacturing method described above is carried out as it is, the bonded body of the crystal unit 331 and the reinforcing plate 91 has a size that covers the entire area of the chip substrate 41, and the structure shown in FIG.
Chip substrate 4 to which the bonding wire 16 therein is connected
The external connection electrode (not shown) on 1 is covered with the crystal element plate 71 and the reinforcing plate 91, and the wire 16 cannot be bonded. So, in fact,
Although not shown in the drawing, for example, an opening is formed in advance in a region corresponding to the region where the external connection electrode is arranged in the reinforcing plate 91, and the crystal blank plate 150 is formed in the process shown in FIG. The openings corresponding to the openings of the reinforcing plate 91 may be formed together with the openings 157. Alternatively, FIG.
The wafer shown in FIG. 4 and the bonded body shown in FIG. 15 are separately half-cut in advance so that the chip portion of the bonded body becomes smaller than the chip portion of the wafer and the wire 16 can be bonded. After joining, the individual chips 101 may be separated along each of the pre-half-cut dicing lines.

The integrated circuit device according to the present embodiment also has the same advantages as the integrated circuit device according to the first embodiment.

The integrated circuit device according to this embodiment may be modified as follows. In the present embodiment, as described above, the expanded frame-shaped regions 71d of the quartz crystal plate 71 are bonded to the protective layer 56 with the adhesive 92 at a plurality of scattered points. Therefore, the vibrating region 71a of the crystal blank 71 is open to any space in the package 2. On the other hand, by providing the adhesive 92 so as to circulate a region including a region facing the vibration region 71a, the adhesive 92 hermetically seals the space where the vibration region 71a of the quartz crystal plate 71 is located. May be provided. In this case, by performing the process shown in FIG. 13 in a vacuum, the space in which the vibration region 71a of the quartz crystal plate 71 is arranged can be made a vacuum. Therefore, in this case, even if the chip 101 is housed in the normal package instead of the package 2, the space in which the vibration region 71a is arranged can be evacuated.

By the way, a manufacturing method obtained by modifying the manufacturing method shown in FIGS.
The crystal unit 31 in FIG. 3 can be manufactured. That is, after the steps shown in FIGS. 16 to 19, in the step shown in FIG. 20, the opening along the outer shape of the crystal unit 31 is formed together with the opening 157, and the resist 152 may be removed. . As a result, the crystal unit 31 is separated from the reinforcing plate 91 and the like, and the crystal unit 31 is completed. In this case, since the crystal oscillator 31 is separated from the reinforcing plate 91 and the like, for example, at the stage shown in FIG. 17, a resist 153 as a sacrificial layer is formed on the entire area of the piezoelectric element plate 150, and the upper surface of the resist 153 is removed. The whole may be bonded to the reinforcing plate 154 with an adhesive.

[Third Embodiment]

FIG. 21 is a schematic sectional view schematically showing a part of the chip 201 used in the integrated circuit device according to the third embodiment of the present invention, and corresponds to FIG. Figure 2
1, the same or corresponding elements as those in FIG. 3 are designated by the same reference numerals, and the duplicated description will be omitted. FIG. 22
21 is a DD ′ arrow view in FIG. 21 in which only the crystal unit 431 is viewed, and corresponds to FIG. 8. 23 is a view taken along the line EE ′ in FIG. 21 in which only the crystal unit 431 is viewed,
It corresponds to FIG. In FIGS. 22 and 23, FIG.
Further, the same or corresponding elements as those in FIG. 9 are designated by the same reference numerals, and the duplicate description thereof will be omitted.

The difference of the integrated circuit device according to the present embodiment from the integrated circuit device according to the first embodiment is that FIG.
21 is replaced with the chip 201 shown in FIG.
However, the only difference is that it is housed in the package 2 in FIG.

The chip 201 shown in FIG. 21 differs from the chip 1 shown in FIG. 3 only in the points described below.

In the chip 201, a crystal oscillator 431 is used instead of the crystal oscillator 31 shown in FIGS. The crystal oscillator 431 is different from the crystal oscillator 131 shown in FIGS. 8 and 9 in that, as shown in FIGS. 21 to 23, the connection pad 77 electrically connected to the excitation electrode 75.
However, like the excitation electrode 75, it is formed only on the upper surface of the quartz crystal plate 71, and the through hole 80 is not formed.

Further, in the chip 201, as shown in FIG. 21, the bump 61 in FIG.
The lower surface of the crystal blank 71 is bonded to the upper surface of the protective film 56 with an adhesive 202 at a position corresponding to 7. The wiring layer 58 is formed on the protective layer 56 and the interlayer insulating film 54 at a position laterally displaced from the region facing the crystal unit 431.
An opening 203 is formed to expose a part of the. And a part of the wiring layer 58 exposed from the opening 203,
The bonding pads 204 on the upper surface of the crystal unit 431 are electrically connected by the bonding wires 204.

Next, an example of a method of manufacturing the integrated circuit device according to this embodiment will be described with reference to FIGS. 24 and 25. 24 and 25 are schematic cross-sectional views schematically showing each step of the manufacturing method and correspond to FIG. 21. 24 and 25, the same elements as those of FIG. 21 are designated by the same reference numerals.

First, according to a normal semiconductor manufacturing process,
A chip substrate 41 on which a portion of the integrated circuit shown in FIG. 2 excluding the crystal oscillator 31 is formed is prepared (FIG. 24). At this time, in the protective layer 56 and the interlayer insulating film 54, the opening 63 exposing the connection portion of the wiring layer 57 with the bump 61 and the opening 2 exposing a part of the wiring layer 58.
03 is formed. At this stage, the chip substrate 41 is in a state in which a plurality of chips are formed on one wafer, as in the normal semiconductor manufacturing process.

On the other hand, a plurality of crystal oscillators 431 described above are prepared for each chip 201. Crystal oscillator 43
1 can be manufactured by the same manufacturing method as that of the crystal oscillator 31. However, the through hole 80 is not formed.

Next, as shown in FIG. 25, the bumps 61 are formed at the openings 63 in the chip substrate 41 in the state shown in FIG. 24, and the adhesive 202 is formed at the positions shown in the figure. Connection pad 76 of oscillator 431
Is bonded to the bump 61, and the lower surface of the crystal unit 31 is bonded to the adhesive 202. Next, as shown in FIG. 21, the connection pad 77 on the upper surface of the crystal unit 431 and the portion of the wiring layer 58 exposed from the opening 203 are connected by a bonding wire 204.

Thereafter, the wafer in which the crystal unit 431 is integrated is processed into individual chips 1 by dicing or the like.
To separate. As a result, the chip 1 is completed.

Finally, the chip 1 is housed in the package 2 in a vacuum state. As a result, the integrated circuit device according to this embodiment is completed.

The integrated circuit device according to the present embodiment also has the same advantages as the integrated circuit device according to the first embodiment. However, in the case of manufacturing the integrated circuit device according to the present embodiment, the step of connecting with the bonding wire 204 as described above is required, and thus the first embodiment is preferable because the manufacturing is easier.

[Fourth Embodiment]

FIG. 26 is a schematic sectional view schematically showing a part of the chip 301 used in the integrated circuit device according to the fourth embodiment of the present invention, and corresponds to FIG. Figure 2
6, elements that are the same as or correspond to the elements in FIG. 3 are assigned the same reference numerals, and duplicate descriptions thereof will be omitted.

The integrated circuit device according to this embodiment is different from the integrated circuit device according to the first embodiment in that FIG.
26, instead of the chip 1 shown in FIG.
However, it is only contained in a normal package instead of the package 2 in FIG.

In the chip 301, the N-type silicon epitaxial layer 45, which is a laminated portion on the chip substrate 41, is formed relatively thick, the MOSFET 44 is removed, and the recess 3 is formed in the N-type silicon epitaxial layer 45 in the vicinity thereof.
02 is formed, and the crystal unit 31 is housed in the recess 302. A lid 303 is provided on the opening side above the recess 302.
Is blocked by. The peripheral portion of the lid 303 is the adhesive 30
4 is airtightly adhered to the interlayer insulating film 54. Recess 30
2 and the lid 303 form a storage chamber for the crystal unit 31. In the present embodiment, this storage chamber is almost vacuumed. It is preferable that the lid 303 is a conductive plate such as a metal plate for electromagnetic shielding or has a conductive layer such as a metal layer for electromagnetic shielding formed in order to prevent EMI.

Next, an example of a method of manufacturing the integrated circuit device according to this embodiment will be described with reference to FIGS. 27 and 28. 27 and 28 are schematic cross-sectional views schematically showing each step of the manufacturing method, and correspond to FIG. 26. 27 and 28, the same elements as those of FIG. 26 are designated by the same reference numerals.

First, according to a normal semiconductor manufacturing process,
A chip substrate 41 on which a portion of the integrated circuit shown in FIG. 2 excluding the crystal oscillator 31 is formed is prepared (FIG. 27). At this time, the N-type silicon epitaxial layer 45 is formed relatively thick, and the recess 302 is formed in the N-type silicon epitaxial layer 45 by a photolithographic etching method or the like. Further, in the recess 302, openings 63 and 64 are formed in the interlayer insulating film 54 to expose the connection portions of the wiring layers 57 and 58 with the bumps 61 and 62.
At this stage, the chip substrate 41 is in a state in which a plurality of chips are formed on one wafer, as in the normal semiconductor manufacturing process.

On the other hand, the crystal unit 31 is attached to each chip 20.
Prepare a plurality corresponding to 1.

Next, as shown in FIG. 28, bumps 61 and 62 are formed at the openings 63 and 64 of the chip substrate 41 in the state shown in FIG. And the connection pads 76 and 77 of the crystal unit 31 are bonded to the bumps 61 and 62, respectively. Then, the peripheral edge of the lid 303 is bonded to the interlayer insulating film 54 with an adhesive 304, and the opening side of the recess 302 is closed with the lid 303. By performing this step in vacuum,
The space in the recess 302 is evacuated.

After that, the wafer in which the crystal unit 31 is integrated and the recess 302 is closed by the lid 303 is separated into individual chips 301 by dicing or the like. As a result, the chip 301 is completed.

Finally, the chip 301 is placed in the normal package.
To house. As a result, the integrated circuit device according to this embodiment is completed.

The integrated circuit device according to this embodiment also has the same advantages as the integrated circuit device according to the first embodiment. According to the present embodiment, even if the chip 301 is housed in the normal package, the crystal unit 3
1 can be placed in a vacuum space.

[Fifth Embodiment]

FIG. 29 is a schematic sectional view schematically showing a part of the chip 401 used in the integrated circuit device according to the fifth embodiment of the present invention, and corresponds to FIG. Figure 2
9, elements that are the same as or correspond to the elements in FIG. 3 are assigned the same reference numerals, and overlapping descriptions thereof will be omitted. Figure 30
29 is a view as seen from the arrow FF ′ in FIG. 29 in which only the crystal unit 531 is viewed, and corresponds to FIG. 10. FIG. 31 is a GG ′ arrow view in FIG. 29 in which only the crystal unit 531 is viewed, and corresponds to FIG. 11. 30 and 31, elements that are the same as or correspond to the elements in FIGS. 10 and 11 are assigned the same reference numerals, and duplicated description thereof is omitted.

3 is different from the integrated circuit device according to the first embodiment in that the integrated circuit device according to this embodiment is different from that shown in FIG.
29, instead of the chip 1 shown in FIG.
However, the only difference is that it is housed in the package 2 in FIG.

The chip 401 shown in FIG. 29 is different from the chip 1 shown in FIG. 3 only in the points described below.

In the chip 401, a crystal oscillator 531 is used instead of the crystal oscillator 31 shown in FIGS. 4 and 5. The crystal oscillator 531 is different from the crystal oscillator 231 shown in FIGS. 10 and 11 in that the crystal oscillator 231 has the same thickness as the entire crystal element plate 71 but is thin. In FIG. 531, the crystal blank 71 is shown in FIG.
As shown in FIGS. 31A to 31C, a thin portion 71A in a rectangular area having a thin center and a thin portion 71A including a vibration area 71a.
And a thick wall portion 71B having a large peripheral thickness. The thin portion 71A has a thickness of, for example, several μm to ten and several μm.
The thickness of 1B can be, for example, several tens of μm to one hundred and several tens of μm. The through hole 80 is formed in a region of the thin portion 71A that is deviated from the vibration region 71a. The connection pads 76 and 77 are formed on the thick portion 71B. The lead 78 is formed on the lower surface of the quartz crystal plate 71 by the thin portion 71.
It extends from the excitation electrode 74 formed in A to the connection pad 76 formed in the thick portion 71B. Through hole 8 formed in thin portion 71A on the lower surface of crystal blank 71
The lead 81 extends from the position 0 to the connection pad 77, whereby the excitation electrode 75 formed on the upper surface of the thin portion 71A is connected to the connection pad 7 via the leads 79 and 81.
7 is electrically connected.

Next, an example of a method of manufacturing the integrated circuit device according to this embodiment will be described with reference to FIG.
32 is a schematic cross-sectional view schematically showing the step of the manufacturing method, and corresponds to FIG. 29. Also, refer to FIG. 6 again.

First, according to the usual semiconductor manufacturing process,
A chip substrate 41 on which a portion of the integrated circuit shown in FIG. 2 excluding the crystal oscillator 31 is formed is prepared (FIG. 6). In addition,
At this stage, the chip substrate 41 is one in which a plurality of chips are formed on one wafer, as in a normal semiconductor manufacturing process.

On the other hand, a plurality of crystal oscillators 531 described above are prepared for each chip 401. Crystal oscillator 53
1 can be manufactured by the following manufacturing method, for example. First, a crystal blank having the same thickness as the thick portion 71B is prepared, and the region corresponding to the thin portion 71 is thinned to a desired thickness by photolithography. The etching at this time may be wet etching, dry etching, or a combination of both. NH ₄ HF ₂ or HF, for example, can be used as an etching solution when performing wet etching. Also,
When dry etching is performed, for example, reactive ion etching using CF4 gas can be used.

Next, a metal film to be the excitation electrode 75 and the lead 79 is formed by vapor deposition or the like on the upper surface of the quartz crystal plate in which the region corresponding to the thin portion 71A is thinned, and those shapes are formed by photolithography etching or the like. Pattern. Then, through holes 80 are formed in the quartz crystal plate by a photolithographic etching method or the like. Then, the excitation electrode 74, the leads 78 and 81, and the connection pad 7 are formed on the lower surface of the crystal blank.
Metal films to be 6, 77 are formed and patterned into those shapes by a photolithographic etching method or the like. Thereby, the crystal unit 531 can be manufactured. However, the manufacturing method of the crystal unit 531 is not limited to such a manufacturing method.

Next, as shown in FIG. 32, the bumps 61 and 62 are formed at the openings 63 and 64 in the chip substrate 41 in the state shown in FIG.
The connection pads 76 and 77 of 31 are connected to the bumps 61 and 6 respectively.
Join to 2.

After that, the wafer in which the crystal unit 531 is integrated is diced or the like into individual chips 4.
Separation into 01. As a result, the chip 401 is completed.

Finally, the chip 401 is housed in the package 2 in a vacuum state. As a result, the integrated circuit device according to this embodiment is completed.

The integrated circuit device according to the present embodiment also has the same advantages as the integrated circuit device according to the first embodiment. Further, according to the present embodiment, since the crystal blank 71 has the thick portion 71B, the strength of the crystal resonator 531 can be increased without using a reinforcing plate.

[Sixth Embodiment]

FIG. 33 is a schematic sectional view showing a part of the chip 501 used in the integrated circuit device according to the sixth embodiment of the present invention, and corresponds to FIG. In FIG. 33, elements that are the same as or correspond to the elements in FIG. 29 are assigned the same reference numerals, and overlapping descriptions thereof will be omitted.

The difference between the integrated circuit device according to the present embodiment and the integrated circuit device according to the fifth embodiment is that FIG.
33, instead of the chip 401 shown in FIG.
1 is only contained in the package 2 in FIG.

The chip 501 shown in FIG. 33 differs from the chip 501 shown in FIG. 29 only in the points described below.

In the chip 501, instead of the crystal unit 531 shown in FIGS. 30 and 31, a crystal unit having the same structure as the crystal unit 531 and having the thick portion 71B of the crystal base plate 71 expanded outward. 631 is used. In the chip 501, the crystal unit 631 having the expanded thick portion 71B is stably integrated with the chip substrate 41 side.
The expanded thick portion 71B is bonded to the protective layer 56 with the adhesive 92 at a plurality of points scattered.

The quartz crystal plate 71 may have a size to cover almost the entire region of the chip substrate 41, or the chip substrate 4
It may have a size that covers one local area. Even in the former case, the size of the crystal element plate 71 is the same as that of the chip substrate 41 to which the bonding wire 16 in FIG. 1 is connected.
The size is set so as not to cover the upper external connection electrode (not shown).

Next, an example of a method of manufacturing the integrated circuit device according to this embodiment will be described with reference to FIG.
34 is a schematic cross-sectional view schematically showing the step of the manufacturing method, and corresponds to FIG. 33. Also, refer to FIG. 6 again.

First, according to a normal semiconductor manufacturing process,
A chip substrate 41 on which a portion of the integrated circuit shown in FIG. 2 excluding the crystal oscillator 31 is formed is prepared (FIG. 6). In addition,
At this stage, the chip substrate 41 is one in which a plurality of chips are formed on one wafer, as in a normal semiconductor manufacturing process.

On the other hand, a plurality of crystal oscillators 631 described above are prepared for each chip 101. The crystal unit 631 can be manufactured by the same manufacturing method as the crystal unit 531 shown in FIGS. 30 and 31.

Next, as shown in FIG. 34, bumps 61 and 62 are formed in the openings 63 and 64 of the chip substrate 41 in the state shown in FIG. 6 and adhered to the protective film 56 at predetermined locations. After the agent 92 is formed, the connection pads 76 and 77 of the crystal unit 631 are formed on the bumps 6 respectively.
1, 62 while bonding the lower surface of the expanded thick portion 71B of the crystal blank 71 of the crystal unit 631 with the adhesive 92.
To join.

Thereafter, the wafer in which the bonded body of the crystal unit 331 and the reinforcing plate 91 is integrated is separated into individual chips 1 by dicing or the like. As a result, the chip 101 is completed.

Finally, the chip 501 is housed in the package 2 in a vacuum state. As a result, the integrated circuit device according to this embodiment is completed.

In the manufacturing method described above, the crystal unit 331 is used.
When the joined body of the reinforcing plate 91 and the reinforcing plate 91 was joined onto the chip substrate 41, the joined body was separated into one chip. However, the crystal unit 631 is also formed on a single crystal element plate for a plurality of chips, and the crystal element plate on which the plurality of chips are formed is bonded to a wafer of a chip substrate on which a plurality of chips are formed. Later, by separating the chips 501 into individual chips 501 by dicing or the like, the quartz crystal resonator 631 can be batch-processed, and the mass productivity is further enhanced. In this case, an opening is previously formed in the crystal blank plate 71 in a region corresponding to a region on the chip substrate 41 where an external connection electrode (not shown) is arranged.

The integrated circuit device according to the present embodiment also has the same advantages as the integrated circuit device according to the first embodiment.

The integrated circuit device according to this embodiment may be modified as follows. In the present embodiment, as described above, the expanded thick portion 71B of the quartz crystal plate 71 is bonded to the protective layer 56 with the adhesive 92 at a plurality of scattered points. On the other hand, the adhesive 92 is applied to the vibration area 71.
By arranging the adhesive 92 so as to circulate a region including a region facing a, the adhesive 92 is applied to the vibration region 71 of the crystal blank 71.
It may be provided so as to hermetically seal the space in which a is located. In this case, by performing the process shown in FIG. 34 in a vacuum, the space in which the vibrating region 71a of the quartz crystal plate 71 is arranged can be made a vacuum. Therefore, in this case, the chip 1 is placed in the normal package instead of the package 2.
Even if 01 is accommodated, the space in which the vibrating region 71a is arranged can be evacuated.

[Seventh Embodiment]

FIG. 35 is a schematic sectional view schematically showing a part of a chip 601 used in the integrated circuit device according to the seventh embodiment of the present invention, and corresponds to FIG. Figure 3
5, elements that are the same as or correspond to the elements in FIG. 3 are assigned the same reference numerals, and overlapping descriptions thereof will be omitted.

The difference between the integrated circuit device according to the present embodiment and the integrated circuit device according to the first embodiment is that FIG.
35, in place of the chip 1 shown in FIG.
However, the only difference is that it is housed in the package 2 in FIG.

The point that the chip 601 is different from the chip 1 is mainly the points described below. The chip 601 also uses the crystal oscillator 31 shown in FIGS. 4 and 5 like the chip 1.

In the chip 1, the N-type silicon substrate is used as the chip substrate 41, while the chip 601 is used.
Then, the material of the chip substrate 41 is not particularly limited, and may be, for example, a metal substrate, a semiconductor substrate, a glass substrate, a ceramic substrate, or the like. Further, the chip 1 and the chip 601 have the same circuit configuration mounted on the chip substrate 41, but the structures of the laminated portions on the chip substrate 41 are different.

In FIG. 35, 602 is a metal wiring layer 57.
Is a P-type impurity layer serving as a conductive path connected to, 603 is a P-type impurity layer serving as a conductive path connected to the metal wiring layer 58, and 604 is P serving as a conductive path connected to the external connection metal wiring layer 605. Type impurity layer 699 is a P type impurity layer 6
A dielectric isolation layer made of an insulating film such as a silicon oxide film for insulating 02, 603 and 604, 605 a metal wiring layer for external connection, 606 an adhesive layer, 607 a PSG film, 6
Reference numeral 08 denotes a metal wiring layer connected to the P-type impurity layer 602 and thereby connected to the clock generation circuit 32 (see FIG. 2) via the wiring layer 57, and 609 connects to the P-type impurity layer 603, which results in the wiring layer 58. Clock generation circuit 3 via
2 (see FIG. 2) is a metal wiring layer connected to the P-type impurity layer 604, which is connected to the external connection wiring layer 605. Note that a wiring layer, another element, another interlayer insulating film, or the like is formed between the interlayer insulating film 54 and the adhesive layer 606 as needed, but they are omitted in FIG. 35. The P-type impurity layers 602, 603 and 604 and the dielectric isolation layer 699 described above are used.
Form a so-called trench structure.

In this embodiment, the connection pads 76 and 77 of the crystal unit 31 are electrically and mechanically connected to the wiring layers 608 and 609 via the bumps 61 and 62, respectively.

Next, an example of a method of manufacturing the integrated circuit device according to the present embodiment will be described with reference to FIGS. 36 to 39. 36 to 39 are schematic cross-sectional views schematically showing each step of the manufacturing method and correspond to FIG. 35. However, in FIG. 35 and FIGS. 36 to 38, the upper and lower sides are inverted. 36 to 39, the same or corresponding elements as those in FIG. 35 are designated by the same reference numerals.

First, by the steps shown in FIGS. 36 to 38, the chip substrate 41 on which the portion of the integrated circuit shown in FIG. 2 excluding the crystal unit 31 is formed is prepared.

These steps will be described with reference to the structure shown in FIG. 35. First, the N-type silicon substrate 641 is prepared, and the N-type silicon epitaxial layer 45 is grown on the substrate 641. Then, the dielectric isolation layer 699 and the P-type impurity layers 602 to 604 are formed on the N-type silicon epitaxial layer 45. At this time, the lower portions of the dielectric isolation layer 699 and the P-type impurity layers 602-604 extend to the substrate 641. Next, according to a normal semiconductor manufacturing process, the P-type well layer 46, the P-type impurity layer 47, the N-type impurity layer 48, and the element isolation impurity layer 4 are formed.
9, silicon oxide films 50 and 51, source or drain electrode 52, gate electrode 53, and interlayer insulating film 54 are formed (FIG. 36).

Next, the silicon substrate 6 in the state shown in FIG.
The chip substrate 41 is bonded onto the interlayer insulating film 54 on 41 with an adhesive 606. The material of the chip substrate 41 is not particularly limited as described above. Then, the silicon substrate 641 is removed and the N-type silicon epitaxial layer 45 is slightly thinned by etching or the like (FIG. 37).

After that, the N-type silicon epitaxial layer 4 is formed.
5, a PSG film 607 is formed by plasma CVD on the lower surface, and a part of the PSG film 607 is removed by a photolithography etching method to expose the P-type impurity layers 602 to 604, and wiring layers 608 to 610 are formed at these locations. Form each. Note that an insulating film that can be formed at a low temperature of 500 ° C. or lower may be used instead of the PSG film 607, and the method for forming the insulating film in that case is not limited to plasma CVD. Next, the electromagnetic shield metal layer 55 and the protective film 56 are formed so that the wiring layers 608 to 610 are not covered (FIG. 38).

As described above, the step of preparing the chip substrate 41 in which the portion excluding the crystal oscillator 31 of the integrated circuit shown in FIG. 2 is prepared is completed.

On the other hand, the crystal unit 31 is attached to each chip 60.
Prepare a plurality corresponding to 1.

Next, as shown in FIG. 39, the wiring layers 608, 60 on the chip substrate 41 in the state shown in FIG.
After forming the bumps 61 and 62 at the positions of 9, respectively, the connection pads 76 and 77 of the crystal unit 31 are bonded to the bumps 61 and 62, respectively.

Thereafter, the wafer in which the crystal unit 31 is integrated is diced or the like into individual chips 60.
Separate into 1. As a result, the chip 601 is completed.

Finally, the chip 1 is housed in the package 2 in a vacuum state. As a result, the integrated circuit device according to this embodiment is completed. The bonding wire 16 in FIG. 1 is connected to the external connection wiring layer 605.

The integrated circuit device according to this embodiment also has the same advantages as the integrated circuit device according to the first embodiment.

[Eighth Embodiment]

FIG. 40 is a schematic sectional view schematically showing a part of a chip 701 used in the integrated circuit device according to the eighth embodiment of the present invention, and corresponds to FIG. Figure 4
0, the same or corresponding elements as those in FIG. 3 are designated by the same reference numerals, and the duplicated description thereof will be omitted.

The difference between the integrated circuit device according to the present embodiment and the integrated circuit device according to the first embodiment is that FIG.
40 is replaced with a chip 701 shown in FIG.
However, the only difference is that it is housed in the package 2 in FIG.

The chip 701 is different from the chip 1 mainly in the points described below. The chip 701 also uses the crystal oscillator 31 shown in FIGS. 4 and 5 like the chip 1.

In the chip 1, the N-type silicon substrate is used as the chip substrate 41, while the chip 701 is used.
Then, the material of the chip substrate 41 is not particularly limited, and may be, for example, a metal substrate, a semiconductor substrate, a glass substrate, a ceramic substrate, or the like. Further, the chip 1 and the chip 701 have the same circuit configuration mounted on the chip substrate 41, but the structures of the laminated portions on the chip substrate 41 are different. In FIG. 40, 705 is a metal wiring layer for external connection, 706 is an adhesive layer, and 707 is an opening formed in the N-type silicon epitaxial layer 45 and the protective film 56 to expose the metal wiring layer for external connection 705 to the outside. It is a department. Note that a wiring layer, another element, another interlayer insulating film, or the like is formed between the interlayer insulating film 54 and the adhesive layer 606 as needed, but they are omitted in FIG. 35.

In this embodiment, the connection pads 76 and 77 of the crystal unit 31 are electrically and mechanically connected to the wiring layers 57 and 58 via the bumps 61 and 62, respectively.

Next, an example of a method of manufacturing the integrated circuit device according to this embodiment will be described with reference to FIGS. 41 to 44. 41 to 44 are schematic cross-sectional views schematically showing each step of the manufacturing method and correspond to FIG. 40. However, in FIGS. 40 and 41 to 43, the upper and lower sides are inverted. 41 to 44, the same or corresponding elements as those of FIG. 41 are designated by the same reference numerals.

First, by the steps shown in FIGS. 41 to 43, the chip substrate 41 on which the portion of the integrated circuit shown in FIG. 2 excluding the crystal unit 31 is formed is prepared.

These steps will be described with reference to the structure in the range shown in FIG. 40. First, the N-type silicon substrate 741 is prepared, and the N-type silicon epitaxial layer 45 is grown on the substrate 741. Next, according to a normal semiconductor manufacturing process, a P-type well layer 46, a P-type impurity layer 47, an N-type impurity layer 48, an element isolation impurity layer 49,
Silicon oxide film 50, 51, source or drain electrode 5
2, gate electrode 53, and interlayer insulating film 54 are formed (FIG. 4).
1).

Next, the silicon substrate 7 in the state shown in FIG.
The chip substrate 41 is bonded onto the interlayer insulating film 54 on 41 with an adhesive 706. The material of the chip substrate 41 is not particularly limited as described above. Then, the silicon substrate 741 is removed and the N-type silicon epitaxial layer 45 is considerably thinned by etching or the like (FIG. 42).

After that, the electromagnetic shield metal layer 55 and the protective film 56 are formed, and openings 708, 709, and 707 for exposing the wiring layers 57, 58, and 705, respectively, are formed in these and the N-type silicon epitaxial layer 45. Yes (Fig. 43)

As described above, the step of preparing the chip substrate 41 on which the portion excluding the crystal oscillator 31 in the integrated circuit shown in FIG. 2 is prepared is completed.

On the other hand, the crystal unit 31 is attached to each chip 70.
Prepare a plurality corresponding to 1.

Next, as shown in FIG. 44, bumps 61 and 62 are formed on the wiring layers 57 and 58 of the chip substrate 41 in the state shown in FIG. 43, respectively, and then the connection pads 76 of the crystal oscillator 31 are formed. , 77 for bump 6 respectively
Joined to 1, 62.

Thereafter, the wafer in which the crystal unit 31 is integrated is diced or the like into individual chips 70.
Separate into 1. As a result, the chip 701 is completed.

Finally, the chip 1 is housed in the package 2 in a vacuum state. As a result, the integrated circuit device according to this embodiment is completed. The bonding wire 16 in FIG. 1 is connected to the external connection wiring layer 705.

The integrated circuit device according to the present embodiment also has the same advantages as the integrated circuit device according to the first embodiment.

Although the respective embodiments of the present invention and their modifications have been described above, the present invention is not limited to these embodiments and modifications.

For example, the crystal oscillator of the chip in each of the embodiments and modifications can be appropriately combined with the portion other than the crystal oscillator of the chip in any of the other embodiments and modifications.

[0197]

As described above, according to the present invention,
Compared with the prior art, when constructing a computer or the like, it is possible to greatly reduce the size and the like, reduce the electromagnetic waves that are generated, and further reduce power consumption. It is possible to provide a piezoelectric vibrator that can be used for this integrated circuit device and the like, and a method for manufacturing the same.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view schematically showing an integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an example of an integrated circuit that is integrally integrated with the chip in FIG. 1 to form a single chip.

FIG. 3 is a schematic cross-sectional view schematically showing a part of the chip in FIG.

FIG. 4 is a view taken along the line AA ′ in FIG. 3 in which only the crystal unit is viewed.

5 is a BB ′ arrow view in FIG. 3 in which only the crystal unit is viewed.

FIG. 6 is a schematic cross sectional view schematically showing a step of the method for manufacturing the integrated circuit device according to the first embodiment of the present invention.

FIG. 7 is a schematic cross sectional view schematically showing another step of the method for manufacturing the integrated circuit device according to the first embodiment of the present invention.

FIG. 8 is a schematic plan view showing another vibrator as viewed from one side.

9 is a schematic plan view showing the vibrator shown in FIG. 8 viewed from the other side.

FIG. 10 is a schematic plan view showing still another vibrator as viewed from one side.

11 is a schematic plan view of the vibrator shown in FIG. 10, viewed from the other side.

FIG. 12 is a schematic cross-sectional view schematically showing a part of a chip used in the integrated circuit device according to the second embodiment of the present invention.

FIG. 13 is a schematic cross sectional view schematically showing a step of the method for manufacturing the integrated circuit device according to the second embodiment of the present invention.

FIG. 14 is a schematic cross sectional view schematically showing another step of the method for manufacturing the integrated circuit device according to the second embodiment of the present invention.

FIG. 15 is a view taken along the arrow C-C ′ in FIG. 20.

FIG. 16 is a schematic cross sectional view schematically showing a step of a method for manufacturing a joined body which constitutes a chip used in the integrated circuit device according to the second embodiment of the present invention.

FIG. 17 is a schematic cross-sectional view schematically showing a step following that of FIG.

FIG. 18 is a schematic cross-sectional view schematically showing a step following the step of FIG.

FIG. 19 is a schematic cross sectional view schematically showing a step following FIG.

20 is a schematic cross-sectional view schematically showing a step following FIG.

FIG. 21 is a schematic cross-sectional view schematically showing a part of a chip used in the integrated circuit device according to the third embodiment of the present invention.

22 is a DD ′ arrow view in FIG. 21 in which only the crystal unit is viewed.

23 is a view taken along the line EE ′ in FIG. 21, looking only at the crystal unit.

FIG. 24 is a schematic cross sectional view schematically showing a step of the method for manufacturing the integrated circuit device according to the third embodiment of the invention.

FIG. 25 is a schematic cross sectional view schematically showing another step of the method for manufacturing the integrated circuit device according to the third embodiment of the invention.

FIG. 26 is a schematic cross-sectional view schematically showing a part of a chip used in the integrated circuit device according to the fourth embodiment of the present invention.

FIG. 27 is a schematic cross sectional view schematically showing a step of the method for manufacturing the integrated circuit device according to the fourth embodiment of the invention.

FIG. 28 is a schematic cross sectional view schematically showing another step of the method for manufacturing the integrated circuit device according to the fourth embodiment of the invention.

FIG. 29 is a schematic cross-sectional view schematically showing a part of a chip used in the integrated circuit device according to the fifth embodiment of the present invention.

FIG. 30 is a view as seen from the arrow FF ′ in FIG. 29, in which only the crystal unit is viewed.

31 is a GG ′ arrow view in FIG. 29 in which only the crystal unit is viewed.

FIG. 32 is a schematic cross sectional view schematically showing a step of the method for manufacturing the integrated circuit device according to the fifth embodiment of the present invention.

FIG. 33 is a schematic cross-sectional view schematically showing a part of the chip used in the integrated circuit device according to the sixth embodiment of the present invention.

FIG. 34 is a schematic cross sectional view schematically showing a step of the method for manufacturing the integrated circuit device according to the sixth embodiment of the invention.

FIG. 35 is a schematic cross sectional view schematically showing a part of the chip used in the integrated circuit device according to the seventh embodiment of the invention.

FIG. 36 is a schematic cross sectional view schematically showing a step of the method for manufacturing the integrated circuit device according to the seventh embodiment of the invention.

FIG. 37 is a schematic sectional view schematically showing a step following the step shown in FIG. 36.

38 is a schematic cross-sectional view schematically showing a step following FIG. 37. FIG.

FIG. 39 is a schematic cross sectional view schematically showing a step following FIG. 38.

FIG. 40 is a schematic cross-sectional view schematically showing a part of the chip used in the integrated circuit device according to the eighth embodiment of the present invention.

FIG. 41 is a schematic cross sectional view schematically showing a step of the method for manufacturing the integrated circuit device according to the eighth embodiment of the invention.

42 is a schematic cross-sectional view schematically showing a step following FIG. 41. FIG.

43 is a schematic sectional view schematically showing a step following FIG. 42. FIG.

44 is a schematic cross-sectional view schematically showing a step following FIG. 43. FIG.

[Explanation of symbols]

1, 101, 201, 301, 401, 501, 60
1,701 Chip 2 package 31, 131, 231, 331, 431, 531, 63
1 crystal oscillator 32 clock generation circuit 33 CPU 41 chip substrate 61, 62 bump 71 piezoelectric element plate 71a vibration region 74, 75 excitation electrode 76, 77 connection pad 80 through hole 302 recessed portion 303 lid

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) H03B 5/32 H01L 41/08 D H03H 3/02 C 9/02 41/22 Z 9/19 41/18 101A (72) Inventor Ken Yagi 3 2-3 Marunouchi, Chiyoda-ku, Tokyo F-Term (Reference) Nikon Headquarters Co., Ltd. 5J079 AA04 BA43 HA07 HA09 HA29 5J108 BB02 CC02 CC04 DD01 EE03 EE07 EE13 EE18 JJ04 KK04 MM01

Claims (28)

[Claims] 1. An integrated circuit comprising a piezoelectric vibrator, a clock generation circuit connected to the piezoelectric vibrator for generating a clock signal, and a CPU operating based on the clock signal, the integrated circuit being mounted on a chip substrate. A circuit device, wherein the integrated circuit including the piezoelectric vibrator is integrally integrated into a single chip. 2. The piezoelectric vibrator has two connection pads, and at least one of the two connection pads is connected to a predetermined wiring layer formed on the chip substrate via bumps. The integrated circuit device according to claim 1, wherein the integrated circuit device is electrically and mechanically connected. 3. The piezoelectric vibrator includes a piezoelectric element plate, a first excitation electrode formed on a surface of the piezoelectric element plate on the chip substrate side, and a side of the piezoelectric element plate opposite to the chip substrate. Second
A second excitation electrode formed on the surface of the piezoelectric element plate, a first connection pad formed on the surface of the piezoelectric element plate on the chip substrate side and electrically connected to the first excitation electrode, and the piezoelectric element. A second connection pad formed on a surface of the plate on the chip substrate side and electrically connected to the second excitation electrode, wherein the first and second connection pads are provided on the chip substrate. 2. The integrated circuit device according to claim 1, wherein each of the formed predetermined wiring layers is electrically and mechanically connected via a bump. 4. The piezoelectric element plate has a through hole, and the second connection pad is electrically connected to the second excitation electrode via a conductive substance existing in the through hole. The integrated circuit device according to claim 3, wherein: 5. The integrated circuit device according to claim 4, wherein the through hole is formed at a position substantially deviating from a predetermined vibration region of the piezoelectric element plate. 6. The integrated circuit device according to claim 1, wherein a predetermined element is formed in a region of the chip substrate facing the piezoelectric vibrator. 7. The integrated circuit device according to claim 1, further comprising a storage chamber in which the piezoelectric vibrator is stored and closed. 8. The storage chamber is formed by a concave portion formed in at least one of the chip substrate and a laminated portion on the chip substrate, and a lid body closing an opening side of the concave portion. The integrated circuit device according to claim 7. 9. The integrated circuit device according to claim 8, wherein the lid is a conductive plate for electromagnetic shielding, or a conductive film for electromagnetic shielding is formed on the lid. 10. The integrated circuit device according to claim 7, wherein the space in the storage chamber is evacuated. 11. A reinforcing plate, which is arranged on a side of the piezoelectric element opposite to the chip substrate with respect to the piezoelectric element plate and supports a portion substantially deviated from a predetermined vibration region of the piezoelectric element plate. , 1 to 10 are provided.
5. The integrated circuit device according to any one of 1. 12. The integrated circuit device according to claim 11, wherein the reinforcing plate is a conductive plate for electromagnetic shielding, or a conductive layer for electromagnetic shielding is formed on the reinforcing plate. 13. An adhesive for bonding between the chip substrate side and the piezoelectric element plate side of the piezoelectric vibrator hermetically seals a space where a predetermined vibration region of the piezoelectric element plate is located. The integrated circuit device according to claim 1, wherein the integrated circuit device is provided. 14. The integrated circuit device according to claim 1, wherein a conductive layer for electromagnetic shielding is formed on an element formation region on the chip substrate. 15. The integrated circuit integrated into one chip,
15. The integrated circuit device according to claim 1, wherein the integrated circuit device is housed in a hermetically sealed package. 16. The integrated circuit device according to claim 15, wherein the space in the package is substantially evacuated. 17. A manufacturing method for manufacturing an integrated circuit device according to claim 1, wherein a step of preparing a chip substrate on which a portion of the integrated circuit excluding the piezoelectric vibrator is prepared; And a step of electrically and mechanically integrating the piezoelectric vibrator with the chip substrate. 18. The step of integrating includes the step of electrically and mechanically connecting a predetermined wiring layer formed on the chip substrate and a connection pad of the piezoelectric vibrator via a bump. The method of manufacturing an integrated circuit device according to claim 17, wherein the integrated circuit device is manufactured. 19. The chip substrate, on which a portion of the integrated circuit excluding the piezoelectric vibrator is formed, has a concave portion at a predetermined location, and the step of integrating the piezoelectric vibrator in the concave portion. 18. The method according to claim 17, further comprising a step of closing the opening side of the concave portion with a lid after the step of arranging and integrating.
8. A method of manufacturing an integrated circuit device according to item 8. 20. The step of preparing the piezoelectric vibrator comprises a first step of forming a first conductive film in an island shape on a first surface of a piezoelectric element plate, and a step of performing the step after the first step. A second sacrificial layer is formed on a predetermined area or the entire area of the first surface of the piezoelectric element plate.
And the second step, the third step of joining the piezoelectric element plate and the reinforcing plate so that the sacrificial layer is on the reinforcing plate side, and the third step after the third step. A fourth step of thinning the piezoelectric element plate by removing a second surface side opposite to the first surface of the piezoelectric element plate, and the first conductive film after the fourth step. A fifth step of forming a through hole in the piezoelectric element plate so that a part thereof faces the second surface side, and a second step in the through hole and on the second surface of the piezoelectric element plate.
20. The method according to claim 17, further comprising a sixth step of forming the conductive film in the form of islands and a seventh step of removing the sacrificial layer after the sixth step. A method for manufacturing the integrated circuit device described. 21. The third step is a step of joining the piezoelectric element plate and the reinforcing plate with an adhesive disposed in at least a part of a region of the piezoelectric element plate where the sacrificial layer is not formed. 21. The method of manufacturing an integrated circuit device according to claim 20, further comprising: 22. In the step of preparing the piezoelectric vibrator, after the sixth step and before the seventh step, a part of the sacrificial layer faces the second surface side. 22. The method of manufacturing an integrated circuit device according to claim 20, further comprising the step of forming an opening in the piezoelectric element plate. 23. The method of manufacturing an integrated circuit device according to claim 20, wherein the fourth step includes a step of etching the piezoelectric element plate. 24. A piezoelectric element plate, a first excitation electrode formed on a first surface of the piezoelectric element plate, and a second surface of the piezoelectric element plate opposite to the first surface. The formed second excitation electrode, the first connection pad formed on the first surface of the piezoelectric element plate and electrically connected to the first excitation electrode, and the first element of the piezoelectric element plate. A second connection pad formed on the first surface and electrically connected to the second excitation electrode, the piezoelectric element plate has a through hole, and the second connection pad is the through hole. A piezoelectric vibrator, characterized in that the piezoelectric vibrator is electrically connected to the second excitation electrode via a conductive substance existing in the hole. 25. A first step of forming a first conductive film in an island shape on a first surface of a piezoelectric element plate, and a predetermined step of the first surface of the piezoelectric element plate after the first step. A second step of forming a sacrificial layer in a region or the entire region, and a third step of joining the piezoelectric element plate and the reinforcing plate so that the sacrificial layer is on the reinforcing plate side after the second step. And a fourth step of thinning the piezoelectric element plate by removing a second surface side of the piezoelectric element plate opposite to the first surface after the third step, After the fourth step, a fifth step of forming a through hole in the piezoelectric element plate so that a part of the first conductive film faces the second surface side, and the inside of the through hole and the piezoelectric element. A sixth step of forming a second conductive film in an island shape on the second surface of the base plate, and a seventh step of removing the sacrificial layer after the sixth step. A method for manufacturing a piezoelectric vibrator, comprising: 26. In the third step, the piezoelectric element plate and the reinforcing plate are bonded to each other with an adhesive which is arranged in at least a part of a region of the piezoelectric element plate where the sacrificial layer is not formed. The method of manufacturing a piezoelectric vibrator according to claim 25, further comprising steps. 27. In the step of preparing the piezoelectric vibrator, after the sixth step and before the seventh step, a part of the sacrificial layer faces the second surface side. 27. The method of manufacturing a piezoelectric vibrator according to claim 25, further comprising the step of forming an opening in the piezoelectric element plate. 28. The method of manufacturing a piezoelectric vibrator according to claim 25, wherein the fourth step includes a step of etching the piezoelectric element plate.