JP2003308355A - System and method for simulation, and computer software - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten an analysis time, and to allow processing without bringing increase of a voltage data accompanied to increase in a scale of a circuit serving as an analytical object. <P>SOLUTION: This simulation system provided with a circuit diagram 11, an input signal data 12, a DC analysis part 13, a transient analysis part 14, a threshold voltage data 15, a voltage value verification part 16 and a verified result outputting part 17 has a means for extracting an element name of a transistor element of which the forward bias voltage comes to a threshold bias voltage value or more, and for extracting the forward bias voltage value, a means for determining whether the forward bias voltage value reaches to an extreme value or not, and a means for outputting the forward bias voltage value and a simulation time when the forward bias voltage value reaches to the extreme value, and for outputting attribute information of the extracted transistor element, as a simulation result. The those means are carried out during execution of transient analysis. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulation system, a simulation method, and computer software, which is a circuit simulation for detecting an overcurrent location by a PN junction forward current in a semiconductor memory device used for designing a semiconductor memory device. Regarding

[0002]

2. Description of the Related Art A circuit simulation system for detecting an overcurrent portion by a PN junction forward current of a semiconductor memory device
Under the operating conditions required for the designed semiconductor memory device, the PN junction of the transistor element in the device becomes a forward bias state, and an unexpected current flows for the circuit operation is detected in advance before the production, and the malfunction is detected. It is a system whose purpose is to prevent it. The conventional circuit simulation system compares the layout database created by the layout design with the circuit database designed by the circuit design, and after both match, the DC operation of the circuit is performed by the DC analysis of the circuit simulation based on the circuit database. Ask for points. After obtaining the DC operating point of the circuit by circuit simulation, the voltage value between the terminals of the elements forming the circuit is obtained, and it is verified whether or not the voltage value exceeds a predetermined withstand voltage. FIG. 9 is a block diagram showing a conventional verification device, which is disclosed in JP-A-4-283942 and JP-A-7-7.
No. 4262 is disclosed. The layout pattern data 81 of FIG. 9 is layout pattern data of the circuit of the semiconductor device, and the circuit diagram data 82 is circuit diagram data including element names, element characteristics, connection information between elements, and the like that configure this circuit. The circuit connection verification unit 83 compares the circuit connection between the layout pattern data 81 and the circuit diagram data 82, and the layout pattern data 81 and the circuit diagram data 8
2 is compared with the circuit connection, and it is verified that the connection specifications between the elements in the layout pattern data 81 and the circuit diagram data 82 are satisfied, and then the layout pattern data 81 and the circuit diagram data 82 are subject to verification. The figure of the element is extracted. On the other hand, the circuit analysis of the semiconductor memory device based on the circuit diagram data 82 is performed by the DC analysis unit 85 using the circuit simulation, and the voltage value of each wiring is obtained and stored in the voltage data 86 of each wiring. The inter-layer withstand voltage verification means 90 of FIG. 9 compares the allowable value holding the withstand voltage value prepared in advance in the inter-layer withstand voltage definition file 87 with the voltage data 86 of each wiring, and the comparison result is the verification result data 91. Output as. On the other hand, in the circuit simulation system for detecting an overcurrent portion by the PN junction forward current of the semiconductor memory device, not only the potential difference between the terminals of the elements constituting the circuit calculated from the DC operating point of the circuit but also the semiconductor memory device is considered. Data relating to the potential difference between the terminals of the elements constituting the circuit under all the operating conditions required is required. To this end, the potential difference between the terminals of the elements forming the circuit is calculated from the simulation result of time-series calculation of the potential of each terminal of the circuit of the semiconductor memory device with respect to the input signal in which the operating conditions considered in the semiconductor memory device are arranged in time series. Need to ask.
In circuit simulation, this analysis is called transient analysis.
The potential of all terminals of the circuit of the semiconductor memory device is obtained by transient analysis and output. The potential difference between the source terminal or the drain terminal and the back gate terminal of the transistor, which is considered to form the PN junction of the elements forming the circuit, is calculated from the output terminal potential at each time. Among the obtained potential differences, the time when the PN junction is in the forward bias state and the potential difference at that time are selected, and the time when the potential difference is larger than the preset potential difference and the potential difference at that time are output. The above procedure is shown in FIG. Steps S201 to S210 of FIG. 10 show a processing procedure for performing the transient analysis in the circuit simulation. In the transient analysis, the numerical integration method is used to find the solution at each time.

A conventional process flow using this method will be described with reference to FIG. In step S201, the solution at the time when the analysis has already been completed is temporarily held. Using this value, a solution at a newly obtained time is calculated in step S203. Using the solution at the new time obtained and the solution at the time when the analysis has already been completed, iterative calculation is performed by the numerical integration method in step S205, and the solution at the new time is updated. In this process, as shown in step S206, for an element having a non-linear characteristic such as a transistor,
The solution is obtained by performing linearization by Newton's method and solving the linear simultaneous equations. If the obtained solution is within the allowable error range that was previously determined by circuit simulation,
The solution at the new time is considered to have converged and the calculation ends. Only the solutions that are specified to be output in advance in the circuit simulation are calculated in step S209.
Is output as a file at. These operations are performed for the time designated in advance by the circuit simulation, and the circuit simulation ends. The result output in step S209 is held in the simulation result data 92 in the conventional flow. In particular, in order to detect an overcurrent location due to the PN junction forward current generated in the circuit of the semiconductor memory device, the transient analysis result at all times of all wirings of the circuit to be simulated is output to the simulation result data 92. There is a need. With the simulation result data 92 as an input, step S3 in FIG.
The post-processing program shown from 01 to S305 detects an overcurrent location due to the PN junction forward current generated in the circuit of the semiconductor memory device. Upon detection, the transient analysis result of the wiring connected to the terminal of the transistor element is extracted from the simulation result of each wiring of the circuit held in the simulation result data 92 of FIG. 10 in step S301. From the result, the potential difference between the source terminal and the drain terminal of the transistor element and the back gate terminal is calculated in step S302. If this calculated value is compared with the preset threshold voltage value in step S303 and the forward bias condition is satisfied, it is output in step S305, and if it is not satisfied, it is connected to the terminal of the next transistor element. The process returns to step S301 for extracting the result of transient analysis of existing wiring. The above steps are performed for a transient analysis time designated in advance by circuit simulation, and output as forward bias point data 93. In the above process,
The analysis result of the transient analysis that should be output to the simulation result data 92 requires all the circuits to be analyzed, and the data amount increases as the circuit scale increases. In order to perform verification under all possible operating conditions in the semiconductor memory device, it is necessary to perform steps S201 to S210 and steps S301 to S305 for a transient analysis time designated in advance by circuit simulation.

[0004]

However, in the case of the prior art disclosed in Japanese Patent Application Laid-Open No. 4-283942, Japanese Patent Application Laid-Open No. 7-74262, etc., in the circuit simulation used for detection of an overcurrent location, etc. The analysis is limited to DC analysis, and the verification result data that is output is also a voltage value that may cause a malfunction in DC operation.
The conventional technique is effective in detecting the withstand voltage and electromigration of the transistor elements constituting the semiconductor memory device, but the PN junction of the transistor elements in the device is normally operated under various operating conditions assumed in the semiconductor memory device. It does not have a function to detect the occurrence of a phenomenon such as latch-up, which is biased in the direction and causes an unexpected current to flow in circuit operation.

Even in the conventional circuit simulation,
It is possible to detect the overcurrent location by the PN junction forward current by using the transient analysis. However, as the circuit scale in the semiconductor memory device increases, the time required for the transient analysis of the circuit simulation and the subsequent voltage value. The time required for analysis by the verification means increases. In addition, the size of the voltage data file of each wiring, which is the result of the circuit simulation used for detection by the voltage value verification means, increases due to the increase in the circuit scale of the semiconductor memory device to be verified and the diversification of the circuit operating conditions to be verified. To do. In the conventional method based on transient analysis of circuit simulation, the size of the transient analysis result data file created by circuit simulation increases, and as a result, the maximum size of data permitted by the computer performing verification work is exceeded. Verification cannot be performed unless an extraction function is added.

The present invention solves the problems of the prior art, in which the forward bias state that may occur for all the transistor elements in the semiconductor memory device is detected in the transient analysis of the circuit simulation in each transistor element. It is possible to detect the case of exceeding the preset threshold value by comparing the voltage between the terminals of, and by incorporating the procedure required for analysis in the conventional technology into the transient analysis of circuit simulation. It is an object of the present invention to provide a simulation system, a simulation method, and computer software capable of shortening the analysis time and capable of processing without increasing the voltage data accompanying the increase in the circuit scale to be analyzed.

[0007]

SUMMARY OF THE INVENTION According to the present invention, when a semiconductor circuit that internally processes multiple power supplies is used to perform temporal transient analysis of an input signal using a circuit simulation method, a numerical integration calculation of transient analysis is performed. In the past, there is a means for comparing the voltage value between the source terminal, the drain terminal and the back gate terminal of the transistor element at the past time with the threshold voltage set before the execution of the circuit simulation. As a result of the above comparison, when the corresponding transistor element is in the forward bias state, the element name and element polarity information (N-channel type or P-channel type transistor) are stored. The voltage between the source terminal, drain terminal, and back gate terminal newly calculated for the transistor element judged to be in the forward bias state after the transient analysis progresses and the transient analysis result at the new time is calculated. Value and
The difference between the voltage values of the source terminal, drain terminal, and back gate terminal of the transistor element at the past time, which was held for the transient analysis calculation, is taken, and the values are almost the same, that is, the forward bias voltage value is When the extreme value is reached, it has means for holding the voltage value that is the extreme value and the time of occurrence thereof.

By outputting these pieces of information to a file while the transient analysis is in progress, only the name of the transistor element in the forward bias state, the forward bias voltage value, and the time when the forward bias state occurs can be performed within the transient analysis time. it can. As a result, in the conventional method and the conventional simulation system, all the simulation information of the semiconductor circuit is once output, and after the transient analysis is completed, the voltage value between the transistor terminals is calculated by the post-processing step and set in advance. Compared with the method of determining the forward bias state after comparing with the threshold voltage, the circuit simulation program and the simulation system using the method of the present invention require the minimum work time and data size.

The present invention includes circuit diagram data, input signal data, a DC analysis unit, a transient analysis unit, threshold voltage data, a voltage value verification unit and a verification result output unit, and is applied to an input to a semiconductor circuit having multiple power supplies. A simulation system for performing transient analysis of semiconductor circuit operation, wherein a voltage applied to a PN junction in a transistor element forming the semiconductor circuit at a simulation time is a forward bias,
Further, means for extracting the attribute information of the transistor element and the forward bias voltage value of which the forward bias voltage value is equal to or higher than the threshold voltage value, and means for determining whether the extracted forward bias voltage value has reached the extreme value, A forward bias voltage value determined to have reached an extreme value, a simulation time thereof, and a means for outputting the extracted attribute information of the transistor element as a simulation result, and each of the means forms a semiconductor circuit. 3 is a simulation system that is a means that is performed during execution of a transient analysis including a calculation process of a forward bias voltage value applied to a PN junction in the inside.

Further, according to the present invention, the means for determining whether the forward bias voltage value has reached the extremal value determines the forward bias voltage value at the simulation time and the extracted forward bias voltage value each time the simulation time advances. It is a means for determining whether the extreme value has been reached by comparing and comparing the voltage difference between the two forward bias voltages and the transistor element that has generated substantially the same voltage difference with the extracted transistor element. It is a simulation system.

The present invention is the simulation system in which the attribute information of the transistor element output as the simulation result includes the unique name of the transistor element and the polarity information of the transistor element.

Furthermore, the present invention is a simulation system in which the semiconductor circuit having multiple power supplies is a semiconductor memory device.

Further, according to the present invention, in a simulation method for performing transient analysis of the operation of a semiconductor circuit having inputs to a semiconductor circuit having multiple power sources, a PN junction in a transistor element forming the semiconductor circuit at a simulation time is applied. Voltage is a forward bias, and the step of extracting the attribute information of the transistor element and the forward bias voltage value of which the forward bias voltage is equal to or higher than a predetermined voltage value, and the order at the simulation time every time the simulation time advances. A step of comparing the bias voltage value with the extracted forward bias voltage value; and a transistor element extracted by a transistor element that has a voltage difference between the compared forward bias voltages that is approximately the same and that has generated a substantially identical voltage difference. The step of judging whether they match and the forward bias voltage when it judges that they match. A value, a simulation time, and a step of outputting the extracted attribute information of the transistor element as a simulation result, and each of the steps includes a forward bias voltage value applied to a PN junction in the transistor element forming the semiconductor circuit. The simulation method is a step that is performed during the execution of the transient analysis including the calculation process.

The present invention is a computer program used in a simulation system for performing transient analysis of the operation of the semiconductor circuit with respect to inputs to the semiconductor circuit having multiple power supplies, which constitutes the semiconductor circuit at a simulation time. The voltage applied to the PN junction in the transistor element is a forward bias, and the attribute information of the transistor element in which the forward bias voltage is a predetermined voltage value or more and the function of extracting the forward bias voltage value, and the simulation time The function of comparing the forward bias voltage value at the simulation time with the extracted forward bias voltage value each time the process is advanced, and the voltage difference between the two forward bias voltages is almost the same, and the almost same voltage difference is generated. If it matches with the function that determines whether the transistor element matches the extracted transistor element The forward bias voltage value at the time of setting, the simulation time, and the function of outputting the extracted attribute information of the transistor element as a simulation result, provided that each of the functions is applied to the PN junction in the transistor element forming the semiconductor circuit. It is computer-readable computer software including a program that causes a computer to realize these functions performed while executing a transient analysis including a calculation process of a forward bias voltage value.

As described above, according to the present invention, it is necessary to separately perform an analysis required for detection in calculating the temporal transient response of the circuit, or to perform the detection after all the circuit simulation results are known. It is possible to identify the location where the problem due to the forward bias state has occurred without the need for such work.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. 1 to 8 for an embodiment embodying the simulation system and the simulation method of the present invention.
Will be explained. FIG. 1 is a block diagram illustrating a simulation system according to an embodiment. FIG. 2 is an explanatory diagram of a processing flow in transient analysis by the simulation system of the embodiment. FIG. 3 is an explanatory diagram of a forward bias state by the simulation system of the embodiment.
FIG. 4 is a diagram illustrating a method of detecting a forward bias state of a transistor by the simulation system of the embodiment. FIG. 5 is an explanatory diagram of an example of a circuit that detects a forward bias portion by the simulation system of the embodiment. FIG. 6 is an explanatory diagram of the transient analysis result of the circuit by the simulation system of the embodiment. FIG. 7 is an explanatory diagram of a voltage between terminals of a transistor and a detection example by the simulation system of the embodiment. FIG. 8 is an explanatory diagram of an example of the detection result of the forward biased portion by the simulation system of the embodiment.

An example will be described. The simulation system of the present embodiment is composed of, for example, a computer and is shown in FIG.
As shown in, the circuit diagram data 11 and the input / output signal data 1
2. It has a DC analysis unit 13, a transient analysis unit 14, a threshold voltage data 15, a voltage value verification unit 16 and a verification result output unit 17, and creates detection result data 18. Then, the circuit simulation system of the present embodiment is a transistor in which the voltage applied to the PN junction in the transistor element forming the semiconductor circuit at the simulation time is forward bias and the forward bias voltage is equal to or higher than the threshold voltage value. A means for extracting the attribute information of the element and its forward bias voltage value, a means for determining whether the extracted forward bias voltage value has reached an extreme value, a forward bias voltage value determined to have reached an extreme value, and its simulation And means for outputting the time and the extracted attribute information of the transistor element as a simulation result, and each means calculates the forward bias voltage value applied to the PN junction in the transistor element forming the semiconductor circuit. It is a means to be performed during the execution of the transient analysis including.

The means for determining whether the forward bias voltage value has reached the extreme value compares the forward bias voltage value at the simulation time with the extracted forward bias voltage value each time the simulation time advances, and the forward bias voltage value and the forward bias voltage value are extracted. The bias voltage difference is substantially the same, and it is a means for determining whether the extreme value has been reached or not depending on whether the transistor element that has generated the substantially same voltage difference matches the extracted transistor element.

In the simulation system of this embodiment, a DC operating point analysis is performed by the DC analysis unit 13 using the circuit diagram data 11 including the element name, element characteristics, connection information between elements, etc., which form the circuit of the semiconductor memory device. Then, the transient analysis unit 14 calculates the temporal transient response of the circuit using the result as the initial voltage value. The transient analysis unit 14 calculates and holds the voltage value of the circuit diagram data 11 with respect to the input signal data 12 at each analysis time. Among the calculated voltage values, the voltage value between the source and the back gate of the transistor element forming the circuit diagram data 11 as the voltage value at each analysis time, and the voltage value of the drain and the back gate are the source and drain of the transistor element, It can be calculated from the voltage value at the terminal of the back gate. Calculated value is NMOS
In the case of a transistor element, when a negative voltage value is applied to the source or drain with respect to the back gate, it is considered that a forward bias state has occurred in the diode between the back gate and the source or drain. Further, in the case of a PMOS transistor, when a positive voltage value is applied to the source or drain with respect to the back gate, it is considered that a forward bias state has occurred in the diode between the back gate and the source or drain. The transient analysis unit 14 enters a state in which the forward bias condition is satisfied, and compared with the given threshold voltage data 15, the back gate and the source or drain calculated based on the analysis result of the transient analysis unit 14 are connected. If the absolute value of the forward bias voltage value of is larger than the absolute value of the threshold voltage data, the element name, the forward bias voltage value, and the generation time, which are given to distinguish the transistor elements, are output as the detection result data 18.

Since the above-described processing steps in this embodiment are all performed during the transient analysis, the processing is executed in a shorter time than in the case where the result of circuit simulation is once again analyzed and detected as in the prior art. To be done. Further, even if the scale of the circuit to be analyzed increases, the detection result data output from the circuit simulation system of the present invention does not include the transient analysis results of all the circuits, and the verification result output unit 17 uses the conditions of the voltage value verification unit 16 for verification. Since only the data satisfying the above is output, the upper limit of the data size allowed by the computer performing the verification work will not be exceeded.

A detailed algorithm for the above process in this embodiment is shown below. When performing transient analysis by circuit simulation, in order to calculate the potential of each terminal of the circuit at a new time and the current flowing through the network, in addition to Kirchhoff's law about the network and the characteristics of the element, the capacitor component It is necessary to solve the ordinary differential equation with respect to time in consideration of the differential relation with respect to time related to the characteristics of the inductor component. In circuit simulation, when solving this ordinary differential equation, in order to find a solution at a new time, the solution up to that time is used to solve by a numerical integration formula. That is, in the transient analysis, the solution calculated by the time T is used to obtain the solution at the time T. Therefore, in the circuit simulation, the solution calculated by the time T is temporarily held in the circuit simulator. In this embodiment, attention is paid to the temporarily held solution until time T, and the solution is compared with a threshold value given in advance to determine whether the PN junction is in the forward bias state. Then, a flag is set to the element corresponding to the forward bias condition. Find the solution at the current time calculated by the numerical integration formula. For the solution at the new time, refer to the difference between the solution at the existing time and the solution at the new time used in the calculation during numerical integration only when the flag of the element that corresponds to the forward bias condition is set in advance. The time at which the voltage value becomes zero, that is, the point at which the voltage value reaches a maximum in the forward bias state, and the voltage value are output as the forward bias point data. An example of the above flow is shown in FIG. The part surrounded by the thick frame in FIG. 2 (step numbers S102, S103, S112, S11
3 and 20) is a part added for detecting the forward bias state according to the present embodiment. Except for the additional portion, it is basically the same as the transient analysis processing of the circuit simulation of FIG. This is a detailed description of the processing between the transient analysis unit 14 and the voltage value verification unit 16 in FIG. Specifically, in step S102 of FIG. 2, if the forward bias condition is satisfied by comparing the temporarily held solution at the time when the analysis has already ended with the threshold value set in advance before the simulation. Flags the corresponding element. When the analysis is completed at a certain time in the transient analysis, the presence or absence of this flag is used as a judgment material, and if the flag is added,
In step S113, the information of the element to which the flag is added is output as the forward bias location data 20. In this way, in this embodiment, the values used in the series of transient analysis calculations can be used to detect only the state in which the PN junctions of all circuits for which circuit simulation is performed exceed the threshold value and are in the forward bias state. it can. Moreover, in this process, it is not necessary to output the voltage information of the terminals of all the circuits as the simulation result data as in the conventional technique. Can be obtained. In addition, the thick frame of FIG. 10 (step numbers S301 to S3
05 and 93), there is no need to add a post-processing step to the simulation result data as in the prior art.
The processing of that part can be shortened.

FIG. 3 shows a verification example in which the transient analysis of the circuit simulation is carried out by using the simulation system of this embodiment using the above algorithm, and the forward bias state is detected. When there is a circuit for handling a negative voltage in the semiconductor memory device, a well region formed by double diffusion is formed on the substrate as shown in FIG. 3, and a transistor element is formed in the well. Generally, a positive potential is applied to the outer well region N-well. This potential is applied from the terminal A21 in FIG. 3 and creates a reverse bias state with the substrate. A negative potential is applied to the well region P-well inside thereof. This potential is applied from the terminal E25 in FIG. 3 and creates a reverse bias state with the outer well region N-well. The normal terminal E25 is applied with a negative potential more than the terminals B22, C23 and D24 of FIG. 3, which are the other terminals of the transistor element.

However, the potential of the terminal E25 shown in FIG. 3 is changed to the terminal B2 shown in FIG. 3 due to noise from an external circuit and operating conditions of the circuit.
2 and the terminal D24 may have a higher potential. In such a state, the transistor element is in the forward bias state, and the terminal D24 or the terminal B22 to the terminal E25 is connected.
A forward current flows toward and does not operate normally as a transistor element. In order to detect the above situation, a transient analysis is performed on the circuit of the semiconductor memory device by circuit simulation. The potential of each terminal of the transistor element calculated at each time of the transient analysis is compared. FIG. 4 is a graph showing an example of the time change of the potential difference between the terminals of the transistor element. This graph is a graph showing the time change of the potential difference between the terminals E25 and D24 of FIG. In the transient analysis of the circuit simulation, FIG.
When a potential difference exceeding the potential difference VTH35 of 1 occurs between the terminal E and the terminal D, the time change of the potential difference is examined and the voltage value and time at the time when the potential difference becomes maximum are recorded. In the case of the graph shown in FIG. 4, V which is the potential difference at P1 point 31
(P1) and T1, which is the time when the potential difference occurs, are recorded as a simulation result. Also, the detected P
The voltage V (P1) 31 at one point and the potential difference VNOISE3 of FIG.
The point P2 32 in FIG. 4, which is the maximum point of the forward bias voltage generated by the voltage within the value (V (P1) + VNOISE) and the value (V (P1) -VNOISE) calculated from 3, is recognized as a noise signal. , Simulation results do not remain. FIG. 5 shows an example of a circuit that detects a forward bias portion. In a semiconductor memory device, there is a circuit that handles a negative voltage as a signal as shown in FIG. 5, and this circuit example is a circuit example that switches to 0 V at a certain time with respect to point A to which a certain negative voltage is applied. The external circuit is replaced with constant voltage power supplies V1 to V3 to perform a circuit simulation, and the main circuit is composed of two transistors M1 and M2. In FIG. 5, "-5V → 0V", "0V → -5V", "-5V → -1V"
→ 0V "means that when the constant voltage power supplies V1 and V2 are -5V and the constant voltage power supply V3 is 0V at a certain time, the voltage at the point A of the main circuit is -5V. Show. After that, when the constant voltage power supplies V1 and V2 change to 0V and the constant voltage power supply V3 changes to -5V, the voltage at the point A of the main circuit gradually changes from -1V to 0V. The forward bias condition is detected for the transistors included in the circuit by using the method shown in FIGS. 3 and 4 and the algorithm shown in FIG.

FIG. 6 is an example of the result of calculating the potential of each terminal shown in FIG. 5 by performing transient analysis on the circuit of FIG.
The potential 41 at point A, the potential 42 at point B and point C, and the potential 43 at point D are shown.

FIG. 7 shows how the forward bias state is calculated using the potential difference between the back gate and the source and drain of the transistor and the threshold voltage given in advance in the system of this embodiment. In FIG. 7, transistors M1 and M2
Regarding the above, during the transient analysis, the potential difference between the back gate, the source, and the drain is given as shown in step S101 of FIG. At the point where this value exceeds the preset threshold value -2V, steps S102 and S10 in FIG.
Then, the flag is added to the transistors M1 and M2.

After that, the transient analysis proceeds, and when it is determined that the potential difference in the forward bias state is the maximum value in the difference calculation of the transient analysis, the time, the voltage value, and the forward bias are calculated by using step S113 in FIG. Record information about the device in a state in a file. In the case of the example in FIG. 7, a value of 2 V is set in advance in the present system, and when a potential difference exceeding that value occurs in the transistors M1 and M2, the maximum value is held, so that the time of 24 nanoseconds from FIG. Then -4.8V is recorded.

FIG. 8 shows detection result examples 51 to 55 of the forward bias portion output by this system. In the output result example of FIG. 8, the forward bias state is detected once in each of the transistors M1 and M2. The output result 51 shows the transistor element name in the forward bias state. The output result 52 shows whether the polarity of each transistor is N-type or P-type. The output result 53 shows whether the source terminal side of each transistor is in the forward bias state or the drain terminal side is in the forward bias state.
The output result 54 shows the time at the maximum of the forward bias state. The output result 55 shows the forward bias voltage at the maximum in the forward bias state.

With the simulation system of this embodiment, the forward bias state that may occur for all the transistor elements in the semiconductor memory device is compared with the terminal voltage of each transistor element in the transient analysis of the circuit simulation. It is possible to detect when the threshold value that has been set in advance is exceeded, and the analysis time can be shortened by incorporating the procedure required for analysis in the conventional technology into the transient analysis of circuit simulation. Moreover, the processing can be performed without increasing the voltage data due to the increase in the circuit scale to be analyzed.

Although the simulation system has been described in the above embodiment, the voltage applied to the PN junction in the transistor element forming the semiconductor circuit at the time of simulation is forward bias, and the forward bias voltage is predetermined. And a function of extracting the attribute information of the transistor element that is equal to or higher than the voltage value of the forward bias voltage value, and a function of comparing the forward bias voltage value at the simulation time with the extracted forward bias voltage value each time the simulation time advances. , The voltage difference between the two forward bias voltages is approximately the same,
In addition, the function of determining whether the transistor elements that generate approximately the same voltage difference match the extracted transistor elements, and the forward bias voltage value and the simulation time when it is determined that they match, and the attribute information of the extracted transistor elements are simulated. The function to output as a result,
However, a program that causes a computer to realize these functions performed while performing a transient analysis including a calculation process of a forward bias voltage value applied to a PN junction in a transistor element that configures a semiconductor circuit A recording medium storing a program (for example, a CD-RO
By using M), the computer can be used as the simulation system of the present invention.

[0030]

As described above, according to the present invention, the forward bias state that may occur for all the transistor elements in the semiconductor memory device is detected between the terminals of each transistor element in the transient analysis of the circuit simulation. It is possible to compare the voltages and detect when the voltage exceeds a preset threshold value.In addition, by incorporating the procedure required for analysis in the conventional technology into the transient analysis of circuit simulation, the analysis time can be reduced. It is possible to obtain a simulation system and a simulation method capable of reducing the number of times, and capable of processing without increasing the voltage data accompanying the increase in the circuit scale to be analyzed.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a simulation system according to an embodiment.

FIG. 2 is an explanatory diagram of a processing flow in transient analysis by the simulation system of the embodiment.

FIG. 3 is an explanatory diagram of a forward bias state by the simulation system of the embodiment.

FIG. 4 is a diagram illustrating a method of detecting a forward bias state of a transistor by a simulation system according to an embodiment.

FIG. 5 is an explanatory diagram of an example of a circuit that detects a forward bias point by the simulation system according to the embodiment.

FIG. 6 is an explanatory diagram of a transient analysis result of a circuit by the simulation system of the embodiment.

FIG. 7 is an explanatory diagram of a voltage between terminals of a transistor and a detection example by the simulation system of the embodiment.

FIG. 8 is an explanatory diagram of an example of a detection result of a forward bias portion by the simulation system of the embodiment.

FIG. 9 is a block diagram illustrating a conventional simulation system.

FIG. 10 is an explanatory diagram of a processing flow in transient analysis according to a conventional technique.

[Explanation of symbols]

11 circuit diagram data 12 input / output signal data 13 DC analysis unit 14 transient analysis unit 15 threshold voltage data 16 voltage value verification unit 17 verification result output unit 18 detection result data 19 simulation result data 20 forward bias point data 21 transistor handling negative voltage By applying the potential to the well region by the diffusion outside the terminal 22 By applying the potential to the source of the transistor 23 By applying the potential to the gate of the transistor 24 By applying the potential to the drain of the transistor 25 By the diffusion inside the transistor that handles negative voltage Terminals 26 and 29 for applying a potential to the well region Point 27 detected as the forward bias state 27 Point not detected as the noise 28 Voltage value range 35 that the forward bias state is not detected as the noise 35 Threshold value detected as the forward bias state

Claims (6)

[Claims] 1. A semiconductor circuit including circuit diagram data, input signal data, a DC analysis unit, a transient analysis unit, a threshold voltage data, a voltage value verification unit and a verification result output unit, and the semiconductor circuit with respect to an input to a semiconductor circuit having multiple power supplies. A simulation system for performing transient analysis of operation, wherein a voltage applied to a PN junction in a transistor element forming the semiconductor circuit at a simulation time is forward bias, and the forward bias voltage value is a threshold voltage value. The above-mentioned attribute information of the transistor element and means for extracting the forward bias voltage value thereof, means for determining whether the extracted forward bias voltage value has reached the extreme value, and forward bias voltage determined to have reached the extreme value And a means for outputting the value, its simulation time, and the extracted attribute information of the transistor element as a simulation result. , Simulation system, wherein each means is a means that is made during the execution of the transient analysis including calculation of the forward bias voltage applied to the PN junction in the transistor element constituting the semiconductor circuit, respectively. 2. The means for determining whether the forward bias voltage value has reached an extreme value compares the forward bias voltage value at the simulation time with the extracted forward bias voltage value each time the simulation time advances, and 3. A means for determining whether an extreme value has been reached by determining whether or not the voltage difference of the forward bias voltage is substantially the same and the transistor element that has generated the substantially the same voltage difference matches the extracted transistor element.
The described simulation system. 3. The attribute information of the transistor element output as the simulation result includes a proper name of the transistor element and polarity information of the transistor element.
Or the simulation system according to 2. 4. The simulation system according to claim 1, wherein the semiconductor circuit having the multiple power supplies is a semiconductor memory device. 5. In a simulation method for performing transient analysis of the operation of a semiconductor circuit with respect to inputs to a semiconductor circuit having multiple power supplies, a voltage applied to a PN junction in a transistor element forming a semiconductor circuit at a simulation time is a forward voltage. A step of extracting the attribute information of the transistor element that is a bias and the forward bias voltage is equal to or higher than a predetermined voltage value and the forward bias voltage value, and the forward bias voltage value at the simulation time each time the simulation time advances. The step of comparing the extracted forward bias voltage value and the compared forward bias voltage value have substantially the same voltage difference, and
A step of determining whether the transistor element that has generated the substantially same voltage difference matches the extracted transistor element;
A forward bias voltage value when it is determined that they coincide with each other, a simulation time, and a step of outputting the extracted attribute information of the transistor element as a simulation result, and each step includes a PN in the transistor element forming the semiconductor circuit. A simulation method, which is a step performed during a transient analysis including a calculation process of a forward bias voltage value applied to a junction. 6. A computer program used in a simulation system for performing transient analysis of the operation of the semiconductor circuit with respect to inputs to a semiconductor circuit having multiple power supplies, the method comprising: The voltage applied to the PN junction is forward-biased, and the attribute information of the transistor element in which the forward-biased voltage is equal to or higher than a predetermined voltage value and the function of extracting the forward-biased voltage value, and each time the simulation time advances The function of comparing the forward bias voltage value at the simulation time with the extracted forward bias voltage value, and the transistor element which has the substantially same voltage difference between the two forward bias voltages and has the substantially same voltage difference is extracted. Function to determine whether it matches with the transistor element that has been And a function of outputting the attribute information of the bias voltage and the simulation time and the extracted transistor element as a simulation result, however, PN in transistor elements each function constituting a semiconductor circuit, respectively
Computer-readable computer software consisting of a program that causes a computer to perform these functions performed while performing a transient analysis including a calculation process of a forward bias voltage value applied to a junction.