JP2003303948A - Solid-state image pickup element and manufacturing method thereof - Google Patents
Solid-state image pickup element and manufacturing method thereofInfo
- Publication number
- JP2003303948A JP2003303948A JP2002107807A JP2002107807A JP2003303948A JP 2003303948 A JP2003303948 A JP 2003303948A JP 2002107807 A JP2002107807 A JP 2002107807A JP 2002107807 A JP2002107807 A JP 2002107807A JP 2003303948 A JP2003303948 A JP 2003303948A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- solid
- photoelectric conversion
- imaging device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 38
- 239000010410 layer Substances 0.000 claims abstract description 122
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 74
- 229910052802 copper Inorganic materials 0.000 claims abstract description 74
- 239000010949 copper Substances 0.000 claims abstract description 74
- 238000006243 chemical reaction Methods 0.000 claims abstract description 70
- 238000009792 diffusion process Methods 0.000 claims abstract description 57
- 238000005530 etching Methods 0.000 claims abstract description 26
- 239000011229 interlayer Substances 0.000 claims abstract description 21
- 238000003384 imaging method Methods 0.000 claims description 44
- 230000002265 prevention Effects 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 8
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000035945 sensitivity Effects 0.000 abstract description 10
- 230000003287 optical effect Effects 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 230000009977 dual effect Effects 0.000 description 9
- 238000005498 polishing Methods 0.000 description 7
- 229910052681 coesite Inorganic materials 0.000 description 6
- 229910052906 cristobalite Inorganic materials 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 229910052682 stishovite Inorganic materials 0.000 description 6
- 229910052905 tridymite Inorganic materials 0.000 description 6
- 238000004380 ashing Methods 0.000 description 5
- 239000007772 electrode material Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000003449 preventive effect Effects 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 101150016011 RR11 gene Proteins 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体基板に光電
変換素子やその読み出し回路を設けたＣＭＯＳ型イメー
ジセンサ等の固体撮像素子に関し、特にその配線材料に
銅を用いた固体撮像素子及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device such as a CMOS type image sensor in which a photoelectric conversion element and a readout circuit thereof are provided on a semiconductor substrate, and more particularly to a solid-state image pickup device using copper for its wiring material and its manufacture. Regarding the method.
【０００２】[0002]
【従来の技術】近年、ＭＯＳプロセスの微細化技術の進
展に伴い、ＣＭＯＳ型イメージセンサが再び注目されて
いる。ＣＭＯＳ型イメージセンサの特徴としては、多数
の光電変換素子で構成される撮像画素領域と、その周辺
のロジック回路部及びメモリ回路部を同一プロセスで形
成可能であるため、比較的、同一チップへの高集積化が
可能であるが、いかに撮像素子としての画質性能を損な
わずに多機能の回路を混載していくかが課題となってい
る。2. Description of the Related Art In recent years, a CMOS type image sensor has been attracting attention again with the progress of miniaturization technology of MOS process. A feature of the CMOS image sensor is that the image pickup pixel region composed of a large number of photoelectric conversion elements and the peripheral logic circuit portion and memory circuit portion can be formed in the same process, so that the image pickup pixel region can be formed on a relatively same chip. Although high integration is possible, how to mount multi-functional circuits together without impairing the image quality performance as an image sensor is an issue.
【０００３】そして、微細化されたＭＯＳプロセスの１
つの鍵となる技術として、素子の配線材料に、従来のア
ルミニウム配線に代えて銅配線を用いることが提案され
ている。すなわち、銅は、アルミニウムよりも抵抗率が
小さいため、配線ピッチを小さくできる。しかし、その
一方で、銅のエッチング技術が確立されていない現在に
おいて、銅を配線材料として適用するためには、金属等
の導電体を埋め込み、その後、ＣＭＰ（化学機械研磨
法）による研磨で配線及び接続孔を同時に形成するデュ
アルダマシンプロセスを採用することが不可欠である。
以下、従来例として、撮像領域を含まない通常のＭＯＳ
プロセス（ロジック回路）の銅配線を用いた場合の多層
配線の形成プロセスにおける特にデュアルダマシンの形
成プロセスについて説明する。One of the miniaturized MOS processes
As one of the key technologies, it has been proposed to use copper wiring instead of conventional aluminum wiring as the wiring material of the device. That is, since copper has a lower resistivity than aluminum, the wiring pitch can be reduced. However, on the other hand, in the present where copper etching technology has not been established, in order to apply copper as a wiring material, a conductor such as a metal is embedded and then wiring is performed by polishing by CMP (chemical mechanical polishing). It is indispensable to adopt a dual damascene process for simultaneously forming a contact hole and a contact hole.
Hereinafter, as a conventional example, a normal MOS that does not include an imaging region
A dual damascene forming process in the multilayer wiring forming process using the copper wiring of the process (logic circuit) will be described.
【０００４】図１０〜図１３は、第１の従来例によるＭ
ＯＳプロセスの各工程を示す断面図である。まず、図１
０（Ａ）において、シリコン基板１００にＭＯＳトラン
ジスタを形成する。これは、まずシリコン基板１００上
に素子分離領域１０１を形成し、次いで、シリコン基板
１００中に所定のウエル領域（図示せず）を形成する。
次いで、このシリコン基板１００上にゲート絶縁膜、ゲ
ート電極を含むゲート電極部１０２を形成した後、イオ
ン注入と熱処理により例えばＬＤＤ（LightlyDoped Dra
in ）構造を有する高濃度拡散層領域１０３を形成す
る。そして、その上層に層間絶縁膜１０４を形成するこ
とにより、下地ＭＯＳトランジスタ領域を完成する。10 to 13 show an M according to the first conventional example.
It is sectional drawing which shows each process of OS process. First, Fig. 1
At 0 (A), a MOS transistor is formed on the silicon substrate 100. For this, first, an element isolation region 101 is formed on a silicon substrate 100, and then a predetermined well region (not shown) is formed in the silicon substrate 100.
Next, after forming a gate insulating film and a gate electrode portion 102 including a gate electrode on the silicon substrate 100, for example, LDD (Lightly Doped Dra) is performed by ion implantation and heat treatment.
A high concentration diffusion layer region 103 having an in) structure is formed. Then, an interlayer insulating film 104 is formed thereover to complete the base MOS transistor region.
【０００５】次に、図１０（Ｂ）において、ＭＯＳトラ
ンジスタ形成領域と接する部分の第１接続孔１０５Ａを
開口し、次いで、この開口された接続孔１０５Ａに窒化
チタンを含むバリアメタル層及びタングステン電極層を
埋め込み、第１接続部１０５を形成する。次いで、図１
０（Ｃ）に示すように、第１配線間絶縁膜１０６を形成
する。この配線間絶縁膜１０６には、ここでは、例え
ば、酸化シリコン膜、あるいは、低誘電率化のためのフ
ッ素添加酸化シリコン膜を用いるが、一般にｌｏｗ−ｋ
膜と呼ばれるような、さらなる低誘電率材料膜を用いて
も良い。次いで、図１０（Ｄ）に示すように、前述した
第１配線間絶縁膜１０６をパターンニングとエッチング
によって加工し、後の銅配線となる部分に第１配線溝１
０６Ａを開口する。Next, in FIG. 10B, a first contact hole 105A in a portion in contact with the MOS transistor formation region is opened, and then the barrier metal layer containing titanium nitride and a tungsten electrode are opened in the opened contact hole 105A. The layers are embedded to form the first connection portion 105. Then, FIG.
As shown in 0 (C), the first inter-wiring insulating film 106 is formed. As the inter-wiring insulating film 106, for example, a silicon oxide film or a fluorine-added silicon oxide film for lowering the dielectric constant is used here, but it is generally low-k.
Additional low dielectric constant material films, such as films, may be used. Next, as shown in FIG. 10D, the above-described first inter-wiring insulating film 106 is processed by patterning and etching, and the first wiring trench 1 is formed in a portion to be a copper wiring later.
Open 06A.
【０００６】次いで、図１１（Ｅ）に示すように、バリ
アメタル１０７及び銅１０８を前述した第１配線溝１０
６Ａに埋め込む。この後、図１１（Ｆ）に示すように、
ＣＭＰにより余剰な銅及びバリアメタルを研磨すること
で、バリアメタル１０７及び銅１０８による第１配線層
１０６Ｂを形成する。次いで、図１１（Ｇ）に示すよう
に、第１配線層１０６Ｂの上層に銅配線を保護するため
の拡散防止膜１０９を成膜することにより、第１配線層
１０６Ｂ及び第１接続部１０５が完成される。ここで、
拡散防止膜１０９は、例えば窒化シリコン膜、あるいは
炭化シリコン膜等を用いるが、これに限るものではな
い。また、この第１従来例においては、第１配線層１０
６Ｂの配線のみを銅の埋め込みと研磨によるシングルダ
マシンプロセスで形成したが、第１接続部１０５と第１
配線層１０６Ｂとを、銅の埋め込みと研磨によって同時
に形成するデュアルダマシンプロセスを用いても良い。Next, as shown in FIG. 11E, the barrier metal 107 and the copper 108 are formed on the first wiring groove 10 described above.
Embed in 6A. After this, as shown in FIG.
The excess copper and the barrier metal are polished by CMP to form the first wiring layer 106B made of the barrier metal 107 and the copper 108. Next, as shown in FIG. 11G, a diffusion prevention film 109 for protecting the copper wiring is formed on the upper layer of the first wiring layer 106B, whereby the first wiring layer 106B and the first connection portion 105 are formed. Will be completed. here,
The diffusion prevention film 109 uses, for example, a silicon nitride film, a silicon carbide film, or the like, but is not limited to this. In the first conventional example, the first wiring layer 10
Although only the 6B wiring was formed by the single damascene process by burying copper and polishing,
A dual damascene process in which the wiring layer 106B and the wiring layer 106B are simultaneously formed by burying copper and polishing may be used.
【０００７】次いで、図１１（Ｈ）に示すように、第１
配線層１０６Ｂの上層に層間絶縁膜１１０を成膜する。
なお、この層間絶縁膜１１０も、上述した第１配線間絶
縁膜１０６と同様に、例えば、酸化シリコン膜、あるい
は低誘電率化のためのフッ素添加酸化シリコン膜を用い
るが、一般にｌｏｗ−ｋ膜と呼ばれるような、さらなる
低誘電率材料膜を用いても良い。次いで、この層間絶縁
膜１１０に、図１２（Ｉ）に示すように、第２接続孔１
１１となる部分をパターンニングとエッチングにより開
口し、さらに図１２（Ｊ）に示すように、第２銅配線と
なる部分をパターンニングとエッチングにより開口す
る。次に、図１２（Ｋ）に示すように、バリアメタル１
１１Ａと銅１１１Ｂを埋め込みにより成膜し、図１３
（Ｌ）に示すように、余剰な銅及びバリアメタルを研磨
により除去する。次いで、図１３（Ｍ）に示すように、
銅配線を保護するための拡散防止膜１１２を成膜すこと
で、第２接続部１１３及び第２配線層１１４を完成す
る。この後、以上のようなデュアルダマシンプロセス
（図１１（Ｈ）〜図１３（Ｍ））を所望の回数だけ繰り
返すことにより、多層配線を有した半導体装置が形成さ
れる。Then, as shown in FIG. 11 (H), the first
An interlayer insulating film 110 is formed on the wiring layer 106B.
As the interlayer insulating film 110, for example, a silicon oxide film or a fluorine-added silicon oxide film for lowering the dielectric constant is used similarly to the above-described first inter-wiring insulating film 106, but a low-k film is generally used. Further low dielectric constant material films, such as Then, in the interlayer insulating film 110, as shown in FIG.
A portion to be 11 is opened by patterning and etching, and a portion to be the second copper wiring is opened by patterning and etching as shown in FIG. Next, as shown in FIG. 12 (K), the barrier metal 1
11A and copper 111B are formed by burying, and FIG.
As shown in (L), excess copper and barrier metal are removed by polishing. Then, as shown in FIG.
The second connection portion 113 and the second wiring layer 114 are completed by forming the diffusion prevention film 112 for protecting the copper wiring. Thereafter, the above dual damascene process (FIGS. 11H to 13M) is repeated a desired number of times to form a semiconductor device having multilayer wiring.
【０００８】図１４〜図１６は、第２の従来例によるＭ
ＯＳプロセスの各工程を示す断面図である。ここでは、
デュアルダマシンプロセスの部分のみを示しており、Ｍ
ＯＳトランジスタ領域の形成は上述した第１の従来例と
同様であるものとし、説明は省略する。まず、シリコン
基板２００にＭＯＳトランジスタを形成した後、図１４
（Ａ）に示すように、配線間絶縁膜２００中にシングル
ダマシン法により第１配線層１０１を形成する。ここで
配線材料に銅を用い、その拡散防止膜２０２として例え
ばＳｉＮ膜（シリコン窒化膜）を用いる。そして、この
保護膜２０２上に、例えば、絶縁膜２０３を成膜する。
この絶縁膜２０３には、例えば、低誘電率絶縁膜として
ＳｉＯ2 膜（シリコン酸化膜）を成膜するが、これには
限らない。ここで、形成する膜は、後の接続孔を形成す
るための絶縁膜となるため、膜厚は接続孔の深さに対応
したものとなる。14 to 16 show an M according to the second conventional example.
It is sectional drawing which shows each process of OS process. here,
Only the part of the dual damascene process is shown, and M
The formation of the OS transistor region is assumed to be similar to that of the above-described first conventional example, and description thereof will be omitted. First, after forming a MOS transistor on the silicon substrate 200, as shown in FIG.
As shown in (A), the first wiring layer 101 is formed in the inter-wiring insulating film 200 by the single damascene method. Here, copper is used as the wiring material, and a SiN film (silicon nitride film) is used as the diffusion prevention film 202. Then, for example, an insulating film 203 is formed on the protective film 202.
For example, a SiO2 film (silicon oxide film) is formed as the low dielectric constant insulating film on the insulating film 203, but the invention is not limited to this. Here, since the film to be formed becomes an insulating film for forming a connection hole later, the film thickness corresponds to the depth of the connection hole.
【０００９】次いで、この絶縁膜２０３上に接続孔を形
成するためのハードマスク（エッチングストッパ）とな
る無機膜２０４を成膜する。このハードマスクとなる無
機膜は、例えばＳｉＮ膜を用いるが、これには限らな
い。次いで、図１４（Ｂ）に示すように、レジスト２０
５を成膜し、接続孔をパターンニングし、図１４（Ｃ）
に示すように、レジスト２０５をマスクとして下層の無
機膜２０４をエッチングし、アッシング及び洗浄により
マスクとして用いたレジスト２０５を剥離する。次いで
図１４（Ｄ）に示すように、配線間絶縁膜となる絶縁膜
２０６を成膜する。この絶縁膜２０６には例えば低誘電
率絶縁膜、例えば、ＳｉＯ2 を用いるが、これには限ら
ない。次いで、図１５（Ｅ）に示すように、レジスト２
０７を成膜し、配線をパターンニングし、図１５（Ｆ）
に示すように、このパターンニングされたレジスト２０
７をマスクとして層間絶縁膜２０６をエッチングし、配
線のための溝２０６Ａを形成する。Next, an inorganic film 204 which serves as a hard mask (etching stopper) for forming a contact hole is formed on the insulating film 203. An SiN film, for example, is used as the inorganic film serving as the hard mask, but the invention is not limited to this. Then, as shown in FIG.
5 is formed into a film, the connection hole is patterned, and FIG.
As shown in FIG. 5, the lower inorganic film 204 is etched by using the resist 205 as a mask, and the resist 205 used as the mask is removed by ashing and cleaning. Next, as illustrated in FIG. 14D, an insulating film 206 which serves as an inter-wiring insulating film is formed. For example, a low dielectric constant insulating film such as SiO2 is used as the insulating film 206, but the insulating film 206 is not limited to this. Then, as shown in FIG.
07 is formed into a film, the wiring is patterned, and FIG.
As shown in FIG.
The interlayer insulating film 206 is etched by using 7 as a mask to form a groove 206A for wiring.
【００１０】次いで、図１５（Ｇ）に示すように、さら
に連続して、このレジスト２０７と接続孔がパターンニ
ングされた無機膜２０４とをハードマスクとして、絶縁
膜２０３をエッチングし、接続孔２０３Ａを形成する。
次いで、図１５（Ｈ）に示すように、この接続孔２０３
Ａの底部の拡散防止膜２０２をエッチングする。次い
で、図１６（Ｉ）に示すように、バリアメタル及び銅を
接続孔２０３Ａ及び配線溝２０６Ａに埋め込み、ＣＭＰ
により余剰な銅及びバリアメタルを研磨することで、配
線２０６Ｂと接続部２０３Ｂを完成する。そして、図１
６（Ｊ）に示すように、拡散防止膜２０８を成膜するこ
とで配線及び接続部が同時に完成する。この後、以上の
ようなデュアルダマシンプロセス（図１４（Ａ）〜図１
６（Ｊ））を所望の回数だけ繰り返すことにより、多層
配線を有した半導体装置が形成される。Then, as shown in FIG. 15G, the insulating film 203 is continuously etched using the resist 207 and the inorganic film 204 having the patterned contact holes as a hard mask to form the contact holes 203A. To form.
Then, as shown in FIG.
The diffusion prevention film 202 at the bottom of A is etched. Then, as shown in FIG. 16I, a barrier metal and copper are embedded in the connection hole 203A and the wiring groove 206A, and CMP is performed.
Then, the excess copper and the barrier metal are polished to complete the wiring 206B and the connecting portion 203B. And FIG.
As shown in FIG. 6 (J), the wiring and the connection portion are completed at the same time by forming the diffusion prevention film 208. After this, the dual damascene process as described above (see FIG. 14A to FIG.
By repeating 6 (J)) a desired number of times, a semiconductor device having multilayer wiring is formed.
【００１１】[0011]
【発明が解決しようとする課題】ところで、上述のよう
な従来例において、銅の拡散を防止するための保護膜
が、接続孔の開口部では除去されるものの、それ以外の
部分では残ってしまうことになる。また、接続孔を開口
するためのハードマスクも同様に、接続孔の開口部では
除去されるものの、それ以外の部分では残ってしまうこ
とになる。しかしながら、このように多層配線層におい
て、余分な拡散防止膜やハードマスクが光電変換素子の
上層の残ると、その分、光の透過経路における配線層の
膜厚が大きくなったり、光の透過率が低下することにな
り、光電変換素子に対する受光効率が悪くなり、感度の
低下等を招くという問題がある。By the way, in the above-mentioned conventional example, the protective film for preventing the diffusion of copper is removed at the opening of the connection hole, but remains at other portions. It will be. Similarly, the hard mask for opening the connection hole is removed at the opening of the connection hole but remains at other portions. However, in such a multilayer wiring layer, if an extra diffusion prevention film or a hard mask remains on the upper layer of the photoelectric conversion element, the film thickness of the wiring layer in the light transmission path is increased and the light transmittance is increased accordingly. Is lowered, the light receiving efficiency for the photoelectric conversion element is deteriorated, and the sensitivity is lowered.
【００１２】そこで本発明の目的は、銅配線を用いた場
合に必要となる拡散防止膜やハードマスク層によって生
じる光電変換素子への入射光の減衰を防止でき、感度や
画質等の特性を向上できる固体撮像素子及びその製造方
法を提供することにある。Therefore, an object of the present invention is to prevent attenuation of incident light to a photoelectric conversion element, which is caused by a diffusion preventive film or a hard mask layer, which is required when a copper wiring is used, and improve characteristics such as sensitivity and image quality. An object of the present invention is to provide a solid-state image pickup device and a method for manufacturing the same.
【００１３】[0013]
【課題を解決するための手段】本発明は前記目的を達成
するため、半導体基板に受光量に応じた信号電荷を生成
する光電変換素子と前記光電変換素子で生成した信号電
荷を読み出す読み出し回路とを含む撮像部を設けるとと
もに、前記半導体基板の上層に前記読み出し回路の配線
層を設けた固体撮像素子において、前記配線層は、少な
くとも一部に銅配線を有するとともに、前記銅配線の上
面を覆う拡散防止膜を有し、さらに前記拡散防止膜が少
なくとも前記光電変換素子の上部領域の所定範囲で開口
していることを特徴とする。In order to achieve the above object, the present invention provides a photoelectric conversion element for generating a signal charge according to the amount of received light on a semiconductor substrate, and a read circuit for reading the signal charge generated by the photoelectric conversion element. In a solid-state imaging device having an image pickup section including a wiring layer of the readout circuit provided on an upper layer of the semiconductor substrate, the wiring layer has at least a part of copper wiring and covers an upper surface of the copper wiring. A diffusion prevention film is provided, and the diffusion prevention film is opened at least in a predetermined range of an upper region of the photoelectric conversion element.
【００１４】また本発明は、半導体基板に受光量に応じ
た信号電荷を生成する光電変換素子と前記光電変換素子
で生成した信号電荷を読み出す読み出し回路とを含む撮
像部を設けるとともに、前記半導体基板の上層に前記読
み出し回路の配線層を設けた固体撮像素子において、前
記配線層は、少なくとも一部に銅配線を有するととも
に、前記銅配線が配置される配線溝形成用のエッチング
ストッパとなるハードマスク層を有し、さらに前記ハー
ドマスク層が少なくとも前記光電変換素子の上部領域の
所定範囲で開口していることを特徴とする。According to the present invention, the semiconductor substrate is provided with an image pickup section including a photoelectric conversion element for generating a signal charge according to the amount of received light and a read circuit for reading out the signal charge generated by the photoelectric conversion element, and the semiconductor substrate is provided. In a solid-state imaging device having a wiring layer for the readout circuit as an upper layer, the wiring layer has a copper wiring in at least a part thereof, and a hard mask serving as an etching stopper for forming a wiring groove in which the copper wiring is arranged. A layer, and the hard mask layer is opened at least in a predetermined range of an upper region of the photoelectric conversion element.
【００１５】また本発明は、半導体基板に受光量に応じ
た信号電荷を生成する光電変換素子と前記光電変換素子
で生成した信号電荷を読み出す読み出し回路とを含む撮
像部を設けるとともに、前記半導体基板の上層に前記読
み出し回路の配線層を設けた固体撮像素子の製造方法に
おいて、前記配線層の少なくとも一部に銅配線を用いる
とともに、前記銅配線の上面を覆う拡散防止膜を形成
し、さらに前記拡散防止膜を少なくとも前記光電変換素
子の上部領域の所定範囲で除去することを特徴とする。According to the present invention, the semiconductor substrate is provided with an image pickup section including a photoelectric conversion element for generating a signal charge according to the amount of received light and a reading circuit for reading out the signal charge generated by the photoelectric conversion element, and the semiconductor substrate is provided. In a method for manufacturing a solid-state imaging device having a wiring layer of the readout circuit as an upper layer, copper wiring is used for at least a part of the wiring layer, and a diffusion prevention film is formed to cover an upper surface of the copper wiring, and It is characterized in that the diffusion prevention film is removed at least in a predetermined range of an upper region of the photoelectric conversion element.
【００１６】また本発明は、半導体基板に受光量に応じ
た信号電荷を生成する光電変換素子と前記光電変換素子
で生成した信号電荷を読み出す読み出し回路とを含む撮
像部を設けるとともに、前記半導体基板の上層に前記読
み出し回路の配線層を設けた固体撮像素子の製造方法に
おいて、前記配線層の少なくとも一部に銅配線を用いる
とともに、前記銅配線を配置する配線溝をエッチングス
トッパとなるハードマスク層を用いて形成し、さらに前
記ハードマスク層を少なくとも前記光電変換素子の上部
領域の所定範囲で除去することを特徴とする。Further, according to the present invention, the semiconductor substrate is provided with an image pickup section including a photoelectric conversion element for generating a signal charge according to the amount of received light and a read circuit for reading out the signal charge generated by the photoelectric conversion element, and the semiconductor substrate is provided. In a method for manufacturing a solid-state imaging device, wherein a wiring layer for the readout circuit is provided on the upper layer of the hard mask layer, copper wiring is used for at least a part of the wiring layer, and a wiring groove in which the copper wiring is arranged serves as an etching stopper. And further, the hard mask layer is removed at least in a predetermined range of the upper region of the photoelectric conversion element.
【００１７】本発明の固体撮像素子およびその製造方法
では、銅配線の上面を覆う拡散防止膜を設けた配線層に
おいて、この拡散防止膜が光電変換素子の上部領域の所
定範囲で除去され、開口しているため、光電変換素子へ
の光の入射が拡散防止膜の影響を受けず、感度等の特性
を向上できる。また、本発明の固体撮像素子およびその
製造方法では、銅配線形成用の配線溝をエッチングスト
ッパとなるハードマスク層を用いて形成した配線層にお
いて、このハードマスク層が光電変換素子の上部領域の
所定範囲で除去され、開口しているため、光電変換素子
への光の入射がハードマスク層の影響を受けず、感度等
の特性を向上できる。In the solid-state imaging device and the manufacturing method thereof according to the present invention, in the wiring layer provided with the diffusion prevention film covering the upper surface of the copper wiring, the diffusion prevention film is removed in a predetermined range in the upper region of the photoelectric conversion element, and the opening is formed. Therefore, the incidence of light on the photoelectric conversion element is not affected by the diffusion prevention film, and characteristics such as sensitivity can be improved. Further, in the solid-state imaging device and the manufacturing method thereof of the present invention, in the wiring layer in which the wiring groove for forming the copper wiring is formed by using the hard mask layer serving as the etching stopper, the hard mask layer is located in the upper region of the photoelectric conversion element. Since it is removed in a predetermined range and has an opening, the incidence of light on the photoelectric conversion element is not affected by the hard mask layer, and characteristics such as sensitivity can be improved.
【００１８】[0018]
【発明の実施の形態】以下、本発明による固体撮像素子
およびその製造方法の実施の形態例について説明する。
本実施の形態例は、ＭＯＳ型イメージセンサ等の固体撮
像素子において、配線に銅を用いたデュアルダマシンプ
ロセスを用いる場合に、光電変換素子の上部領域から銅
の拡散防止膜とデュアルダマシン形成のためのハードマ
スクとを除去することにより、光電変換素子に対する光
学効率を高め、感度や画質の向上を図るようにしたもの
である。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a solid-state image sensor and a method of manufacturing the same according to the present invention will be described below.
This embodiment is for forming a copper diffusion prevention film and a dual damascene from the upper region of the photoelectric conversion element when a dual damascene process using copper for wiring is used in a solid-state image sensor such as a MOS image sensor. By removing the hard mask of (1), the optical efficiency of the photoelectric conversion element is increased, and the sensitivity and the image quality are improved.
【００１９】図１〜図９は、本発明の実施の形態例によ
るＭＯＳプロセスの各工程を示す断面図である。なお、
以下の説明では、半導体基板中に入射した光を信号電荷
に変換することを目的する箇所（すなわち光電変換素子
の受光面）を光電変換領域とし、また、それ以外の部
分、例えば、ロジック回路、アナログ回路、メモリ回路
等の各素子を配置した領域を非光電変換領域として説明
する。まず、図１（Ａ）では、シリコン基板３００の非
光電変換領域３００Ｂの少なくとも一部に所定のＭＯＳ
トランジスタを形成し、光電変換領域３００Ａに光電変
換素子としてのフォトダイオード３０４を形成する。こ
れは、まずシリコン基板３００上に素子分離領域３０１
を形成し、次いで、シリコン基板３００中に所定のウエ
ル領域（図示せず）を形成する。次いで、このシリコン
基板３００上にゲート絶縁膜、ゲート電極を含むゲート
電極部３０２を形成した後、イオン注入と熱処理により
例えばＬＤＤ（LightlyDoped Drain ）構造を有する高
濃度拡散層領域３０３を形成する。1 to 9 are sectional views showing respective steps of a MOS process according to an embodiment of the present invention. In addition,
In the following description, a portion intended to convert the light entering the semiconductor substrate into a signal charge (that is, the light receiving surface of the photoelectric conversion element) is a photoelectric conversion region, and other portions, for example, a logic circuit, A region in which each element such as an analog circuit and a memory circuit is arranged will be described as a non-photoelectric conversion region. First, in FIG. 1A, a predetermined MOS is formed on at least a part of the non-photoelectric conversion region 300B of the silicon substrate 300.
A transistor is formed, and a photodiode 304 as a photoelectric conversion element is formed in the photoelectric conversion region 300A. First, an element isolation region 301 is formed on a silicon substrate 300.
Then, a predetermined well region (not shown) is formed in the silicon substrate 300. Next, after forming a gate insulating film and a gate electrode portion 302 including a gate electrode on the silicon substrate 300, a high concentration diffusion layer region 303 having, for example, an LDD (Lightly Doped Drain) structure is formed by ion implantation and heat treatment.
【００２０】次いで、光電変換領域３００Ａ側でシリコ
ン基板３００の上面からイオン注入等を行うことによっ
てフォトダイオード３０４を形成するが、フォトダイオ
ード３０４の構造は図では省略している。なお、フォト
ダイオードは埋め込み型であってもよい。そして、その
上層に第１層間絶縁膜３０５を形成することにより、下
地ＭＯＳトランジスタ領域を形成する。なお、第１層間
絶縁膜３０５には、例えば、ＳｉＯ2 やｌｏｗ−ｋ材料
を用いるが、それには限らない。Next, the photodiode 304 is formed by performing ion implantation or the like from the upper surface of the silicon substrate 300 on the photoelectric conversion region 300A side, but the structure of the photodiode 304 is omitted in the figure. The photodiode may be a buried type. Then, a first interlayer insulating film 305 is formed thereover to form a base MOS transistor region. The first interlayer insulating film 305 is made of, for example, SiO2 or low-k material, but is not limited thereto.
【００２１】次いで、図１（Ｂ）に示すように、ＭＯＳ
トランジスタの各領域に対応して接続孔をパターンニン
グし、エッチングすることで、接続孔を開口する。そし
て、開口された接続孔に、例えばバリアメタルと電極材
料を埋め込むことで、接続部３０５Ａ、３０５Ｂを形成
する。例えば、バリアメタルには窒化チタンを、電極材
料にはタングステンを用いるが、それには限らない。次
いで、図１（Ｃ）に示すように、第１配線間絶縁膜３０
６を形成する。この配線間絶縁膜３０６には、ここで
は、例えば、ＳｉＯ2 等の低誘電率材料膜を用いるが、
それには限らない。次いで、図２（Ｄ）に示すように、
第１配線間絶縁膜３０６をパターンニングとエッチング
によって加工し、後の銅配線となる部分に第１配線溝３
０６Ａを開口する。Then, as shown in FIG.
The contact holes are opened by patterning and etching the contact holes corresponding to the respective regions of the transistor. Then, for example, a barrier metal and an electrode material are embedded in the opened connection hole to form the connection portions 305A and 305B. For example, titanium nitride is used for the barrier metal and tungsten is used for the electrode material, but not limited thereto. Then, as shown in FIG. 1C, the first inter-wiring insulating film 30 is formed.
6 is formed. For the inter-wiring insulating film 306, a low dielectric constant material film such as SiO2 is used here,
It is not limited to that. Then, as shown in FIG.
The first inter-wiring insulating film 306 is processed by patterning and etching, and the first wiring groove 3 is formed in a portion to be a copper wiring later.
Open 06A.
【００２２】次いで、図２（Ｅ）に示すように、バリア
メタル及び銅の層を成膜して第１配線溝３０６Ａに埋め
込み、図３（Ｆ）に示すように、ＣＭＰにより余剰な銅
及びバリアメタルを研磨することで、バリアメタル及び
銅による第１配線層３０６Ｂを形成する。なお、バリア
メタルとしては例えば窒化タンタルを用い、配線材料に
は銅を用いるが、これには限るものではない。次いで、
図３（Ｇ）に示すように、第１配線層３０６Ｂの上層に
銅配線を保護するための拡散防止膜３０７を成膜するこ
とにより、第１配線層３０６Ｂ及び第１接続部３０５
Ａ、３０５Ｂが完成される。ここで、拡散防止膜３０７
は、例えば窒化シリコン膜、あるいは炭化シリコン膜等
を用いるが、これに限るものではない。Next, as shown in FIG. 2 (E), a barrier metal and copper layer is formed and embedded in the first wiring trench 306A, and as shown in FIG. 3 (F), excess copper and copper are removed by CMP. By polishing the barrier metal, the first wiring layer 306B made of the barrier metal and copper is formed. Although tantalum nitride is used as the barrier metal and copper is used as the wiring material, the barrier metal is not limited to this. Then
As shown in FIG. 3G, by forming a diffusion prevention film 307 for protecting the copper wiring on the first wiring layer 306B, the first wiring layer 306B and the first connection portion 305 are formed.
A, 305B is completed. Here, the diffusion prevention film 307
For example, a silicon nitride film or a silicon carbide film is used, but the present invention is not limited to this.
【００２３】次いで、図４（Ｈ）に示すように、非光電
変換領域３００Ｂ側にレジストマスク３１８をパターン
ニングし、図４（Ｉ）に示すように、このレジストマス
ク３１８をマスクとして光電変換領域３００Ａ側の拡散
防止膜３０７をエッチングにより除去する。次にアッシ
ング等によりレジストマスク３１８を除去する。なお、
拡散防止膜３０７を除去する領域は、光電変換領域３０
０Ａ全体でなくともよく、フォトダイオードの受光量域
だけを選択的に除去するようにしてもよい。次いで、図
５（Ｊ）に示すように第２層間絶縁膜３０８を成膜し、
次いで、接続孔のエッチングストッパ用のハードマスク
層３０９を成膜する。なお、第２層間絶縁膜としては、
例えば、ＳｉＯ2 やｌｏｗ−ｋ材料等の低誘電率絶縁膜
を用いるが、それらに限らない。また、接続孔のハード
マスク層３０９としては、窒化シリコンや炭化シリコン
を用いるが、それらに限らない。Next, as shown in FIG. 4H, a resist mask 318 is patterned on the non-photoelectric conversion region 300B side, and as shown in FIG. 4I, the resist mask 318 is used as a mask for the photoelectric conversion region. The diffusion barrier film 307 on the 300A side is removed by etching. Next, the resist mask 318 is removed by ashing or the like. In addition,
The region where the diffusion prevention film 307 is removed is the photoelectric conversion region 30.
It is not necessary to use the entire 0A, and only the light receiving amount region of the photodiode may be selectively removed. Then, a second interlayer insulating film 308 is formed as shown in FIG.
Then, a hard mask layer 309 for an etching stopper of the connection hole is formed. In addition, as the second interlayer insulating film,
For example, a low dielectric constant insulating film such as SiO2 or a low-k material is used, but not limited to them. Further, although silicon nitride or silicon carbide is used as the hard mask layer 309 of the connection hole, it is not limited to them.
【００２４】次いで、図５（Ｋ）に示すように、ハード
マスク層３０９の第２接続孔３０９Ａとなる箇所にパタ
ーンニングし、エッチングすることで、ハードマスク層
３０９を完成する。次いで、図では省略しているが、拡
散防止膜３０７の場合と同様に、非光電変換領域３００
Ｂ側にレジストマスクをパターンニングし、このレジス
トマスクをマスクとして光電変換領域３００Ａ側のハー
ドマスク層３０９をエッチングにより除去する。次にア
ッシング等によりレジストマスクを除去する。なお、ハ
ードマスク層３０９を除去する領域は、光電変換領域３
００Ａ全体でなくともよく、フォトダイオードの受光量
域だけを選択的に除去するようにしてもよい。また、こ
のようなハードマスク層３０９に対する第２接続孔３０
９Ａの開口と、光電変換領域３００Ａ上のハードマスク
層３０９の除去とを同時に行っても良い。Next, as shown in FIG. 5K, the hard mask layer 309 is completed by patterning and etching the portions of the hard mask layer 309 to be the second connection holes 309A. Next, although not shown in the figure, as in the case of the diffusion prevention film 307, the non-photoelectric conversion region 300 is formed.
A resist mask is patterned on the B side, and the hard mask layer 309 on the photoelectric conversion region 300A side is removed by etching using this resist mask as a mask. Next, the resist mask is removed by ashing or the like. The region where the hard mask layer 309 is removed is the photoelectric conversion region 3.
00A does not have to be the whole and only the light receiving amount region of the photodiode may be selectively removed. In addition, the second connection hole 30 for the hard mask layer 309.
The opening of 9A and the removal of the hard mask layer 309 on the photoelectric conversion region 300A may be performed at the same time.
【００２５】次いで、図６（Ｌ）に示すように、第２配
線間絶縁膜３１０を成膜する。この第２配線間絶縁膜と
しては、例えば、ＳｉＯ2 等の低誘電率絶縁膜を用いる
が、それに限らない。次いで、図６（Ｍ）に示すよう
に、第２配線を形成するためのレジストマスク３１１を
パターンニングし、次に、図７（Ｎ）に示すように、パ
ターン３１１をマスクとして第２配線間絶縁膜３１０を
エッチングし、次いで、接続孔３０９Ａが開口されたハ
ードマスク層３０９をマスクとして、第２層間絶縁膜３
０８、拡散防止膜３０７をエッチングすることで、接続
孔３０８Ａと配線溝３１０Ａを形成する。この後、図７
（Ｏ）に示すように、レジストマスク３１１をアッシン
グと洗浄により除去する。Next, as shown in FIG. 6L, a second inter-wiring insulating film 310 is formed. As the second inter-wiring insulating film, for example, a low dielectric constant insulating film such as SiO2 is used, but it is not limited thereto. Next, as shown in FIG. 6M, a resist mask 311 for forming a second wiring is patterned, and then, as shown in FIG. The insulating film 310 is etched, and then the second interlayer insulating film 3 is formed using the hard mask layer 309 having the connection hole 309A opened as a mask.
08 and the diffusion prevention film 307 are etched to form the connection hole 308A and the wiring groove 310A. After this, FIG.
As shown in (O), the resist mask 311 is removed by ashing and cleaning.
【００２６】次いで、図８（Ｐ）に示すように、バリア
メタル、配線電極材料を成膜することにより、接続部３
０８Ｂと配線３１０Ｂを形成する。バリアメタルとして
は窒化タンタル等を用い、配線電極材料には銅を用いる
が、それらに限らない。次いで、研磨により余剰なバリ
アメタルと配線電極材料を除去する。次に、図８（Ｑ）
に示すように、拡散防止膜３１２を成膜する。なお、こ
の拡散防止膜としては、例えば、窒化シリコン、炭化シ
リコンを用いるが、これに限らない。この後、図９
（Ｒ）に示すように、拡散防止膜３０７の場合と同様
に、非光電変換領域３００Ｂ側にレジストマスク３１３
をパターンニングし、図９（Ｓ）に示すように、このレ
ジストマスク３１３をマスクとして光電変換領域３００
Ａ側の拡散防止膜３１２をエッチングにより除去する。
次にアッシング等によりレジストマスク３１３を除去す
る。なお、拡散防止膜３１２を除去する領域は、光電変
換領域３００Ａ全体でなくともよく、フォトダイオード
の受光量域だけを選択的に除去するようにしてもよい。
この後、以上のデュアルダマシンプロセス（図５（Ｊ）
〜図９（Ｓ））を所望の回数だけ繰り返すことにより、
多層配線を形成する。Next, as shown in FIG. 8 (P), a barrier metal and a wiring electrode material are deposited to form the connecting portion 3
08B and wiring 310B are formed. Although tantalum nitride or the like is used as the barrier metal and copper is used as the wiring electrode material, it is not limited thereto. Then, excess barrier metal and wiring electrode material are removed by polishing. Next, FIG. 8 (Q)
As shown in, a diffusion prevention film 312 is formed. As the diffusion prevention film, for example, silicon nitride or silicon carbide is used, but the diffusion prevention film is not limited to this. After this,
As shown in (R), as in the case of the diffusion prevention film 307, a resist mask 313 is formed on the non-photoelectric conversion region 300B side.
Is patterned, and as shown in FIG. 9 (S), the photoelectric conversion region 300 is formed using this resist mask 313 as a mask.
The diffusion prevention film 312 on the A side is removed by etching.
Next, the resist mask 313 is removed by ashing or the like. The region where the diffusion prevention film 312 is removed need not be the entire photoelectric conversion region 300A, and only the light receiving amount region of the photodiode may be selectively removed.
After this, the above dual damascene process (FIG. 5 (J))
By repeating FIG. 9 (S) a desired number of times,
Form multilayer wiring.
【００２７】以上のように、本例では、光電変換領域３
００Ａで、拡散防止膜３０７、３１２やハードマスク３
０９を除去した層構造とすることにより、光学特性に優
れた個体撮像素子を形成できる。なお、拡散防止膜およ
びハードマスクのいずれか一方を除去した構成について
も一定の効果を得ることができ、本発明の範囲に含まれ
るものとする。また、本発明は、ＭＯＳ型イメージセン
サに限定されず、他の固体撮像素子に広く適用し得るも
のである。As described above, in this example, the photoelectric conversion region 3
00A, diffusion barrier films 307 and 312 and hard mask 3
By adopting a layered structure in which 09 is removed, a solid-state image sensor having excellent optical characteristics can be formed. It should be noted that a certain effect can be obtained even in the configuration in which either one of the diffusion prevention film and the hard mask is removed, and is included in the scope of the present invention. Further, the present invention is not limited to the MOS type image sensor, but can be widely applied to other solid-state image pickup devices.
【００２８】[0028]
【発明の効果】以上説明したように本発明の固体撮像素
子によれば、銅配線の上面を覆う拡散防止膜を設けた配
線層において、この拡散防止膜が光電変換素子の上部領
域の所定範囲で開口しているため、光電変換素子への光
の入射が拡散防止膜の影響を受けず、感度や画質等の特
性を向上できる。また、本発明の固体撮像素子によれ
ば、銅配線形成用の配線溝をエッチングストッパとなる
ハードマスク層を用いて形成した配線層において、この
ハードマスク層が光電変換素子の上部領域の所定範囲で
開口しているため、光電変換素子への光の入射がハード
マスク層の影響を受けず、感度や画質等の特性を向上で
きる。As described above, according to the solid-state image pickup device of the present invention, in the wiring layer provided with the diffusion prevention film covering the upper surface of the copper wiring, this diffusion prevention film has a predetermined area in the upper region of the photoelectric conversion element. Since the light is incident on the photoelectric conversion element, it is not affected by the diffusion prevention film, and characteristics such as sensitivity and image quality can be improved. Further, according to the solid-state imaging device of the present invention, in the wiring layer in which the wiring groove for forming the copper wiring is formed by using the hard mask layer serving as an etching stopper, the hard mask layer has a predetermined area in the upper region of the photoelectric conversion element. Since the openings are provided in the photoelectric conversion element, the incidence of light on the photoelectric conversion element is not affected by the hard mask layer, and characteristics such as sensitivity and image quality can be improved.
【００２９】また、本発明の製造方法によれば、銅配線
の上面を覆う拡散防止膜を設ける場合に、この拡散防止
膜を光電変換素子の上部領域の所定範囲で除去するた
め、光電変換素子への光の入射が拡散防止膜の影響を受
けず、感度や画質等の特性を向上できる。また、本発明
の製造方法によれば、銅配線形成用の配線溝をエッチン
グストッパとなるハードマスク層を用いて形成する場合
に、このハードマスク層を光電変換素子の上部領域の所
定範囲で除去するため、光電変換素子への光の入射がハ
ードマスク層の影響を受けず、感度や画質等の特性を向
上できる。Further, according to the manufacturing method of the present invention, when the diffusion preventive film covering the upper surface of the copper wiring is provided, the diffusion preventive film is removed within a predetermined range of the upper region of the photoelectric conversion device. The incidence of light on is not affected by the diffusion prevention film, and characteristics such as sensitivity and image quality can be improved. Further, according to the manufacturing method of the present invention, when the wiring groove for forming the copper wiring is formed by using the hard mask layer serving as an etching stopper, the hard mask layer is removed in a predetermined range in the upper region of the photoelectric conversion element. Therefore, the incidence of light on the photoelectric conversion element is not affected by the hard mask layer, and characteristics such as sensitivity and image quality can be improved.
【図１】本発明の実施の形態例による固体撮像素子の製
造方法を示す断面図である。FIG. 1 is a cross-sectional view showing a method of manufacturing a solid-state image sensor according to an embodiment of the present invention.
【図２】本発明の実施の形態例による固体撮像素子の製
造方法を示す断面図である。FIG. 2 is a cross-sectional view showing the method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
【図３】本発明の実施の形態例による固体撮像素子の製
造方法を示す断面図である。FIG. 3 is a cross-sectional view showing the method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
【図４】本発明の実施の形態例による固体撮像素子の製
造方法を示す断面図である。FIG. 4 is a cross-sectional view showing the method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
【図５】本発明の実施の形態例による固体撮像素子の製
造方法を示す断面図である。FIG. 5 is a cross-sectional view showing the method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
【図６】本発明の実施の形態例による固体撮像素子の製
造方法を示す断面図である。FIG. 6 is a cross-sectional view showing the method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
【図７】本発明の実施の形態例による固体撮像素子の製
造方法を示す断面図である。FIG. 7 is a cross-sectional view showing the method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
【図８】本発明の実施の形態例による固体撮像素子の製
造方法を示す断面図である。FIG. 8 is a cross-sectional view showing the method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
【図９】本発明の実施の形態例による固体撮像素子の製
造方法を示す断面図である。FIG. 9 is a cross-sectional view showing the method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
【図１０】第１の従来例による固体撮像素子の製造方法
を示す断面図である。FIG. 10 is a cross-sectional view showing the method of manufacturing the solid-state imaging device according to the first conventional example.
【図１１】第１の従来例による固体撮像素子の製造方法
を示す断面図である。FIG. 11 is a cross-sectional view showing the method of manufacturing the solid-state imaging device according to the first conventional example.
【図１２】第１の従来例による固体撮像素子の製造方法
を示す断面図である。FIG. 12 is a cross-sectional view showing the method of manufacturing the solid-state imaging device according to the first conventional example.
【図１３】第１の従来例による固体撮像素子の製造方法
を示す断面図である。FIG. 13 is a cross-sectional view showing the method of manufacturing the solid-state imaging device according to the first conventional example.
【図１４】第２の従来例による固体撮像素子の製造方法
を示す断面図である。FIG. 14 is a cross-sectional view showing the method of manufacturing the solid-state imaging device according to the second conventional example.
【図１５】第２の従来例による固体撮像素子の製造方法
を示す断面図である。FIG. 15 is a cross-sectional view showing the method of manufacturing the solid-state imaging device according to the second conventional example.
【図１６】第２の従来例による固体撮像素子の製造方法
を示す断面図である。FIG. 16 is a cross-sectional view showing the method of manufacturing the solid-state imaging device according to the second conventional example.
３００……シリコン基板、３０１……素子分離領域、３
０２……ゲート電極部、３０３……高濃度拡散層領域、
３０４……フォトダイオード、３０５……第１層間絶縁
膜、３０５Ａ、３０５Ｂ……第１接続部、３０６……第
１配線間絶縁膜、３０６Ａ……第１配線溝、３０６Ｂ…
…第１配線層、３０７、３１２……拡散防止膜、３０８
……第２層間絶縁膜、３０８Ａ……第２接続孔、３０８
Ｂ……第２接続部、３０９……ハードマスク層、３０９
Ａ……第２接続孔、３１０……第２配線間絶縁膜、３１
０Ａ……第２配線溝、３１０Ｂ……第２配線層。300: Silicon substrate, 301: Element isolation region, 3
02: gate electrode part, 303: high-concentration diffusion layer region,
304 ... Photodiode, 305 ... First interlayer insulating film, 305A, 305B ... First connecting portion, 306 ... First inter-wiring insulating film, 306A ... First wiring groove, 306B ...
... First wiring layer, 307, 312 ... Diffusion prevention film, 308
...... Second interlayer insulating film, 308A ...... Second connection hole, 308
B ... Second connection portion, 309 ... Hard mask layer, 309
A: second connection hole, 310: second inter-wiring insulating film, 31
0A: second wiring groove, 310B: second wiring layer.
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 4M118 AA01 AB01 BA14 CA03 CA04 CB14 EA01 FA06 5C024 CX41 CY47 EX25 GY31 5F033 HH11 HH32 JJ01 JJ11 JJ19 JJ32 JJ33 KK01 KK11 KK32 MM01 MM02 MM12 MM13 NN06 NN07 QQ08 QQ09 QQ10 QQ25 QQ28 QQ37 QQ48 RR01 RR04 RR06 RR11 TT01 XX29 ─────────────────────────────────────────────────── ─── Continued front page F-term (reference) 4M118 AA01 AB01 BA14 CA03 CA04 CB14 EA01 FA06 5C024 CX41 CY47 EX25 GY31 5F033 HH11 HH32 JJ01 JJ11 JJ19 JJ32 JJ33 KK01 KK11 KK32 MM01 MM02 MM12 MM13 NN06 NN07 QQ08 QQ09 QQ10 QQ25 QQ28 QQ37 QQ48 RR01 RR04 RR06 RR11 TT01 XX29
Claims (26)
生成する光電変換素子と前記光電変換素子で生成した信
号電荷を読み出す読み出し回路とを含む撮像部を設ける
とともに、前記半導体基板の上層に前記読み出し回路の
配線層を設けた固体撮像素子において、 前記配線層は、少なくとも一部に銅配線を有するととも
に、前記銅配線の上面を覆う拡散防止膜を有し、 さらに前記拡散防止膜が少なくとも前記光電変換素子の
上部領域の所定範囲で開口している、ことを特徴とする
固体撮像素子。1. A semiconductor substrate is provided with an image pickup unit including a photoelectric conversion element that generates a signal charge according to the amount of received light and a readout circuit that reads out the signal charge generated by the photoelectric conversion element, and an upper layer of the semiconductor substrate. In the solid-state imaging device provided with the wiring layer of the readout circuit, the wiring layer has a copper wiring in at least a part thereof, a diffusion prevention film covering an upper surface of the copper wiring, and the diffusion prevention film is at least A solid-state imaging device having an opening in a predetermined range of an upper region of the photoelectric conversion device.
により形成されていることを特徴とする請求項１記載の
固体撮像素子。2. The solid-state imaging device according to claim 1, wherein the copper wiring is formed by embedding copper in a wiring groove.
ングステン金属を用い、その上層配線の少なくとも一部
に銅金属を用いることを特徴とする請求項１記載の固体
撮像素子。3. The solid-state image pickup device according to claim 1, wherein a tungsten metal is used for a connection portion of a first layer from the bottom of the wiring layer, and a copper metal is used for at least a part of an upper layer wiring thereof.
ことを特徴とする請求項１記載の固体撮像素子。4. The solid-state imaging device according to claim 1, wherein the diffusion prevention film is made of silicon carbide.
ことを特徴とする請求項１記載の固体撮像素子。5. The solid-state imaging device according to claim 1, wherein the diffusion prevention film is made of silicon nitride.
層に形成され、前記層間絶縁膜がｌｏｗ−ｋ材料よりな
ることを特徴とする請求項１記載の固体撮像素子。6. The solid-state imaging device according to claim 1, wherein the wiring layer is formed in a plurality of layers with an interlayer insulating film interposed therebetween, and the interlayer insulating film is made of a low-k material.
生成する光電変換素子と前記光電変換素子で生成した信
号電荷を読み出す読み出し回路とを含む撮像部を設ける
とともに、前記半導体基板の上層に前記読み出し回路の
配線層を設けた固体撮像素子において、 前記配線層は、少なくとも一部に銅配線を有するととも
に、前記銅配線が配置される配線溝形成用のエッチング
ストッパとなるハードマスク層を有し、 さらに前記ハードマスク層が少なくとも前記光電変換素
子の上部領域の所定範囲で開口している、ことを特徴と
する固体撮像素子。7. A semiconductor substrate is provided with an image pickup section including a photoelectric conversion element for generating signal charges according to the amount of received light and a readout circuit for reading out the signal charges generated by the photoelectric conversion element, and an upper layer of the semiconductor substrate. In the solid-state imaging device provided with the wiring layer of the readout circuit, the wiring layer has at least a part of copper wiring and a hard mask layer serving as an etching stopper for forming a wiring groove in which the copper wiring is arranged. Further, the solid-state imaging device, wherein the hard mask layer is opened at least in a predetermined range of an upper region of the photoelectric conversion device.
により形成されていることを特徴とする請求項７記載の
固体撮像素子。8. The solid-state imaging device according to claim 7, wherein the copper wiring is formed by embedding copper in a wiring groove.
ングステン金属を用い、その上層配線の少なくとも一部
に銅金属を用いることを特徴とする請求項７記載の固体
撮像素子。9. The solid-state image pickup device according to claim 7, wherein a tungsten metal is used for the connection portion of the first layer from the bottom of the wiring layer, and a copper metal is used for at least a part of the upper layer wiring.
コンよりなることを特徴とする請求項７記載の固体撮像
素子。10. The solid-state imaging device according to claim 7, wherein the etching stopper layer is made of silicon carbide.
コンよりなることを特徴とする請求項７記載の固体撮像
素子。11. The solid-state imaging device according to claim 7, wherein the etching stopper layer is made of silicon nitride.
の層に形成され、前記層間絶縁膜がｌｏｗ−ｋ材料より
なることを特徴とする請求項７記載の固体撮像素子。12. The solid-state imaging device according to claim 7, wherein the wiring layer is formed in a plurality of layers with an interlayer insulating film interposed therebetween, and the interlayer insulating film is made of a low-k material.
を生成する光電変換素子と前記光電変換素子で生成した
信号電荷を読み出す読み出し回路とを含む撮像部を設け
るとともに、前記半導体基板の上層に前記読み出し回路
の配線層を設けた固体撮像素子において、 前記配線層は、少なくとも一部に銅配線を有するととも
に、前記銅配線の上面を覆う拡散防止膜と、前記銅配線
が配置される配線溝形成用のエッチングストッパとなる
ハードマスク層を有し、 さらに前記拡散防止膜およびハードマスク層が少なくと
も前記光電変換素子の上部領域の所定範囲で開口してい
る、ことを特徴とする固体撮像素子。13. A semiconductor substrate is provided with an image pickup section including a photoelectric conversion element for generating a signal charge according to an amount of received light and a readout circuit for reading out the signal charge generated by the photoelectric conversion element, and an upper layer of the semiconductor substrate. In the solid-state imaging device provided with the wiring layer of the readout circuit, the wiring layer has copper wiring in at least a part thereof, a diffusion prevention film covering an upper surface of the copper wiring, and a wiring groove in which the copper wiring is arranged. A solid-state imaging device, comprising a hard mask layer serving as an etching stopper for formation, and further, the diffusion prevention film and the hard mask layer are opened at least in a predetermined range of an upper region of the photoelectric conversion device.
を生成する光電変換素子と前記光電変換素子で生成した
信号電荷を読み出す読み出し回路とを含む撮像部を設け
るとともに、前記半導体基板の上層に前記読み出し回路
の配線層を設けた固体撮像素子の製造方法において、 前記配線層の少なくとも一部に銅配線を用いるととも
に、前記銅配線の上面を覆う拡散防止膜を形成し、 さらに前記拡散防止膜を少なくとも前記光電変換素子の
上部領域の所定範囲で除去する、 ことを特徴とする固体撮像素子の製造方法。14. A semiconductor substrate is provided with an image pickup section including a photoelectric conversion element for generating a signal charge according to an amount of received light and a readout circuit for reading out the signal charge generated by the photoelectric conversion element, and an upper layer of the semiconductor substrate. In the method for manufacturing a solid-state imaging device provided with a wiring layer of the readout circuit, copper wiring is used in at least a part of the wiring layer, and a diffusion prevention film is formed to cover an upper surface of the copper wiring, and the diffusion prevention film is further formed. Is removed at least in a predetermined range of the upper region of the photoelectric conversion element.
により形成することを特徴とする請求項１４記載の固体
撮像素子の製造方法。15. The method for manufacturing a solid-state imaging device according to claim 14, wherein the copper wiring is formed by embedding copper in a wiring groove.
タングステン金属を用い、その上層配線の少なくとも一
部に銅金属を用いることを特徴とする請求項１４記載の
固体撮像素子の製造方法。16. The manufacture of a solid-state image pickup device according to claim 14, wherein tungsten metal is used for the connection portion of the first layer from the bottom of the wiring layer, and copper metal is used for at least a part of the upper layer wiring. Method.
成することを特徴とする請求項１４記載の固体撮像素子
の製造方法。17. The method for manufacturing a solid-state imaging device according to claim 14, wherein the diffusion barrier film is formed of silicon carbide.
成することを特徴とする請求項１４記載の固体撮像素子
の製造方法。18. The method of manufacturing a solid-state image sensor according to claim 14, wherein the diffusion barrier film is formed of silicon nitride.
の層に形成し、前記層間絶縁膜をｌｏｗ−ｋ材料より形
成することを特徴とする請求項１４記載の固体撮像素子
の製造方法。19. The method of manufacturing a solid-state imaging device according to claim 14, wherein the wiring layers are formed in a plurality of layers with an interlayer insulating film interposed therebetween, and the interlayer insulating film is formed of a low-k material. .
を生成する光電変換素子と前記光電変換素子で生成した
信号電荷を読み出す読み出し回路とを含む撮像部を設け
るとともに、前記半導体基板の上層に前記読み出し回路
の配線層を設けた固体撮像素子の製造方法において、 前記配線層の少なくとも一部に銅配線を用いるととも
に、前記銅配線を配置する配線溝をエッチングストッパ
となるハードマスク層を用いて形成し、 さらに前記ハードマスク層を少なくとも前記光電変換素
子の上部領域の所定範囲で除去する、 ことを特徴とする固体撮像素子の製造方法。20. A semiconductor substrate is provided with an image pickup unit including a photoelectric conversion element that generates a signal charge according to the amount of received light and a readout circuit that reads out the signal charge generated by the photoelectric conversion element, and an upper layer of the semiconductor substrate. In the method for manufacturing a solid-state imaging device provided with a wiring layer of the readout circuit, copper wiring is used in at least part of the wiring layer, and a hard mask layer serving as an etching stopper is used for a wiring groove in which the copper wiring is arranged. A method of manufacturing a solid-state image pickup device, comprising: forming and further removing the hard mask layer at least in a predetermined range of an upper region of the photoelectric conversion device.
より形成されていることを特徴とする請求項２０記載の
固体撮像素子の製造方法。21. The method of manufacturing a solid-state image sensor according to claim 20, wherein the copper wiring is formed by embedding it in a wiring groove.
タングステン金属を用い、その上層配線の少なくとも一
部に銅金属を用いることを特徴とする請求項２０記載の
固体撮像素子の製造方法。22. The manufacturing of a solid-state image pickup device according to claim 20, wherein a tungsten metal is used for a connection portion of the first layer from the bottom of the wiring layer, and a copper metal is used for at least a part of an upper layer wiring thereof. Method.
コンより形成することを特徴とする請求項２０記載の固
体撮像素子の製造方法。23. The method according to claim 20, wherein the etching stopper layer is formed of silicon carbide.
コンより形成することを特徴とする請求項２０記載の固
体撮像素子の製造方法。24. The method according to claim 20, wherein the etching stopper layer is formed of silicon nitride.
の層に形成され、前記層間絶縁膜がｌｏｗ−ｋ材料より
なることを特徴とする請求項２０記載の固体撮像素子の
製造方法。25. The method of manufacturing a solid-state imaging device according to claim 20, wherein the wiring layer is formed in a plurality of layers via an interlayer insulating film, and the interlayer insulating film is made of a low-k material.
を生成する光電変換素子と前記光電変換素子で生成した
信号電荷を読み出す読み出し回路とを含む撮像部を設け
るとともに、前記半導体基板の上層に前記読み出し回路
の配線層を設けた固体撮像素子の製造方法において、 前記配線層の少なくとも一部に銅配線を用いるととも
に、前記銅配線の上面を覆う拡散防止膜と、前記銅配線
を配置する配線溝をエッチングストッパとなるハードマ
スク層を用いて形成し、 さらに前記拡散防止膜およびハードマスク層を少なくと
も前記光電変換素子の上部領域の所定範囲で除去する、 ことを特徴とする固体撮像素子の製造方法。26. The semiconductor substrate is provided with an image pickup section including a photoelectric conversion element for generating a signal charge according to the amount of received light and a readout circuit for reading out the signal charge generated by the photoelectric conversion element, and an upper layer of the semiconductor substrate. In the method for manufacturing a solid-state imaging device provided with a wiring layer of the readout circuit, a copper wiring is used for at least a part of the wiring layer, a diffusion prevention film covering an upper surface of the copper wiring, and a wiring for disposing the copper wiring. A groove is formed by using a hard mask layer serving as an etching stopper, and the diffusion prevention film and the hard mask layer are removed at least in a predetermined range of an upper region of the photoelectric conversion element. Method.
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| JP2005268748A (en) * | 2004-02-18 | 2005-09-29 | Nec Electronics Corp | Semiconductor device and method of manufacturing the same |
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