JP2003303042A - Key scan circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a key scan circuit which needs little electric current to work and performs stable operation. <P>SOLUTION: This circuit is the key scan circuit to detect ON and OFF status of a key switch connected to an intersection of each row and each column in which scan lines forming each of the rows and sense lines forming each of the columns are arranged in a matrix shape, a pull-up/down switch circuit is connected to each sense line, the status of the pull-up/down switch signal and the sense line status is returned and inputted, the pull-up/down switch circuit is switched to a pull-up element or a pull-down element and is operated according to the ON and OFF status of the key. <P>COPYRIGHT: (C)2004,JPO

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a key scan circuit for sequentially scanning key switches arranged in a matrix to detect a pressed state of a key. 2. Description of the Related Art FIG. 4 is a circuit diagram showing a conventional example for detecting the state of m × n keys. A push-type key switch is connected to the intersection of each row and each column in the key matrix 13 of m rows × n columns. The scan signal output circuit 23 sequentially outputs a scan signal to each row of the scan lines S0 to Sm. The sense circuit 14 reads the state of each column of the sense lines K0 to Kn, detects the ON / OFF state of the key based on the scan information signal 101 from the scan signal output circuit 23, and outputs the information as key data 100. I do.
The pull-down element 20 having the same configuration is for preventing the sense line from being in a floating state when the key is not pressed, and is constituted by a transistor having high resistance or high on-resistance. In this example, when the sense line is at a high level, it is in an active state, and when it is at a low level, it is in an inactive state. FIG. 5 is a timing chart showing the operation of the circuit shown in FIG. 4, in which scan signals are sequentially output to scan lines S0 to Sm. The scan signal is a positive logic pulse. Each of the sense lines K0 to Kn is set to a low level by a pull-down element unless any key arranged on each sense line is pressed. When any key is pressed, a signal of the scan line to which the key is connected appears. Therefore, if K0 also goes high at the timing when S0 goes high, it can be determined that the key at the intersection of S0 and K0 has been pressed. In this circuit, when a key is pressed, a through current flows from a scan signal output circuit through a pull-down element while a scan signal connected to the key is at a high level. FIG. 6 shows the relationship between the waveform of the x-th scan line and the y-th sense line whose key is pressed and the through current. It can be seen that when the key is pressed, the through current continues to flow while the scan signal is at the high level. To reduce this through current, it is conceivable to shorten the pulse width of the scan signal. However, before the scan signal is transmitted to the sense circuit via the key switch, there is a delay due to the time constant of the output impedance of the scan signal output circuit and the parasitic capacitance of the scan line / sense line. It was necessary to keep the above pulse width. Further, in order to reduce a through current, the pull-down element is constituted by an element which can be turned on / off such as a transistor. It is also conceivable to use a so-called precharge system in which the scan signal is turned to a high level after being turned off. However, in this method, when the key is not pressed, the low level is maintained only by the parasitic capacitance of the sense line, so that the method is susceptible to noise. Also, when the key starts to be pressed and released, the contact vibrates and turns on / off in a short time of about several milliseconds.
There is a problem that the state of the sense line becomes unstable due to so-called chattering that is repeatedly turned off, and a malfunction may occur. As described above, in the conventional key scan circuit, the pulse width of the scan signal cannot be reduced to a certain degree or more. Further, in the precharge method, chattering may occur and a malfunction may occur. SUMMARY OF THE INVENTION An object of the present invention is to provide a key scan circuit which solves the above-mentioned problems and consumes less current and operates stably. According to the present invention, in order to attain the above object, a scan line constituting each row and a sense line constituting each column are arranged in a matrix, and an intersection of each row and each column is provided. A key scan circuit for detecting an on / off state of a key switch connected to a switch, a pull-up / down switching circuit connected to each of the sense lines, a scan signal, a scan information signal, and a pull signal sequentially supplied to each scan line. A scan signal output circuit for generating an up / down switching signal; and a sense circuit for reading a state of the scan information signal and each of the sense lines and outputting an on / off state of a key. The circuit is provided with a pull-up element, a pull-down element, and a gate circuit,
The pull-up / down switching signal is input to one of the gate circuits and the state of the sense line is fed back to the other of the gate circuits, whereby the pull-up / down switching is performed according to the on / off state of the key switch. The circuit is operated by switching to a pull-up element or a pull-down element. An embodiment of the present invention will be described below. FIG. 1 is a circuit diagram of one embodiment of the present invention. Reference numeral 10 denotes a pull-up / down switching circuit having the same configuration, which includes an NMOS transistor 1 serving as a pull-down element, a PMOS transistor 2 serving as a pull-up element, and a NAND gate 3. Reference numeral 13 denotes a key matrix of m rows × n columns, and a push-type key switch is connected to an intersection of each row and each column.
Reference numeral 15 denotes a scan signal output circuit, which sequentially outputs a scan signal to each row of the scan lines S0 to Sm and outputs a pull-up / down switching signal 102 to each of the n pull-up / down switching circuits 10. . Reference numeral 14 denotes a sense circuit for reading the state of each column of the sense lines K0 to Kn. Based on the state of each sense line and the scan information signal 101 from the scan signal output circuit 15, a key ON / OFF state is detected. , And outputs the result as key data 100. FIG. 2 shows the timing of the signal output from the scan signal output circuit 15. Positive logic pulses are sequentially output to the scan lines S0 to Sm, and a period in which all scan lines are at a low level is provided between each pulse. The scan signal output circuit 15 outputs a pull-up / down switching signal 102 of a negative logic pulse from the scan signal output circuit 15 in synchronization with a period in which the scan line is at a low level, resets all the pull-up / down switching circuits, and Is in operation. A detailed operation will be described with reference to FIGS. First, a low-level pull-up / down switching signal 102 is output from the scan signal output circuit 15 in synchronization with a period in which all scan lines are at a low level. The NAND gate 3 to which the pull-up / down switching signal 102 is input
The output becomes high level, the NMOS transistor 1 is turned on, and the PMOS transistor 2 is turned off. As a result, the pull-up / down switching circuit 10 operates as a pull-down element. Next, the pull-up / down switching signal goes high, and one of the scan lines Sx (x is any integer from 0 to m) goes high. At this time, Sx and sense line Ky
If the key at the intersection of (y is any integer from 0 to n) is not pressed, the state of the sense line Ky does not change, and no through current flows through the NMOS transistor 1. If the key at the intersection of Sx and Ky is pressed, the scan signal is transmitted to the sense line Ky and goes high. When the feedback input from the sense line Ky, which is one input of the NAND gate 3, goes high, the other input, the pull-up / down switching signal, is already high,
The output of the NAND gate 3 becomes low level, the NMOS transistor 1 is turned off, the PMOS transistor 2 is turned on, and the pull-up / down switching circuit 10 operates as a pull-up element. After outputting the high level to the scan line Sx for a predetermined time, the scan signal output circuit 15 returns to the low level. At the same time, the pull-up / down switching signal 102
Then, a low level is output to switch the pull-up / down switching circuit 10 to a pull-down element to prepare for the next scan. FIG. 3 shows a waveform of a through current flowing from the scan signal output circuit 15 via the NMOS transistor 1. A period from when the voltage of the sense line Ky starts rising according to the time constant to when the voltage exceeds the input threshold voltage of the NAND gate 3 and the NMOS transistor 1 is turned off, and in preparation for the next scan
When the NMOS transistor 1 turns on again, the sense line Ky
It can be seen that a through current flows during a period in which the charge charged in the parasitic capacitance is discharged. During that period, no current flows because the NMOS transistor 1 is off. In addition, since the PMOS transistor 2 is turned on while the NMOS transistor 1 is turned off and the sense line Ky is held at the high level, the voltage level of the sense line Ky becomes unstable even if the key contacts are separated due to chattering. Nor. In the above example, a pulse of a positive logic is used as a scan signal. However, a pulse of a negative logic can be used. In this case, pull-up is performed so that the operation of the NMOS and PMOS transistors is opposite to that of the above example. / Down switching circuit may be configured. As described above, according to the present invention, the flow time of the through current is only a part during the scan period,
It is possible to reduce current consumption as compared with the conventional method in which current flows during the entire period. Further, after detecting that the key is pressed, the level of the scan signal is maintained so that chattering becomes strong.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of one embodiment of the present invention. FIG. 2 is a timing chart of a scan signal output circuit according to the present invention. FIG. 3 is a waveform diagram of a through current in the present invention. FIG. 4 is a circuit diagram of a conventional example. FIG. 5 is a timing chart of a scan signal output circuit in a conventional example. FIG. 6 is a waveform diagram of a through current in a conventional example. [Description of Signs] 1 NMOS transistor 2 PMOS transistor 3 NAND gate 10 Pull-up / down switching circuit 13 m row × n column key matrix 14 sense circuit 15 scan signal output circuit 20 pull-down element

Claims (1)

Claims 1. A scan line constituting each row and a sense line constituting each column are arranged in a matrix, and the on / off state of a key switch connected to the intersection of each row and each column is determined. In a key scan circuit for detecting, a pull-up / down switch circuit connected to each of the sense lines, and a scan signal output circuit for generating a scan signal, a scan information signal, and a pull-up / down switch signal sequentially supplied to each scan line And a sense circuit for reading the scan information signal and the state of each of the sense lines and outputting a key ON / OFF state. The pull-up / down switching circuit includes a pull-up element, a pull-down element, and a gate circuit. And the pull-up / down switching signal is input to one of the gate circuits, and the state of the sense line is input to the other of the gate circuits as a feedback input. A key scan circuit that switches the pull-up / down switching circuit to a pull-up element or a pull-down element in response to an on / off state of the key switch.