JP2003299090A - Image encoder and image encoding method, image recorder, and image transmitter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image encoder and an image encoding method in which errors are not accumulated, a VBV (video buffering verifier) control can be correctly performed for each picture in a split image encoder, and a VBV delay of a bit stream after being composited can be correctly determined, and to provide an image recorder and an image transmitter. <P>SOLUTION: A VBV buffer control operation section 171 determines the total of amounts of input bits into the VBV buffer controlled by each of split image encoders 120-1 through 120-4, and assigns the bits to the encoders 120-1 through 120-4 according to complexity of an image. Further, in the image encoder, a VBV buffer for operating a VBV delay of an integrated bit stream is provided. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, an HDTV.
Image coding apparatus and method for compressing and coding a moving image signal such as (High Definition TeleVision) signal, image recording apparatus for recording the coded signal, and image transmission apparatus for transmitting the coded signal Regarding

[0002]

2. Description of the Related Art MPEG2 is used as a moving image coding system.
The standard (ISO / IEC13818) is widespread. In this MPEG2, the concept of a profile that mainly defines the classification of functions (difference in syntax) and a level that defines the difference in the amount of processing such as image size is introduced, and the coding performance that can be supported is classified into classes. ing. For example, 720 x 480 pixels, 60 fields /
For the image of ITU-R601 of second, MP @ ML (Mai
n Profile at Main Level) is 1920 x 1080 pixels and M for HDTV images with 60 fields / sec.
P @ HL (Main Profile at High Level) is normally used.

An encoder of the MPEG2 standard uses a so-called VBV buffer, which is conceptually connected to the output of the encoder, in order to control the buffer state at the time of reception on the decoder side. (2), that is, by preventing the VBV buffer from overflowing or underflowing, the data amount of the bit stream is controlled on the encoder side. In order to perform accurate control, the bit amount input to the VBV buffer during one picture period (input bit amount), the VBV buffer occupation amount calculated by the input bit amount, and the like must be accurately obtained. As a method for accurately determining the input bit amount, there is, for example, the method disclosed in Japanese Patent Laid-Open No. 2000-152232. That is, the input bit amount is accurately obtained without accumulating errors according to a constant input bit rate given from the outside.

On the other hand, an apparatus for encoding a moving picture signal having a screen configuration with a large number of pixels such as an HDTV signal, for example, MP.
A device that executes @HL encoding requires very high-speed processing, and thus is difficult to realize and is a very expensive device. On the other hand, a device that executes MP @ ML encoding and decoding may be smaller and have a lower operation speed than a device of MP @ HL, and it is widely used because it has already been integrated into an LSI. Therefore, it can be used very inexpensively. Therefore, for example, in the moving picture coding or decoding apparatus disclosed in Japanese Patent Laid-Open No. 10-234043 or 2001-346201, a moving picture signal having a screen configuration with a large number of pixels, such as an HDTV signal, is generated. A method of performing MP @ HL encoding or decoding by dividing into a plurality of screens, encoding or decoding the signals of each divided screen with an MP @ ML device, and integrating the processing results is known. Has been.

As described above, one image signal is divided,
In an image encoding device that encodes using a plurality of encoders, a target generated code bit amount is appropriately allocated to each encoder in order to obtain high image quality. For example, in the moving picture coding apparatus described in Japanese Patent Laid-Open No. 10-234043, coding is controlled so that the code amount generated in each divided image area is uniform. Further, in Japanese Patent Laid-Open No. 2001-346201, the bit rate of each encoder is set according to the complexity of each divided image, and the total output bit rate of each encoder is
We are trying to match the target bitrate of the integrated bitstream.

[0006]

In an image coding apparatus having such a plurality of encoders, the bit rate and the target generated code bit amount assigned to each encoder change in picture units according to the complexity of the image. . for that reason,
In such an image coding device, when the plurality of encoders divide and control the amount of generated code bits by the VBV buffer, the Vs controlled by each encoder are controlled.
The input bit rate of the BV buffer and the input bit amount of each picture also change for each picture. In order to control the generated code bit amount by the VBV buffer, it is necessary to deal with the bit rate and the input bit amount which change in units of such a picture. However, in the normal encoding used independently, the bit rate does not change for each picture, so there is usually no encoder that can change the input bit amount to the VBV buffer for each picture. Therefore, in an image coding apparatus having a plurality of encoders, when the bit rate and the generated code bit amount of each encoder change for each picture, an appropriate VBV buffer control method is not known.

Further, in an image encoding device having a plurality of encoders, the image encoding device inputs VBV delay (VBV delay: picture image data of a picture into a VBV buffer) which is header data of a picture layer of an integrated bit stream. Time from when the data is extracted to the time when the data is extracted), and attaches it to the bitstream. The VBV delay can be calculated using the VBV buffer occupancy. In an image encoding device that divides an image and encodes it, it is necessary to know the VBV buffer occupation amount in a state before combining in order to control the amount of generated code bits performed by each encoder. On the other hand, VB attached to the bitstream after composition
To calculate the V delay, it is necessary to know the VBV buffer occupancy in the combined state. However, in an image encoding device that divides an image into a plurality of pieces and encodes the combined bitstreams of a plurality of divided images into one integrated bitstream, in each bitstream,
Since the value of a part of the header data changes, the code bit amount of the header data changes due to the combining, and the total bit amount of the bit stream after combining does not match the bit amount of each bit stream before combining. As a result, the values of the input bit amount and the VBV buffer occupation amount used for calculating the VBV delay are different before and after combination. Therefore, the VBV buffer for controlling the amount of generated code bits before combining cannot be used at the same time for calculating the VBV delay of the combined bitstream.

The present invention has been made in view of the above problems. A first object of the present invention is to divide a plurality of images into one image signal and encode the divided image in each divided image encoding device. Allows precise control by the VBV buffer while changing the input bit amount of the VBV buffer, and the VBV of the synthesized bit stream can be controlled.
An object of the present invention is to provide an image coding apparatus and an image coding method capable of accurately obtaining V delay. A second object of the present invention is to provide an image recording device using the above image encoding device and image encoding method. Also,
A third object of the present invention is to provide an image transmission device using the above image coding device and image coding method.

[0009]

In order to solve the above-mentioned problems, an image coding apparatus according to the first aspect of the present invention comprises a dividing means for dividing an input image signal and generating N divided image signals, The N divided image signals are encoded to generate N bit streams, and N having N VBV buffers.
Number of divided image coding means, integrating means for integrating the N bit streams into one bit stream, and total amount of input bits for each picture of the N bit streams in the N VBV buffers. And a control means for allocating the total amount of input bits for each picture to the N divided image coding means.

The control means is an average synthesis which is an average value per one picture of a change amount of the code bit amount in the integrated bitstream which occurs when the N bitstreams are integrated into one bitstream. A first combined change amount calculating means for calculating a change amount and a correction using the average combined change amount are performed, and in each of the N VBV buffers, the input bit amount of each picture of the N bit streams is calculated. First input bit amount calculation means for calculating the total amount, image complexity calculation means for calculating the image complexity of N divided images included in the N divided image signals, and a predetermined number of pictures before the encoding target picture Is calculated by the first input bit amount calculating means in accordance with the image complexity of the N divided images of the picture The total force of bits, and an input bit amount allocation means for allocating to each of said N divided image encoding means.

Each of the N divided image coding means is
According to the input bit amount allocated from the input bit amount allocating means, the VBV of each of the N VBV buffers
The buffer occupancy is obtained, and the coding bit rate of the N divided image signals is controlled based on the obtained VBV buffer occupancy.

In order to solve the above-mentioned problems, an image coding apparatus according to the second aspect of the present invention divides an input image signal to generate N divided image signals, and the N dividing means.
There are N divided image encoding means for encoding N divided image signals to generate N bit streams, an integrating means for integrating the N divided bit streams into one bit stream, and a VBV buffer. And a control means for calculating a delay time in the VBV buffer of each picture included in the integrated bit stream.

The control means calculates a combined change amount which is a change amount of the code bit amount of each picture in the integrated bit stream that occurs when the N bit streams are integrated into one bit stream. The second combined change amount calculating means, the sum of the code bit amounts generated by the coding of the N divided images of the current picture to be coded, and the combined change amount are added, and the combined bit stream of the integrated bit stream is added. The code bit amount adding means for obtaining the code bit amount for each picture, the second input bit amount calculating means for calculating the input bit amount for each picture of the integrated bit stream in the VBV buffer, and the code bit amount adding means. The obtained code bit amount for each picture of the integrated bit stream and the second input bit amount calculation means are obtained. An occupancy calculation means for calculating an occupancy of the integrated bitstream in the VBV buffer from the input bit amount of each picture to the VBV buffer, and the occupancy of the VBV buffer are combined. A delay time calculating means for calculating the delay time of the bit stream in the VBV buffer.

In order to solve the above-mentioned problems, the image coding method of the third aspect of the present invention divides an input image signal into N divided image signals and encodes the N divided image signals. An image coding method for generating N bitstreams and integrating the N bitstreams into one bitstream, wherein each of the N bitstreams is converted into each of N VBV buffers. Virtual buffering is performed to obtain the total amount of input bits for each picture in the N VBV buffers of the N bit streams, and the total amount of input bits is calculated as N
Allocating the divided image signals to N divided image encoding processes for encoding, and by the assigned input bit amount,
The occupancy of each of the N VBV buffers is calculated, and the coding bit rate of each of the N divided image signals is controlled based on the calculated occupancy of each of the N VBV buffers.

An average synthesis change amount which is an average value per picture of a change amount of the code bit amount in the integrated bit stream which occurs when the N bit streams are integrated into one bit stream; Correction is performed using the average combined change amount to obtain the total amount of input bits for each picture in the N VBV buffers, and the image complexity of N divided images of a picture that is a predetermined number of pictures before the encoding target picture Accordingly, the total amount of input bits is allocated to each of the N divided image coding processes.

In order to solve the above-mentioned problems, the image coding method of the fourth aspect of the present invention divides the input image signal into N divided image signals, and divides each of the N divided image signals. Encode and generate N bitstreams, said N
An image coding method for integrating a plurality of bitstreams into a single bitstream, wherein the combined bitstreams are virtually buffered in a VBV buffer, and the combined bitstreams are delayed in the VBV buffer. Calculate time.

The combined change amount, which is the change amount of the code bit amount of each picture in the integrated bit stream that occurs when the N bit streams are integrated into one bit stream, and the N of the picture to be encoded. The sum of the code bit amounts generated by the encoding of the divided images is added to obtain the code bit amount for each picture of the integrated bit stream, and the VBV buffer calculates the code bit amount of the integrated bit stream. Calculating an input bit amount for each picture, calculating an occupancy amount of the VBV buffer from a code bit amount for each picture of the integrated bit stream, and an input bit amount for each picture to the VBV buffer, From the VBV buffer occupancy, the delay in the VBV buffer of the integrated bitstream is delayed. To calculate the time.

In order to solve the above problems, the image recording apparatus of the fifth aspect of the present invention divides an input image signal,
Dividing means for generating N divided image signals, N divided image signals for encoding the N divided image signals to generate N bit streams, and N divided image coding means having N VBV buffers, A unit for integrating the N bit streams into one bit stream, a recording unit for recording the integrated bit stream on a recording medium, and a picture of the N bit streams in the N VBV buffers. An input bit amount allocation control means for obtaining a total input bit amount for each picture and allocating the total input bit amount for each picture to the N divided image encoding means; and a VBV buffer for integrated bit stream, VB for integrated bitstream of integrated bitstream
And a control unit including a delay time calculation control unit for calculating the delay time in the V buffer.

In order to solve the above-mentioned problems, the image transmission apparatus of the sixth aspect of the present invention divides an input image signal,
Dividing means for generating N divided image signals, N divided image signals for encoding the N divided image signals to generate N bit streams, and N divided image coding means having N VBV buffers, Integrating means for integrating the N bitstreams into one bitstream, transmitting means for transmitting the integrated bitstreams, and the N VBs
An input bit amount allocation control means for obtaining a total input bit amount for each picture of the N bit streams in the V buffer, and allocating the total input bit amount for each picture to the N divided image encoding means; And a control unit including a delay time calculation control unit for calculating a delay time in the integrated bitstream VBV buffer for the integrated bitstream.

According to the present invention described above, when one image signal is divided into a plurality of divided images for encoding, the bit stream of each divided image is virtually buffered by V.
The total amount of input bits for each picture in the BV buffer is
The calculation is performed without accumulating errors, and the divided images are allocated to the encoding process at an appropriate ratio. As a result, when the generated code bit amount of encoding of each divided image changes,
The value of the input bit amount of the VBV buffer can be changed in picture units. Further, since the total amount of input bits is calculated without accumulating errors, the VBV buffer can be correctly controlled even in an image encoding device having a plurality of divided image encoding devices. Further, since the value of the input bit amount of the VBV buffer is changed on a picture-by-picture basis in accordance with the change of the generated code bit amount of the encoding of each divided image, the VBV buffer unnecessarily overflows or underflows. What happens is greatly reduced.

Further, a VBV buffer for the integrated bit stream is provided, correction is performed by using the increase / decrease in the generated code bit amount due to image division and combination, and the delay time in the VBV buffer of the combined bit stream is accurately obtained.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of an image coding apparatus and an image coding method of the present invention, and an image recording apparatus and an image transmission apparatus using the same will be described below with reference to the accompanying drawings. First Embodiment In the image coding apparatus according to the present embodiment, a picture of a VBV buffer controlled by each divided image coding apparatus according to an externally set bit rate, for example, a bit rate written in a sequence header. The total amount of input bits for each is calculated by the control device, and is allocated to each divided image encoding device according to the image complexity of each divided image,
The occupied amount of each VBV buffer is obtained, and the coding bit rate of the divided image coding device is controlled. In order to accurately obtain the total input bit amount for each picture, an increase / decrease (synthesis change amount) in the generated code bit amount due to image division and synthesis is corrected. Further, the generated code bit amount of the remaining pictures in the GOP is assigned to each divided image coding device for each picture, and the coding bit rate of each divided image coding device is controlled.

[Configuration of Moving Image Encoding Device] FIG. 1 is a block diagram showing the configuration of a moving image encoding device 101 as one embodiment of the image encoding device of the present embodiment. The moving picture coding device 101 includes a screen dividing device 110, first to fourth
The divided image coding devices 120-1 to 120-4, the bitstream integration device 150, and the control device 170.

The structure of each section of the moving picture coding apparatus 101 will be described. The screen dividing device 110 divides each picture of the input moving image signal into four image signals for each predetermined image area, and each of the first to fourth divided image encoding devices 120-1 to 120-4. Output to. The moving picture signal input to the moving picture coding apparatus 101 is, as shown in FIG.
HDTV video signal, luminance signal is horizontal 1920 pixels x
Vertical 1080 lines, color difference signal is horizontal 960 pixels × vertical 108
It is an interlaced signal of 4: 2: 2 format with 0 line. The frame rate is 30 frames / second.

The screen division device 110 first converts a luminance signal into 1440 pixels in the horizontal direction and a color difference signal into 720 pixels in the horizontal direction by a filtering process. In the vertical direction, MP
Since it is determined by the EG2 standard that the interlaced image must be a multiple of 32 lines, dummy data of 8 lines is added below the image for both the luminance signal and the color difference signal to make 1088 lines. Then, the screen division device 110 divides the image whose size has been converted in this way into four areas A, B, C, and D as shown in FIG. It is output to the fourth divided image encoding devices 120-1 to 120-4. For example, the luminance signal is divided into four signals of horizontal 720 pixels × vertical 544 lines.

First to fourth divided image coding devices 120-
1-120-4 (divided image coding devices A, B, C, D)
Encodes the image signal of each divided area input,
Generate an MPEG2-MP @ ML bitstream,
Output to the integrated device 150. In the bitstream output from the divided image encoding device 120-i (i = 1 to 4), the independent values of the image size and the frame rate are MP.
Within the @ML range, but their associated sample rates (pixels per second) slightly exceed that range,
To be exact, it is not MP @ ML. Here, for convenience of explanation, the expression MP @ ML is used for convenience.

FIG. 3 shows a divided image coding device 120-1.
An example of the configuration of the divided image coding devices 120-i (i = 1 to 4) will be described by taking the (divided image coding device A) as an example. For example, the divided image coding device 120-i (i = 1 to 4)
Each of them has a processor 130-i (i = 1 to 4) and an output buffer 131-i (i = 1 to 4). In order to control the state of the input buffer when receiving on the decoder side,
The VBV buffers 132-i (i = 1 to 4), which are input buffers of the virtual decoder, are respectively provided to the encoder 13
0-i (i = 1 to 4) is connected conceptually.

The processors 130-i (i = 1 to 4) are
It is a general MPEG2-MP @ ML encoder,
The input image signal is encoded by MPEG2. Further, the generated bit stream is output to the output buffer 131-i (i = 1 to 4) on a picture-by-picture basis. The four encoders 130-i (i = 1 to 4) have a target value of the code bit amount instructed by the control device 170 and a VBV buffer 132-i for the input divided image signals.
Bit rate control is performed based on the occupancy of (i = 1 to 4), for example, variable rate coding is performed according to the complexity of each divided image of the previous picture, and MPEG2
-MP @ ML bit stream buffer 131-i
(I = 1 to 4). In addition, each encoder 130
-I (i = 1 to 4) is an amount relating to the complexity of the coded divided image, for example, the code bit amount Sa, n, Sb, n, Sc, n, Sd, n, the average generated for each picture. Quantization scale code (average value of quantizer scale code) Qa, n, Q
b, n, Qc, n, Qd, n are calculated and transferred to the control device 170.

The buffer 131-i (i = 1 to 4) temporarily stores the coded bit stream input from the encoder 130-i (i = 1 to 4), and the control unit 170.
It is output to the bitstream integration device 150 at the bit rate instructed by. Therefore, from the first to fourth divided image coding devices 120-1 to 120-4,
An MPEG2-MP @ ML bit stream is output. The format of the moving image signal input to the moving image encoding apparatus 101 is 4: 2: 2, but since it is converted to the 4: 2: 0 format in the divided image encoding apparatus 120-i,
The bit stream output from the divided image coding device 120-i is a bit stream of a moving image signal in the 4: 2: 0 format.

The bitstream integration device 150 has a first
~ Fourth divided image coding device 120-i (i = 1 to 4)
The four MPEG2-MP @ ML bit streams output from are combined to generate an MPEG2-MP @ HL bit stream. That is, four MPEG2-
One MPEG2-MP @ HL bit stream is obtained by decomposing the MP @ ML bit stream in slice units and reconstructing them into one bit stream. FIG. 4 is a diagram for explaining the arrangement of bit streams decomposed in slice units in the present embodiment.

The control device 170 controls the moving picture coding device 10.
Each component is controlled so that 1 performs a desired operation. The control device 170 includes a VBV buffer control calculation unit 171 and a control unit 172. The control unit 172 controls each component so that the moving image coding apparatus 101 performs a desired operation. The VBV buffer control calculation unit 171 is configured to operate the divided image coding device 1 according to the bit rate set from the outside.
VBV buffer 13 controlled by 20-i (i = 1 to 4)
2-i (i = 1 to 4), the total amount of input bits for each picture is accurately calculated, and each divided image coding device 120-i (i = 1 to 1) is calculated according to the image complexity of each divided image. Allocate to 4). As shown in FIGS. 1 and 3, from the VBV buffer control calculation unit 171, the input bit amounts IBa, n, IBb, n,
IBc, n and IBd, n are divided image coding devices 120, respectively.
-I (i = 1 to 4) is output. Each encoder 130
-I (i = 1 to 4) is the input bit amount IBa, n, IBb,
Depending on n, IBc, n and IBd, n, the VBV buffer 132-
The occupancy of i (i = 1 to 4) is obtained, and the bit rate of encoding is controlled.

The control device 170 determines, for example, the generated code bit amount of the remaining pictures in the GOP according to the image complexity of each divided image, and the divided image encoding device 1 for each picture.
20-i (i = 1 to 4) is assigned to indicate the target value of the generated code bit amount for each picture. Based on that
Each of the divided image coding devices 120-i (i = 1 to 4) performs variable rate coding on the input image signal. In order to accurately calculate the total input bit amount and the generated code bit amount of the remaining pictures in the GOP, the increase / decrease of the code bit amount (composition change amount) due to image division and combination is corrected. Next, the increase / decrease of the code bit amount (composition change amount) due to image division and combination will be described, and then the configuration and operation of the VBV buffer control calculation unit 171 will be described.

[Increase / decrease of code bit amount by combining] In the plurality of moving image encoding apparatuses 101 of the present embodiment, when one bit stream is combined from a plurality of bit streams, it is included in each stream in order to comply with the standard. Among the stored header data, there is header data whose value changes and needs to be rewritten. Due to this change, the bit amount of the bitstream after combining usually increases or decreases, and becomes different from the total bit amount of the plurality of bitstreams before combining. For example, as shown in FIG. 4, four MPEG2-MP
Decompose @ML bitstream in slice units and
Reconstructed into one bitstream and one MPEG2-
When synthesizing the MP @ HL bit stream, only one sequence, GOP, picture-level header data, extension data, and user data higher than the slice unit is required. Divided image coding apparatus 120-1 (divided image coding apparatus A)
Using only the bitstream output from the first to fourth divided image coding devices 120-2 to 120-4 (divided image coding devices B to D).

More specifically, the bitstream integration device 150 includes the first to fourth divided image coding devices 120-
1 to 120-4, after starting encoding, in each of the four bit streams output from the four divided image coding devices 120-1 to 120-4, until the first slice start code appears, Only the bit stream output from the first divided image coding device 120-1 (divided image coding device A) is output, and the second to fourth divided image coding devices 120-2 to 120-1 are output.
20-4 (divided image encoding devices B to D) discards the bitstream output.

As a result, after combining, the bit amount of header data etc. is reduced to 1/4. In this embodiment, in order to make the reduction amount the same for each picture type, the encoding such that the length of the header data is changed is not performed, and the sequence header is added for each GOP. Make the length of evenings constant.

In addition, four MPEG2-MP @ ML bit streams are decomposed into slices to obtain one MPE.
When synthesizing G2-MP @ HL bitstream,
In the combined MPEG2-MP @ HL bit stream header data, a parameter that needs to be rewritten, for example, the horizontal pixel size (HS) of the sequence layer
V: Horizontal Size Value), vertical pixel size (VS
V: Vertical Size Value), aspect ratio information (AR
I: Aspect Ratio Information), bit rate (BR
V: Bit Rate Value), VBV buffer size (VBS
V: VBV Buffer Size Value). For these parameters, the bitstream integration device 150
According to the instruction from the control unit 172 of the control device 170,
Alternatively, each divided image encoding device 120-i (i = 1 to 1
4) Rewrite each value of the bit stream output from 4) to the value calculated. Also, it is necessary to rewrite the VBV delay (VD: VBV delay) of the picture layer. This is calculated in the control device 170 by a method described later. It should be noted that the F code (F-code) representing the search range of the motion vector is rewritten to the same value in picture units in the first to fourth divided image coding devices 120-i (i = 1 to 4). Then, conversion and rewriting of the motion vector value are also required, which is a complicated process. Therefore, before encoding each picture, the control unit 17
2 to each divided image coding device 120-i (i = 1 to 4)
It is desirable to set the same value to.

The bitstream integrating device 150 decomposes the bitstream after the slice start code into slice units, and as shown in FIG. 4, A1, B1, A2, B2, ..., A34, B34, C.
1, D1, C2, D2, ..., C34, D34 are rearranged in this order and output. At this time, the value of the slice header indicating the vertical position information of the slice is rewritten to a correct value as necessary. In addition, a macroblock address increment (MBAI: macroblock address increment) that represents horizontal position information in the first macroblock of a slice.
nt) is also rewritten to the correct value if necessary. The bitstream integration device 150 outputs the bitstream of the slice D34 and then outputs the divided image coding device 120-i (i =
1 to 4) to a sequence end code (SEC: sequence)
If a ce end code) is output, one sequence end code is output from the bitstream integration device 150, and synthesis is completed or the next sequence header code (SHC: sequence header code) is input. If the sequence end code is not output, the next picture start code (PSC: picture start co
de), or until the sequence header attached to each GOP is output, the bitstream integration device 150
Repeats the same process.

By rewriting the header data such as the MBAI of the slice, the bit amount of the combined bit stream increases or decreases so much that it cannot be ignored compared to before the combining. In the header data that requires rewriting of the bitstream, the macroblock address increment (MBA) of the first macroblock of the slice, which is variable-length coded, is used.
I: macroblock address increment). MBAI
Represents horizontal position information in the first macroblock of the slice. When the screen is divided by vertical dividing lines as in the present embodiment, the image regions B and D in FIG. 2, that is, the image region B is included in the bit stream obtained by encoding the screen on the right side of the dividing line. Since the horizontal position of the first macroblock (left end) of the slices (B1, ..., B34 and D1, ..., D34) in D is not at the left end of the screen compared to before the synthesis, the first macro of all slices It is necessary to rewrite the MBAI of the block with a new value. Since MBAI is variable length header data,
The rewriting changes the MBAI bit amount.

Specifically, as shown in FIG. 4 and FIG. 5, before combining, the first macroblocks of all the slices of the image areas B and D are both at the left end of the screen, so MPEG
According to the two standards, the value of MBAI is 1. That is, MBA
When “1” is written in I and this bit stream having a bit length of 1 bit is combined, there are image areas A and C on the left side of the slices of image areas B and D, and in this embodiment, 720 There are image data of pixels, that is, 45 macroblocks. That is, in the slices of the image areas B and D, the horizontal position of the first macroblock is 46 macroblocks, and therefore the bitstream integration device 150 rewrites so that the value of MBAI represents 46. In MPEG2, "MBAI = 46"
"Macroblock Escape (MBESC: macroblock
escape) ”+“ MBAI = 13 ”. M
The BESC value is 33, and the MBAI value 13 represented by a fixed length of “0000 0001000” of 11 bits is “0000 1000” of 8 bits. That is, as shown in FIG. 5, the data MBAI having a length of 1 bit is rewritten to the data having a length of 19 bits. Furthermore, in order to obtain byte alignment, that is, to align the start code with the 8-bit position,
In this embodiment, the bitstream integration device 150
At the end of each slice data, 6-bit zero "000"
000 ", that is, as shown in FIG.
The data representing the horizontal position of the first macroblock in each slice of the image areas B and D is rewritten to 25-bit data. Therefore, in the image areas B and D, 1
This will increase (19 + 6) -1 = 24 bits per slice. As shown in FIG. 4, in the present embodiment, there are 68 such slices per picture in the image areas B and D, so 24 per picture.
X68 = 1632 bits increase. This is constant regardless of the picture type.

In the present embodiment, the bit amount of the header data above the slice layer in one bit stream is 888 bits for I pictures and 144 bits for P pictures and B pictures, respectively. In addition, the total bit amount of header data above the slice layer is 4 × 888 bits for I pictures and 4 × 144 bits for P and B pictures. As described above, after combining, the bit amount of the header data above the slice layer is reduced to 1/4. Therefore, the increase / decrease value of the generated code bit amount by combining is + 1632−3 × 888 = −1032 bits in the case of I picture, and + 1632−3 × 144 = in the case of P picture and B picture.
It becomes +1200 bits. Further, in this embodiment, GO
The so-called N value of P = 15 and M value = 3. Ie 1
There are one I picture, four P pictures, and ten B pictures in the GOP. Therefore, the increase / decrease value of the generated code bit amount for one GOP due to the bitstream synthesis is 14 × 1200-1032 = + 15768 bits, which is constant for each GOP.

As described above, four MPEG2-MP @ M
When the L bit stream is decomposed in slice units and one MPEG2-MP @ HL bit stream is combined, the generated code bit amount for one GOP is increased by 15768 bits after the combination before the combination. Therefore, the simple sum of the code bit amount of each divided image encoding device does not match the code bit amount of the combined bit stream. In the present embodiment, the increase / decrease amount of the generated code bit amount due to this combination (referred to as the combined change amount) is corrected.

[Structure of VBV Buffer Control Calculation Unit 171] FIG. 6 is a block diagram for explaining the structure of the VBV buffer control calculation unit 171. As shown in FIG. 6, VBV
The buffer control calculation unit 171 includes a combined change amount calculation unit 161.
An input bit amount calculation unit 162 and an image complexity calculation unit 1
63 and an input bit amount allocating unit 164. VBV
The buffer control calculation unit 171 uses the externally set bit rate to divide each divided image coding device 120-i (i = 1.
4), the total amount IBn (n is a picture number) of the input bit amount for each picture of the VBV buffer controlled by each is calculated, and each divided image coding device 120-i (i = 1) is appropriately calculated.
~ 4). For example, IBn is assigned according to the image complexity of each divided image. Therefore, the VBV buffer control calculation unit 171 determines that each divided image encoding device 120-
generated code amount data Sa, n output from i (i = 1 to 4),
Sb, n, Sc, n, Sd, n and average quantization scale code Qa, n,
The image complexity of each divided image is obtained from Qb, n, Qc, n and Qd, n. Each divided image coding device 120-i (i = 1 to 4)
Is the allocated input bit amount IBa, n, IBb, n, IBc,
From n and IBd, n, the occupied amount Ba, V, of each VBV buffer
Obtain n, Bb, n, Bc, n, Bd, n and control the bit rate of their own encoding.

As will be described later, the combined change amount calculation unit 161
An externally set bit rate R used when calculating the input bit amount for each picture (for example, the bit rate written in the sequence header in 400 bps units)
Is the bit rate of the integrated bit stream after combining. Therefore, the input bit amount for each picture obtained using the bit rate R is the input bit amount IBt for each picture of the integrated bit stream. As described above, by combining, the code bit amount of the integrated bitstream can be calculated by dividing each divided image coding device 120-i (i =
It is increased or decreased from the total code bit amount of the bit stream output from (1) to (4). Therefore, the VBV buffer 132- of each divided image encoding device 120-i (i = 1 to 4)
In order to accurately obtain the total amount IBn of the input bit amount for each picture to i (i = 1 to 4), it is necessary to correct the combined change amount ΔT which is the change amount of the code bit due to the above combination. The combined change amount calculation unit 161 calculates the combined change amount ΔT and inputs it to the input bit amount calculation unit 162. In the input bit amount calculation unit 162, the total input bit amount IBn for each picture obtained from the bit rate R. From, the combined change amount per picture is subtracted.

The amount to be obtained by the VBV buffer control calculation unit 171 is the total amount I of input bits per picture.
Since it is Bn, the combined change amount calculation unit 162 also calculates the combined change amount ΔTn per picture. As described above, in the present embodiment, the combination of 15 within one GOP period is performed.
768 bits increase. In addition, 1 GOP includes 15 pictures. The combination change amount calculation unit 162 evenly allocates the generated code bit amount, which is increased or decreased in one GOP by combining, to the pictures included in the GOP. Since the average value of the combined change amount per picture is not an integer, here, the combined change amount calculation unit 162 sets the consecutive 1
After outputting 051 bits, a value of 1052 bits is output to one picture, and this is repeated. This is repeated three times during one GOP period.

Input Bit Amount Calculation Unit 162 The input bit amount calculation unit 162 considers the combined change amount based on the bit rate R set from the outside, and the divided image coding device 120-i (i = 1 to 4). ), The total input bit amount IBn of each picture to the VBV buffer 132-i (i = 1 to 4) is calculated. First, the input bit amount IBt before correcting the combined change amount is obtained. The method disclosed in Japanese Unexamined Patent Application Publication No. 2000-152232 is used as the method for obtaining the value. Next, a brief description will be given. In MPEG, a real number operation is defined as an operation for controlling an input buffer of a virtual decoder, a so-called VBV buffer. For example, when the bit amount IBt input to the VBV buffer in one picture period is calculated according to the input bit rate R, the input bit amount is obtained as a real value.
However, in the process of actual calculation, the part exceeding the calculation precision of the real number calculation is truncated. However, if the part that exceeds the calculation precision of the real number calculation is truncated, the error gradually accumulates, and as a result, the actual input bit amount may gradually become smaller than the value obtained by the real number calculation. Occur. Therefore, for each number of pictures in which the theoretical value of the input bit amount is an integer value, the theoretically correct input bit amount (theoretical value in which the portion exceeding the calculation precision is not truncated) and the actually input bit amount (calculation precision The actual value obtained by truncating the part exceeding () is added to the actually input bit amount to cancel the error. In general, the input bit amount IBt for each picture according to the bit rate R is represented by the following expression (1).

[0046]

IBt = R / P (1) where IBt is the input bit amount for each picture, R is the input bit rate, and P is the picture rate.

In MPEG, the bit rate is 400 bp
It is set in units of s (the bit rate set from the outside), and in the present embodiment, the frame rate is 30.
The input bit amount IBt for each picture corresponding to the bit rate set in the unit of 400 bps is expressed by the following expression (2) as a real value.

[0048]

[Equation 2]   IBt = (R / 400) × 400/30 = (R / 400) × 40/3 ・ ・ ・ (2)

According to equation (2), the total input bit amount for every three pictures is 3 × IBt = R / 10. For example, when R = 10 Mbps, the total input bit amount for every three pictures is 3 × IBt = R / 10 = 1000.
000. The theoretical value of the input bit amount IBt for each picture is IBt = R / 10/3 = 3333333.33.
33333. 33333 was actually input
Since it is 3, 0.333333 ... Is discarded for each picture. This error gradually accumulates. The actual input bit amount for every 3 pictures is 3 × 333333 = 999.
Since it is 999, if the input bit amount calculation unit 162 adds 1 to the actual input bit amount for every 3 pictures, the correct bit amount is 1000000 and no error is accumulated.

Further, as described above, the VBV buffer 132 of each divided image coding device 120-i (i = 1 to 4) is used.
In order to accurately obtain the total amount IBn of the input bit amount for each picture to -i (i = 1 to 4), it is necessary to correct the average combined change amount ΔTn, which is the change in the code bit due to the combination per picture. Input bit amount calculation unit 162
Subtracts the average combined change amount ΔTn per picture input from the combined change amount calculation unit 161 from the input bit amount IBt for each picture obtained from the bit rate R, and outputs each divided image encoding device 120-i (i = 1 to 4) VBV
An accurate value of the total amount IBn of the input bit amount for each picture to the buffer 132-i (i = 1 to 4) is obtained.

Image Complexity Calculation Unit 163 The image complexity calculation unit 163 obtains the complexity of each divided image. As the method of obtaining the complexity of the image, for example, the generated code bit amount and the quantization scale code output from each divided image encoding device 120-i (i = 1 to 4) are used. In the image complexity calculation unit 163, for example, when the nth picture is to be encoded after the nth picture is to be encoded, each divided image encoding device 120-
From i (i = 1 to 4), the generated code bit amount Sa, n, Sb, n, Sc, n, Sd, n of each divided image of the n-th picture and the quantization scale code Qa, n, Qb, n, Qc, n, Qd, n are transferred, and the complexity Xa, n, Xb, n, Xc, n, Xd, n of each divided image of the n-th picture is obtained by the following equation (3): n +
It is used for encoding each divided image of the first or subsequent pictures.

[0052]

[Equation 3] Xa, n = Sa, n x Qa, n Xb, n = Sb, n x Qb, n Xc, n = Sc, n x Qc, n Xd, n = Sd, n × Qd, n (3)

Alternatively, as in the following formula (4), the ratios Ya, n, Yb, n, Yc, n corresponding to the complexity Xa, n, Xb, n, Xc, n, Xd, n of each divided image are obtained. , Yd, n. The image complexity calculation unit 163 calculates the image complexity Xa, n to Xd, n, or
The ratios Ya, n, Yb, n, Yc, n, Yd, n are transferred to the input bit amount allocating unit 164.

[0054]

[Equation 4]   Ya, n = Xa, n / (Xa, n + Xb, n + Xc, n + Xd, n)   Yb, n = Xb, n / (Xa, n + Xb, n + Xc, n + Xd, n)   Yc, n = Xc, n / (Xa, n + Xb, n + Xc, n + Xd, n)   Yd, n = Xd, n / (Xa, n + Xb, n + Xc, n + Xd, n) (4)

Input Bit Amount Allocation Unit 164 The input bit amount allocation unit 164 is an input bit amount calculation unit 16
The total input bit amount IBn of each corrected picture transferred from No. 2 is allocated to each divided image coding device 120-i (i = 1 to 4) according to the image complexity. For example,
When the n + 1-th picture is to be encoded after the n-th picture is encoded, that is, when the n + 1-th picture is the encoding target picture, for example, the complexity of each divided image of the n-th picture To use. That is, the input bit amount allocating unit 164 controls the image complexity calculating unit 163.
Then, the image complexity ratio Ya calculated by the equation (4),
Each divided image code is multiplied by n, Yb, n, Yc, n, Yd, n by the total amount IBn of the input bit amount for each picture transferred from the input bit amount calculation unit 162 as in the following Expression (5). Allocation amount IBa to the I / O device 120-i (i = 1 to 4),
n, IBb, n, IBc, n and IBd, n are obtained. Also, the calculated input bit amounts IBa, n, IBb, n, IBc, n, IBd, n
Are transferred to the divided image encoding device 120-i (i = 1 to 4).

[0056]

[Equation 5]  IBa, n = Ya, n × IBn  IBb, n = Yb, n × IBn  IBc, n = Yc, n × IBn  IBd, n = Yd, n × IBn (5)

[Operation of VBV Buffer Control Calculation Unit 171] FIG. 7 is a flowchart for explaining the operation of the VBV buffer control calculation unit 171. Step S71: The input bit amount calculation unit 162 calculates the input bit amount IBt for each picture according to the designated bit rate R by the formula (1). In order to cancel the accumulation of error, the necessary error amount is added to the total of the actual input bit amount for each given picture to obtain the correct input bit amount. For example, the specified bit rate R = 1
In the case of 0 Mbps, if one bit is added to the actual input bit amount for every three pictures, the correct bit amount can be obtained and no error is accumulated.

Step S72: Combined change amount calculation unit 161
Average combined change amount ΔTn per picture calculated in
Is input to the input bit amount calculation unit 162. The input bit amount calculator 162 subtracts ΔTn from the total input bit amount IBt for each picture to obtain the accurate VBV.
The total input bit amount IBn for each picture to the buffer 132-i (i = 1 to 4) is input to the input bit amount allocation unit 164.
Output to.

Step S73: Image complexity calculator 163
For example, the complexity of each divided image of the previous picture, which is obtained in step S1, is input to the input bit amount allocating unit 164, and the input bit amount allocating unit 164 inputs the corrected for each picture according to the image complexity. Allocation amount IB of total bit amount IBn to each divided image encoding device 120-i (i = 1 to 4)
a, n, IBb, n, IBc, n, IBd, n are calculated and output to each divided image coding device 120-i (i = 1 to 4).

Each divided image coding device 120-i (i = 1
4) are input bit amounts IBa, n, IBb, n, IBc, n, I allocated from the VBV buffer control calculation unit 171.
Using Bd, n, the divided image coding device 120-i (i =
1 to 4) VBV buffer 132-i (i = 1 to 1)
4) Occupied amounts Ba, n, Bb, n, Bc, n, Bd, n are calculated, and the generated code bit amount is controlled based on the calculated values.

Next, referring to FIGS. 3 and 8, from the input bit amounts IBa, n, IBb, n, IBc, n, IBd, n, the occupation amounts Ba, n, Bb, n, Bc of the VBV buffer are calculated. , n, Bd, n will be described. As shown in FIG. 3, the encoder 130-
i (i = 1 to 4) is the coded bit amount Sa, n, Sb, n, Sc, n, Sd, n generated by coding the input divided image signal.
Are output to the VBV buffer 132-i (i = 1 to 4), respectively. Also, the input bit amounts IBa, n, IBb, n, IBc, assigned from the VBV buffer control operation unit 171 are input.
n and IBd, n are VBV buffers 132-i (i = 1 to 1)
4) is input. Video encoding device 10 of the present embodiment
1, the generated code bit amount of the remaining pictures in the GOP is allocated to each divided image encoding device 120-i (i = 1 to 4) for each picture according to the complexity of the image, thereby performing each divided image encoding. The amount of code bits generated by the device 120-i (i = 1 to 4) for each picture changes depending on the complexity of the image. Correspondingly, the input bit amount IBa, n, I of the VBV buffer 132-i (i = 1 to 4)
Bb, n, IBc, n and IBd, n also change for each picture. When the code bit amount generated for each picture is large, the input bit rate of the VBV buffer is high and the input bit amount is large. When the code bit amount generated for each picture is small, the input bit rate of the VBV buffer is low and the input bit amount is small.

FIG. 8 shows the VBV buffer 1 conceptually connected to the divided image device 120-1 (divided image device A).
32-1 illustrates the transition of the VBV buffer occupancy Ba obtained as follows. Note that the same calculation can be performed in other divided image devices. Occupied amounts Ba, n, Bb, n, B of the VBV buffer 132-i (i = 1 to 4)
The initial values of c, n and Bd, n are, for example, VBV buffer size × 0.75. Encoder 130-i (i = 1
4), the generated code bit amount Sa, n, S for each picture
When b, n, Sc, n, and Sd, n are output, in the virtual decoder-side VBV buffer 132-i (i = 1 to 4),
The code bit amounts of Sa, n, Sb, n, Sc, n, and Sd, n are decoded so that each VBV buffer 132-i (i = 1 to 4)
Is extracted from. As shown in FIG. 8, the generated code bit amounts Sa, n, Sb, n, Sc, n, and Sd, n are determined by the respective VBV buffers 1.
It is subtracted from the buffer occupancy held by 32-i (i = 1 to 4).

Further, as shown in FIG. 8, for example, n-
From immediately after the encoding of the first picture (time tn-1) to immediately before the encoding of the nth picture (time tn), the encoded data of each divided image of the nth picture has predetermined bit rates Ra, Rb, Rc and Rd are used for each VBV buffer 132-i
(I = 1 to 4), and the VBV buffer 132-i is input.
It is added to the occupied amount of (i = 1 to 4). The code bit amount input from tn-1 to tn is the input bit amount IBa, n. In this way, the result of the VBV buffer occupancy illustrated in FIG. 8 is obtained by subtracting the generated code bit amount and adding the input bit amount. Video encoding device 10 of the present embodiment
1, each divided image coding device 120-i (i = 1
4), the generated code bit amount for each picture can be changed according to the complexity of the image. Therefore, the input bit amount IBa of the VBV buffer 132-i (i = 1 to 4),
It is also possible to change n, IBb, n, IBc, n, and IBd, n for each picture. As shown in FIG. 8, the coding bit rate of the n-3rd picture is low, and the input bit amount of the VBV buffer is also small. Pictures n-2, n-1,
Since the coding bit rate of the nth picture is higher than that of the n-3rd picture, the input bit amounts IBa, n-1, IBa, n-2, IBa, n of the VBV buffer are also relatively large. Since the coding bit rate of the (n + 1) th picture is higher, the input bit amount IBa, n + 1 of the VBV buffer is increased.
Is also getting bigger. Further, in the present embodiment, the generated code bit amount of the remaining pictures in the GOP is divided for each picture according to the complexity of the image.
Since 20-i (i = 1 to 4) is allocated, in FIG.
The sum of the code bit amount Sn generated by each picture in the GOP is the target bit amount assigned during the GOP period.
Further, the sum of the input bit amount IBn of each picture in 1 GOP is also the target bit amount assigned in the GOP period.

FIG. 9A shows the occupancy Bn of the entire four VBV buffers of the moving picture coding apparatus 101 according to this embodiment, and FIG. 9B shows each picture shown in FIG. The total amount I of input bits of the four VBV buffers
Bn is assigned to each divided image encoding device 120-i (i = 1 to 4)
And the obtained divided image coding devices 120-i.
(I = 1 to 4) VBV buffer 132-i (i = 1 to 1)
4) The buffer occupancy amounts Ba, n, Bb, n, Bc, n and Bd, n of 4) are illustrated. In each VBV buffer, the buffer is
To prevent overflow and underflow,
Each divided image coding device 120-i (i = 1 to 4) controls the coding bit rate and the generated code bit amount, and controls the buffer occupancy amount to an appropriate value between the maximum value and the minimum value.

Further, when the input bit amount is set from the outside in this way, a change in the generated code bit amount, which should correspond to the change, and a time lag occur, and so on. While the VBV buffer occupancy amount of the above is low, the VBV buffer occupancy amount of another divided image encoding device is likely to be high. At this time, when viewing all the VBV buffers of the divided image encoding device 120-i (i = 1 to 4) collectively, the occupancy changes near the middle of the VBV buffer, and preferable rate control is performed. It will be. However, individual VBV
Looking at the buffer, there is a bias in the occupancy. In other words, while there are encoders that are limited in the amount of bits that can be generated and cannot obtain sufficient image quality, there are encoders that are forced to generate more bits than necessary, so that the image quality is not appropriate. Has become.

In this case, Japanese Patent Laid-Open No. 2001-346201
As disclosed in the publication, first, the maximum value of the generated bit amount of each divided image encoding device 120-i (i = 1 to 4) is further limited to the maximum value for preventing underflow. There is. As a result, even when the image suddenly changes to a complicated image, the bit rate is controlled to gradually increase, so that the bit rate allocation for the second and subsequent images becomes extremely small and the image quality deteriorates. The harmful effect can be prevented.

Further, each divided image coding device 120-i
The VBV buffer occupancy of (i = 1 to 4) is managed by the intermediate value of the processing for each picture, and the VBV buffer occupancy is corrected so that the intermediate value becomes even. That is,
The buffer occupancy is shared between the plurality of VBV buffers. As a result, in the divided image coding apparatus 120-i (i = 1 to 4), the amount of bits that can be generated is limited so that sufficient image quality cannot be obtained, or the generation of more bits than necessary is forced. It is possible to avoid peculiar conditions such as.

The image coding apparatus according to the present embodiment enables control of the VBV buffer in the moving image coding apparatus 101 as a whole without error accumulation. In each divided image coding device 120-i (i = 1 to 4), VB
Input bit amount I of V buffer 132-i (i = 1 to 4)
It is possible to change Ba, IBb, IBc, and IBd in picture units. As a result, in the VBV buffers 132-i (i = 1 to 4) controlled by the respective divided image coding devices 120-i (i = 1 to 4), unnecessary overflow or underflow occurs. To prevent deterioration of image quality.

Second Embodiment In the image coding apparatus according to this embodiment, when the image data is coded, the VBV of the bit stream after the synthesis is combined.
A VBV buffer for determining the delay is provided, and the total amount of generated code bits for each picture and the input bit amount for each picture of the combined bitstream are calculated according to the bit rate set from the outside, and each of the combined bitstreams is calculated. Accurately determine the VBV delay of the picture. Figure 1
0 is a block diagram showing a configuration of a moving picture coding apparatus 201 as an embodiment of the image coding apparatus of the present embodiment. The moving picture coding device 201 includes a screen dividing device 110,
First to fourth divided image coding devices 120-1 to 120-
4, bitstream integration device 150 and control device 2
70. The configuration and operation of the moving picture coding apparatus 201 are basically the same as those of the moving picture coding apparatus 101 of the first embodiment.
Is the same as that of the control device 27 of the present embodiment.
0 has a VBV buffer for obtaining the VBV delay of the bitstream after synthesis, and the control device 27 is used for encoding.
0 obtains the VBV delay of each picture of the integrated bitstream and outputs it to the bitstream integration device 150. Hereinafter, with regard to the configuration and operation of the moving picture coding apparatus 201, redundant description will be appropriately omitted, and mainly the difference will be described.

In MPEG, when encoding the n-th picture, a virtual decoder is provided to control the status of the output buffer of the decoder on the receiving side, and the VBV buffer which is its input buffer serves as the encoder. Connected conceptually. The encoding bit rate of the encoder can be controlled based on the occupied amount of the VBV buffer. The encoded data of the nth picture is VBV
The time from the beginning of input to the buffer to the removal is called VBV delay (vbv_delay). That is, the VBV delay represents a waiting time until the encoded data of the nth picture is decoded in the VBV buffer. The VBV delay is written in the header data of each picture in the picture layer. The image compression encoding device is
It is possible to obtain the BV delay and add the VBV delay information to the bitstream.

When the input bit rate R to the VBV buffer is constant, the VBV delay is defined by the following equation (6).

[Formula 6] τn = 90000 · Bn / R (6) where τn is VBV in the VBV buffer of picture n
R represents a delay, R represents an input bit rate to the VBV buffer, and Bn represents an occupied amount of the VBV buffer immediately before the picture n is removed from the VBV buffer. VB
The V delay is expressed by the number of the system clock 90 kHz period.

As in the above equation (6), the VBV buffer occupation amount is not limited to the control of the generated code bit amount, but VBV buffer occupation amount.
Also used for delay calculation. In order to obtain the VBV delay by the calculation of the equation (6), it is necessary to accurately obtain the buffer occupation amount Bn. In particular, the calculation of the VBV delay added to the combined bitstream requires the VBV buffer occupation amount in the combined state. However, as described in detail in the first embodiment, in an image encoding device having a plurality of encoders, when synthesizing a bitstream of a plurality of divided images into one integrated bitstream, the Since the value of the header data of the part changes, the code bit amount of the header data changes due to the combining, and the total bit amount of the bit stream after combining does not match the bit amount of each bit stream before combining. As a result, the calculation of the input bit amount before combining is different from that after combining, and the buffer occupancy before combining is also different. Therefore, in order to accurately calculate the VBV delay of the bitstream after the synthesis by using, for example, the generated code bit amount before the synthesis, a change in the code bit amount of the synthesized bitstream by the synthesis is considered. Therefore, the amount of input bits to the VBV buffer must be corrected.

Image coding apparatus 201 according to the present embodiment
In, a VBV buffer for determining the VBV delay of the combined bitstream is provided, and the input bit amount for each picture of the combined bitstream according to an externally set bit rate R, for example, the bit rate written in the sequence header. Is calculated, and the total amount of generated code bits for each picture output by the divided image encoding device is calculated, the total amount of generated code bits is corrected in consideration of the amount of code bits generated by combining, and the combined bits are calculated. The VBV buffer occupancy of the stream and the VBV delay of each picture of the combined bitstream are accurately obtained.

In the moving picture coding device 201, the control device 270 controls each component so that the moving picture coding device 201 performs a desired operation. The control device 270 is V
A BV buffer control calculation unit 271 and a control unit 172 are included.
The control unit 172 controls each component so that the moving image encoding device 201 performs a desired operation. The VBV buffer control calculation unit 271 uses the divided image coding device 120-i (i
= 1 to 4), the generated code bit amount Sa, n, Sb, n, Sc, n, Sd, n for each picture and the combined change amount ΔT that is the increase / decrease amount of the code bit amount by combining are used. Then, the total amount Sn of code bit amounts generated by decoding the image data of the integrated bit stream by the virtual VBV buffer is obtained, and the total bit bit is transferred to the VBV buffer of the integrated bit stream according to the bit rate R set from the outside. Of the input bit amount IBn is calculated, and the VBV buffer occupancy amount Bn of the integrated bit stream is obtained from this. V
From the BV buffer occupancy Bn, the time until the integrated bitstream is decoded in the VBV buffer, that is, the so-called VBV delay, is obtained and output to the bitstream integration device 150. The bitstream integration device 150 attaches the VBV delay of each picture to the integrated bitstream. Next, the configuration and operation of the VBV buffer control calculation unit 271 will be described with reference to FIG.

FIG. 11 shows the VBV buffer control calculation unit 27.
It is a block diagram explaining the structure of 1. As shown in FIG. 11, the VBV buffer control calculation unit 271 includes a generated code bit amount addition unit 165, a combined change amount calculation unit 166, an input bit amount calculation unit 167, an occupancy calculation unit 168, and V.
It has a BV delay calculation unit 169.

In the generated code bit amount addition unit 165, which will be described later, the combined change amount calculation unit 166 generates the generated code bit amount Sa, n for each picture output from the divided image coding apparatus 120-i (i = 1 to 4). Sb, n, Sc,
The sum of n and Sd, n is the amount of generated code bits before combining,
To calculate the VBV buffer occupancy of the integrated bitstream, the generated code bit amount Sn for each picture after combining is calculated.
Ask for. As a result of the synthesis, the code bit amount of the integrated bit stream is the same as that of each divided image coding device 120-i before synthesis.
It increases or decreases from the total code bit amount of the bit stream output from (i = 1 to 4), and the two do not match. The generated code bit amount Sn for each picture after combining is the sum of the generated code bit amount before combining and the combined change amount ΔT. The combined change amount calculation unit 166 obtains the combined change amount ΔT of each picture. In the present embodiment, not the average of the combined change amount per picture but the combined change amount of each picture according to the picture type is output. That is, as described in the first embodiment, ΔT = −1 for I pictures.
032 for 032, P picture and B picture
Output 0 bit.

Generated Code Bit Amount Adder 165 In order to calculate the VBV buffer occupation amount, the generated code bit amount Sn for each picture is required. The generated code bit amount addition unit 165 obtains the generated code bit amount Sn for each picture after combining. First, the generated code bit amount addition unit 1
65 denotes each divided image encoding device 120-i (i = 1 to 1).
4) The generated code bit amounts Sa, n, Sb, n, Sc, n and Sd, n for each picture transferred from 4) are added. In the present embodiment, as an example, four values are simply summed. Then, the combined change amount output ΔT of each picture output from the combined change amount calculation unit 166 is added to the total. As a result, the generated code bit amount Sn for each picture after combining is obtained.

Input Bit Amount Calculation Unit 167 The input bit amount calculation unit 167 obtains the input bit amount IBn for each picture in the VBV buffer of the integrated bit stream based on the bit rate R set from the outside. The method of obtaining is similar to that of the first embodiment. That is, the difference between the theoretically correct input bit amount and the actually input bit amount is added to the actually input bit amount for each picture number for which the theoretical input bit amount is an integer value, and the error is canceled. To For example, if the picture rate P is 30 Hz and the bit rate R is 10 Mbps, 1
The theoretical value of the input bit amount IBn for each picture is IBn
= R / 10/3 = 3333333.33333333, the total input bit amount for each of 3 pictures is 3 × IBn = 3 ×
R / P = R / 10 = 1,000,000. The actually input bit amount per picture is 333333, and 0.333333 ... Is discarded. This error gradually accumulates. Therefore, the input bit amount calculation unit 16
In 2, if 1 is added to the actual input bit amount for every 3 pictures, the actually input bit amount is 3 × 33.
Since 3333 + 1 = 1,000,000, the correct bit amount can be obtained without accumulating errors. In this way, the input bit amount IBn for each picture is obtained.

Occupancy calculation section 168 Occupancy calculation section 168 calculates VB for each input picture.
Using the V buffer input bit amount IBn and the generated code bit amount Sn for each picture, V of the integrated bit stream
Obtain the occupied amount of the BV buffer. FIG. 12 illustrates changes in the VBV buffer occupancy of the integrated bitstream. In the occupancy calculation unit 168, for example, the initial value of the occupancy Bn of the VBV buffer is VBV buffer size × 0.75. When the generated code bit amount addition unit 165 outputs the generated code bit amount Sn for each picture, a virtual VBV buffer (here,
(Corresponding to the occupancy calculation unit 168), the code bit amount of Sn is extracted from the VBV buffer by decoding, that is, the generated code bit amount Sn is the buffer occupancy held by the VBV buffer. Drawn from. Further, for example, from immediately after the encoding of the (n-1) th picture (time tn-1) to immediately before the encoding of the nth picture (time tn).
Up to, the encoded data of each divided image of the n-th picture is
It is input to the VBV buffer at a predetermined bit rate R,
It is added to the occupied amount of the VBV buffer. The code bit amount input from tn-1 to tn is the input bit amount IBn.
Thus, for example, a change in the VBV buffer occupancy as shown in FIG. 12 can be obtained.

VBV Delay Calculator 169 The VBV delay calculator 169 calculates the V of the nth picture.
The VBV delay of the n-th picture of the integrated bitstream is calculated from the BV buffer occupation amount Bn and the bit rate R input to the VBV buffer. The VBV delay calculation unit 169 calculates the VBV delay using the equation (6). In Expression (6), Bn represents the occupied amount of the VBV buffer immediately before the picture n is removed from the VBV buffer. The input bit rate R to the VBV buffer has a specified value. In FIG. 12, Bn
And R are shown. Using Bn and R, the VBV delay τn of the nth picture is obtained.

Based on the VBV buffer occupation amount Bn, V
When the BV delay τn is obtained, the occupation amount Bn is obtained by removing the header data before the data of the picture n. That is, the bit amount of the header is required separately. The bit amount of the header is set to the divided image coding device 120-i (i
= 1 to 4), but in the present embodiment, the bit amount of the header data is encoded so as to be a fixed value for each picture type, and this is a known value. By doing so, the calculation of the VBV delay can be simplified.

[Operation of VBV Buffer Control Calculation Unit 271] FIG. 13 is a flowchart for explaining the operation of the VBV buffer control calculation unit 271. Step S81: The generated code bit amount addition unit 165 causes the generated code bit amount Sa, n, S for each picture transferred from each divided image encoding device 120-i (i = 1 to 4).
b, n, Sc, n and Sd, n are added. Step S82: Further, the combined change amount output ΔT of each picture output from the combined change amount calculation unit 166 is added to the sum of the generated code bit amounts Sa, n, Sb, n, Sc, n, Sd, n,
The generated code bit amount Sn is calculated for each picture after composition. The generated code bit amount Sn for each picture after composition is
It is input to the occupation amount calculation unit 168.

Step S83: On the other hand, the input bit amount calculator 167 calculates the input bit amount IBn for each picture according to the bit rate R by the formula (1) based on the specified bit rate R and obtains it. The obtained result is input to the occupation amount calculation unit 168.

Step S84: The occupation amount calculation unit 168
The VBV buffer input bit amount IBn for each picture and the generated code bit amount Sn for each picture are used to occupy the VBV buffer occupation amount B of the integrated bit stream B.
Find n. The obtained result is used as the VBV delay calculation unit 16
Output to 9.

Step S85: VBV delay calculation section 1
69 calculates the VBV delay of the nth picture of the integrated bitstream from the VBV buffer occupation amount Bn and the bit rate R input to the VBV buffer. The obtained VBV delay τn is transferred to the bitstream integration device 150, and the VBV delay value transferred at the time of combining the bitstreams is rewritten here.

According to the present embodiment, the VBV delay can be correctly obtained even in the image coding apparatus in which the generated code bit amount changes due to the combination of bit streams.

Third Embodiment FIG. 14 is a block diagram showing an example of the arrangement of an image recording apparatus 300 of this embodiment. The image recording device 300 has a moving image encoding device 301 and a recording means 302.
The basic configuration of the moving picture coding device 301 is the same as that of the moving picture coding devices 101 and 201 of the first and second embodiments. However, in the video encoding device 301, VBV
The buffer control calculation unit 371 includes both the VBV buffer control calculation units 171 and 271 in the moving picture coding apparatuses 101 and 201 of the first and second embodiments.

FIG. 15 shows the VBV buffer control calculation unit 37.
It is a schematic diagram explaining the composition of 1. As shown in FIG. 15, the VBV buffer control calculation unit 371 determines that the pre-combination VBV
It has a buffer operation unit 371a and a post-combination VBV buffer operation unit 371b. Pre-combination VBV buffer operation unit 37
1a has the same configuration and function as the VBV buffer control operation unit 171 in the first embodiment, that is, four bit streams transferred from the divided image encoding device 120-i (i = 1 to 4). Before combining, the pre-combination VBV buffer operation unit 371a considers the increase / decrease in the code bit amount due to combining, and based on the bit rate R designated from the outside, each divided image encoding device 120-i (i = 1 to 4) controls the total amount of input bits to the VBV buffer 132-i (i = 1 to 4) controlled by each of the divided image coding devices 120-i (depending on the image complexity of the divided image. i = 1 to
Allocate to 4). Each divided image coding device 120-i (i
= 1 to 4) is VBV from the allocated input bit amount.
The buffer occupancy is obtained, and the coding bit rate of each divided image coding device 120-i (i = 1 to 4) by the VBV buffer is controlled.

The post-combination VBV buffer operation unit 371b is
VBV buffer control calculation unit 27 in the second embodiment
It has the same configuration and function as those of 1. That is, the post-combination VBV buffer operation unit 371b considers the increase / decrease in the code bit amount due to the combination, and each divided image encoding device 120-i (i = 1).
4) is added to the transferred generated code bit amount to obtain the combined generated code bit amount. On the other hand, the input bit amount for each picture in the VBV buffer of the bit stream is calculated based on the bit rate R designated from the outside. Based on the generated code bit amount and input bit amount for each picture,
The VBV buffer occupation amount is calculated, and the VBV delay is calculated from the VBV buffer occupation amount. The post-combination VBV buffer operation unit 371b transfers the obtained VBV delay to the bitstream integration device 150. The bitstream integration device 150 writes the obtained VBV delay into the combined bitstream.

Detailed description of the other structure and operation of the moving picture coding apparatus 301 will be omitted. The recording means 302 is, for example, a video tape recording / reproducing device. In the moving picture coding apparatus 301, four bit streams are time-division multiplexed on a picture-by-picture basis to form one MPEG2-MP.
A bitstream of @HL is generated. The MPEG2-MP @ HL bit stream thus generated is multiplexed with an audio signal as necessary, and then recorded on the magnetic tape medium by the video tape recording / reproducing apparatus 300. Video data recording / reproducing device 3 for image data
When recording at 00, the tape advances at a constant speed, so the tape must be written at a constant bit rate. That is, the bit rate of the bit stream output from the moving image coding apparatus 301 must match the constant bit rate required when writing to the tape. In the moving picture coding apparatus 301, the target value of the code bit amount generated by the remaining pictures in the GOP is allocated to each divided picture coding apparatus 120-i (i = 1 to 4) for each picture, and Divided image coding device 12
By performing bit rate control by the VBV buffer while changing the input bit amount to the VBV buffer controlled by 0-i (i = 1 to 4) for each picture, an integrated bit stream having a target bit rate can be generated. .

According to this embodiment, the VBV buffer control can be correctly performed without error accumulation even in the image coding apparatus which divides an image and performs coding. Further, even if the allocated bit amount to each divided image encoding device changes in picture units, and thereby the generated code bit amount also changes, the value of the input bit amount of the VBV buffer changes in picture units accordingly. This makes it possible to significantly reduce the occurrence of unnecessary overflow or underflow in the VBV buffer controlled by each divided image encoding device, and prevent deterioration of image quality. Further, the VBV delay can be correctly obtained even with an encoding device in which the generated code bit amount changes due to the combination of bit streams. Further, when the output bit rate is required to be constant, it is possible to correct the increase or decrease in the generated code bit amount due to the division encoding, and it is possible to exactly match the required bit rate.

Fourth Embodiment FIG. 16 is a block diagram showing an example of the arrangement of an image transmission device 400 of this embodiment. The image transmission device 400 includes a moving image coding device 401 and a transmission unit 402.
The moving picture coding device 401 has the same configuration as the moving picture coding device 301 of the third embodiment. Omit detailed explanation. In the moving picture coding apparatus 401, four bit streams are time-division multiplexed in units of pictures and one M
A PEG2-MP @ HL bitstream is generated. The MPEG2-MP @ HL generated in this way
The bit stream of 1 is multiplexed with an audio signal as needed, and then transmitted from the transmission path via the transmission means 402. Since the transmission capacity of the transmission line is limited to a certain maximum value, this limit must not be exceeded when the transmission means 402 transmits image data. Furthermore, it is desirable that the coding bit rate be constant regardless of the complexity of the image. Therefore, it is desirable that the bit rate of the bit stream output from the moving image coding apparatus 401 is within a required constant bit rate and that the bit rate is substantially constant regardless of the complexity of the image. According to the description of the above-mentioned embodiment, the moving picture coding apparatus 401 can generate an integrated bit stream of a target bit rate.

This embodiment has the same effect as the third embodiment.

The present invention has been described above based on the preferred embodiments, but the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the gist of the present invention. Is. The image encoding device described in the present embodiment is an example, and various modifications of its configuration are possible. For example, in the embodiment of the present invention, regarding parameters that need to be rewritten as one MPEG2-MP @ HL bit stream such as horizontal pixel size, vertical pixel size, aspect ratio information, bit rate, VBV buffer size, and VBV delay. Is to be rewritten in the bitstream integration device 150. However, from the control unit 172, each divided image encoding device 1
Based on an instruction to 20-i (i = 1 to 4), a bit stream of a value to be rewritten in each divided image coding device 120-i (i = 1 to 4) is generated and output in advance, The bitstream integration device 150 may output the data as it is without any rewriting.

Although the input bit amount is allocated based on the generated code bit amount and the average quantization scale of the image one picture before, for example, the images two pictures before and three pictures before can be referred to. , A plurality of previous images may be referred to. by this,
This is useful because it eliminates the need for high-speed processing required for bit rate control for each picture.

Further, in the above-mentioned embodiment, the number of divisions of the image is four, but it may be a natural number other than four.
In addition, high definition TV (HDTV) signals and standard TV
(SDTV) signal type (eg NTSC signal, P
The AL signal) is not limited at all and may be applied to signals of any standard. Further, the present invention is not limited to the MPEG2 standard, and can be applied to other image compression coding techniques similar to this.

[0097]

According to the present invention, even when an image is divided and coded, the VBV buffer can be correctly controlled without error accumulation. Further, since the input bit amount of the VBV buffer can be changed in units of pictures, the occurrence of unnecessary overflow or underflow in the VBV buffer is significantly reduced, and deterioration of image quality can be prevented. Even if the generated code bit amount changes due to the combination of bit streams, the VBV delay can be correctly obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image coding apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining an HDTV video signal input to the image encoding device according to the first embodiment of the present invention and a dividing method thereof.

FIG. 3 is a block diagram showing an example of a configuration of a divided image coding device in the image coding device according to the first embodiment of the present invention.

[Fig. 4] Fig. 4 is a diagram for describing an arrangement of video streams decomposed in slice units in the image encoding device according to the first embodiment of the present invention.

FIG. 5 is a chart showing changes in the bit amount of header data of a bitstream due to synthesis in the image encoding device according to the first embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a VBV buffer control calculation unit in the image encoding device according to the first embodiment of the present invention.

FIG. 7 is a flowchart illustrating an operation of a VBV buffer control calculation unit in the image encoding device according to the first embodiment of the present invention.

FIG. 8 is a diagram exemplifying a change in the occupancy amount in the VBV buffer controlled by the divided image coding device in the image coding device according to the first embodiment of the present invention.

FIG. 9 illustrates the control of the generated code bit amount by allocating the total input bit amount of the VBV buffer to each divided image coding device in the image encoding device according to the first embodiment of the present invention. Here, (a) shows the occupancy of the VBV buffer of the entire image encoding device, and (b) shows the occupancy of the VBV buffer of each divided image encoding device.

FIG. 10 is a block diagram showing a configuration of an image encoding device according to a second embodiment of the present invention.

FIG. 11 is a block diagram illustrating a configuration of a VBV buffer control calculation unit in the image encoding device according to the second embodiment of the present invention.

FIG. 12 is a diagram illustrating a VBV delay calculation method in the image encoding device according to the second embodiment of the present invention.

FIG. 13 is a flowchart illustrating an operation of a VBV buffer control calculation unit in the image encoding device according to the second embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of an image recording apparatus according to a third embodiment of the present invention.

FIG. 15 is a block diagram illustrating a configuration of a VBV buffer control calculation unit in the image recording device according to the third embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration of an image transmission device according to a fourth embodiment of the present invention.

[Explanation of symbols]

101 ... Moving picture coding device, 110 ... Screen dividing device, 1
20 ... Divided image encoding device, 130 ... Encoder, 13
1 ... Output buffer, 132 ... VBV buffer, 150 ...
Bitstream integration device, 161 ... Combined change amount calculation unit, 162 ... Input bit amount calculation unit, 163 ... Image complexity calculation unit, 164 ... Input bit amount allocation unit, 165 ... Generated code bit amount addition unit, 166 ... Combined change Quantity calculator, 167
... Input bit amount calculation unit, 168 ... Occupancy amount calculation unit, 169
... VBV delay calculation unit, 170 ... Control device, 171 ...
VBV buffer control calculation unit, 172 ... Control unit, 201 ...
Moving picture coding device, 270 ... Control device, 271 ... VBV
Buffer control calculation unit, 300 ... Image recording device, 301 ...
Moving picture coding device, 302 ... Video tape recording / reproducing device, 370 ... Control device, 371 ... VBV buffer control calculation unit, 371a ... Pre-combination VBV buffer calculation unit, 371
b ... Post-combination VBV buffer operation unit, 400 ... Image transmission device, 401 ... Moving image coding device, 402 ... Transmission means, S
... Generated code bit amount, Q ... Quantization scale code, R ...
Bit rate, IB ... Input bit amount, B ... VBV buffer occupancy amount, τ ... VBV delay, ΔT ... Increase / decrease amount of code bit amount by combining.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hideyuki Narita             6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Soni             -Inside the corporation F-term (reference) 5C053 FA17 GB28 GB38 KA04                 5C059 KK13 KK22 LC00 MA00 PP04                       PP16 SS03 SS06 SS12 TA60                       TB03 TC10 TC16 TC41 TD06                       TD11 UA02 UA32 UA38                 5D044 AB07 DE03 DE12 GK08 HL11

Claims (17)

[Claims] 1. A dividing unit for dividing an input image signal to generate N divided image signals, encoding the N divided image signals to generate N bit streams, and N VBV ( video buffering veri
fier) N divided image coding means having a buffer, integrating means for integrating the N bitstreams into one bitstream, and each picture of the N bitstreams in the N VBV buffers And a control unit that allocates the total input bit amount for each picture to the N divided image encoding units. 2. The control means is an average value per one picture of a change amount of a code bit amount in the integrated bitstream which occurs when the N bitstreams are integrated into one bitstream. A first combined change amount calculating means for calculating an average combined change amount;
The image coding apparatus according to claim 1, further comprising: first input bit amount calculation means for obtaining a total input bit amount for each picture of the N bit streams in each of the V buffers. 3. The control means comprises: an image complexity calculating means for obtaining the image complexity of N divided images included in the N divided image signals; According to the image complexity of the N divided images calculated by the image complexity calculating means, the total amount of input bits calculated by the first input bit amount calculating means is converted into the N divided image codes. The image coding apparatus according to claim 2, further comprising input bit amount allocating means allocated to each of the coding means. 4. Each of the N divided image coding means comprises:
According to the input bit amount allocated from the input bit amount allocating means, the VBV of each of the N VBV buffers
The image encoding device according to claim 3, wherein a buffer occupancy amount is obtained, and the encoding bit rates of the N divided image signals are controlled based on the obtained VBV buffer occupancy amount. 5. A dividing means for dividing an input image signal to generate N divided image signals, and N divided image codes for encoding the N divided image signals to generate N bit streams. And a VBV buffer for integrating the N bitstreams into one bitstream, and a delay time in the VBV buffer for each picture included in the integrated bitstream. An image encoding device having a control means for performing an operation. 6. The control means sets a combined change amount that is a change amount of a code bit amount of each picture in the integrated bitstream, which occurs when the N bitstreams are integrated into one bitstream. A second combined change amount calculating means for calculating; a sum of code bit amounts generated by the coding of N divided images of the current picture; and the combined change amount, and the integrated bit The image coding apparatus according to claim 5, further comprising code bit amount adding means for obtaining a code bit amount for each picture of the stream. 7. The image coding apparatus according to claim 6, wherein said control means has second input bit amount calculation means for calculating an input bit amount for each picture of said integrated bit stream in said VBV buffer. 8. The control means, the code bit amount for each picture of the integrated bit stream obtained by the code bit amount adding means, and the VBV obtained by the second input bit amount calculating means. The image coding apparatus according to claim 7, further comprising: an occupancy calculation unit that calculates an occupancy of the integrated bitstream in the VBV buffer from an input bit amount of each picture to the buffer. 9. The control means determines the VB of the integrated bitstream from the occupied amount of the VBV buffer.
The image coding apparatus according to claim 8, further comprising delay time calculating means for calculating a delay time in the V buffer. 10. An input image signal is divided into N divided image signals, the N divided image signals are encoded to generate N bit streams, and the N bit streams are converted into 1 bit. An image coding method for integrating into a stream, wherein each of the N bit streams is virtually buffered in each of the N VBV buffers, and the N VBVs of the N bit streams are buffered. Find the total amount of input bits for each picture in the buffer,
The total amount of the input bit amount is allocated to the N divided image encoding processes for encoding the N divided image signals, and the occupancy amount of each of the N VBV buffers is determined by the assigned input bit amount. Obtained and obtained N VBs
An image encoding method for controlling an encoding bit rate of each of the N divided image signals based on an occupied amount of each V buffer. 11. An average combined change amount, which is an average value per one picture of a change amount of a code bit amount in the integrated bit stream that occurs when the N bit streams are integrated into one bit stream, 11. The image coding method according to claim 10, wherein correction is performed using the average combined change amount to obtain a total amount of input bits for each picture in the N VBV buffers. 12. A total amount of the input bit amount is assigned to each of the N divided image encoding processes according to the image complexity of N divided images of a picture that is a predetermined number of pictures before the encoding target picture. The image coding method according to claim 11, wherein the image coding is performed. 13. An input image signal is divided into N divided image signals, each of the N divided image signals is coded to generate N bit streams, and the N bit streams are divided into one piece. Image encoding method for integrating the integrated bitstream into a VBV buffer, and calculating a delay time of the integrated bitstream in the VBV buffer. Method. 14. A combined change amount, which is a change amount of code bit amount of each picture in the integrated bit stream that occurs when the N bit streams are integrated into one bit stream, and a coding target picture. And the sum of the code bit amounts generated by the encoding of the N divided images, the sum of the code bit amounts for each picture of the integrated bit stream is obtained, and the integrated bit amount is calculated in the VBV buffer. The input bit amount for each picture of the stream is calculated, and the occupation amount of the VBV buffer is calculated from the code bit amount for each picture of the integrated bit stream and the input bit amount for each picture to the VBV buffer. The image encoding method according to claim 13. 15. The image coding method according to claim 14, wherein a delay time in the VBV buffer of the integrated bit stream is calculated from an occupied amount of the VBV buffer. 16. A dividing means for dividing an input image signal to generate N divided image signals, encoding the N divided image signals to generate N bit streams, and N VBV buffers. N divided image encoding means having, N integrating means for integrating the N bit streams into one bit stream, recording means for recording the integrated bit stream on a recording medium, and N Input bit amount allocation control means for obtaining the total input bit amount for each picture of the N bit streams in the VBV buffer and assigning the total input bit amount for each picture to the N divided image encoding means. ,
An image recording apparatus having a VBV buffer for integrated bitstream, and a control unit including a delay time operation control unit for calculating a delay time in the VBV buffer for integrated bitstream of the integrated bitstream. 17. A dividing means for dividing an input image signal to generate N divided image signals, encoding the N divided image signals to generate N bit streams, and N VBV buffers. N divided image coding means having, N integrating means for integrating the N bitstreams into one bitstream, transmitting means for transmitting the integrated bitstreams, N VBV buffers In, the input bit amount allocation control means for obtaining the total input bit amount for each picture of the N bit streams, and allocating the total input bit amount for each picture to the N divided image encoding means,
An image transmission apparatus comprising: a VBV buffer for integrated bitstream; and control means including delay time operation control means for calculating a delay time of the integrated bitstream in the VBV buffer for integrated bitstream.