JP2003298058A5

JP2003298058A5 -

Info

Publication number: JP2003298058A5
Application number: JP2002094606A
Authority: JP
Filing date: 2002-03-29
Publication date: 2005-09-15

Claims

A gate electrode provided on the surface of the insulating base layer;
An insulating layer provided over the surface of the base layer and the surface of the gate electrode;
A semiconductor layer provided on a surface of the insulating layer;
A thin film transistor and having a respective different polarities channel region provided in the semiconductor layer located on a side surface of the gate electrode.

In the semiconductor layer on the upper surface of the gate electrode, two source regions or drain regions having different conductivity types are formed,
2. The thin film transistor according to claim 1, wherein a drain region or a source region is formed on a side opposite to the source region or the drain region with respect to the channel region in the semiconductor layer.

A gate electrode provided on the surface of the insulating base layer;
An insulating layer provided on the gate electrode;
A semiconductor layer provided on the insulating layer;
At least one source region or drain region provided on the gate electrode in the semiconductor layer;
A thin film transistor comprising:

A bottom gate type thin film transistor in which a gate electrode, a gate insulating film, and a semiconductor layer are sequentially laminated on the surface of an insulating base layer
A thin film transistor, wherein at least a source region or a drain region of the thin film transistor is provided in the semiconductor layer on the gate electrode.

5. The thin film transistor according to claim 1, wherein a channel region of the thin film transistor is provided in the semiconductor layer provided on the side wall of the gate electrode with the gate insulating film interposed therebetween. .

A circuit comprising two or more bottom-gate thin film transistors provided on the surface of an insulating base layer,
The bottom gate type thin film transistor is characterized in that at least a source region or a drain region of the two or more bottom gate type thin film transistors is provided on a gate insulating film on one gate electrode.

A bottom gate thin film transistor CMOS circuit configured by providing a plurality of bottom gate thin film transistors on the surface of an insulating base layer,
A CMOS circuit of a thin film transistor, wherein a source region or a drain region of each bottom gate thin film transistor constituting the CMOS circuit is provided on a gate insulating film provided on one gate electrode.

Forming a Gate electrode on the surface of the insulating base layer,
Forming a insulation layer on the surface of the surface and the gate electrode of the base layer,
Forming a semiconductor layer on the surface of the insulating layer;
Covering the semiconductor layer of the first region including the region on one side of the gate electrode with a first resist film;
Using the first resist film as a mask, a first impurity region is formed in the semiconductor layer by ion-implanting a first conductivity type impurity in the semiconductor layer substantially perpendicularly to the surface of the base layer. And a process of
Removing the first resist film;
Coating the semiconductor layer on the semiconductor layer in the second region, which is a region other than the first region, with a second resist film;
Using the second resist film as a mask, a second conductivity type impurity having a conductivity type opposite to the first conductivity type is ion-implanted into the semiconductor layer substantially perpendicularly to the surface of the base layer. Forming a second impurity region in the semiconductor layer;
And a step of removing the second resist film.

Forming a gate electrode on the surface of the insulating base layer; and
Forming an insulating layer over the surface of the base layer and the surface of the gate electrode; and
A semiconductor layer forming step of forming a semiconductor layer on the surface of the insulating layer;
Forming a source or drain region in the semiconductor layer located on the gate electrode;
A method of manufacturing a thin film transistor, comprising: