JP2003296191A - 汎用プロセッサおよび周辺装置のプロセッサとして動作可能な集積回路 - Google Patents

汎用プロセッサおよび周辺装置のプロセッサとして動作可能な集積回路

Info

Publication number
JP2003296191A
JP2003296191A JP2003058077A JP2003058077A JP2003296191A JP 2003296191 A JP2003296191 A JP 2003296191A JP 2003058077 A JP2003058077 A JP 2003058077A JP 2003058077 A JP2003058077 A JP 2003058077A JP 2003296191 A JP2003296191 A JP 2003296191A
Authority
JP
Japan
Prior art keywords
processor
cache
memory
integrated circuit
convertible
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2003058077A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003296191A5 (enExample
Inventor
Samuel Naffziger
サミュエル・ナフザイガー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2003296191A publication Critical patent/JP2003296191A/ja
Publication of JP2003296191A5 publication Critical patent/JP2003296191A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem
    • G06F2212/2515—Local memory within processor subsystem being configurable for different purposes, e.g. as cache or non-cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Microcomputers (AREA)
JP2003058077A 2002-03-06 2003-03-05 汎用プロセッサおよび周辺装置のプロセッサとして動作可能な集積回路 Withdrawn JP2003296191A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/092,668 2002-03-06
US10/092,668 US6789167B2 (en) 2002-03-06 2002-03-06 Method and apparatus for multi-core processor integrated circuit having functional elements configurable as core elements and as system device elements

Publications (2)

Publication Number Publication Date
JP2003296191A true JP2003296191A (ja) 2003-10-17
JP2003296191A5 JP2003296191A5 (enExample) 2006-04-06

Family

ID=29399134

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003058077A Withdrawn JP2003296191A (ja) 2002-03-06 2003-03-05 汎用プロセッサおよび周辺装置のプロセッサとして動作可能な集積回路

Country Status (2)

Country Link
US (1) US6789167B2 (enExample)
JP (1) JP2003296191A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007128175A (ja) * 2005-11-01 2007-05-24 Hitachi Ltd ストレージシステム
JP2008176699A (ja) * 2007-01-22 2008-07-31 Renesas Technology Corp マルチプロセッサ装置
EP2075705A1 (en) 2007-12-28 2009-07-01 Fujitsu Limited Cache memory having sector function

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7167952B2 (en) * 2003-09-17 2007-01-23 International Business Machines Corporation Method and system for performing a memory-mode write to cache
EP1794979B1 (en) * 2004-09-10 2017-04-12 Cavium, Inc. Selective replication of data structure
US7594081B2 (en) * 2004-09-10 2009-09-22 Cavium Networks, Inc. Direct access to low-latency memory
US7941585B2 (en) * 2004-09-10 2011-05-10 Cavium Networks, Inc. Local scratchpad and data caching system
US20060171244A1 (en) * 2005-02-03 2006-08-03 Yoshiyuki Ando Chip layout for multiple cpu core microprocessor
US20060230253A1 (en) * 2005-04-11 2006-10-12 Lucian Codrescu Unified non-partitioned register files for a digital signal processor operating in an interleaved multi-threaded environment
US7580821B2 (en) * 2005-08-10 2009-08-25 Nvidia Corporation Application programming interface for fluid simulations
US9015399B2 (en) 2007-08-20 2015-04-21 Convey Computer Multiple data channel memory module architecture
US8561037B2 (en) * 2007-08-29 2013-10-15 Convey Computer Compiler for generating an executable comprising instructions for a plurality of different instruction sets
US8156307B2 (en) * 2007-08-20 2012-04-10 Convey Computer Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set
US8122229B2 (en) * 2007-09-12 2012-02-21 Convey Computer Dispatch mechanism for dispatching instructions from a host processor to a co-processor
US8095735B2 (en) * 2008-08-05 2012-01-10 Convey Computer Memory interleave for heterogeneous computing
US9710384B2 (en) * 2008-01-04 2017-07-18 Micron Technology, Inc. Microprocessor architecture having alternative memory access paths
US8806506B2 (en) * 2008-09-30 2014-08-12 Ebay Inc. System and method for processing messages using a common interface platform supporting multiple pluggable data formats in a service-oriented pipeline architecture
US20100115233A1 (en) * 2008-10-31 2010-05-06 Convey Computer Dynamically-selectable vector register partitioning
US8205066B2 (en) * 2008-10-31 2012-06-19 Convey Computer Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor
KR101543581B1 (ko) * 2009-02-25 2015-08-11 삼성전자주식회사 시스템 온 칩 및 이를 포함하는 전자 시스템
US8423745B1 (en) 2009-11-16 2013-04-16 Convey Computer Systems and methods for mapping a neighborhood of data to general registers of a processing element
US10430190B2 (en) 2012-06-07 2019-10-01 Micron Technology, Inc. Systems and methods for selectively controlling multithreaded execution of executable code segments
US9430239B2 (en) 2013-03-12 2016-08-30 Qualcomm Incorporated Configurable multicore network processor
CN117940908B (zh) * 2021-08-31 2025-09-09 苹果公司 动态分配高速缓存存储器作为ram
US11704245B2 (en) 2021-08-31 2023-07-18 Apple Inc. Dynamic allocation of cache memory as RAM
US11893251B2 (en) 2021-08-31 2024-02-06 Apple Inc. Allocation of a buffer located in system memory into a cache memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6334173B1 (en) * 1997-11-17 2001-12-25 Hyundai Electronics Industries Co. Ltd. Combined cache with main memory and a control method thereof
US6070200A (en) * 1998-06-02 2000-05-30 Adaptec, Inc. Host adapter having paged data buffers for continuously transferring data between a system bus and a peripheral bus
US20030191876A1 (en) * 2000-02-03 2003-10-09 Fallon James J. Data storewidth accelerator
US20030046492A1 (en) * 2001-08-28 2003-03-06 International Business Machines Corporation, Armonk, New York Configurable memory array

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007128175A (ja) * 2005-11-01 2007-05-24 Hitachi Ltd ストレージシステム
JP2008176699A (ja) * 2007-01-22 2008-07-31 Renesas Technology Corp マルチプロセッサ装置
US8200878B2 (en) 2007-01-22 2012-06-12 Renesas Electronics Corporation Multi-processor device with groups of processors consisting of respective separate external bus interfaces
US8621127B2 (en) 2007-01-22 2013-12-31 Renesas Electronics Corporation Multi-processor device with groups of processors and respective separate external bus interfaces
US10372654B2 (en) 2007-01-22 2019-08-06 Renesas Electronics Corporation Multi-processor device
EP2075705A1 (en) 2007-12-28 2009-07-01 Fujitsu Limited Cache memory having sector function
US8583872B2 (en) 2007-12-28 2013-11-12 Fujitsu Limited Cache memory having sector function

Also Published As

Publication number Publication date
US20030172232A1 (en) 2003-09-11
US6789167B2 (en) 2004-09-07

Similar Documents

Publication Publication Date Title
JP2003296191A (ja) 汎用プロセッサおよび周辺装置のプロセッサとして動作可能な集積回路
US10942737B2 (en) Method, device and system for control signalling in a data path module of a data stream processing engine
US11243775B2 (en) System, apparatus and method for program order queue (POQ) to manage data dependencies in processor having multiple instruction queues
TWI810166B (zh) 用於異質計算之系統，方法，及設備
JP3509067B2 (ja) ストア命令転送方法およびプロセッサ
US9405552B2 (en) Method, device and system for controlling execution of an instruction sequence in a data stream accelerator
JP6507435B2 (ja) 命令エミュレーションプロセッサ、方法、およびシステム
JP5801372B2 (ja) システム管理モードのためのプロセッサにおける状態記憶の提供
JP4128956B2 (ja) デュアル・インライン・メモリモジュール・フォーマットにおいて一連のマルチアダプティブプロセッサを採用したクラスタ型コンピュータ用スイッチ／ネットワークアダプタポート
TWI433032B (zh) 具有階層式微碼儲存之多核心處理器
CN104221005B (zh) 用于从多线程发送请求至加速器的机制
EP3716055A1 (en) System, apparatus and method for symbolic store address generation for data-parallel processor
US20090037932A1 (en) Mechanism for broadcasting system management interrupts to other processors in a computer system
JP2000250810A (ja) ロード命令を実行する方法、プロセッサ、およびシステム
US20060064518A1 (en) Method and system for managing cache injection in a multiprocessor system
WO2017172240A1 (en) Processors, methods, systems, and instructions to fetch data to indicated cache level with guaranteed completion
US20190205061A1 (en) Processor, method, and system for reducing latency in accessing remote registers
CN111400986A (zh) 一种集成电路计算设备及计算处理系统
US11775336B2 (en) Apparatus and method for performance state matching between source and target processors based on interprocessor interrupts
US7552269B2 (en) Synchronizing a plurality of processors
US9830154B2 (en) Method, apparatus and system for data stream processing with a programmable accelerator
CN110941452A (zh) 一种配置方法、bios芯片和电子设备
KR102900878B1 (ko) 레지스터 데이터 소거
CN117762493A (zh) 一种支持dsp处理器的内核屏蔽非法地址的方法及装置

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060221

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060221

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20070313