JP2003281893A - Semiconductor memory device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which high integration is achieved and high speed operation can be performed. <P>SOLUTION: This semiconductor memory device has a plurality of main word lines MWL extending and crossing a memory block 80, and four sub-word lines SWL1-SWL4 arranged in each of the memory block and belonging to the plurality of main word lines MWL. A potential of one sub-word selection line (one line of PDCXZ1-4) made active in a selected block 80 is boosted by the prescribed period. This boosting operation is performed by turning off a switching element T1 supplying an active potential Vdd to a first terminal of a capacitor C1 for boosting and finishing charge to the capacitor C1 for boosting, and varying a potential of a second terminal of the capacitor C1 for boosting, by a boosting control circuit 140. Consequently, a potential of the first terminal of the capacitor C1 for boosting is boosted, and a line VLINE1 to be boosted connected to the first terminal is boosted. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as SRAM and electronic equipment using the same, and more particularly to a semiconductor memory device capable of satisfying both high integration and high speed and an electronic device using the same. Regarding equipment. More specifically, the present invention relates to an improvement for driving a sub word line at high speed.

[0002]

2. Description of the Related Art This type of semiconductor memory device has a problem of satisfying both high integration and high speed. When high integration is achieved, the number of memory cells in the vertical and horizontal directions increases.

When the number of memory cells in the horizontal direction is large, the number of memory cells directly connected to one word line is large, the load resistance and load capacitance of one word line are large, and the word line is operated at high speed. It becomes impossible to drive selectively.

Therefore, the memory cell array is horizontally divided into blocks and a plurality of main word lines are arranged across a plurality of memory blocks. Further, in each of the plurality of memory blocks, a plurality of sub word lines subordinate to each of the plurality of main word lines are arranged. In this way, the load capacitance of one main word line is reduced.

On the other hand, if the number of memory cells in the vertical direction increases, it becomes difficult to drive the sub-word lines at high speed. Here, a plurality of subword selection signal lines for selecting one of the plurality of subword lines in each memory block are arranged along the vertical direction. If the number of memory cells in the vertical direction is large, the vertical length of the plurality of subword selection signal lines becomes long, and the load resistance and load capacitance increase. Therefore, the waveforms of the subword selection signals supplied to the plurality of subword selection signal lines are blunted, which makes it difficult to drive the subword lines at high speed.

Therefore, an object of the present invention is to provide a semiconductor memory device which can satisfy both high integration and high speed, and an electronic apparatus using the same.

[0007]

A semiconductor memory device according to one aspect of the present invention is a memory cell array, a plurality of main word lines extending along a first direction in the memory cell array, and a plurality of main word lines. A row decoder for selecting one of the word lines, a plurality of memory blocks obtained by dividing the memory cell array in the first direction, and a plurality of main word lines arranged in each of the plurality of memory blocks. A plurality of sub-word lines respectively subordinate to
Each of the plurality of memory blocks is provided with a plurality of sub-word selection signal lines extending in a second direction intersecting the first direction, and one of the plurality of sub-word lines is selected. Multiple sub row decoders
One of the plurality of subword selection signal lines provided in any of the plurality of subrow decoders based on the logic of a plurality of predecode signal lines selecting one of the plurality of subword lines and a block selection signal line. A signal supply unit that supplies a plurality of subword selection signals that activate a book, and the subword selection signal that is connected to the signal supply unit and that is activated to the one subword selection signal line is set to an active potential. A boosted line which is set and boosted to a boosted potential higher than the active potential for a predetermined period, and a boosting capacitor having first and second terminals, the first terminal being connected to the boosted line , Provided in the middle of the wiring for supplying the active potential to the first terminal of the boosting capacitor, and when the precharge signal is active, And a switching element for precharging the boosting capacitor to the active potential, and turning off the switching element by making the precharge signal nonactive after the address signal changes, and at the same time A boosting control circuit for changing the potential to the second terminal to set the boosted line to the boosted potential.

According to one aspect of the present invention, an active potential subword selection signal is supplied from one end of one selected subword selection signal line through the signal supply unit.
As a result, the potential of the one sub-word selection signal line changes from the non-active potential to the active potential. However, due to the load capacitance and the load resistance of the sub-word selection signal line, especially the other end side of the sub-word selection signal line is charged. Or the discharge is delayed.

Therefore, in one aspect of the present invention, the potential of the active sub-word selection signal line is boosted for a predetermined period. Therefore, the boosted line connected to the signal supply unit is set to a boosted potential higher than the active potential after the address changes, and the potential of the active subword selection signal is boosted.

In this step-up operation, the step-up control circuit turns off the switching element for supplying the active potential to the first terminal of the step-up capacitor to finish charging the step-up capacitor, and at the same time, the step-up of the step-up capacitor Two
This is done by changing the potential to the terminals. As a result,
The potential of the first terminal of the boosting capacitor is boosted, and the boosted line connected to this first terminal is boosted.

Since the sub-word selection signal line is boosted in this manner, the time at which the original active potential is reached is hastened. As a result, even in a highly integrated semiconductor memory device, the sub-word line can be selectively driven at high speed, and high-speed data writing or data reading can be performed.

In one aspect of the present invention, the boost control circuit is configured to, based on an address transition signal that is active for the predetermined period, each time an address that selects a memory cell in the memory cell array is transitioned. The switching element can be turned off to finish charging the boosting capacitor.

According to one aspect of the present invention, it can be suitably implemented in a semiconductor memory device having the following configuration. That is, in each of the plurality of sub-word selection signal lines, the resistance value per unit length between the signal supply unit and the plurality of sub row decoders is greater than the resistance value per unit length in other regions. Is also set high. In this case, the load resistance of the sub-word selection signal line increases and the waveform rounding becomes noticeable. However, the boosting operation can reduce the waveform rounding and enable high-speed operation.

The following case is an example in which a part of the sub-word selection signal line has a high resistance. That is, a plurality of fuse elements for switching defective memory cells to redundant memory cells are arranged between the signal supply unit and the plurality of sub row decoders. In this case, each of the plurality of sub-word selection signal lines has a high resistance layer that is routed under the plurality of fuse elements.

In another aspect of the present invention, an electronic device including the semiconductor memory device described above is defined. By mounting a semiconductor memory device that is highly integrated and capable of operating at high speed, the performance of electronic devices is improved.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described below with reference to the drawings.

(Planar Layout of Semiconductor Memory Device) FIG.
FIG. 1 shows an example of a plane layout diagram of a semiconductor memory device according to an embodiment of the present invention. This semiconductor memory device is, for example, SRAM (Static Random Access Memory).
Is. In FIG. 1, the semiconductor memory device 10 includes, for example, four memory cell arrays 20A, 20B, 20C, 2
It has 0D. Each memory cell array 20A to 20D
Has a storage capacity of 4 Mbits, for example, and the total storage capacity is 4M × 4 = 16 Mbits. The present invention can also be applied to one having one memory cell array.

This semiconductor memory device 10 is, for example, 1 at the same time.
6-bit (2 bytes) data writing or data reading is possible. For example, for the two memory cell arrays 20A and 20B on the upper side of FIG.
Reading and writing are performed through the input / output terminal group 30 arranged along the line. Two memory cell arrays 20C on the lower side of FIG.
For example, lower 8 bits (lower byte) of data is read from or written to 20D through the input / output terminal group 32 arranged along the lower side 14 of the semiconductor memory device 10.

A 20-bit address signal (X, Y.Z) for writing or reading 16-bit data at the same time is provided with an address terminal group 3 arranged along the upper side 12 and the lower side 14 of the semiconductor memory device 10, respectively.
Input from 4. The X, Y, and Z address signals input from the address terminal group 34 are predecoded by the X predecoders 40 and 42, the Y predecoder 44, and the Z predecoder 46 arranged in the central region of the semiconductor memory device 10. It

The two memory cell arrays 20A and 20C arranged on the left side of the semiconductor memory device 10, for example, are
It is connected to a first power supply line 50 that is supplied with power from a power supply terminal 36. Similarly, for example, the two memory cell arrays 20B and 20D arranged on the right side of the semiconductor memory device 10 are
It is connected to the second power supply line 52 which is supplied with power from the power supply terminal 38. In the present embodiment, since the upper and lower 8-bit data are simultaneously written or read, two memory cell arrays connected to the same power supply line are not selected at the same time. Therefore, the memory cell array 20
A and 20D are simultaneously selected, or memory cell arrays 20B and 20C are simultaneously selected.

The terminal group arranged along the upper side 12 and the lower side 14 of the semiconductor memory device 10 includes command terminals and the like in addition to the above-mentioned terminal groups 30 to 38.

In each of the memory cell arrays 20A to 20D, the signal supply section 60 and the first fuse region 62 are provided on one side near the predecoders 40 to 46, and the input / output is provided on the other side near the upper side 12 or the lower side 14. The drive circuits 66 are arranged respectively. Further, the memory cell array 20A
The second fuse region 64 is arranged on each of the other sides of the power supply lines 50 to 52D on the other side.

Here, in the first fuse region 62, a plurality of fuse elements for switching defective memory cells to redundant memory cells are arranged. In the second fuse region 64, a plurality of fuse elements for cutting off the power supply to the defective memory cell are arranged.

(Details of Memory Cell Array) FIG. 2 is a schematic explanatory view showing a structure which the memory cell arrays 20A to 20D have in common. In FIG. 2, for example, the memory cell array 20C has a row decoder 70 at the center in the Y direction (first direction). Both sides of the row decoder 70 are divided into 16 parts, respectively, into 32 (M1 to M32) memory blocks 80 in total.

The storage capacity of one memory block 80 is
64 bits (Y direction) x 2048 bits (X direction) = 1
It is 28 kbits, and the total storage capacity of 32 memory blocks 80 is 4 Mbits. Between the two memory blocks 80, 80, both memory blocks 80, 8
A sub row decoder 90 commonly used for 0 is arranged. Therefore, a total of 16 sub row decoders 90 are provided. One sub row decoder 90 may be arranged for each one memory block 80.

In the memory cell array 20C, for example, 512 main word lines MWL1, MWL2, ... Are provided along the Y direction over almost the entire width in the Y direction.
In addition, two redundant main word lines are provided.

In each of the 32 memory blocks 80,
For example, four sub word lines SWL1 to SWL4 subordinate to each of the 512 main word lines MWL are provided, and there are a total of 2048 sub word lines SWL. Three
Each of the two memory blocks 80 further has a total of eight redundant subword lines subordinate to the two redundant main word lines.

Here, among the X, Y, and Z address signals described above, the X, Y address signal specifies an address in the X, Y direction shown in FIGS. 1 and 2, and the Z address signal is, for example, One is selected from the 32 memory blocks 80.

The row decoder 70 selects one of 512 main word lines MWL based on the X predecode signal. The sub row decoder 90 selects one of the four sub word lines SWL1 to SWL4 subordinate to the selected one main word line MWL in one memory book 80. These four sub word lines SWL1
The Z predecoded signal (block selection signal ZSB) and the lower 4 bits of the X predecoded signal are used to select 4 to 4.

In this way, one sub-word line SWL is selected, and the input / output drive circuit 66 selects a bit line pair for 8 bits based on the Y and Z predecode signals, whereby one memory block 80 is selected. It is possible to write or read 8-bit data. In this embodiment, four memory cell arrays 20A to 20B are provided.
Two of them are selected at the same time, and 8-bit data (total 16-bit data) can be simultaneously written or read in each one memory block 80 in the two memory cell arrays.

(Details of Sub Row Decoder) FIG.
The details of the sub row decoder 90 shared by the -1) th and nth memory block areas 80 are shown. Hereinafter, a common configuration for selecting the sub-word lines SWL1 to SWL4 in the (n-1) th and nth memory blocks 80 will be described.

The sub row decoder 90 has four sub word selection signal lines (X & Z predecode signal lines) PD.
CXZ1 to 4 extend along the X direction (second direction). These four sub word selection signal lines PDCXZ1 to
A high active subword selection signal is supplied to each of the four. Each sub word selection signal is shown in FIG.
As shown in FIG. 5, the block address signal ZSB (low active) obtained by predecoding the Z address signal by the Z predecoder 46 and the X address signal by the X predecoders 40,
2 is generated based on the lower 4 bits of X predecode signals PDCX1 to 4 (low active) predecoded in 2. Further, in the sub row decoder 90, the block selection signal line ZSB described above extends along the X direction,
The input / output drive circuit 66 has been reached. This block selection signal line ZSB drives the sense amplifier in the input / output drive circuit 66 or Y driver (bit line drive driver).
It is used for driving.

512 main word lines MWL1 to MWL51
In order to select one sub-word line SWL from two and four sub-word selection signal lines PDCXZ1 to PDCXZ4, 5
Twelve switch groups 100 are provided.

Each switch group 100 has four transfer gates 102, 104, 1 as shown in FIG.
06,108. Transfer gate 102-
Based on the logic of the main word line MWL and the inverted main word line / MWL, each of 108 connects / disconnects one of the four subword selection signal lines PDCXZ and the corresponding one subword line SWL. Switch the connection. In this embodiment, a low active main word selection signal is supplied to the main word line MWL.

For example, the potential of the main word line MWL1 is LOW and the potential of the sub word selection signal line PDCXZ1 is H.
If the potentials of the IGH and the other subword selection signal lines PDCXZ2 to 4 are LOW, the potential of the subword line SWL1 subordinate to the main word line MWL1 becomes HIGH. As a result, it becomes possible to write or read data to or from the memory cell 110 connected to the sub word line SWL1.

(Necessity of High Speed Driving of Sub-Word Lines) As the memory becomes highly integrated, the number of memory cells in the X direction in FIG. 3 increases. Therefore, the lengths of the four sub-word selection signal lines PDCXZ1 to 4 shown in FIG. 3 in the X direction become long, and the load resistance and the load capacitance become large. Therefore, the waveform of the subword selection signal supplied to the subword selection signal line PDCXZ is blunted, and it becomes difficult to drive the subword line SWL at high speed. This is the first reason.

The second reason is that the first fuse region 62 shown in FIGS. 1 and 3 exists between the signal supply unit 60 and the sub row decoder 90.

In this embodiment, the sub word selection signal line P
DCXZ1 to 4 are formed of, for example, a metal second layer (aluminum layer). However, the first fuse region 6
Since the second fuse element is formed in the same layer as the metal second layer, in this region, the sub-word selection signal lines PDCXZ1 to 4 are formed by a layer bypassing the first fuse region 62, for example, a polysilicon layer. is doing. As a result of this bypass, the length of the bypass layer is increased and the material of the bypass layer itself has a higher resistance than the metal second layer. Therefore, as shown in FIG. 3, the sub-word selection signal lines PDCXZ1 to PDCXZ1 to By bypassing the fuse region 62, it has a high resistance R. For this reason, the sub word selection signal line PDCX
The load resistance of Z1 to Z4 is further increasing. (Booster circuit for sub-word line) As shown in FIG. 5, the booster circuit 130, the booster control circuit 140, the address transition detection circuit 150, the data transition detection circuit 170, and the auto power-down signal generation circuit are shared by each block. 1
80 and a write enable signal transition detection circuit 190 are provided.

Here, the booster circuit 130 comprises a boosting capacitor C1 and a PMOS transistor T1. The PMOS transistor T1 is a switching element connected between the power supply line (supply source of the active potential Vdd) and the positive terminal of the boosting capacitor C1. The precharge control signal φ2 is supplied to the gate of the PMOS transistor T1 from the boost control circuit (for example, NOR gate) 140, and the PMOS transistor T1 is turned on and off. When the PMOS transistor T1 is turned on, the power supply voltage Vdd can be supplied to the boosting capacitor C1. The boost drive signal φ1 from the boost control circuit 140 is supplied to the negative terminal of the boost capacitor C1. When the potential of the boosting drive signal φ1 changes from the low potential to the power supply potential, the boosted line connected to the positive terminal thereof can be boosted. In the present embodiment, the logics of the signals φ1 and φ2 are set to be the same.

First, various signals input to the boost control circuit 140 for driving and controlling the boost circuit 130 will be described.

The row address signal ADD is input to the address transition detection circuit 150. Address transition detection circuit 15
0 generates a pulse by detecting a change in the row address signal ADD, and generates a pulse signal φ3 of logic "H" only when the row address signal ADD changes. This pulse signal φ
3 is input to the boost control circuit 140.

Write data IN from the outside is input to the data input terminal DIN. A data transition detection circuit 170 that detects this change in the data IN and generates a pulse.
Generates a pulse signal φ4. This pulse signal φ4
Is also input to the boost control circuit 140.

Write enable signal transition detection circuit 190
Detects the fall of the write enable signal / WE and outputs a pulse WEP to the boost control circuit 140 and the auto power down signal generation circuit 180.

Automatic power-down signal generation circuit 180
In response to the pulse signals φ3, φ4 and the pulse WEP, a timer circuit (not shown) generates an auto power down signal φ5. This auto power down signal φ
When 5 is at L level, the circuit of this embodiment operates. The auto power down signal φ5 is input to the boost control circuit 140.

The boosting control circuit 140, to which the pulses φ3, φ4, φ5 and WEP are input, receives the boosting drive signal φ supplied to the boosting capacitor C1 based on these pulses.
1 and a precharge control signal φ2 for controlling the PMOS transistor T1.

The boost control circuit 140 has a pulse φ3.
It can be composed of a NOR gate circuit to which φ4, φ5 and WEP are input. The boosting capacitor C1 is formed by an NMOS gate.

The four NAND gates NAND functioning as the block selection decoder shown in FIG. 5 are arranged in the signal supply unit 60 shown in FIG. The positive power supplies of these four NAND gates NAND are connected to the boosted line VLINE1 boosted by the boosting capacitor C1, and the negative power supplies are connected to the ground. This boosted line VLINE1 is
It is shared by each memory block 80 shown in FIG.

In this embodiment, the load capacitance connected to the boosting capacitor C1 is the boosted line V which is the power supply line of the NAND gate AND for the block selection decoder.
LINE1, first to fourth sub-word selection signal lines PDCXZ1 which are output lines of the block selection decoder AND
~ PDCXZ4 and the sum of the load capacities of one sub word line SWL in one selected memory block 80.

Next, the operation of this embodiment will be described with reference to FIGS.
Using. First, the row address signal ADD is input to the address transition detection circuit 150, and the column address is input to a column selection decoder (not shown). Here, a case where both the row address signal ADD and the write data IN change in the write cycle will be described as an example. The write enable signal / WE changes from logic "H" to "L" at the timing of time t. When this change is detected, the write enable signal transition detection circuit 190 detects a predetermined time t.
During 1, a logic "H" pulse WEP is generated. The row address signal ADD also changes, the change is detected, and the output of the address transition detection circuit 150 is output for a predetermined period t2.
A pulse signal φ3 of logic "H" is generated. Further, the input data IN also changes, and the output of the data transition detection circuit 170 that detects the change generates a pulse signal φ4 of logic "H" for a predetermined time t3.

The output of the auto power-down signal generation circuit 180 to which the above signals φ3 and φ4 are input, generates a signal φ5 which becomes logic "L" for a predetermined period t4. After that, the WEP signals, the signals φ3, φ4, and φ5 are input to the NOR gate in the boost control circuit 140, and the pulses φ1 and φ2 (φ1 = φ2) of logic “H” are generated during the period t4.

When the precharge control signal φ2 is in the precharge state of logic "L", the boosting capacitor C1 is used.
Are charged so that a potential difference of the power supply voltage Vdd occurs.
After that, the signal φ2 changes to the logic "H", the precharge transistor T1 is turned off, and the precharge is completed. Since φ1 = φ2 in the present embodiment, at the same time, the boost drive signal φ1 rises from the logic “L” to the logic “H”, and the boost operation is started. During this boosting operation, the charging voltage of the boosting capacitor C1 is added, so that the boosted line VLINE1 is pulled up to the boosted potential Vpp of the power supply voltage Vdd + ΔV. At this time, a block selection decoder (nand gate) NA of a certain block
The block selection signal ZSB that becomes active is supplied to ND.
And any one signal PDCX1 to be active
4 has been entered. Therefore, the four sub-word selection signal lines PDCZ1 to PDCZ1 to 4 which are the outputs of the NAND gate NAND.
Is the boosted potential Vpp (Vpp of the boosted line VLINE1).
dd + ΔV).

This boosted potential is supplied to the selected sub-word line SWL via any one of the transfer gates 102 to 108 shown in FIG. 4, and can boost one selected sub-word line. it can.

After this, the auto power down signal φ5 is
After the time t4 has elapsed, the logic level becomes "H". In response to this, the outputs φ1 and φ2 of the boost control circuit (NOR gate) 140 shown in FIG. 5 both become logic LOW, and the boost operation ends, and at the same time, the boost capacitor C1 and the boosted line V
LINE1 is precharged to the potential Vdd again.

Although the boosting operation in the write cycle has been described above, the address signal A in the read cycle as well.
Since the pulse φ3 is generated by detecting the change in DD, the boosting operation is performed as in the write cycle. Further, it is possible that the address signal ADD does not change when the write cycle shifts to the read cycle. In this case, the write enable signal transition detection circuit 19 shown in FIG.
0 detects the rising edge of the / WE signal and generates the WEP signal, which is the auto power down signal generation circuit 180.
If the configuration for inputting is adopted, the boosting operation is performed even when the read cycle is entered.

Even in this read cycle, as in the boosting operation in the write cycle, in one memory cell array block 200 selected by the block selection signal ZSB, the predecode signal line PDC of the X lower address is selected.
Only one sub word line SWL selected by X1 to X4 can be boosted.

(Description of Electronic Equipment) This semiconductor memory device 1
0 can be used, for example, in electronic devices such as mobile devices. FIG. 7 is a block diagram of a part of a mobile phone system. SRAM is the semiconductor memory device 1 described above.
It is 0. The CPU 200, SRAM 10, and flash memory 210 are connected to each other by a bus line. Also, the CPU 200 and the SRAM 1
0, 210 for flash memory, address signals A _{0 to} A
₁₉ , bus lines for transmitting data signals I / O _{0 to} I / O ₁₅ and commands are connected to each other. Further, the CPU 200 uses the bus line to operate the keyboard 2
20 and the LCD driver 230. L
The CD driver 230 is connected to the liquid crystal display section 240 by a bus line. CPU200, SRAM10
The flash memory 210 constitutes a memory system.

FIG. 8 is a perspective view of a mobile phone 300 including the system of the mobile phone shown in FIG. Mobile phone 3
00 is the keyboard 220 and the liquid crystal display unit 24 described above.
In addition to 0, a main body section 330 including a receiver section 310 and an antenna section 320, and a lid section 350 including a transmitter section 340 are provided.

The present invention is not limited to the above-described embodiment, but various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied only to SRAMs, but can be applied to all other semiconductor memory devices that select memory cells using main word lines and sub word lines.

[Brief description of drawings]

FIG. 1 is a plan layout diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a schematic explanatory diagram showing the details of one memory cell array in FIG.

3 is a circuit diagram showing details of a sub row decoder in FIG.

FIG. 4 is a circuit diagram showing a relationship among a switch group, a main word line, a sub word line, and a sub word selection signal line in FIG.

5 is a block diagram showing a booster circuit for a sub word line shown in FIG.

FIG. 6 is a timing chart for explaining the boosting operation according to the embodiment of the present invention.

7 is a block diagram of a part of a system of a mobile phone using the semiconductor memory device shown in FIG.

8 is an external perspective view of a mobile phone using the system shown in FIG.

[Explanation of symbols]

10 Semiconductor memory device (SRAM) 20A to 20D memory cell array 30, 32 Input / output terminal group 34 Address terminal group 36, 38 Power terminals 40, 42 X predecoder 44 Y predecoder 46 Z predecoder 50,52 power line 60 signal supply unit 62 First fuse area 64 Second fuse area 66 I / O drive circuit 70 row decoder 80 memory blocks 90 Sabouraud decoder 100 switch group 102-108 Transfer gate 110 memory cells 130 Booster circuit 140 Boost control circuit 150 address transition detection circuit 170 Data transition detection circuit 180 Auto Power Down Signal Generation Circuit 190 write enable signal transition detection circuit PDCXZ1 to 4 Sub word selection signal lines ZSB block selection signal line PDCX1 to 4X lower address predecode signal line

Claims (6)

[Claims] 1. A memory cell array, a plurality of main word lines extending along a first direction in the memory cell array, a row decoder for selecting one of the plurality of main word lines, and the memory cell array. A plurality of memory blocks divided in the first direction; a plurality of sub-word lines arranged in each of the plurality of memory blocks and subordinate to each of the plurality of main word lines; A plurality of sub-row decoders that are provided corresponding to each other, each having a plurality of sub-word selection signal lines extending along a second direction intersecting the first direction, and selecting one of the plurality of sub-word lines; , Based on the logic of a plurality of pre-decode signal lines selecting one of the plurality of sub word lines and a block selection signal line, A signal supply unit that supplies a plurality of subword selection signals that activate one of the plurality of subword selection signal lines provided in any of the row decoders; and the signal supply unit that is connected to the signal supply unit and becomes active. While setting the sub-word selection signal supplied to the sub-word selection signal line of the book to the active potential,
A boosted line which is boosted to a boosted potential higher than the active potential; a boosting capacitor having first and second terminals, the first terminal being connected to the boosted line; A switching element that is provided in the middle of the wiring that supplies the active potential to the first terminal, is turned on when a precharge signal is active, and precharges the boosting capacitor to the active potential; and A boost control circuit that sets a boosted potential to the boosted potential by changing the potential to the second terminal of the boosting capacitor at the same time by turning off the switching element by making the precharge signal inactive. A semiconductor memory device comprising: 2. The boost control circuit according to claim 1, wherein the boost control circuit is activated based on an address transition signal that is active for the predetermined period each time an address that selects a memory cell in the memory cell array is transitioned. A semiconductor memory device characterized in that a switching element is turned off. 3. The semiconductor memory device according to claim 1, wherein each of the plurality of sub row decoders has the block selection signal line extending along the second direction. 4. The resistance value per unit length between the signal supply unit and the plurality of sub row decoders according to claim 1, wherein each of the plurality of sub word selection signal lines has a resistance value per unit length. A semiconductor memory device characterized in that the resistance value is set higher than the resistance value per unit length in other regions. 5. The fuse element according to claim 4, wherein a plurality of fuse elements for switching a defective memory cell to a redundant memory cell are arranged between the signal supply unit and the plurality of sub row decoders, and the plurality of sub word selections are performed. The semiconductor memory device, wherein each of the signal lines has a high resistance layer which is routed under the fuse elements. 6. An electronic device including the semiconductor memory device according to claim 1.