JP2003281889A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronous semiconductor memory device being operated at high speed and stably without increasing chip area. <P>SOLUTION: Internal potential generating circuits (1914 and 1916) generating internal potentials conforming to charge pump operation corresponding to each of banks are arranged. For this internal potential generating circuits, a switch circuit (1912) receiving bank address signals (BAA, BAB) specifying a bank and a clock signal and transmitting a clock signal to a selected bank as a clock signal for driving the charge pump are arranged. Internal potentials can be generated with the bank unit and internal potentials can be supplied stably to a selected bank. <P>COPYRIGHT: (C)2004,JPO

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.
In particular, a clock signal that is given periodically from the outside
Synchronous Semiconductor Memory Device Acquires External Signals Synchronously with Clock
About the installation. More specifically, the present invention randomly
Accessible synchronous dynamic random access
-Regarding a memory (SDRAM). 2. Description of the Related Art Microprocessors (MPUs) have been in recent years.
Increasingly faster. On the other hand, used as main memory
Dynamic random access memory (hereinafter
(Hereinafter referred to as DRAM)
However, its operation speed still follows the operation speed of the MPU.
I can't do that. For this reason, DRAM access time and
And cycle time become bottlenecks,
It is often said that the performance of the body is reduced. [0003] In order to improve system performance, DR
Fast static random between AM and MPU
.Key consisting of access memory (SRAM)
A method of allocating high-speed memory called cache memory
Often used. Frequently used data in the cache memory
Data stored in the MPU
Fast cache when stored in flash memory.
Access to memory. MPU in cache memory
Access to DRAM only when there is no data required by
You. Frequently used data in high-speed cache memory
Access frequency to DRAM is large because it is stored
To reduce the DRAM access time and
And cycle time to improve system performance.
Up. A method using this cache memory is described in S
Because RAM is more expensive than DRAM,
Not suitable for relatively inexpensive devices such as computers
No. Therefore, a system using an inexpensive DRAM can be used.
There is a demand for improving the performance of such a device. [0005] The MPU and the DRAM are simply operated synchronously.
If only, give the system clock to the DRAM and
Operating the DRAM in synchronization with the system clock of
Good. Operates DRAM in synchronization with system clock signal
The arrangement for causing this is disclosed in US Pat. No. 5,083,296 by Hara.
Is shown in [0006] Hara's DRAM uses the clock signal CLK
Synchronize with chip select signal / CS and write enable
Latch signal / WE. Latched chip selector
Signal / CS is active and DRAM is selected
Indicates that the internal R
An AS signal and an internal CAS signal are generated. Internal RA
Address signal in response to S signal and internal CAS signal
Latch the internal row address signal and internal column address signal
Generate a number. Data input / output also uses clock signal CLK
It is performed synchronously. Hara makes the DRAM operate in clock synchronization.
As a result, the DRAM is
Control of RAS, column address strobe signal CAS, etc.
Such as timing deviations when operating with control signals
Trying to solve the problem. [0008] The above-mentioned hara DRAM
Only requires that the DRAM be clock-synchronized.
Intended. The address signal is the same as the clock signal CLK.
Internal RAS signal and internal CAS signal generated
Latched. A relatively slow clock signal
Or have sufficient setup and hold time
External address signal if the address signal has
To generate a desired internal address signal in response to
Wear. However, the clock signal CLK has a high speed.
The address signal setup time and
And the hold time margin is small, the internal RAS signal
Internal address signal when signal and CAS signal are generated
Has already transitioned to the invalid state. But
This Hara's DRAM is synchronized with a high-speed clock signal
Can not be operated. That is, high-speed MP
It cannot be used as high-speed main memory for U. The DRAM of Hara has an internal structure and
Then, it has the same configuration as a normal standard DRAM,
Clock only for external control signal and data input / output part
Only an operating latch circuit is provided. On the other hand, US JEDEC (Joint El
electron Device Engineering
(Council) is the main memory for high-speed MPU
Synchronous DRAM that operates in synchronization with a clock signal
(Synchronous DRAM; hereinafter referred to as SDRAM)
We are currently working on the standardization of SDRAM specifications.
I have. The details of this standard have not yet been disclosed.
Not. Nikkei Electronics, February 3, 1992
According to the article on page 85 of the Japanese issue, the following configuration was proposed.
Yes: (1) A clock with a period of 10 to 15 ns (nanosecond)
Synchronize with signals. (2) In the first random access,
Data is input in 4 to 6 clocks after the row address signal is input.
Access. After that, the address
Can access the data of (3) Pipeline operation of the circuit in the chip
The serial I / O buffer to the data I / O section.
To reduce access time. The above-described configuration is merely an idea, and
Nothing is said about how to achieve these.
Not. Therefore, an object of the present invention is to provide a novel structure
To provide a high-speed SDRAM. Another object of the present invention is to stably provide a desired voltage.
Semiconductors that can accurately generate internal potential at the level
It is to provide a storage device. According to the present invention, there is provided a semiconductor device comprising:
The storage device includes a plurality of banks each having a plurality of memory cells.
And these banks are provided corresponding to these banks.
The charge pump operates in response to the driving clock signal
Internal potential generating means for generating an internal potential by
Each according to the clock signal and the selected bank address
Receives the bank identification signal to be activated and generates the clock signal.
For driving the internal potential generation circuit corresponding to the selected bank
A switch circuit that transmits the clock signal. The number of times an internal potential is generated for each bank
And the internal potential generator provided for the selected bank.
Clock signal to the raw circuit
The bank selection status by transmitting the
The internal potential can be generated according to the
Places can be generated. Also, multiple banks
Even if the bank is driven to the selected state,
As a result, an internal potential can be stably generated. [Embodiment] [Arrangement of memory cell array] In SDRAM
System clock signal for high-speed access
A plurality of bits (1 bit, for example, 8 bits)
For high-speed access to
Is proposed. Meet this continuous access specification
A standard timing diagram is shown in FIG. In FIG. 2, data input / output terminal DQ0
Or input of 8-bit data (byte data) of DQ7
In SDRAM capable of output and output, 8
Bit data (8 × 8 total 64 bits)
Indicates a read operation. As shown in FIG. 2, in the SDRAM,
External clock, for example the system clock
External control signal at the rising edge of the
Row address strobe signal / RAS, column address
Strobe signal / CAS, output enable signal (output enable
Enable signal) / OE, write enable signal (write enable signal)
/ WE and address signal ADD. A
The dress signal ADD includes a row address signal X and a column address signal.
Y are multiplexed in a time division manner and provided. Low address
Strobe signal / RAS rises clock signal CLK
If it is in the active state "L" at the trailing edge, then
Address signal ADD is taken in as row address signal X.
It is. Next, column address strobe signal / C
AS is active at the rising edge of clock signal CLK.
If the address signal ADD at that time is L,
Taken in as address signal Y. This captured line
SD according to the dress signal Xa and the column address signal Yb.
A row and column selection operation is performed in the RAM.
Row address strobe signal / RAS falls to "L"
A predetermined clock period (6 clocks in FIG. 2)
Cycle), the output enable signal / OE is
If it is at "L", the first 8-bit data b0 is output
You. Thereafter, in response to the rise of clock signal CLK,
Data is output. In a write operation, row address signal X
The acquisition of c is the same as during data reading. Clock signal
Column address strobe at rising edge of CLK
And the write enable signal / WE
If both are in the active state “L”, the column address signal Yd
Is captured and the data given at that time
Data d0 is taken as the first write data. This signal
SDRA in response to falling of / RAS and / CAS
A row and column selection operation is performed inside M. K
In synchronization with the lock signal CLK, the input data d1,.
d7 is taken in, and this input data is stored in a continuous memory cell.
Is written. As described above, the conventional DRAM has
Address strobe signal / RAS and column address
Synchronized with an external control signal called strobe signal / CAS
Operation by taking in address signals and input data.
Unlike SDRAM, SDRAMs require external
A clock signal, for example a system clock
Address strobe signal / R at the rising edge of CLK
AS, / CAS, address signal and input data
Capture an external signal. As described above, in synchronization with an external clock signal,
Synchronous operation to capture external signals and data
The advantage of performing is that the skew (ta
Of data input / output time due to
Gin is not necessary, which reduces cycle time
And that it can be shortened. Also, this SD
Depending on the system in which RAM is used,
Frequency of accessing memory cells of several bits
There are cases. Thus, continuous data is synchronized with the clock signal.
Data can be written and read.
If that is the case, the continuous access time can be shortened
The average access time of this SDRAM can be
It becomes possible to make it comparable. 64 bits (8 × 8) in SDRAM
It is simplest to select all memory cells at the same time.
8 times continuous writing / reading of this 8-bit data is realized
Can be thought of as a way to: Now, an array arrangement as shown in FIG.
Consider SDRAM. Figure 3 shows a standard 16Mbit
FIG. 2 is a diagram showing a chip configuration of a DRAM. In FIG.
Four DRAMs each having a storage capacity of 4M bits
Memory mats MM1, MM2, MM3, and MM4
including. Each of the memory mats MM1 to MM4 is
16 memory cells having a storage capacity of 256 Kbits
Rays MA1 to MA16 are included. No memory mat MM1
One side of the chip MM4 in the chip long side direction (vertical direction in FIG. 3)
Along the row decoders RD1, RD2, RD3 and R
D4 is arranged. 2 adjacent in the chip short side direction
Read data between row decoders for one memory mat
Preamplifier circuit PA for amplifying data and write data
Write buffer for amplifying the amplifier and transmitting it to the selected memory cell.
Fa WB is arranged. This preamplifier circuit PA and
Each block of the write buffer WB has four memories
1 for an array block or 1 Mbit array
Two blocks are provided. Each of the memory mats MM1 to MM4
At the center of the chip along the short side of the chip.
Ram decoders CD1, CD2, CD3 and CD4
Be placed. Chip center (area between column decoders)
Address buffer and control signal generation circuit etc.
And a peripheral circuit PH including the same. The configuration of the 16M DRAM shown in FIG.
Provides a word x 8 bit configuration. In operation,
Four memory arrays are selected. In FIG.
Memory arrays MA1 and MA5 of Morimat MM3
And memory arrays MA1 and M1 of memory mat MM4
The state where A5 is selected is shown. From each memory array
A 4-bit memory cell is selected. So this figure
In the case of the configuration shown in FIG.
Access is possible. Finally, the address signal bits
In this case, 8 bits are selected from the 16 bits. Each of the memory mats MM1 to MM4
In 1 Mbit (four memory arrays) units.
Selection, and then the selected 1 Mbit array
Maximum one memory array is selected
You. As shown in FIG. 3, one RAS cycle (signal / R
(One cycle specified by AS)
The cut array is activated. Such partial activation is not
Notes excluding activated memory arrays to reduce power consumption
The rearray is maintained in a precharged state. FIG. 4 shows the four DRAMs shown in FIG.
FIG. 3 is a diagram schematically illustrating a configuration of a memory array unit. Four
256K bit memory arrays MA # 1-MA # 4
That is, only one memory array is activated during operation.
(Word line selection, bit line charge / discharge, etc.). In FIG. 4, for one memory array,
Along the long side of the memory array (the short side of the chip)
To transmit selected data from the memory array
Local IO line pairs LIO1, LIO2, LIO3,
And LIO4. Located between memory arrays
Local IO line pairs are shared by adjacent memory arrays.
You. For example, local IO line pairs LIO3 and LIO4
Are the memory arrays MA # 1 and memory array in FIG.
Shared with MA # 2. Each bit line pair of the memory array
BLP and local IO line pair LIO (hereinafter referred to as local IO
When a line pair is generically referred to simply as LIO)
To connect according to the output of the column decoder.
Switches GS1, GS2, GS3, and GS4 are provided.
It is. IO switches GS1 to GS4 are column decoders
CD (code is used to indicate a column decoder generically)
Output signal (column selection signal) is supplied to one column selection line CS
L. The column selection line CSL has two signal lines CS.
It is divided into La and CSLb. This divided column selection line C
SLa and CSLb each have two bit line pairs BL
Select P. That is, one column selection line CSL
Bit line pair BLP is selected and local IO line pair L
Connected to IO. The configuration of the memory array MA will be described later in detail.
As described in the above, the sense amplifier is connected to both sides of the bit line pair BLP
Have an alternate arrangement type sense amplifier configuration
And this sense amplifier is shared by adjacent memory arrays.
You. In other words, each memory array has an
A sense amplifier configuration. As described above, the shared sense amplifier configuration
And share a local IO line pair
Required for signal wiring area reduction and sense amplifier
Reduce the area. Further alternate sense amplifier configuration
In this way, even if the bit line pitch becomes smaller,
A good sense amplifier pitch is secured. The column selection line is
This memory array extends along the vertical direction in the figure. The four memory arrays MA # 1 to MA # 4
Global IO line pairs GIO1 to GIO4
Is arranged. Global IO line pair GIO1 to GIO4
At the intersection of the local IO line pairs LIO1 to LIO4
In response to the lock selection signal, the local IO line pairs LIO1 to LIO1
Connect LIO4 to global IO line pair GIO1 to GIO4
Block selection switches BS1, BS2, BS3,
And BS4 are arranged. This makes it possible to
Only the memory array in the active state is a global IO line pair.
GIO (The symbol is used to indicate the global IO line pair generically.
GIO) and data can be exchanged. Global IO line pair GIO1 to GIO4
Are pre-installed in the corresponding input / output circuits PW.
Via the amplifier PA and the write buffer WB
Read data bus RDB and write data bus WDB
Connected to. A program included in this data input / output circuit PW
The re-amplifier PA and the write buffer WB are
Response to the clock select signal, read instruction signal and write enable signal
And activated. With the above-described configuration, four 1-Mbit memories are provided.
Read 4-bit memory cell data from memory array
And writing data to 4-bit memory cells
it can. Therefore, in the configuration of the 16MDRAM,
Is to access 16-bit memory cells at the same time
Can be. Read data bus RDB and write data
The tabus WDB passes through the input / output circuit PW, and
It is connected to the data input / output terminal via the path PH. 8 bit
Peripheral circuit PH when data input / output in
In the selection of 8-bit data from 16-bit data
Selection is performed. Input / output data in 8-bit units
In this case, instead of this, only one memory mat
May be used. As described above, a 2M word × 8 bit configuration
8 bits (one data input / output) using DRAM
Realize SDRAM that is accessible)
Is accessed in the 16 MDRAM shown in FIG.
Access to four times as many memory cells as
Required. 256Kbits that can be activated
The number of memory arrays is easily increased in terms of power consumption.
I can't let it. If you activate the memory array,
The amplifier operates to charge and discharge the bit line.
The bit line is charged and discharged by this sense amplifier and
Bit line precharge to return to recharge cycle
This is because current is consumed for charging / discharging or the like. The number of memory arrays that can be activated simultaneously is increased.
Increase the number of memory cells accessed simultaneously without adding
To be selected simultaneously in one memory array.
It is necessary to increase the number of selected memory cells. sand
That is, local IO line pair LIO, global IO line pair GI
O, the number of preamplifiers PA, and the number of write buffers WB
It is necessary to increase by four times. This state is shown in FIG.
You. In FIG. 5, the local IO line pair LIO is
16 pairs are provided for one memory array, and
There are also provided 16 pairs of global IO lines GIO. Column selection line C
SL is 16 bit line pairs in one memory array
Select BLP at the same time and connect to local IO line pair LIO
I do. Also in FIG. 5, the portion divided from column selection line CSL
The split column select line selects two bit line pairs at the same time and
Connected to the IO line pair LIO. Similarly, the local IO line pair LIO is
Global IO line pair GIO via the select switch BS
Connected to As is apparent from the configuration of FIG.
Number of IO line pairs LIO and global IO line pairs GIO
Increases the wiring area significantly, and the chip area
Increase significantly. Therefore, the structure as shown in FIG.
8-bit continuous access to 16Mbit DRAM
It is not a good idea to use it to realize a simple SDRAM.
No. Embodiment 1 FIG. 6 shows a preferred embodiment of the present invention.
FIG. 3 is a diagram showing a chip layout of the SDRAM according to the embodiment;
is there. In FIG. 6, as an example, 2M words × 8
A 16 MS DRAM in a bit configuration is shown. SDRAM
Are four memories each having a storage capacity of 4 Mbits
Mats MM1 to MM4 are included. Memory mat MM1
MM4 each have 256K bits of storage
16 memory arrays MA1 to MA16 having a capacity
Including. One side of the memory mats MM1 to MM4
Row decoders RD1 to RD4 are
Each is arranged. Also, the memory mats MM1 to MM1
Column decoding along the short side direction on the center side of the chip of MM4
Disks CD1 to CD4 are arranged respectively. Column de
Coder CD (general term for column decoders CD1 to CD4)
Use the CD for reference)
Remat MM (memory mats MM1 to MM4 are generically
Column selection line CSL extending across each array of
Is placed. One column selection line CSL will be described later in detail.
Thus, eight pairs of bit lines are simultaneously selected. Global I for transmitting internal data
O line pair GIO is also along the long side direction of memory mat MM
Are arranged across each array. For each of the memory mats MM1 to MM4,
Then, the data of the selected memory cell is
Preamplifier PA and memo selected for amplification of
Write buffer for transmitting write data to recell
WB and input / output circuits PW1 to PW4 are arranged.
It is. An address signal is generated at the center of the chip.
And a circuit for generating control signals.
Peripheral circuits PH including the same are arranged. The SDRAMs shown in FIG. 6 are independent of each other.
Can perform precharge operation and activation operation
And two banks # 1 and # 2. Bank # 1
Includes memory mats MM1 and MM2, and includes bank #
2 includes memory mats MM3 and MM4. This van
The number of clicks can be changed. Each of the memory mats MM1 to MM4 has 2
With two array blocks (each storage capacity 2Mbit)
You. One array block includes memory arrays MA1 through MA1.
MA8, and the other array block is a memory array.
It is composed of rays MA9 to MA16. One array
At most one memory array is selected
You. The number of memory arrays activated simultaneously is four.
FIG. 6 shows the memory array of the memory mat MM3.
MA1 and MA9 and memory of memory mat MM4
The state where arrays MA1 and MA9 are activated is shown.
That is, in the selected bank, each memory mat
Memory array is selected from the array block
You. The number of simultaneously selected column select lines CSL is eight.
It is a book. One column select line CSL selects eight pairs of bit lines.
Select. Therefore, at the same time, 8 × 8 = 64 bit memo
Resel is selected. The input / output circuit PW is connected to the corresponding memory mat M
Commonly used for each of the M memory arrays. One entry
Preamplifier PA and light bar included in output circuit PW
The number of buffer WBs is 32 each,
There are 128 in each body. The configuration of FIG. 3 is expanded
The preamplifier PA and the light bar in the configuration shown in FIG.
Buffer WB is reduced by half compared with 256 of each buffer WB.
As a result, the area occupied by the chip is greatly reduced. Preamplifier PA included in input / output circuit PW
And the write buffer WB are concentrated in the central part of the chip.
Is placed. These are control circuits included in the peripheral circuit PH.
Driven by Therefore, the preamplifier PA and the
Signal lines for controlling the operation of the write buffer WB are also short.
Therefore, the load on the signal line is reduced and high-speed operation
Can be realized. The peripheral circuits PH are concentrated in the central part of the chip.
Data input / output in this chip
It will be done through the center, when mounting the package
The pin arrangement of
At the center of the page. Peripheral circuit PH and data
Data input / output terminals are shorter and data
Output can be performed. The SDRAM shown in FIG.
Alternating type share like 16MDRAM shown above
A sense amplifier configuration. That is, the selected
Only the memory array is activated and the unselected memory arrays are
It is maintained in a recharged state. Notes activated at the same time
The number of re-arrays is four, and the structure of the DRAM shown in FIG.
The current consumption does not increase in comparison. FIG. 7 shows the IO line arrangement of the SDRAM shown in FIG.
It is a figure which shows an arrangement concretely. In FIG. 7, two 2
M-bit memory arrays MSA1 and MSA2 are shown
You. The 2M bit memory array MSA1 is located at the center of the chip.
2M bit array block located far from
Yes, the 2M bit memory array MSA2 is located at the center of the chip.
2 shows a 2M bit array block close to the section. 2M bit memory arrays MSA1 and M
SA2 is composed of 64 32 bits arranged in 8 rows and 8 columns.
Includes a K-bit memory array MK. 2M bit memory
Ray MSA (total memory arrays MSA1 and MSA2)
4) along the direction in which the word lines WL extend.
Array groups AG1, AG2, AG3 and AG4
Is divided into 3 adjacent along the direction of the word line WL
Word line shunt between 2K bit memory arrays MK
An area WS is provided. Usually, in DRAM, word
Made of polysilicon to lower the resistance of the lead wire
In parallel with the word line WL, low-resistance gold such as aluminum
Place a metallization line and make this polysilicon word line and low resistance gold
The metal wiring is electrically connected at predetermined intervals. This word
The line shunt region is described below. FIG. 8 shows a transistor constituting a memory cell.
FIG. 3 is a diagram schematically showing a cross-sectional structure of the radiator. Included in memory cells
The access transistors to be used are shown in the table of the semiconductor substrate SUB.
Region formed on the surface and impurity region I
Polysilicon formed on PR via gate insulating film
And a gate electrode PL composed of One impurity region I
PR is a bit consisting of, for example, a first layer aluminum interconnection.
Connected to the scanning line BL. In the upper layer of the bit line BL,
Low resistance made of aluminum etc. for lead wire contacts
Conductive layer AL is arranged. As shown in FIG. 9, this low resistance conductive layer AL
And polysilicon gate electrode (word line) PL
Electrically connected by a contact CNT at intervals
You. The area where the electrical connection CNT is provided is a word line
This is referred to as a shunt area WS. Word line drive signal DWL is low
It is transmitted to the resistance conductive layer AL. So one word
Word line drive signal DW at high speed to the end of line
L is transmitted, and the rise of the word line potential can be performed at high speed.
Can be. For such an electrical connection CNT,
As shown in FIG. 8, the poly under the bit line BL exists.
Silicon gate electrode (word line) PL and bit line BL
It is necessary to connect to the low resistance conductive layer AL which exists in the upper layer of
is there. For this reason, the bit line BL exists in the electrical connection CNT.
Area where no memory cells exist, that is,
It is necessary to provide in advance. This memory cell does not exist
The regions are adjacent to each other along the direction of the word line WL in FIG.
Area between the memory arrays MK. This word line
In the shunt region WS, a polysilicon gate electrode (W)
Electrical connection between PL and low resistance conductive layer AL
It is. Referring again to FIG. 7, global IO line pair
GIO is arranged in this word line shunt region WS.
In one word line shunt region WS, the center of the chip
In the 2M bit memory array area MSA2 close to the section
Has four global IO line pairs. These four pairs
Two of the global IO lines are more
2Mbit memory array area M farther from the center of the chip
Extends at SA1. That is, rather than the chip center
Words in the distant 2 Mbit memory array area MSA2
In the line shunt region WS, two global I
An O line pair GIO is provided. Two global IO line pairs
Are used by the 2M bit memory array MS. Transfer of data with the selected memory array
Local IO line pairs LIO to perform
Corresponding to loops AG1, AG2, AG3, and AG4
Provided. One 32K bit memory array MK
For example, two local IO line pairs L
IO and two local IO line pairs LI arranged on the other side
O and a total of four local IO line pairs are arranged. locker
The IO line pair LIO is adjacent to the word line WL in the direction of the word line WL.
32K bit memory array in the same array group
And the direction of the bit line BL
Along the 32K bit memory array MK
Even shared. The memory array MK will be described later in detail.
As described in the configuration,
It has a pump configuration. Adjacent to each other in the direction of the bit line BL.
Area between two 32K bit memory arrays MK.
A sense amplifier is arranged. With global IO line pair GIO
Select a block to connect the local IO line pair LIO.
A selection switch BS is provided. Block selection switch B
S is the intersection between the word line shunt region WS and the sense amplifier row.
Placed at a point. Transmits a column selection signal from a column decoder
Column selection line CSL is connected to each of array groups AG1 to AG4.
In each case, one is selected. One column selection line C
SL is 4 pairs in the area MSA1 far from the chip center.
Bit line BLP of the corresponding local IO line pair L
2Mbit memo connected to IO and near the center of chip
Four pairs of bit lines BLP are connected in the rearray region MSA2.
Select and connect to the corresponding local IO line pair LIO. You
That is, eight bit line pairs are provided by one column selection line CSL.
BLP is set to the selected state, and is connected via the local IO line pair LIO.
And is connected to eight global IO line pairs GIO. 2
One memory mat is selected and one memory mat MM
In this case, 8 × 4 = 32 bit line pairs BLP are selected.
Therefore, a total of 64 bit line pairs BLP are selected.
And a total of 64 bits of memory cells at the same time
It is possible to access. FIG. 10 shows one 32K bit memory array.
It is a figure showing composition of a part relevant to a. Figure 10
The 32K bit memory array MK2 is a row decoder.
And a word line WL to which a row selection signal from
Bit line pair BL arranged in a direction intersecting node line WL
P and the intersection of the word line WL and the bit line pair BLP
Dynamic memory cells MS correspondingly arranged.
No. The memory cell MS includes an access transistor,
And a capacitor for storing information. Bit line pair BLP
Are bit lines BL and BL to which complementary signals are transmitted.
/ BL. In FIG. 10, bit line BL and word line
Memory cell MS is arranged corresponding to the intersection with
Is shown. An array selection is provided on both sides of the memory array MK2.
Gates SAG1 and SAG2 are arranged. Array selection
The selection gate SAG1 and the array selection gate SAG2 are
Are alternately arranged with respect to the line pairs BLP. Array selection
The gate SAG1 becomes conductive in response to the array selection signal φA1.
State, and the array selection gate SAG2 is
It becomes conductive in response to signal φA2. Each of the bit line pairs BLP is an array selection gate.
Through the gate SAG1 and the array selection gate SAG2.
Connected to sense amplifier SA1 and sense amplifier SA2
It is. That is, the sense amplifier SA1 is connected to the memory array
MK2 is arranged on one side in parallel with word line WL,
The amplifier SA2 is connected to the other side of the memory array MK2.
In parallel with the scanning line WL. Sense amplifiers SA1 and
And SA2 are connected to the bit line pair BLP of the memory array MK2.
They are alternately arranged on both sides. Sense amplifier SA1
Is shared by the memory arrays MK1 and MK2.
Is done. The sense amplifier SA2 is connected to the memory array MK2.
Shared by the memory array MK3. In parallel with the row of the sense amplifier SA1, the local
A pair of IO lines LIO1 and LIO2 are arranged. Ma
In parallel with the sense amplifier SA2, the local IO line
A pair LIO3 and LIO4 are arranged. Figure 10
Two local IO line pairs are connected to one sense amplifier SA.
The arrangement provided on one side is shown. Local IO line
The pairs may be arranged on both sides of the sense amplifier SA. This sense amplifier is connected to sense amplifier SA1.
The data detected and amplified by the amplifier SA1 is
Column select gate for transmitting to line pair LIO1, LIO2
CSG1 is provided. Similarly, the sense amplifier SA2
Then, the data detected and amplified by the sense amplifier SA2 is
Data to the local IO line pairs LIO3 and LIO4.
Column selection gate CSG2 is provided. Column decor
Column select line CSL from the two column select gates CSG1
And the two column selection gates CSG2 are simultaneously turned on.
You. As a result, four bit line pairs BLP are connected to the local IO.
Line pairs LIO1, LIO2, LIO3 and LIO4
Sometimes connected. Detected and amplified by sense amplifier SA1
Data is transmitted to local IO line pairs LIO1 and LIO2.
Is reached. The data detected and amplified by the sense amplifier SA2
Data transmitted to local IO line pairs LIO3 and LIO4
Is done. Local IO line pair LIO is changed to global IO
In order to connect to the line pair GIO, the block selection signal φB
A block selection switch BS that conducts in response to the
You. In FIG. 10, the local IO line pair LIO1 is grouped.
Block selection for connecting to global IO line pair GIO1
Select switch BS1 and local IO line pair LIO2
Block select switch connected to global IO line pair GIO2
H BS2 is shown. Local IO line pair LIO3 and LIO4
Is, as shown in FIG. 7, two adjacent global IO lines
Connected to GIO via block selection switch
(However, not shown in FIG. 10). Next, the operation will be briefly described. Selected
When the selected word line WL is included in the memory array MK2.
In this case, array selection signals φA1 and φA2 are activated.
The bit line pair BLP included in the memory array MK2 is
Connected to sense amplifiers SA1 and SA2. memory
Array selection provided for arrays MK1 and MK3
Select gates SAG0 and SAG3 are turned off,
Memory arrays MK1 and MK3 maintain the precharge state
I do. In each bit line pair BLP, the memory cell data
After the data appears, the sense amplifiers SA1 and SA2 are
When activated, the memory cell data is detected and amplified. Next, the signal on column select line CSL is activated.
Rise to "H" of column select gates CSG1 and CSG1.
SG2 conducts and is detected by sense amplifiers SA1 and SA2.
The amplified data is transmitted to the local IO line pair LIO1 to LIO1 or
It is transmitted to LIO4. Subsequently or simultaneously, block select signal φB
Attains an active "H" level, and local IO line pair LIO1
Or LIO4 is a global IO line pair GIO1 to GIO
Connected to IO4. When reading data,
Data of the global IO line pair is amplified via the preamplifier PA
Is output. When writing data, write back
Write data given by the global WB
Each bit via line pair GIO, local IO line pair LIO
Is transmitted to line pair BLP, and the data is written to the memory cell.
Be executed. The block selection signal φB is the selected word
Active only for memory array MK2 to which line WL belongs
State. The same applies to array selection signals φA1 and φA2.
is there. The block selection signal φB and the array selection signal φA
1, and φA2 are a predetermined number of bits of the row address signal.
(For example, upper 4 bits)
You. As described above, word line shunt region WS
A global IO line pair GIO is arranged in
To be arranged in an alternating arrangement type shared sense amplifier configuration
Select memory cells of 64 bits at the same time
Even with such a configuration, the wiring area of the signal line may not increase.
Absent. In addition, the 256K memory array
Since the number is 4 which is the same as the standard 16 MDRAM,
There is no increase in flow. [Embodiment 2] FIG. 11 shows a 4 Mbit memory.
Memory array MSA1 and memory array M in mat
The figure which expands and shows the structure of the array part of the boundary area | region with SA2.
It is. In FIG. 11, a 256K bit memory array
32K bit memory array in MA8 and MA9
I MK. In FIG. 11, a 256K bit memory
Ray MA8 is a 32K bit memory array MK81 and
And MK82 and the memory arrays MK81 and MK82.
The sense amplifier groups SA81 and SA81 provided on one side
And SA82. 256K bit memory array MA9
Are 32K bit memory arrays MK91 and MK92
And each of the memory arrays MK91 and MK92.
Sense amplifier groups SA91 and SA9 provided correspondingly
2 Memory array MK81 and memory array MK9
1 and a sense amplifier group SA85 is provided between
Sense between array MK82 and memory array MK92
An amplifier group SA86 is provided. For memory arrays MK81 and MK82,
The global IO line pairs UGIO1, UGIO2,
UGIO3 and UGIO4 are provided and a memory array
Global IO line for MK91 and MK92
Against LGIO1, LGIO2, LGIO3 and LGIO
4 are provided. Also, the memory arrays MK81 and MK81
Local IO line pair LIO81, LIO for K92
82 is provided on one side and the local IO line pair L is provided on the other side.
IO83 and LIO84 are provided. Memory array
Local IO line pair on the other side of MK91 and MK92
LIO 85 and LIO 86 are provided. Local I
O line pairs LIO83 and LIO84 are connected to memory array M
Common to K81, MK82, MK91 and MK92
Used for Global IO line pair UGIO1 to UGIO
4 is the data of the memory cells included in the memory array MSA1.
Transmit data. Global IO line pair LGIO1-LG
IO4 stores the data of the memory cells of the memory array MSA2.
introduce. In this array division structure, the memory array
One 256Kbit memory array is selected from MSA1.
Selected and one 256K from memory array MSA2
A bit memory array is selected. At this time, each memory
Arranged at the same position in arrays MSA1 and MSA2
256K bit memory array MA (MA1 to M
A16 are generically activated at the same time. memory
When array MA8 is activated, the memory array
MA9 is maintained in a precharge state, and memory array M
A16 is activated. Now, a column of memory array MK81 is selected.
Think about the state. At this time, the memory array MK81
Connected to sense amplifier groups SA81 and SA85.
Memory arrays MK91 and MK92 are precharged
Stay state. Memory array MK82 is a sense amplifier group
Connected to SA82 and SA86. Memory array M
When the column in K81 is selected, the sense amplifier group SA
The memory array MK81 is connected via
Local IO line pair LIO81, LIO82, LIO83
And LIO84. Memory array MK81
Is a 32K bit memory included in the memory array MSA1.
It is a rearray. In this case, as shown by a circle in the figure
And the local I through the block selection switch BSa.
O line pair LIO81, LIO82, LIO83 and LI
O84 is the global IO line pair UGIO1 to UGIO4
Connected. On the other hand, memory array MK91 is selected
In this case, memory array MK91 has global IO
Connected to line pairs LGIO1 to LGIO4. That is,
In FIG. 11, it is indicated by a block selection switch BSb marked with a cross
As shown, the local IO line pairs LIO83, LIO84,
LIO85 and LIO86 are global IO line pairs LG
Connected to IO1 to LGIO4. That is, the local IO line pair LIO83 and LIO83
And LIO 84 are memory arrays MK81 and MK8.
2 is selected, the global IO line pair UGIO
1 and UGIO2. Local IO line pair L
IO83 and LIO84 are connected to the memory arrays MK91 and MK91.
When MK92 and MK92 are selected (when activated
), Global IO line pairs LGIO1 and LGIO
2 is connected. Therefore, the memory array MSA1
Located in the boundary area between memory cell array and memory array MSA2
For the LIO line pairs LIO83 and LIO84,
It is necessary to provide two block selection switches. memory
When the array MA8 is selected, the block selection switch
B is turned on and the memory array MA9 is selected.
In this case, the block selection switch BSb is turned on.
You. With this configuration, the array activation section (memory array
(Indicates the unit area during operation corresponding to MSA.)
One-to-one correspondence with global IO wire pairs
You. [Embodiment 3] FIG. 12 shows the row shown in FIG.
Shows another connection form between the Cal IO line and the Global IO line
FIG. 12 corresponds to the one shown in FIG.
The same reference numerals are given to the same parts. In FIG. 11, memory array MA8 includes
32K bit memory arrays MK81 and MK82
On the other hand, as in the case of FIG.
O81, LIO82, LIO83 and LIO84
Be killed. For memory arrays MK91 and MK92
The local IO line pair LIO83, LIO84, LI
O91 and LIO92 are provided. Memory array M
K161 and MK162 are connected to the memory array MA16.
Included, local IO line pair LIO161, LIO16
2, LIO 163 and LIO 164. Local IO line pair LIO81 and LIO
82 denotes block selection switches BS81 and B, respectively.
Global IO line pair UGIO3 and U via S82
GIO4. Local IO line pair LI
O83 and LIO84 are block selection switches BS
Global IO line pair LGI via 83 and BS84
It is connected to O1 and LGIO2, respectively. local
IO line pairs LIO91 and LIO92 are block select
Global IO via switches BS91 and BS92
Connected to line pair LGIO3 and LGIO4. locker
The IO line pairs LIO161 and LIO162 are
Group via switch selection switches BS161 and BS162.
Connected to global IO line pair LGIO3 and LGIO4
It is. Local IO line pair LIO163 and LIO16
4 are block selection switches BS163 and B, respectively.
Global IO line pair UGIO via S164
1 and UGIO2. In operation, memory array MA8 is
When selected, memory array MA16 is selected.
You. Memory arrays MA8 and MA9 are simultaneously
It is not selected. Memory array MK81
When selected, the memory array MK161 is similarly selected.
It is. The memory array MK81 includes a local IO line pair LI
O81 and LIO82 and block selection switch B
Global IO line pair UG via S81 and BS82
Local IO connected to IO3 and UGIO4
Line pairs LIO83 and LIO84 and the block selection switch
Global IO line pair via BS83 and BS84
Connected to LGIO1 and LGIO2. Memory array
During the operation of reading data from MK81,
The selected 4-bit memory cell of the memory array MK81
Data of the global IO line pair LGIO1, LGIO
2, transmitted to UGIO3 and UGIO4. In the memory array MK161, the low
Cal IO line pair LIO 161 and L array 162
Via the clock selection switches BS161 and BS162
Connected to global IO line pair LGIO3 and LGIO4
And local IO line pairs LIO163 and LIO1
64 is a block selection switch BS163 and BS16
4 via the global IO line pair UGIO1 and UGI
Connected to O2. That is, the data read operation is difficult.
In other words, the selected 4-bit data of the memory array MK161 is
When the data of the memory cell is the global IO line pair UGIO1,
Transmitted to UGIO2, LGIO3 and LGIO4
You. In the case of the connection configuration shown in FIG.
Correspondence between activation section and global IO line pair is stored in memory
This is not true for arrays MA8 and MA16. Both
In the memory arrays MA8 and MA16,
Data to global IO line pairs belonging to different groups
Is transmitted. From the viewpoint of activation category,
Ray MA8 and memory array MA16 are half (alternately)
Data is exchanged (if a sense amplifier is
It will be. Access any memory cell from outside
Doing it has no actual meaning. Addressed
Data is written to the memory cell
Is to be read. In the case of the connection configuration shown in FIG.
One block selection switch is used for all the Cal IO line pairs.
Only a switch is provided. Therefore, the memory map
Boundary area of memory array (or activation section) in the center
The number of elements in the area can be reduced, and the wiring area can be reduced.
Can be reduced. The remaining memory arrays MA1 to MA
7 is the global I
The O line pair is connected to UGIO1 to UGIO4. Memoria
Rays MA9 to MA15 are gross when selected.
Global IO line pair LGIO1 to LGIO4. [Embodiment 4] FIG. 13 shows a general DRAM.
FIG. 3 is a diagram showing an arrangement of bit lines in an array. Figure 13
The bit line pair BL1, / BL1 to BLn, / BLn
Is shown. Bit line pair BL1, / BL1 to BLn, /
In each of BLn, a memory cell is connected.
During operation, the data of the corresponding memory cell is transmitted.
Then, it is detected and amplified by the sense amplifier. Neighbor bits
Parasitic capacitance exists between the lines. In the same bit line pair
The parasitic capacitance between the parasitic capacitance C2 and the bit line of the adjacent bit line pair
Quantity C1. In operation, read on bit line
The information signal, that is, the read voltage, is equal to the bit line capacitance Cb.
1 and the ratio Cs / Cbl of the capacity Cs of the memory cell.
Is determined. During operation, this bit
The read voltage and reference voltage (precharge voltage)
Pressure). For accurate sensing operation
It is preferable that the capacity of each bit line is the same. Bit
If the line capacitance is different, the read voltage will be different,
This is because the operation cannot be performed. In the memory array, it is arranged at the end.
Further dummy adjacent to bit lines BL1 and / BLn
Bit lines DBL0 and DBL1 are provided, respectively.
You. Dummy bit lines DBL0 and DBL1 are provided.
The bit located at the end of the memory array
The parasitic capacitance of lines BL1 and / BLn is
Identical, constant read voltage level during sensing operation
And That is, dummy bit line DBL0 is provided.
If not, the parasitic capacitance for the bit line BL1 is
Only the parasitic capacitance C2 generated by the bit line / BL1
You. On the other hand, the parasitic capacitance of bit line / BL1 is
And the parasitic capacitance C1 due to the adjacent bit line BL2.
You. Therefore, bit line BL1 and bit line / BL1
The capacitance differs and appears on the bit line BL1 during operation.
Of the read voltage appearing on bit line / BL1
Different levels enable accurate sensing operation
Gone. To prevent this state, the dummy bit line D
BL0 and DBL1 are provided, respectively. FIG. 14 shows a semiconductor memory according to the fourth embodiment.
FIG. 2 is a diagram illustrating a configuration of an array arrangement of the device. Figure 14
32K bit memory arrays MKa, MKb, NK
Near the word line shunt region associated with c and MKd
Is shown. The memory array MKa includes a pair of bit lines BLa,
/ BLa and dummy bit line DBLa.
It is. Memory array MKb includes a bit line pair / BLb and
BLb and dummy bit line DBLb.
It is. For bit line pair BLa, / BLa,
Conducted in response to the array selection signal φAa, and the corresponding sense
Connect bit line pair BLa, / BLa to amplifier SAa
Select gate SAGa is provided. array
Between the selection gate SAGa and the sense amplifier SAa,
Conduction occurs in response to a signal on column selection line CSLa, and sense
The latch node of the amplifier SAa (bit lines BLa, / BLa
To local IO lines LIOa and / LIOa
A column selection gate CSGa to be connected is provided. Sensea
The other side of the amplifier SAa responds to the equalizing signal φEQ.
Then, the latch node of the sense amplifier SAa is set to a predetermined potential.
Vbl (normally, 1/2 of the power supply voltage Vcc)
A precharge gate EQa is provided. For the memory array MKc, the array selection
In response to the selection signal φAb, and the corresponding bit line is sensed.
Array selection gate connected to the latch node of the
A port SAGc is provided. Similarly, the memory array MKb is
Array selection gate that conducts in response to ray selection signal φAa
And SAGb in response to a signal on column select line CSLb.
Through bit lines BLb and / BLb to local IO lines
Column select gate CS connected to LIOa and / LIOa
Gb and the potentials on the bit lines BLb and / BLb are detected and increased.
Widen sense amplifier SAb and equalize / precharge
In response to the signal φEQ, the bit lines BLb and
/ BLb is precharged to a predetermined potential Vbl
In response to the array selection signal φAb
A conductive array select gate SAGd is provided. The same applies to dummy bit line DBLb.
And an array selection which becomes conductive in response to an array selection signal φAa.
Select gate DAGb and equalize / precharge signal φ
Conducts in response to EQ, and sets dummy bit line DBLb to a predetermined
Precharge gate DE for precharging to potential Vbl
Qd and the equalizing / precharge signal φEQ
And the dummy bit line DBLb is connected to the local IO line L
Precharge gate DEQb connected to IOa is provided
It is. In the precharge state, array selection
Signals φAa and φAb are both at “H”. array
Select gates SAGa to SAGd are all conducting
Bit line pairs included in memory arrays MKa to MKd are paired.
Connected to the corresponding sense amplifier SA. At this time
And the precharge signal φEQ is also at “H”,
Charge gates EQa and EQb are conducting,
Precharge all bit line pairs to a predetermined potential Vbl
You. In response to this equalize / precharge signal φEQ,
Precharge gates DEQc and DEQd are both
Conduction, dummy bit lines DBLa and DBLb
It is precharged to the potential Vbl. Further precharge
Gates DEQa and DEQb conduct, and this gate DQa
Precharge voltage transmitted from EQc and DEQd
Vbl is transmitted onto local IO line LIOa. In operation, only the selected array
Are connected to the sense amplifier to be activated. Unselected
The memory array maintains the precharge state and the selected array
When sharing the sense amplifier with the
Be separated. In the conventional DRAM, the precharge
Gates DEQa and DEQb always remain off.
ing. Simply these gates DEQa and DEQb
Is provided for adjusting the shape (pattern). this
Using precharge gates DEQa and DEQb
Pre-charge the local IO line to
The area of the shunt region can be reduced. That is,
Local IO line precharge transistor and logic
Transistor for local IO line equalization to word line
If a new area is provided in the channel area, the area of this area will increase.
I do. However, such a dummy bit line DBL
a and the gates DEQa and
Precharge the local IO line using DEQb and DEQb
With this configuration, the sense amplifier row and the word line
It is necessary to provide extra transistors in the
Without increasing the area of the word line shunt region.
it can. Also, the control signal for local IO line precharge is used.
There is no need to provide signal lines for transmitting signals
The area occupied by the amplifier rows (the adjacent memory arrays MAa and
Area between MAbs) can be reduced. [Embodiment 5] FIG. 15 shows an array according to the present invention.
It is a figure showing composition of an important section of a 5th example of arrangement. FIG.
5 has connection type between local IO line and global IO line
State. In FIG. 15, bit line pair BLa, / BL
a and bit line pairs BLb and / BLb
Connected to the amplifiers SAa and SAb. In FIG.
Bit lines BLa, / BLa, BLb, / BLb
At the intersection of the local IO lines LIOa and / LIOa
Column selection gate CSGa which conducts in response to a column selection signal
And CSGb are provided respectively. The column selection line is shown
Not. Sense amplifier SA (SAa and SAb)
Is a p-channel MO having a gate and a drain cross-coupled.
S (insulated gate type field effect) transistor PT1 and
PT2 and n-channel with gate and drain cross-coupled
MOS transistors NT1 and NT2 are included. Tiger
Transistors PT1 and NT1 are connected in series,
The transistors PT2 and NT2 are connected in series. In addition to the sense amplifier SA,
Conducted in response to amplifier activation signal / SOP, power supply potential
P-ch for transmitting the Vcc level potential to sense amplifier SA
Channel MOS transistor PAST (PASTa, PA
STb) and the sense amplifier activation signal SON
N channel for conducting and transmitting ground potential to sense amplifier SA
Flannel MOS transistor NAST (NASTa, NAS
Pb) is provided. Transistor NAST is conducting
, The corresponding bit line pair BL and / BL
The bit line with a lower potential to the ground potential level.
It is. When the transistor PAST turns on, the corresponding bit
The high potential bit lines of the pair of gate lines BL and / BL are at the power supply potential.
It is charged to the Vcc level. Sense amplifier activation signal
The signals SON and / SOP are used in this semiconductor memory device.
The selected (activated) memory array MA
(Only active). Non-selection
The sense amplifier activation signal is transmitted to the memory array MA.
It is not reached and maintains the precharge state. Therefore,
The sense amplifier drive signals SON and / SOP are
Contains information identifying the activated memory array
Can be considered. A group provided in word line shunt region WS
The global IO line pair GIOa and / GIOa
Block that conducts in response to the sense amplifier activation signal SON.
Local IO line pair LIOa and LIOa
/ LIOa. Block selection gate BS
Changes the local IO line LIOa to the global IO line GIO
transistor BST2 connected to the global IO
To connect the line / GIOa to the local IO line / LIOa
Including the transistor BST1. As described above, the sense amplifier drive signal SO
N is active only for the selected memory array MA
State. This sense amplifier drive signal is applied to the local IO
Used as a connection control signal between the line and the global IO line
If the local I associated with the selected memory array MA
O line pair LIO is connected to global IO line pair GIO
You. Local IO line pair LIO and global IO line pair GI
It is necessary to provide a dedicated signal line for controlling the connection with
No longer necessary, reducing the area occupied by the sense amplifier rows
be able to. [Embodiment 6] FIG. 16 shows bit lines and local
FIG. 2 is a diagram showing a connection configuration of a global IO line and a global IO line.
is there. The configuration shown in FIG. 16 is similar to that shown in FIGS.
It corresponds to the combination of the configuration shown. In FIG. 16, bit line pair BLa and
/ BLa is a bit line equalize / precharge
Bit lines BLa and / BL in response to
A precharge circuit BEQ for precharging a is provided.
It is. The precharge circuit BEQ is also connected to the bit line BL
a and complementary bit line / BLa equalize / precharge
Equalize tiger electrically connected in response to signal φEQ
Transistors may be included. Bit lines BLa and / BL
a between the local IO lines LIOa and / LIOa
Column selection gate CS that conducts in response to column selection signal CSL
G is provided. The local IO line LIOa has a bit
Line in response to the line equalize / precharge signal φEQ.
-Precharge bit line DBLa to predetermined potential Vbl
And the potential on the dummy bit line DBLa is lowered.
Equalizing / pre-charging transmitted on the cull IO line LIOa
A storage circuit DEQ is provided. Local IO line LIOa
Between the local IO line / LIOa and the local IO line
Conducted in response to equalize signal φLEQ, causing local I
Icon for electrically connecting O lines LIOa and / LIOa
Rise transistor LEQ is provided. Local IO lines LIOa and / LIOa
Between global IO lines GIOa and / GIOa
At the same time in response to the sense amplifier activation signal SON.
A block selection gate BS is provided. Global IO
Lines GIOa and / GIOa have global IO line I
Conduction occurs in response to the rise signal φGEQ, and this global
IO lines GIOa and / GIOa are set to a predetermined potential Vcc /
Globalizer that precharges and equalizes to 2 potentials
Equipped with IO line equalize / precharge circuit GEQ
It is. Next, the operation of the connection configuration shown in FIG.
This will be described with reference to FIG. 17 which is a waveform diagram. In the standby state, signals φEQ,
φLEQ and φGEQ are both at “H”, while
The sense amplifier activation signal SON is at the “L” level.
In this state, equalize / precharge circuit B
EQ, DEQ, GEQ and equalizing transistor L
EQ is in an active state, and bit lines BLa, / BLa,
Local IO lines LIOa, / LIOa and global I
O lines GIOa and / GIOa are all at a predetermined potential Vbl.
(= Vcc / 2). Dummy bit
At this time, the line DBLa is also equalized / precharged.
Precharged to a predetermined potential Vbl by the circuit DEQ
I have. In operation, first, signal φEQ is
Fall to "L", precharge / equalize circuit BE
Q is deactivated. Thereby, the bit line BL
a, / BLa are floating at the precharge potential
It becomes. Next, a word line is selected, and its potential is
To rise. As the word line potential rises, the memory cell
Data is read out by the corresponding bit line. FIG.
As a result, data “0” is read in the bit line pair BLP.
One example is the potential change of the bit line pair BLP in the output state.
Shown. Make sure that the potential difference between the bit line pairs is
Then, sense amplifier drive activation signals SON and / SO
P is generated. In FIG. 17, the sense amplifier driving activity
Only the activation signal SON is shown. This sense amplifier activation signal
Signal SON in response to the signal SON.
The operation is performed, and the potential difference on the bit line is further amplified.
You. At this time, the sense amplifier activation signal S
The block selection gate BS is turned on in response to ON.
Local IO line LIO and global GIO line pair GI
Connect to O. Next, signals φLEQ and φGEQ are non-active.
Is activated, and the column select line CSL is activated in accordance with the column select signal.
Column rises to “H”, and column select gate CSG is conductive
It becomes. Thus, the signal on the selected bit line pair BLP is
Signal is the local IO line pair LIO (LIOa and / LIO
a) is transmitted on. In FIG. 17, the local IO line pair
The potential amplitude of LIO is smaller than that of bit line pair BL.
Are the sense amplifiers provided for the bit line pairs.
Is the global IO line pair GIO and the local IO line pair L
IO must be driven together, and global IO
The line pair is provided with a clamp transistor (not shown).
Because it is. Signal potential is transmitted to local IO line pair LIO
When the block selection gate BS is already turned on,
This potential is immediately applied to the global IO line pair G
It is transmitted to IO. In this state, data reading
Performed or written via a preamplifier not shown
When the write data from the buffer is
Data transmitted to the Cal IO line pair and the bit line pair BL
Is written. As described above, the local IO line pair LIO
Perform recharge using dummy bit lines and block
Control signal to control the conduction of the clock select gate.
The signal for transmitting the control signal by using
The number of wires can be reduced and the
The number of transistors can be reduced, and the sense amplifier
Area and / or plane of word line shunt area for
Reduce chip area without increasing product
Can be. [Specific Configuration of 32K Bit Array] FIG.
The difference from the arrangement shown in FIG. Local I
A block for connecting the O line pair to the global IO line pair
The select gate BSG is connected to the sense amplifier activation signal SON.
Conducts in response. Used compared to the configuration shown in FIG.
The number of control signals is low. That is,
The clock selection signal φB (see FIG. 10) is
Has been replaced by a number. The local IO line pair LIO is
Precharge transformer for precharging to a predetermined potential
The transistor is a transistor provided on the dummy bit line DBL.
Using the DEQ. Word line shunt area and
The area of the sense amplifier array area can be reduced.
You. In operation, the operation is the same as that described above.
However, if this memory array is selected,
Select signal φAa maintains the “H” state, and the remaining array selection
The selection signals φAb and φAc fall to “L”. Remaining
For unselected memory arrays, this array select signal is
"H" is maintained, and the precharge state is maintained.
An unselected memory array associated with the selected memory array
Only the sense amplifier is disconnected. After that,
And the sense operation by the lower sense amplifier SA is performed.
Connection between local IO line pairs and global IO line pairs
Is performed in response to sense amplifier activation signal SON.
You. This operation is not limited to SDRAM,
The same applies to array selection and memory cell sensing.
As far as the behavior is concerned). Therefore, the local IO line pair
Connection with global IO line pairs and bit line pairs and local
In this embodiment of connecting and precharging with the IO line pair
Configuration can be applied to standard DRAM
it can. [Global IO lines and data input / output terminals
Correspondence] Eight bits by one column selection line CSL
Select line pair BLP, 4 lines in one memory mat
Column selection line CSL is selected. Two memory maps
Are activated simultaneously, so a total of 64 bits of memory
The cell can be accessed by specifying the address once.
Wear. As shown in FIG. 20, one column select line CS
L corresponds to eight pairs of global IO lines. One memory
One in each array group AG in mat MM
Column selection line CSL is selected. Array Group AG
(See FIG. 7) Eight pairs of global IO lines GI
O0 to GIO7 are provided. Two memory maps at the same time
MMA and MMB are selected. Therefore, the sum
64 global IO line pairs GIO are accessible
is there. These 64 global IO line pairs, that is, 64
Between the memory cell of the unit and the data input / output terminal DQ
Various methods can be considered. Hereafter this data
The correspondence between the output terminal DQ and the 64-bit memory cell
This will be briefly described. (1) Method 1 There are eight data input / output terminals DQ, DQ0 to DQ7.
I do. In this method 1, one column select line CSL
Eight corresponding global IO lines GIO0-GIO7
To 8 data input / output terminals DQ0 to DQ7 respectively
Correspond. This correspondence is shown in FIG. In the case of the correspondence shown in FIG.
Data input / output terminals DQ0 to DQ7 are provided by column selection line CSL.
Global IO line pairs at the same time
You. In this case, the wrap length (for continuously accessible data
Can be easily changed if the number changes)
You. That is, for example, if the wrap length is 8, select a column
By simultaneously selecting eight lines CSL, eight
It is possible to continuously map continuous data to the column selection line sequentially.
it can. If the wrap length is 4, the column selection lines must be
What is necessary is just to make it into a full selection state. A column selected according to the change of the wrap length
The configuration for changing the number of selection lines is based on the lap length setting information and
Column address bit applied to the system decoder for 1 bit
That are simultaneously selected in the column decoder.
What is necessary is just to change the number of phase decoder circuits. That is,
Provided corresponding to ray group or memory mat
1 according to the wrap length setting information for the column decoder
If a bit column address is given as an activation signal,
Change the number of selected column selection lines according to the wrap length.
Can be. In this case, the preamplifier PA or line
The buffer WB is sequentially arrayed in synchronization with the clock signal.
Continuous data writing / reading can be performed by switching each loop.
Can be manifested. (2) Method 2 In the second method, as shown in FIG.
The line CSL corresponds to one data input / output terminal DQ.
That is, when the wrap length is 8, the global IO line pair GIO
0 to GIO7, 8
Set lap data. In the case of this configuration, one array group A
G, the preamplifier PA or the write buffer WB
Are sequentially activated. As shown in FIG. 22, one column selection line is
When associating with two data input / output terminals DQ, for example,
It is possible to easily cope with the write per bit operation.
In the write per bit operation, the data input / output terminal D
Write data independently for each of Q0 to DQ7
Prohibited. In this case, the data for which data writing is prohibited
Column select line CSL corresponding to the data input / output terminal DQ
Can be used. [Bank Configuration] In SDRAM,
The rearray is divided into a plurality of banks. Each bank
Precharge operation and activation operation (
(E.g., select a logic line, activate a sense amplifier, etc.)
Is needed. In the arrangement shown in FIG.
Memory mats MM1 to MM4 of two banks # 1
And # 2. Bank # 1 is a memory mat M
M1 and MM2, and bank # 2 has a memory map
MM3 and MM4. In this configuration, the row decoder and
Column decoders are set for each memory mat.
The internal data transmission line is also provided for each memory mat.
They are independent and satisfy the conditions of the bank. Further, in the configuration shown in FIG.
I / O circuit P including amplifier PA and write buffer WB
W is also provided for each memory mat.
In which bank # 1 and bank # 2 are accessed alternately.
It is also possible to realize a tarley operation. That is, for example, access to bank # 1 is performed.
Precharging bank # 2 while accessing
it can. In this case, when bank # 2 is precharged
Can be accessed without hassle. Bank # 1 and
Execute access and precharge alternately for # 2
Required before access in DRAM
Time loss due to precharge
High-speed access can be realized. In a standard DRAM, the same chip
The constructed DRAM is reduced to 8 × by wire bonding.
Switching between the configuration and the × 4 configuration is often performed. Through
Usually, the internal circuit is configured to operate in the × 8 configuration.
And a specific pad is connected to the power supply potential Vcc or the ground potential Vs
s, the internal configuration is changed to × 4 configuration.
You. In this case, the special among the 8-bit internal data transmission buses
By setting the potential by wire bonding of fixed pads
Only 4-bit data bus is selectively data input / output pin
A configuration that is connected to may be used. Generally, × 4
When converted to configuration, memory array activation is also × 4 configuration
Is converted to correspond to [Functional Configuration of SDRAM] FIG.
Block functionally showing the configuration of the main part of the SDRAM according to
FIG. In FIG. 1, the SD of a × 8-bit configuration
Functional configuration related to 1-bit input / output data of RAM
Is shown. Array related to data input / output terminal DQi
The part includes a memory array 1a constituting bank # 1, and a
And a memory array 1b forming link # 2. For memory array 1a of bank # 1
Decodes the address signals X0 to Xj and
X constituting a row decoder for selecting the corresponding row of Ia
Decoder group 2a and column address signals Y3 to Yk are decoded.
Column selection signal for selecting the corresponding column of the memory array 1a
Decoder group 4 forming a column decoder for generating a signal
a and a memory connected to a selected row of the memory array 1a.
Sense amplifier group 6a for detecting and amplifying data of the memory cell
including. The X decoder group 2a is provided for each channel of the memory array.
X decoder provided corresponding to the read line. Address
Corresponding X decoder is selected according to the
And the corresponding word line is selected. Y deco
D group 4a is provided with Y data provided for each column selection line.
Including coder. One column selection line CSL has eight pairs of bit lines
Is selected. X decoder group 2a and Y decoder
By the group 4a, an 8-bit memory is stored in the memory array 1a.
The memory cells are simultaneously selected. X decoder group 2a
And Y decoder group 4a are provided with bank designating signal B1
Activated by For bank # 1, a sense amplifier is further provided.
While transmitting the data detected and amplified by the group 6a,
Write data to a selected memory cell in memory array 1a
Internal data transmission line (global IO
Line GIO). This global IO line
Bus GIO includes eight pairs of global IO lines. For data reading, this global IO
The data on the line bus GIO is transferred to the preamplifier activation signal φPA
Preamplifier group 8a activated and amplified in response to 1
To store the data amplified by the preamplifier group 8a.
Read register 10a and read register 10
output buffer for sequentially outputting data stored in a
12a is provided. Preamplifier group 8a, lead
The register 10a and the output buffer 12a
8 bit width for each global IO line pair
Is provided. The read register 10a is a register register
Output signal of the preamplifier group 8a in response to the activation signal φRr1.
Latch data and output them sequentially. The output buffer 12a
In response to the output enable signal φOE1, the read register
The 8-bit data stored in the master 10a is sequentially
The signal is transmitted to the input / output terminal DQi. Data input / output terminal DQi
, Data input and data output are performed in common.
Is To write data, an input buffer
Is activated in response to the
From input data applied to output terminal DQi to write data
1-bit input buffer 18a for generating
Is activated in response to the
Write data for sequentially storing the write data from the
In response to the write buffer activation signal φWB1.
Is activated and stored in the write register 16a.
Amplified data is transmitted to global IO line pair GIO
Write buffer group 14a. Write buffer group 1
4a and the write register 16a each have 8 bits
Have a width. Similarly, bank # 2 has X decoder group 2b, Y decoder
Decoder group 4b responds to sense amplifier activation signal φSA2.
Sense amplifier group 6b activated in response to the
Preamplifier group activated in response to activation signal φPA2
8b, activated in response to register activation signal φRr2
Read register 10b, output enable signal φO
The output buffer 12b and the buffer activated in response to E2
Write activated in response to the activation signal φWB2
Buffer group 14b responds to register activation signal φRw2
Register 16b, which is activated by
Input buffer 1 activated in response to activation signal φDB2
8b. Configuration for bank # 1 and bank # 2
The configuration is the same. Read registers 10a, 10
b and the write registers 16a and 16b
Wrap data for continuous access
Register. Control signals for banks # 1 and # 2
In response to the bank designation signals B1 and B2
Only the control signal for one of the banks is generated
You. In correspondence with the chip arrangement of FIG.
Register 10a, 10b, write register 16
a, 16b, input buffers 18a, 18b, output buffer
The drivers 12a and 12b are arranged in the peripheral circuit PH. Preah
Pump groups 8a and 8b, and write buffer groups 14a and
And 14b are arranged in the input / output circuit PW. This function block 200 is used to input / output each data.
Provided for force terminals. Function for × 8 bit configuration
Eight blocks 200 are provided. As described above, bank # 1 and bank #
2 have substantially the same configuration, and the bank designating signals B1 and B2
By activating only one of them, bank # 1 and bank # 1 are activated.
And # 2 can operate almost completely independently of each other
It works. Further, data reading register 10a and
10b and registers 16a and 16b for writing data
Separately and for each bank # 1 and # 2.
Is used to switch data read and write and
Accurate data without data collision during switching
Data can be read and written. Bank # 1 and bank # 2 are independent
Externally as a control system for activating the memory array
, Ie, external row address
The strobe signal ext. / RAS, external column address
The strobe signal ext. / CAS, external output enable
The signal ext. / OE, external write enable signal (write enable
Signal) ext. / WE and the mask instruction signal WM.
For example, an external clock signal CLK which is a system clock
In synchronization with the internal control signals φxa, φya, φW,
First control signal generating circuit 2 for generating φO, φR, φC
0, bank designation signals B1 and B2, and internal control signal
φW, φO, φR, and φC and clock signal CLK
In response, banks # 1 and # 2 are independently driven
Amplifier activation signal φS
A1, φSA2, preamplifier activation signals φPA1, φP
A2, write buffer activation signals φWB1, φWB2,
Input buffer activation signals φDB1, φDB2,
Output buffer activation signals φOE1 and φOE2.
2 control signal generating circuits 22. Internal control signal φW is external write enable signal ex
t. / WE is an internal write enable signal generated in synchronization with / WE
You. Internal control signal φO is external read enable (read enable
F) signal ext. Internal read generated in synchronization with / OE
This is a permission signal. The internal control signal φR is
The strobe signal ext. Generated in sync with / RAS
Internal row address strobe signal (internal RAS signal)
It is. The internal control signal φC is applied to the external column address
The lobe signal ext. Internal generated in synchronization with / CAS
Column address strobe signal (internal CAS signal)
You. The internal control signals φxa and φya are
Unit control signal ext. / RAS and ext. / CAS
Synchronous internal address buffer activation signal
is there. The second control signal generation circuit 22 is connected to the bank finger.
According to the fixed signals B1 and B2, the designated bank
Is activated only. Second control
The timing of the control signal generated by the signal generation circuit 22 is
It is controlled by the lock signal CLK. For example, read permission
The signal φOE1 or φOE2 is an external row address signal.
The lobe signal ext. / RAS (or internal row address)
After the strobe signal φR) is activated,
It is generated after counting the signal CLK for 6 times. Also,
Write buffer activation signal φWB1 or φWB2
In response to the clock signal after eight pieces of embedded data are given
Generated. That is, external write enable signal ext. / W
After E becomes active, the clock counts eight CLKs.
To the selected memory cell in the memory array after
Is transmitted. This is lap length 8
It is assumed that in normal operation mode,
The SDRAM operates assuming length 8. [0146] The SDRAM further includes internal circuits as peripheral circuits.
External address signal ex in response to the external control signal φxa.
t. A0 to ext. Ai internal address signal
X0 to Xj and bank select signals B1 and B2
X address buffer 24 and an internal control signal φya
Column address to specify the column selection line.
Y3 to YK and the first bit at the time of continuous access
Bits Y0 to Y for wrap address designating a line pair (column)
2 for generating a Y address buffer and a clock signal
CLK, the wrap address bits Y0 to Y0
Decode Y2 and wrap addresses WY0-WY7,
For controlling the load registers 10a and 10b
Drive signals φRr1 and φRr2, and write signals
Control signal for driving registers 16a and 16b
Register control circuit 2 for generating φRw1 and φRw2
8 inclusive. The bank is specified to the register control circuit 28 again.
Signals B1 and B2 are applied to the selected bank.
Is used only when the register drive signal is generated.
It may be. Next, a specific internal operation will be described. [Continuous Write Mask Function]
In normal operation mode, one data input / output
8-bit data is continuously written to the
You. For example, even-numbered bytes in a series of data strings
If you want to rewrite only the
Then, if you apply a mask, only the desired even-numbered data
Is rewritten. In this continuous access operation,
The configuration for masking the byte data of
This is described below. FIG. 23 shows a mask at the time of a continuous address.
It is a timing chart which shows operation | movement which multiplies. Figure 23
Therefore, all control signals are external control signals.
The symbol “ext.” Indicating that this is a unit control signal is omitted.
You. At the time of data write operation, first, external row address
The strobe signal / RAS falls to "L". to this
External address ADD is taken as row address signal Xa.
And an internal row address signal is generated. Follow this
Select bank and memory in selected bank
Activate the array (select word lines and activate sense amplifiers)
Drive). Next, an external column address strobe signal
/ CAS and external write enable signal / WE fall to "L"
I'm sorry. Here, usually, the external row address
External column address after trobe signal / RAS falls
Necessary before falling strobe signal / CAS
RAS-CAS delay time tRCD is 2
A clock cycle. When write enable signal / WE falls to "L"
This activates the input buffer in the selected bank.
And the data is written to the write register. This
The write position of data to the write register of
When the address strobe signal / CAS falls
Within the range generated by the fetched external address signal ADD
By the lower three bits Y0 to Y2 of the row address signal Yb
It is specified. Next, it is input at the rising edge of the clock signal.
Data is sequentially written to the write register via the output buffer.
Be included. Thereby, 8 bytes of data b0 continuously
b7 is written. 8-byte data b0 to b7 are written
After being selected, the already selected 64-bit memory cell
This 8-byte data is simultaneously written to the file. This selection
Transmission of write data to the selected memory cell is write enabled.
Clock signal CL after signal / WE falls to "L"
Rise of the next clock signal CLK after counting K for 8
This is done in response to the glue. At the time of this continuous write operation,
When masked write operation that masks data
The external mask corresponding to the data to be masked.
The disk instruction signal WM rises to "H". In FIG.
Are the second byte data d1 and the fifth byte data
The case where a mask is applied to the tab d4 is shown. This place
In this case, 64-bit memory cells are simultaneously selected.
However, the write data is not transmitted to the corresponding memory cell.
Not. In this case, the note corresponding to the masked data
Only the rewriting operation is performed on the recell. next
A structure for applying a mask during this continuous write operation
The configuration will be described. FIG. 24 is a diagram showing a mask in a continuous write operation.
FIG. 2 is a diagram showing a circuit configuration for realizing an
You. FIG. 24A shows the write register 16 and the input buffer.
18 is shown. The input buffer 18 is a data input / output terminal.
Captures input data given to child DQi and writes write data
Generate. The input buffer 18 receives the input buffer activation signal.
Activated in response to signal φDB. This input buffer activity
Activating signal φDB is the second control signal generating circuit shown in FIG.
22 is generated in response to the internal write signal φW. Entering
The output of the force buffer 18 has an 8-bit unit register.
To the write register 16. Regis for light
Data 16 is activated among wrap addresses wy0 to wy7.
To the unit register corresponding to the wrap address
Latches the write data from the input buffer 18 of FIG. La
The write register 16 receives a write register activation signal φR
w in response to write data WD0-W
Generate D7. No wrap address wy0-wy7
Only one of them is activated. Each clock cycle
Each time the activated wrap address is shifted
You. FIG. 24 (B) shows a method for generating mask data.
FIG. 3 is a diagram showing a configuration for the second embodiment. In FIG. 24B,
The data generation system responds to the input buffer activation signal φDB.
Activated to take in the write mask instruction signal WM
Write mask data generation to generate write mask data
Circuit 160 and the write mask data generation circuit 160
Mask register that takes in the write mask data from
Data 162. The write mask register 162 has 8 bits.
Includes the unit register of the unit. Write mask register 16
In step 2, before the write operation starts, each unit is
Position register is set, and the held data is set to “1”.
Is set. When the data held in the unit register is "1"
In this case, writing is prohibited, and when the held data is "0",
Is written. The write mask register 162 stores
Write mask data from the mask data generation circuit 160.
Data sequentially in accordance with the wrap addresses wy0 to wy7.
Store in register. Protection of the write mask register 162
Data in response to the write mask register activation signal φWM.
And at the same time output as mask data MD0-MD7.
It is. The write mask register activation signal φWM is
Timing almost same as write register activation signal φRw
Generated by This write mask register 162
The mask data MD0 to MD7 held will be described later.
Is transmitted to the write buffer and the corresponding write buffer
Control the output of the key. FIG. 24C generates a wrap address.
FIG. In FIG. 24 (c),
A 3-bit internal column address Y0
Wrap address decoder 166 for decoding .about.Y2
Latch the output of the wrap address decoder 166,
And latch data sequentially in response to clock signal CLK.
It includes a wrap address register 164 to shift. Luck
Address decoder 166 has a 3-bit column address Y0.
~ Y2 and one of its outputs y0-y7
Only the selected state is set. The wrap address register 164 has eight stages.
This wrap address decoder has a shift register configuration.
Latch the outputs y0 to y7 of the
And then sequentially shift according to the clock signal CLK.
You. Each unit shift of the wrap address register 164
Memory cell location where data is first written from the register
Wrap addresses wy0 to wy7 are generated. La
The address register 164 is provided in the configuration shown in FIG.
In the register control circuit 28. Light mask cash register
The star 162 generates the first control signal in the configuration of FIG.
A second control signal generating circuit which may be included in the raw circuit 20;
22 may be included. Next, the mask shown in FIG.
The operation type of the circuit that realizes the write function
This will be described with reference to FIG. Now, FIG.
As shown in the figure, the second input data d1 and the fifth input data d1
Consider a case where a mask is applied to the input data d4. The wrap address decoder 166 has three bits.
Decodes the internal column addresses Y0 to Y2 of the
The dresses y0 to y7 are generated. Now, 3-bit column address
(Y0, Y1, Y2) = (0, 1, 0)
Then, first, from the wrap address decoder 166,
Is set to the selected state. This output signal y2
Is taken into the wrap address register 164. Wrap
Wrap address wy2 of address register 164 is selected
State. Thereafter, the clock signal CLK is toggled.
Every time the wrap address register 164 outputs
Address is sequentially wy3 → wy4 → wy5 → wy6 → w
It is activated as y7 → wy0 → wy1. The mask bit instruction signal WM from the outside is
Generated corresponding to the input data d1 and d4. Lightma
In the register 162, the write enable signal / WE
In response, the data held in each unit register is set to “1”.
It is. Each unit register of the write mask register 162
Is the write mask data according to the wrap address wy.
The write mask data WM from the generation circuit 160 is stored.
You. Therefore, in the write mask register 162,
Indicates that the mask data MD3 and MD6 are write-protected
The active state becomes "1", and the remaining mask data MD2,
MD4, MD5, MD7, MD0 and MD1 are writable
Data "0" indicating the enabled state is stored. The write register 16 stores the input buffer 1
Wrap addresses wy0 to wy
7 is stored. 8-bit data has been written
Then, in response to the rising of the clock signal CLK, the write
Register activation signal φRw and write mask register activation
Activation signal φWM is activated, and is stored in each register.
The stored data is transmitted to the write buffer in parallel.
You. As described in detail later, the write buffer
Write data WD according to mask data MD0 to MD7 of
0 to WD7 are transmitted to the corresponding global IO line pair GIO
You. FIG. 26 shows the write register shown in FIG.
FIG. 14 is a diagram illustrating a configuration of 16 unit registers. In FIG.
And the unit write register receives data from the input buffer 18.
The write data D is passed in response to the wrap address wyi.
N channel MOS transistor 216
Latch the write data transmitted via the star 216
Circuit that constitutes an inverter latch circuit for
217 and 218 and this inverter latch circuit (I
Inverters 217 and 218)
The output of the inverter circuit 219 and the inverter circuit 219
Output in response to the register activation signal φRw.
Including a channel MOS transistor 220. Inverter times
The output of path 217 is coupled to the input of inverter circuit 218.
The output of the inverter circuit 218 is
7 inputs. In operation, this unit register is
When the wrap address wyi is activated ("H")
Input data 18 from the input buffer 18
Latch by an inverter latch circuit. Activation signal φRw is
When activated, transistor 220 is turned on to enable internal write data.
Data WDi is generated. In the configuration shown in FIG.
The transistor 220 is the input of the inverter circuit 219.
And an inverter latch circuit (the inverter circuit 217 and
218). Also Inva
Input section of the data latch circuit (input of the inverter circuit 217)
Is normally precharged to a predetermined potential.
May be used. FIG. 27 shows the light mask register shown in FIG.
FIG. 3 is a diagram showing a configuration of a unit register of a star. In FIG.
And the unit mask register corresponds to the wrap address wyi.
In response, the write mask data generation circuit 160 generates
N channel MOS transistor for passing the mask data M
Given through a transistor 222 and a transistor 222
Inverter latch circuit to latch the mask data
Inverter circuits 226 and 228 forming a path,
In response to the unit mask register activation signal φWM,
Output of inverter latch circuit (of inverter circuit 226)
Output) to generate mask data MDi
Channel MOS transistor 230 and responds to set signal
To the input section of the inverter latch circuit (inverter circuit 2
26 input) to the ground potential.
And a transistor 224. Set signal is row address
It may be generated in response to strobe signal / RAS.
Before the write mask data M is generated, the
The input of the inverter latch circuit is set to ground potential
It should just be done. In operation, first, the set signal is
The potential of the input section of the inverter circuit 226 is set to the ground potential.
It is. This allows the data to be written to the unit write mask register.
“1” is initialized. Next, the wrap address wy
i, the transistor 222 conducts, and the light mask
The mask data M from the data generation circuit 160 is inverted.
To the input section of the data circuit 226. Transistor 224
It is already off. This allows the mask date
M is latched by inverter circuits 226 and 228
Is done. Write mask register activation signal φWM is activated
Transistor 230 is turned on,
Write mask instruction by passing output of barter circuit 226
The signal MDi is generated. FIG. 28 shows the wrap address register shown in FIG.
FIG. 14 is a diagram showing a configuration of a unit register of a star 164. FIG.
8, the unit wrap address register stores the large drive
Inverter circuit 232 having dynamic capability and relatively small drive
An inverter circuit 234 having a dynamic capacity and a clock signal
Transmits the output of inverter circuit 232 in response to CLK
N-channel MOS transistor 238
Relatively large to invert the signal transmitted through the
An inverter circuit 240 having an appropriate driving capability;
Relatively small driving ability to invert the output of the data circuit 240
And an inverter circuit 242 having the following. The output of inverter circuit 232 is a transistor.
To the inverter 234.
Is given to the input. The output of inverter circuit 234 is
It is provided to the input of an inverter circuit 232. Unit Wrap
The dress register further wraps in response to the set signal
The selection signal yi generated from the address decoder 166 is
Including an n-channel MOS transistor 236
No. The output of this transistor 236 is the inverter circuit 2
32 and the output of the inverter circuit 234.
It is. From the output of this inverter circuit 234,
Less wyi is generated. Applied to the gate of transistor 236
The set signal activates the wrap address decoder 166
Generated for a predetermined period in response to a control signal for
A one-shot pulse signal may be used. Also Kora
In response to activation of the address strobe signal / CAS.
One generated at the rising edge of clock signal CLK
Shot pulses may be used. Next, about operation
explain. When the set signal is activated, the
The transistor 236 is turned on, and the wrap address
The output yi of the coder 166 is taken and latched. This capture
The output signal yi is output as a wrap address wyi.
You. When this set signal is generated, the clock signal
CLK is “H” and complementary clock signal / CLK is “L”
is there. The output of the inverter circuit 232 is the transistor 2
38 to the inverter circuit 240,
Data circuits 240 and 242. Next, clock signal CLK falls to "L".
And complementary clock signal / CLK falls to "H"
And the output of this inverter circuit is
Transmitted to the address register and the adjacent wrap address is
It becomes active. Inverter circuit 240 is relatively large
It has a driving force, and the adjacent unit lap address register
Of the inverter latch circuit provided at the input
Correct the latch state according to its output state. to this
Wrap address sequentially according to the clock signal CLK.
Are activated. In the above-described wrap address generation system,
The initially set wrap address wy is used as the initial address.
Adjacent rows are selected in sequence, and the wrap address
The method of occurrence is unique. Occurrence order of this wrap address
An introductory programming arrangement may be used. [Write Buffer] FIG. 29 shows a write buffer.
FIG. 3 is a diagram illustrating a configuration of a key. Write buffer group shown in FIG.
14 has eight write buffers shown in FIG.
Referring to FIG. 29, the write buffer includes a write register
16 receiving write data WDi from memory 16
, Write buffer activation signal / φWB, and write
Receiving the mask data MDi from the register 162
A two-input NOR circuit 61 and an output of the NOR circuit 61
Including an inverter circuit 62. Write buffer control signal
/ ΦWB is activated when it becomes “L”, and data
Instruct writing. The write buffer further includes a power supply potential Vc
p channel cascade-connected between c and ground potential Vss
MOS transistors 63 and 64 and n-channel MO
S transistors 65 and 66 are included. Transistor 6
The output of the inverter circuit 60 is applied to the gates of 3 and 66.
Given. Inverter to gate of transistor 64
The output of circuit 62 is provided. Transistor 65 gate
The output of the NOR circuit 61 is provided to the gate. The write buffer further includes power supply potential Vcc
P-channel M cascade-connected between ground and ground potential Vss
OS channels 67 and 68 and n-channel MOS transistor
Transistors 69 and 70. Transistor 67 and
Write data WDi is applied to the gates of
The output of inverter circuit 62 is applied to the gate of
Output from the NOR circuit 61 to the gate of the transistor 69.
Power is given. Transistor 64 and transistor 65
Is connected to one of the global IO line pairs GIO
Connected to the IO line GIOi, and the transistor 68 and
69 connection points are connected to the other global IO line / GIOi
Is done. Next, the operation will be described. (I) Mask data MDi is "1"
("H") and specifies the mask for the write data.
Think about it. In this case, the output of the NOR circuit 61
Becomes “L” and the output of the inverter circuit 62 becomes “H”.
Become. This allows transistors 64, 65, 68 and
And 69 are turned off and the global IO lines GIOi and
And / GIOi attain the potential holding state at that time, and write
No data is transmitted. (Ii) When the mask data MDi is "0"
Write data WDi is at "L" level indicating "0"
, The output of the inverter circuit 60 becomes “H”. this
In the case, the transistor 63 is off and the transistor 6
6 is on, transistor 67 is on, transistor
The star 70 is turned off. Global IO line GIOi
Is discharged through transistors 65 and 66 to ground.
The potential becomes the “L” level of the potential Vss level and the global I
O line / GIOi is connected via transistors 67 and 68
It is charged to "H". With the above-described configuration, there is a problem in continuous writing.
It is possible to mask only the desired data
You. [Frequency-Latency] In SDRAM
In some cases, the output timing of read data is
The number is determined by the number of toggles of the signal CLK. Of this clock
Relationship between number of toggles and read data output timing
Is called latency. For example, the clock signal CLK
When the frequency is 100 MHz, external row address storage
6 clocks from the cycle in which the slave signal / RAS falls
Valid data is output at the cycle. However, the frequency of the clock signal CLK is
When using this SDRAM in a 50 MHz system
In this case, the external row address strobe signal / R
Read data after 6 clock counts from AS falling
Is output, the access time becomes 120 nanoseconds.
The SDRAM performance of high-speed operation
Can not be. Even if the clock frequency changes
To fully exploit the high-speed performance of SDRAM
The configuration that can be performed will be described below. FIG. 30 shows an SDRAM according to the present invention.
FIG. 3 is a diagram illustrating a relationship between frequency and latency. Leyte
Is determined by the combination of address bits A4 and A5.
Is determined. This latency set cycle corresponds to the clock signal.
The signals / RAS, / CAS and
And / WE are all set to "L" under the condition of WCBR
Be executed. When the clock frequency is 100 MHz, R
The AS access time tRAC is 6 clock cycles.
And the CAS access time tCAC is four clock cycles.
RAS precharge cycle time is 4 clocks
Cycle and the RAS-CAS delay time tRCD is minimized.
Set to two clock cycles. Hereinafter, the clock signal C
As the frequency of LK decreases, each access time and
And the number of clock cycles required for precharge time
Frustrate FIG. 31 shows the RAS access time, CA
S access time and RAS precharge time
FIG. 3 is a diagram illustrating a RAS-CAS delay time tRCD. The RAS access time tRAC corresponds to the external row.
Address strobe signal / RAS falls to "L"
Is the time required until valid data is output from
Yes (in SDRAM, all clock cycles
). The CAS access time tCAC is equal to the column access time tCAC.
Does the dress strobe signal / CAS fall to "L"?
Is the time required for valid data to be output. R
The AS precharge time tRP precharges the memory array.
Signal / RAS is maintained at "H".
It is the time needed to hold. RAS-CAS late
The delay time tRCD is determined by the row address signal and the column address signal.
These addresses must be multiplexed and given.
Required to ensure that the source signal is separated and set to a defined state
And the external address strobe signal / R
After the fall of AS, the column address strobe signal
/ CAS is required to fall to "L"
You. Next, to change this latency according to the frequency
Will be described with reference to FIG. In FIG. 32, the latency changing circuit
WCBR detection circuit 38 for detecting the condition of WCBR
0 and the address signal bit in response to the clock signal CLK.
Address set circuit 382 which takes in A4 and A5
And activated in response to the output of WCBR detection circuit 380.
Address latched by the address set circuit 382.
Latency to decode bits and detect latency
Decoder 384 and the latency decoder 384
Adjust the output timing in response to the intensity setting signal
An output control circuit 386 is included. The output control circuit 386 corresponds to FIG.
Internal control signal from the first control signal generation circuit 20 shown in FIG.
In response to φR (or int.RAS), a predetermined number of clocks
Output buffer control signal by counting lock signal CLK
Generates φOE. The output control circuit 386 counts
The number of clocks is the latency from the latency decoder 384.
It is adjusted according to the setting signal. The address set circuit 382 has an address
The internal address bits A4 and A5 from the buffer
In response to the WCBR detection signal from the BR detection circuit 380
A latching configuration may be used. In this case smell
Data output timing when the latency is changed
Is only adjusted according to the clock count.
You. The internal control signal φR
Especially when executed in response to
384 output to RAS control system and CAS control system
No need to be given. Sense amplifier activation timing
And the clock generation timing of the column selection signal
This latency, if set according to the number of
Each cell is set according to the latency setting signal from the decoder 384.
Generation timing of sense amplifier activation signal and column selection signal
Is adjusted. Clock counting in this case as well
Only the numbers are changed. As described above, the frequency of the clock signal CLK is
By adjusting the data output timing according to the number
Irrespective of the frequency of the clock signal CLK,
The performance of M can be sufficiently brought out. [Lap Length Change] In the above description,
The lap length is set to 8. However, once
Number of data continuously written in access cycle
May be variable in each case. For example
Even in standard DRAM, nibble mode and page mode
Mode, static column mode, and the like.
In this case, data written or read continuously
The number of can be easily changed, except for nibble mode
You. Therefore, the lap length can be changed even in SDRAM.
Configuration is provided. FIG. 33 shows a program for programming the lap length.
It is a figure which shows a law in a list. Wrap length is WCBR
This is performed by setting the address key under the conditions. Ad
As a key, 3-bit address signals A0, A1 and
And A2 are used as an example. As a unit of lap length
4, 8, 16, 32 and all pages (one line)
it can. FIG. 34 shows the configuration of the lap length setting control system.
FIG. In FIG. 34, a lap length setting control system
Is a WCBR detection circuit 390 for detecting the condition of WCBR.
And the address in response to the output of the WCBR detection circuit 390.
Address bits A0, A generated from the
Wrap length latch circuit 392 for latching 1 and A2
And the data latched by the wrap length latch circuit 392
Therefore, the clock for selecting the number of clocks indicating the lap length
From the number selection circuit 394 and the clock number selection circuit 394.
The clock signal CLK is counted according to the clock number information.
To generate a write buffer activation signal / φWB /
φWB generation circuit 396 is included. The / φWB generation circuit 396 has an internal CAS system.
Control signal φC (generated in synchronization with signal / CAS)
Activated in response and counted a predetermined number of clocks
Thereafter, write register activation signal / φWB is generated. This
FIG. 34 shows only a configuration for writing data.
However, similarly, when reading is performed,
Circuit for generating register activation signal φRr
It is controlled by the output of the number selection circuit 394. / ΦWB
The raw circuit 396 includes an internal write enable signal φW and an internal CA
Write register activation signal in response to S-system control signal φC
/ ΦWB. / ΦRr generation circuit (not shown)
Register system for read in response to internal RAS control signal φR
Generates a control signal. The output buffer and the input buffer are
Active state during the power cycle. The lap length control circuit further selects the number of clocks.
Shift clock according to the clock number information from selector circuit 394.
And a shift clock generation circuit 398 for generating a clock.
The shift clock generation circuit 398 outputs the set clock.
Of the column selection line CSL selected by the column decoder in accordance with the number
Generate a shift clock to shift the position one by one
You. Usually, the lap length is set to 8 and the number of clocks
The selection circuit 394 is programmed to have this lap length of eight.
A shift clock is generated according to the difference from the lap length. When the programmed lap length is 8,
Is the same as in normal operation, and no shift clock is generated.
No. When the lap length is 16, one shift clock is generated
When the lap length is 32, the shift clock becomes 3
Generated. In this case, the basic lap length is 8,
When the lap data of the
(In the case of data writing). That is,
If the loop length is larger than the standard value, for example, 8, write
Of the data, continuous 8-bit wrap data is for writing
Data transfer is performed when data is stored in the register.
You. After the data transfer, the next continuous 8-bit data
Data is stored in the register (write register). This
Between the shift clock generation circuit 398
Column select line from the column decoder according to the shift clock
Is shifted by one. This period is enough (next consecutive 8
The next column select line rises before the bit data is written.
), The desired lap length data should be sufficiently continuous.
Can be written. A configuration in which these column selection lines are sequentially activated
Will be described below. FIG. 35 shows a state in the lap length program.
FIG. 3 is a diagram showing a configuration for generating a column selection signal. FIG.
5, the column selection signal generating system generates the internal control signal φya
Fetches external address signals A3-Ak in response to
Column address signal generating internal column address signals Y3 to Yk
Buffer 26a and external column address strobe
Internal control signal φC generated in synchronization with signal / CAS
Activated in response, the column address buffer 26a
Internal column address signals Y3 to Yk generated by
Counter 400 to take in as a count value and clock number selection
In response to lap length information from circuit 394 (see FIG. 45).
The output of the counter 400 and the column address buffer.
A selection circuit 402 for selecting one of the outputs of the
Column address signal from select circuit 402 to decode the column
It includes a group of Y decoders 404 for activating the selection line CSL. The counter 400 has a count value shifted.
Increment (or decrement) by 1 according to the clock signal SC
Is done. The counter 400 has a shift clock shown in FIG.
Response to the shift clock signal SC from the clock generation circuit 398.
Then, the count value is incremented by one. The selection circuit 402 includes a clock number selection circuit 3
If the clock number information from 94 is 1 or more,
If the length is 16 or more, the counter 4
00 is selected and applied to the Y decoder group 404. Y decoder group 404 is a decoder activation signal
In response to φCD, the signal applied from selection circuit 402
Decode the signal and select the column select line. Wrap length of 8 or less
In the case below, the selection circuit 402
The output of the file 26a is selected. Decoder applied to Y decoder group 404
Activation signal φCD receives information from clock number selection circuit.
External column address strobe signal / CA
S (or write enable signal (write enable signal))
Once a predetermined number of clocks have passed since the
It becomes inactive and becomes active again. In this FIG.
In the configuration shown, the counter 400 has a shift clock
Falling of Y decoder activation signal φCD instead of SC
Is used in which the count value is incremented by 1 in response to
It may be. At this time, the shift clock signal SC becomes Y
The shift clock signal S is supplied to the decoder control system.
Activation / inactivation of activation signal φCD at timing of occurrence of C
Control of sexualization is performed. Next, this normal lap length becomes 8
Wrap length 16 is selected in the set SDRAM.
The operation when selected is shown in FIG.
It will be described in the light of the above. First, the external row address strobe signal /
When RAS falls to "L", the next clock signal CLK
Address signal ADD is taken in at the rising edge of
A row address signal Xa is generated. This internal row address
In accordance with the signal Xa, the potential of the word line WL rises,
The potential of this one row of memory cells is transmitted to each bit line pair BLP.
Is reached. Next, the external column address strobe signal
/ CAS and write enable signal (write enable signal)
No.) / WE falls to "L", then data input / output
The data supplied to the input terminal DQ is changed to the clock signal CL.
Captured at the rising edge of K,
Is touched. When latching this write register,
As shown in the above, the register position indicated by the wrap address
Data is stored. At that time, the column address signal Y
b has already been imported. The selection circuit 402 includes a clock number selection circuit 3
The wrap length from 94 (see FIG. 34) is 16
The output of the counter 400 is selected according to the indicated information.
The counter 400 has a column address according to the internal control signal φC.
The output of the dress buffer 26a is used as the initial count value.
Latched. The Y decoder group 404 then outputs
Activated in response to coder activation signal φCD and column deco
A column operation is performed to set one column selection line CS1 to a selected state.
You. 8-bit wrap data b0 is stored in the write register.
To b7 are sequentially stored. 8th bit wrap data b
7 is latched at the rising edge of the latched clock signal.
Buffer activation signal φWB is generated. At this time
Has already been selected for the column selection line CSL. This
8 bits of wrap data b0 to b7 are selected.
Written to the memory cell. This lap data b0 to b7
In parallel with writing to the memory cell of
Is the next 8-bit wrap data b8 to b15
Latched at the rising edge of the clock signal. The clock signal into which the lap data b7 has been taken
Data from the write register on the rising edge of
Writing is performed, and in accordance with the next rising of the clock signal.
Since the next lap data has been imported,
No data writing occurs. Selection of this column selection line CSL1
Selected, data is written to memory cells
Thereafter, decoder activation signal φCD temporarily shifts to the inactive state
I do. In response to the inactivation of the column decoder, the counter 4
The count value of 00 is incremented by one. Memory array
Only the selected system temporarily returns to the precharge state. The word line WL maintains the selected state. did
Therefore, the potential of each bit line pair BLP is
The latched state is maintained by the amplifier. Predetermined clock
When the number is counted, that is, in the write register
Before the next lap data b8 to b15 are all written
Then, the Y decoder group 404 is activated. Selection circuit 40
2 gives the output of the counter 400 to the Y decoder group 404
ing. The count value of the counter 400 is incremented by one.
You. Therefore, the Y decoder group 404
Select the selection line. [0202] The selected column selection line CSL2 is
Memory cell is latched in the write register.
The 8-bit wrap data b8 to b15 are
Transferred in response to the register activation signal φWB, the global
Data to the selected memory cell via the IO line pair GIO.
Data is written. By repeating the above operation, one line
Continuous memory access to all memory cells connected to
Access is possible. Here, data transfer from the write register is performed.
Data is transferred in the middle of the wrap length for the transmission timing
When the 8-bit wrap data is written,
In response to the rising edge of the clock signal at
A register activation signal is generated to write data.
It is. When the last lap data is written,
Last lap data is written as well as data write timing
Data transfer at rising edge of clock signal
Is performed. In this case, the last lap data is written
Data at the rising edge of the clock signal
May be executed. In the structure shown in FIG.
02 is according to the wrap length data of the clock number selection circuit.
The output of the counter 400 is always selected. in this case,
In the first cycle, the column address buffer 26
a of the output of the counter 400 in the next cycle.
It may be configured to select an output. In the structure shown in FIGS.
Only the configuration of wrap length extension for data writing
Is shown. However, in this case the write register
If a read register is used instead of
The length of the lap at the time of going out can also be extended. sand
That is, in a continuous read cycle, the operation of the memory array is performed.
The operation is the same as during continuous data writing. Write register
The read register activation signal is used instead of the activation signal
It is just done. In a continuous read cycle,
The wrap data of the 8th bit is read through the output buffer
When the next 8-bit wrap data is read,
Is stored in the star. Read data from read register
For the next wrap data in the memory array in parallel with
Is performed for the column selection. The SDRAM standardized with a wrap length of 8
When setting lap length 4, the number of banks increases
May be used, and the number of banks is set to two.
4-bit wrap data using mask data
Only the data may be written. Hey when reading data
The 4-bit wrap data
Since the start address of the data is specified, mask data etc.
It is not necessary to use
At this point, the data reading is completed. [Pin Arrangement] FIG. 37 shows an SD pin according to the present invention.
FIG. 3 is a diagram illustrating an appearance of a package that stores a RAM. This
The 16 MS DRAM according to the present invention has a 44-pin lead pin.
0.8mm, 400mil, TSOP TypeI
I. This package is a standard 16 MDRA
SOJ (Single Outline Jerry) in which M is stored
Dit package)
The lead pitch is small and the number of pins can be increased
Has advantages. [0209] In FIG.
SDRAM is switched by changing the bonding wire.
A × 4 configuration and a × 8 configuration are realized. Power supply potential Vcc is applied to pin numbers 1 and 22.
Can be Data input / output terminals are located in the center of the package.
And pin numbers 9, 10, 12, 13, 32, 33, 35
And the pin terminals of the 36 pin numbers are the data input / output terminals D
Used as Q0-DQ7 (however, in the case of × 8 configuration)
). Data input / output terminals DQ0, DQ1 and DQ
Used for input / output buffer across Q7 and DQ6
Pin terminal (number) receiving power supply potential Vcc (Q)
Nos. 11 and 34) and the ground potential Vss (Q)
Pin terminals of pin numbers 8 and 37 are arranged. This de
Power used exclusively for input / output buffers
Using source potentials Vcc (Q) and Vss (Q)
Data generated when data is input / output at high speed.
Effectively reduce noise caused by charging and discharging of input / output terminals
Can guarantee the stability of internal operation. Pin numbers 1 and 22 at both ends of the package
The power supply potential Vcc is applied to the pin terminals of
Ground potential Vss is applied to pin terminals 3 and 44.
You. Write enable signal / WE is given to the pin end of pin number 2
External pin address pin 3
A trobe signal / RAS is applied. Pin number 4 terminal
Is supplied with a clock enable signal / CKE. Pi
Clock signal CLK is applied to the pin terminal of
You. The address signal bits A0 to A11 correspond to the pin number 18
To 21, 24 to 29, 17 and 16 respectively
Given. Address signal applied to pin number 16
Bit A11 is used as bank select signal BS.
You. That is, in this case, a two-bank configuration is used. This
To address pin terminals 16 to 29 of
The row signal is a time division of the row address signal and the column address signal.
Given. In the × 8 configuration, the address signal bit
A0 to A8 or A0 to A9 as column address signals
Used. Which one is used depends on the internal refresh
Determined by the refresh unit in the cycle
You. A light mask is applied to the pin terminal of pin number 41.
An instruction signal WM is provided, and the pin terminal of pin number 42 is
Output enable signal (output enable signal) / OE
The column terminal of pin number 43 is
Is provided. Pins 7 and 38
VT applied to the connection terminal and the pin number 15 and
The voltage Vref applied to the 30 pin terminals is equal to this SD
Required if RAM is used for GTL interface
This is the required reference potential. The GTL level is “H”
And the comparison reference potential of “L” is 0.8 V,
The signal has a logic amplitude of 0.8V. recent years,
Proposed in microprocessors operating at high speed
I have. The pin terminals of pin numbers 6, 39 and 40 are not used.
And its specification is not defined. In the case of the × 4 configuration, the pin terminals 12, 1
Pin terminals (data input / output terminals) of 3, 32 and 33 are
Used as a mask data input / output terminal. This mask
Data M0 to M3 are transmitted through specific data input / output pin terminals.
Is masked for the writing of the data. like this
The configuration that realizes the write per bit operation is easily realized.
Mask data to the data input / output terminals at the same time.
To make its input buffer inactive
May be used. Alternatively, certain parables
If the mask data is taken under the WCBR condition,
Latch during the continuous access.
Specific data according to the mask data held in the register
Invalidates data given via the data input / output terminal
Or keep the input buffer inactive.
It may be used. [Second type SDRAM] Synchronization shown above
In semiconductor memory devices, externally supplied clocks
Control signal, address signal and input in synchronization with the
Import of data and the like into the device is being performed. same
The period type semiconductor memory device has a plurality of banks. this
By interleaving banks alternately,
Can be implemented inside the SDRAM. Note
Recycling is performed during the activation period of the control signal / RAS (“L”).
Period). To switch banks,
This control signal / RAS is raised to an inactive state of "H" once.
Need to be To set the bank address.
You. Bank # 1 and Bank # 2 are alternately
There are two ways to access. The first method is to use bank # 1 and bank #
2 is provided with control signal / RAS independently
It is. In the second method, all external control signals are one-shot.
It is a method of making a pulse of the unit. Specify the operation mode
It is determined by the combination of the states of the external control signal. Operation mode
Only when it is necessary to specify the
Set the default. This set operation inside the SDRAM
The required operation is executed according to Thus the control signal
In accordance with the control signal / RAS
Even when taking in address signals, one bank
The other bank can be precharged during access
It works. In addition, this control signal is all pulsed
Means that the control signal has the same signal form as the address signal,
It also has the advantage of making control signals extremely easy.
Let's have. All required signals are of the same form.
Signal, and puts extra load on the external processing unit.
This is because there is no need to do this. Hereinafter, this control signal is
A description will be given of a configuration that is an expression. [Definition of Signals] All signals are pulsed.
Operation is determined by the combination of control signals
Is done. First, the state of each control signal and the
The corresponding relationship with the operation mode will be described. FIG. 38 shows a pulse type synchronous semiconductor device.
It is a figure showing pin arrangement of a memory device. Synchronous type shown in FIG.
The semiconductor memory device has the same structure as the first synchronous semiconductor device.
Word consists of 4 bits and 1 word consists of 8 bits
Is provided. Word configuration settings for pad bonding
Is realized. Pin numbers 1, 5, 9, 22, 36, and
Operation power supply voltage Vcc is applied to pin terminals 40. Pi
Operating power to be provided to channel numbers 5, 9, 36, and 40
The voltage Vcc (shown as VccQ in FIG. 38) is
Used for output circuits (especially input / output buffers). pin
Ground to pin terminals numbered 3, 7, 23, 38, and 42
The potential Vss is applied. Pin numbers 3, 7, 38, and
And the ground potential Vss (reference numeral in FIG. 38)
(Indicated by the symbol VssQ) is used for an input / output circuit. Working power
The source voltage is divided into two for the input / output circuit and the rest
To prevent noise on the power and ground lines.
To stop. In particular, the operating power supply voltage for input / output circuits
Pin terminal for VccQ and ground potential VssQ
Four pin terminals are provided for each ground pin.
To prevent noise from being generated
is there. By distributing the power and ground lines,
Reduces the parasitic inductance component of the wire and prevents ringing
Prevent life. Even if spike noise occurs,
The effect of pike noise is only partially suppressed. The pin numbers 2, 4, 6, 8, 37, 39, 4
Pin terminals 1 and 43 are used for data input / output.
(In the case of a configuration of 8 bits per word). 1 word is 4
In the case of the bit configuration, pin numbers 2, 6, 39 and 43
Pin terminals are used to input mask data M0 to M3.
Used. Pin numbers 17 to 21 and 24 to
29 pin terminals are used as address signal input terminals.
You. To specify the bank to the pin terminal of pin number 16
Is provided. Pin number 12
A write enable signal / WE is applied to the connection terminal. Pi
Column address strobe signal / C to pin 13
AS is provided. Row address to pin number 14
Strobe signal / RAS is applied. Pin number 33
Data input / output / mask signal DQM is applied to
It is. This signal DQM is the output enable signal in the previous embodiment.
Combination of both the bull signal / OE and the write mask signal WM
Corresponding to Clock signal to pin number 32
CLK is provided. To pin terminal 31
Clock signal CLK and generates an internal clock signal.
A lock for controlling activation / inactivation of the lock buffer.
Lock buffer enable signal / CKE is applied.
Semiconductor memory device is selected for pin number 15
Chip select signal / CS indicating that
You. These control signals operate in the form of pulses.
Only given in the cycle that specifies the code. Everything
All control signals, address signals and data are all
Clock signal CLK is taken in at the rising edge.
Control signals / WE, / CAS, / RAS, / CS and D
State at rising edge of QM clock signal CLK
Of the operation mode specified inside the device according to the combination of
A determination is made. Next, this control signal and the specified operation
The correspondence with the mode will be described. FIG. 39 shows the state of the control signal and the finger at that time.
FIG. 7 is a diagram showing a correspondence relationship with a set operation mode. Less than
Below, referring to FIG. 39, the relationship between the control signal and the operation mode
Will be described. (A) / CS = / RAS = "L" and /
CAS = / WE = "H" In this state, the acquisition of the row address is specified and the array
Activation of b is specified. In other words, take in the row address
The bank whose bank address is also taken and selected at the same time
The operation related to the row selection is executed in. (B) / CS = / CAS = "L" and /
RAS = / WE = "H" In this state, fetching of a column address is designated and data
The read operation mode is designated. In this mode of operation
Indicates that the read data register is selected and the selected memory
The data transfer operation to the cell read data register is executed.
It is. (C) / CS = / CAS = / WE =
“L” and / RAS = “H” This state corresponds to a column address fetch and data write operation.
Is specified. In this operation mode, the write register
Is activated, and a write register for applied data is
And writing to the selected memory cell is performed. (D) / CS = / RAS = / WE =
“L” and / CAS = “H” (e) / CS = / RAS = / CAS = “L” and / W
E = “H” In this state, refresh is specified and self-refresh is performed.
The flash operation starts. In this mode of operation,
Internal generation of refresh address and selection line
Refresh of the memory cells
It is performed using a counter and a timer. (F) / CS = / RAS = / CAS = / WE = “L” In this operation mode, data is stored in the mode register.
Set. This mode register is not specifically described.
There is no unique operation mode in the synchronous semiconductor memory device.
A mode register is provided to specify the
According to the data set in this mode register,
Is performed. Uses of such mode registers
As the setting of the lap length in the previous embodiment,
There is a long sequence setting. (G) DQM = "L" In this operation mode, the signals / CAS and //
In the operation mode determined by the WE, the data
Or reading is performed. That is, given from outside
The read data stored in the write register or read data
The data stored in the data register is read. (H) DQM = "H" In this operation mode, data reading is inactive.
And the write mask operation (continuous bit data (L
Mask operation) is specified. write
Masking of data is performed when this signal DQM is set to “H”.
At the rising edge of the next clock signal CLK
Is performed on the given data. One clock delay
By masking the write data
Signal timing can be easily set. (I) / CS = "L" and / RAS = /
CAS = / WE = "H" In this state, there is no change in operation. Which operation mode
Is also not specified. The semiconductor memory device is in the selected state and
It is just performing the specified action. (J) / CS = "H" In this state, the SDRAM is in the non-selected state.
The signals / RAS, / CAS, and / WE are ignored. Here, in FIG. 39, a symbol “-” is used.
Signal states are "don't care" states and "X"
Indicates an "arbitrary" state. Next, specific operations will be described.
You. [Specific Operation Sequence] Data reading FIG. 40 is a diagram showing data readout of the SDRAM of the second type.
Timing chart showing the state of the external signal indicating the operation
FIG. Hereinafter, the data read operation will be described. In cycle 1, clock signal CLK
Signal / RAS attains a low level at the rising edge of
The signals / CAS and / WE are both set to "H".
At this time, the row address signal bits A0 to A10 are
And the internal address is generated.
You. At this time, the bank address signal BA is also taken in at the same time.
It is. The bank address signal BA is "0". This place
The bank corresponding to the bank address BA is selected.
You. In accordance with the bank address, the SDRAM operates in bank 0 and
And bank 1. In bank 0,
Row decode operation and array activation are performed. In one cycle, in cycle 3,
At the rising edge of clock signal CLK, signals / RAS and
And / WE are set to "H" and signal / CAS is set to "L".
Is set to This state indicates data reading and
At the rising edge of clock signal CLK in cycle 3 of
The address signal bits A0 to A10 correspond to the column address signal Yb.
Captured as As a result, the row address signal X
a and row / column selecting operation according to column address signal Yb
Operation is executed, and the data of the selected memory cell is read out.
Data register. After 6 clock cycles
Data is read in cycle 7. In this case, the signal
DQM is set to “L” in advance. This allows data reading
It is possible to go out. In cycle 7, the read register is stored.
The stored eight data sequentially rises the clock signal CLK.
The data is read out in synchronization with the leading edge. Continuous 8-bit data
Are indicated as b0 to b7. In parallel with this data read, in cycle 7
Signal / R at the rising edge of clock signal CLK.
AS and / WE are set to “L”, and signal / CAS is set to
Set to “H”. At this time, the bank address BA
Is set to “0”. This allows the bank 0
And the precharge of the array of bank 0 is executed.
Is performed. Here, signal DQM is high during data reading.
Activation of the read register with a delay of two clock cycles /
Control inactivation. Of control signal for reading data
This is for facilitating the timing setting. Output buffer
And control of the shift of the read register is controlled by this signal DQM.
Is activated after two clocks have passed since
It is only necessary to use a configuration that is suitable for use. This configuration allows the signal DQM to be
By using a delay circuit that delays two clock periods
Is easily realized. Bank 0 which has entered the precharge state is a predetermined
RAS precharge period (2 or 3 clock cycles)
Can be activated again after elapse. In cycle 11, clock signal CLK
Signal / RAS goes low and signal / C
AS and / WE both become "H". Bank address
The signal BA is "0". Bank 0 is activated again
You. At the same time, the acquisition of the row address signal Xc is executed. Clock signal CLK in cycle 13
Signal / CAS is at "L" at the rising edge of
S and / WE are both set to "H". Column address
Signal Yd is taken in and data read operation is performed.
The operation is specified. In bank 0, the row addresses Xc and
A selection operation is performed according to the column address Yd and the selection is performed.
The data of the memory cell read back to the read data register
Will be transferred. As for the data output, the signal / RAS goes low.
6 clocks from the beginning of the memory cycle
Will be executed after In this state, the signal DQM is
“L”, indicating that the output is enabled.
You. In cycle 17, clock signal CLK
Selected by address Xc and Yd at rising edge of
The eight pieces of data d0 to d7 are sequentially output to the clock signal CL.
Read in response to the rise of K. In cycle 17
At the same time, the signals / RAS and / WE are set to "L",
The link address signal BA is set to “L”. This allows the van
Qu 0 enters the precharge state again. Next, in cycle 19, signal / RAS
Is set to “L” and the signals / CAS and / WE are set to “H”.
The link address BA is set to “1”. In this state
Bank 1 is selected, and the address given at that time is
Signal bits A0 to A10 are taken in as row address Xe
I will. As a result, the row address Xe in the bank 1
Is performed according to the above. Clock signal CLK in cycle 21
Signal / RAS and / WE attain "H" at the rising edge of
And the signal / CAS is set to "L". to this
A data read operation for bank 1 is designated. This
At the same time, the column address Yf is taken in. Signal DQ
M is in the “L” state and indicates the output enable state.
You. After data d7 is read from bank 0, the next clock
Rising edge of clock signal CLK in clock cycle 25
The data f0 from the bank 1 is read out at the same time. At this time
Also, the signal / RAS is "L", the signal / WE is "L" and
Signal / CAS is set to "H" and the bank address signal
BA is "1" and bank 1 precharge is specified.
It is. From the data register, the data of bank 1 is
Is read. Precharge is executed in bank 1.
It is. In cycle 28, signal / RAS is again applied.
"L" and the signals / CAS and / WE to "H",
By setting the bank address signal BA to "0"
Bank 0 is activated again. Rising of clock signal CLK in cycle 28
At the time of cutting, the clock buffer enable signal / C
KE is set to “H”. The signal / CKE is the clock back
This is a signal for enabling / disabling the fa. signal
When / CKE becomes “H”, the level in the read register
Generation of the register shift clock is the next clock cycle
Prohibited in. That is, in cycle 29
The read data f4 continues in the next cycle 30.
It is subsequently read. As a result, the outside of the SDRAM
Data processing speed of the data processing device.
The data cannot keep up with this data reading or
If the clock buffer enable signal is not
No./CKE is set to “H” for the same period of time
Data can be output continuously. This operation is called “sus
In cycle 30, in bank 0,
Column address Yh is taken in, and in cycle 34
And the precharge of bank 0 is executed. As described above, the signal / RAS is set in the pulse system.
Only during the first period of the operating cycle
Control signals / RAS, / CAS and / WE are in a predetermined state
The operation mode is specified by combining
Bank switching can be performed easily, and bank 0 is activated.
Bank 1 can be precharged at the time of conversion.
Therefore, it is necessary to consider the RAS precharge time.
Data from bank 0 and bank 1
Data can be read, and data can be read at high speed.
It works. Also, "suspended output" operation
The mode allows easy reading during continuous data reading.
Data acquisition according to the operation speed of the processing unit.
System timing design.
It will be easier. Here, when viewed from the outside, the signal / CKE
Becomes "H" and the second clock signal is erased.
Is shown as This is internally the next clock
Register shift operation is executed at the rising edge of the clock signal.
Internally, the signal / CKE becomes "H" internally
The clock of the next cycle is erased. 2. Write data
FIG. 41 shows the data write operation of the SDRAM of the second type.
FIG. Write operation is the same as the fall of signal / CAS.
Sometimes specified by setting the signal / WE to "L".
You. In FIG. 41, first, a data write
Operation is specified. In this state, signal / CA
Write register simultaneously with setting of S and / WE to "L"
Writing of data to external memory, that is, fetching of external data
It is. In writing operation, signal DQM is internally
Enable data capture one clock later /
Disable. At the time of data writing, the data
It is only necessary to fetch the data at the same time as the write instruction
Because it is. At this time, the state of the write register is still
It does not have to be completely reset. Next clock
The reset state of the register is determined by the
This is because it is sufficient that writing of b0 can be performed. Therefore read
Unlike during operation, signal DQM is one clock
Controls enable / disable of data writing with delay
I do. When reading data, after the memory cycle starts
The read operation is performed after the count of six clock signals CLK is performed.
Be done. The output buffer can be operated by this time
As well as from the register
It is necessary to take the read data into the output buffer and read it. This
Signal DQM is enabled earlier than in write mode.
It is. When the signal DQM is set to "H", the next clock
Mask for write data given in lock cycle
Can be hung. Data is delayed by one clock cycle.
It is easy to set the timing
That's why. Mask data for this one clock delay
In the configuration shown in FIG.
Mask data WM is delayed by one clock and write mask data is generated.
The configuration given to the raw circuit may be used. This one
A configuration that masks data that is delayed in lock
Wrap address from the wrap address decoder.
This makes timing design for the network easier. In the data write mode, the signal
When / CKE is set to “H”, the next clock cycle
In the next clock cycle
Will continue to be entered. In the write register
The shift operation of the register is prohibited. As a result,
When writing necessary data,
Can be written. This behavior is described in Suspend
It is called "do input." Each instruction and address signal is controlled by an external clock.
Captured at the rising edge of signal CLK. Instructions and
It is not possible to anticipate when the address signal will be given.
I can't. Therefore, the rising of external clock signal CLK
Capture these external control signals at the edge and generate the internal control signals.
It is necessary to stabilize the state that occurred. Input section for this
Next, the configuration will be described. [Control Signal Buffer] FIG.
AS, / CAS and / WE are connected to an external clock signal CLK.
FIG. 3 is a diagram showing a configuration of a buffer circuit that takes in in synchronization with the buffer circuit.
In FIG. 42, an external signal is distinguished from an internal signal.
For reference, an external signal is denoted by a symbol “ext.”. Referring to FIG. 42, the RAS buffer
Control signal ext. Activated when / CS is “L”,
External clock signal ext. External control signal in synchronization with CLK
No. ext. / RAS taken in and issues internal control signal / RAS
Live. The CAS buffer 504 has an external control signal ex
t. / CS is activated in response to “L” and the external clock
Signal ext. External control signal at rising edge of CLK
ext. Takes in / CS and generates internal control signal / CAS
You. The WE buffer 506 outputs the external control signal ext. / C
Activated in response to the “L” of S, the external clock signal e
xt. CLK at the rising edge of signal ext. Take / WE
And an internal signal / WE. FIG. 43 shows the case where the internal address signal is generated.
FIG. 3 is a diagram showing a circuit configuration for the second embodiment. In FIG.
Buffer 508 receives the external clock signal ext. CLK
To generate an internal clock signal CLK.
You. State decoder 510 includes internal control signals / RAS, /
CS and / WE from clock buffer 508
Captured at rising edge of internal clock signal CLK
The state of the signal is determined, and a necessary internal control signal is generated.
State decoder 510 outputs signals / RAS, / CAS and
/ WE specifies address signal capture
Activates the address buffer 512. Address bar
The buffer 512 receives the decoding from the state decoder 510.
In response to the external clock signal ext. CLK
At the rising edge, the external address ext. In Ai
Generating the unit address Ai (including the bank address BA)
You. [Internal Control Signal Generating System] FIG.
Schematic configuration of internal control signal generation system of SDRAM
It is a block diagram shown. In FIG. 44, the memory array
I is the first bank (bank 0) 600a and the second bank
(Bank 1) includes 600b and two banks. This van
The circuits 600a and 600b correspond to the circuit part 20 shown in FIG.
Contains 0. In FIG. 44, in order to avoid complication of the drawing,
For this purpose, internal control signals are shared by banks 600a and 600b.
It is shown to occur commonly. Bank address signal BA
Only one bank is activated according to
Control signals are applied only to the banks. Bank 60
0a and 600b are the same as those of the previous embodiment.
It is like. Referring to FIG. 44, the internal control system
The signal ext. / CS is buffered and the internal control signal /
A CS buffer 614 for generating CS,
Clock buffer enable signal ext. / CKE
Generates control signals CLKBE and / CKE in response to
CKE buffer 612 and control signal CLKBE and
/ CKE is activated in response to an external clock signal.
No. ext. CLK buffered and internal clock signal
Clock buffer 6 for generating CLK1 and CLK2
10 inclusive. The CKE buffer 612 controls the external control signal e
xt. / CKE is inactive (“H” level
The clock signal CL from the clock buffer 610
The generation of K1 and CLK2 is stopped. CKE buff
612 is the first internal clock from the clock buffer 610.
In synchronization with the lock signal CLK1, the external control signal ext. /
It takes in CKE and generates an internal control signal / CKE. control
Signal / CKE is also provided to clock buffer 610.
You. Clock buffer 610 receives the internal control signal / CK
E in response to the external clock signal ext. Synchronous with CLK
The generated second internal clock signal CLK2 is generated. CK
E-buffer 612 also indicates that a special mode has been set.
External control signal ext. / CKE to the clock signal CL
K1 (ie, external clock signal ext.CLK)
Synchronously generates capture control signal CLKBE and generates clock
The generation of the signals CLK1 and CLK2 is prohibited. That is, the clock buffer 610
Control signal CLKBE from KE buffer 612 and / or
CKE is received in parallel and its activation / inactivation is controlled
You. One of control signals CLKBE and / CKE is active
If the clock buffer 610 is in the
Issue a signal. Only when the special mode is specified
The generation of the internal clock signal of the buffer 610 is stopped.
You. Here, the first internal clock from the clock buffer 610 is output.
Lock signal CLK1 and second clock signal CLK2
And two clock signals are generated
Unnecessary during refresh and standby operation
This is for inhibiting the operation of the buffer circuit. I.e.
1 internal clock signal CLK1 is an external control signal ex
t. / RAS, ext. / CAS and ext. / WE
It is used to capture control signals such as The second interior
The clock signal CLK2 controls data input / output.
Used for This second clock signal CLK2 is
By providing only to the I / O control system of the
Pending input operation and suspended out
A put operation can be realized. The SDRAM further includes a CS buffer 614.
Is activated in response to an internal control signal / CS from
Control signal ext. / RAS, ext. / CAS, ex
t. / WE and ext. DQM capture internal control signal
A first control signal generating circuit 616 for generating
Selection in response to a control signal from the control signal generation circuit 616
Control for generating a control signal for driving a controlled array
The signal generation circuit 618 and the first control signal generation circuit 616
Refresh operation in response to a refresh instruction from
Refresh circuit 620 to be performed. The first control signal generation circuit 616 has the first
External control signal ex in response to internal clock signal CLK1
t. / RAS, ext. / CAS, and ext. / W
E is specified by the combination of the signal status at that time.
The operation mode is determined. According to this determination result,
1 control signal generation circuit 616 outputs the write control signal φW and the read control signal φW.
Output control signal φO, row selection control signal φR, and column selection control
Signal φC, row address buffer activation signal RADE and
And a column address buffer activation signal CADE.
The first control signal generation circuit 616 also outputs the external control signal ex.
t. When DQM rises first internal clock signal CLK1
Input and output buffers are enabled.
I do. The second control signal generation circuit 618 is provided for the first control signal generation circuit 618.
Internal clock signal CLK1 and bank address signal B
A, and receives the control signal from the first control signal generation circuit 616.
Signal, the sense amplifier activation signal φSA,
Activation signal φPA, write register activation signal φW
B, input buffer activation signal φDB, and output buffer
Generates an enable signal φOE. Generate second control signal
Control signals φWB, φDB and
And φOE are determined by the first internal clock signal CLK1.
It is determined. That is, the location of the internal clock signal CLK1
These control signals φWB, φD
B and φOE are generated. The refresh circuit 620 controls the first control signal.
Signal in response to a refresh instruction from the signal generation circuit 616.
Generates a refresh address SRA, and
Replace with internal row address Xa given from buffer
Refresh address SRA of bank 600a and
600b (banks 600a and 600b are
Sometimes when refreshed). Refresh circuit 62
0 is an address for generating this refresh address.
Counter and refresh address and normal
It includes a multiplexer for switching between a row address. The timer that defines the refresh interval is the first
Of the control signal generation circuit 616. Refresh times
The refresh address SRA from the path 620 will be described later.
To the address buffer 624 to
The refresh address SRA is provided before the buffer 624.
And a normal external address ext. A to switch to A
Wedges may be provided. In this case, the first control signal is generated.
When the refresh instruction is given by the raw circuit 616,
Are the row address buffer activation signal RADE and the row selection signal.
Select control signal φR. The SDRAM further generates a first control signal.
Row address buffer activation signal RAD from circuit 616
Response to E and column address buffer activation signal CADE
Is activated, and external address signal ext. A
In the row address signal and column address signal
Section row address signal Xa and internal column address signal Ya and
And address buffer for generating bank address signal BA
624 and a second internal clock signal CLK2.
And a predetermined bit from the address buffer 624.
Receiving the internal column address signal Ym shown in FIG.
Signals that control registers and write registers
Wrap address WY, read register drive signal φR
r and write register drive signal φRW
It includes a transistor control circuit 622. This register control circuit 6
22 in synchronization with the second internal clock signal CLK2
As a result, the second internal clock signal CLK2 is
When the occurrence is stopped, the suspend
Dynamic input and suspended output
Work can be realized. Control signal φRr or φR
w indicates that the second internal clock signal CLK2 is not supplied.
The shift operation in the register
Because it is not done. As shown in FIG. 44, the first control signal
Activation of the clock buffer as an input to the generation circuit 616
Control signal ext. / CKE
This control signal causes the clock buffer
Control behavior. An external clock is output from the clock buffer 610.
Lock signal ext. Internal clock signal synchronized with CLK
CLK1 and CLK2 are generated. External control signal e
xt. First control signal generation circuit 61 for taking in / RAS and the like
6 is synchronized with the first internal clock signal CLK1
That is, the external clock signal ext. Outside)
Captures unit control signals. The CS buffer 614 uses the first
External control at rising edge of internal clock signal CLK1
The signal ext. Incorporate / CS. The first control signal generation circuit 616 has an internal
External control signal is taken only when control signal / CS is active.
Put in. When the internal clock signal CLK1 is not generated,
First control signal generation circuit 616 and CS buffer 61
No capture of the external control signal at 4 is performed. this
Allows the buffer circuit to capture the external control signal to always operate
Power consumption can be reduced.
You. When the clock signal CLK1 is generated
Even if the internal control signal / CS is inactive
If the internal control signal ext. / RAS, etc.
Therefore, power consumption can be similarly reduced. The address buffer 624 has an internal control
External only when signals RADE and CADE are generated
Address signal ext. A is taken. Therefore
Address buffer 624 also indicates that the address has been specified.
Address is latched only when
Unit clock signal ext. Operate in each cycle of CLK
And power consumption is reduced. In the clock buffer 610,
Control signal CLKBE from CKE buffer 612 and
It is activated only when necessary according to / CKE. This
As a result, the clock buffer 610 is activated by the SDRAM.
External clock, such as during standby
Signal ext. CLK acquisition can be prohibited. This
Internal clock signal CLK1 and
CLK2 is generated, so that the external clock signal ext.
It is not necessary to perform the operation of always taking in CLK,
Power consumption is reduced. [Data Read Circuit System] FIGS. 46 to 47
Is a data read circuit of the SDRAM shown in FIGS. 1 and 45.
It is a figure showing composition of a system. As shown in FIG.
AM700 has two banks #A and #B and a bank
Output buffer 702 provided commonly for #A and #B
including. In FIG. 45, data input / output terminals DQ0 to DQ0
DQ7 is shown and data is input / output in 8-bit units.
Such a configuration is shown as an example. Output buffer 702
Is activated in response to read control signal OEM, and
Read data received from the selected bank
And transmits the data to the data input / output terminals DQ0 to DQ7.
You. FIG. 46 shows the data read portion of bank #A.
FIG. 3 is a diagram showing a specific configuration. In FIG. 46, one
2 shows a configuration of a portion related to a data input / output terminal DQ. In FIG. 46, bank #A has eight groups.
Global IO line pair GIO0A to GIO7A
Provided in response to the preamplifier enable signal PAEA.
In response, amplify the data on the corresponding global IO line pair
Read registers RG0A to RG7A to be latched,
For each of the read registers RG0A to RG7A
Provided, and wrap addresses RWY0, / RWY0 to RW
In response to Y7 and / RWY7, the corresponding read register is
Three-state inverter buffer for inverting and amplifying data held
TB0A to TB7A and the inverter buffer TB0A to
Latch circuit for latching data transmitted from TB7A
LA-A and inverter buffers TB0A to TB7A
(The data latched by the latch circuit RA-A)
) Is inverted and amplified and transmitted to the output buffer.
Includes inverter buffer TB8A. Inverter buffer
TB8A is a buffer generated according to the bank address BA.
Activated in response to link designating signals BAA and BAB.
You. FIG. 47 shows the data of bank #B shown in FIG.
FIG. 2 is a diagram illustrating a configuration of a data reading system. Bank B is Bank
It has the same configuration as A. That is, bank #B is
Activated in response to reamp enable signal PAEB
On the corresponding global IO lines GIO0B to GIO7B
Read register RG0B to amplify and latch the data of
RG7B is activated in response to the wrap address.
The output of the corresponding read register RG0B to RG7B is inverted and increased.
Three-state inverter buffers TB0B to TB7B to be widened
And the outputs of the inverter buffers TB0B to TB7B.
Latch circuit LA-B to be latched, and latch circuit LA-B
Three-state inverter buffer for inverting and amplifying latch data
TB8B. The inverter buffer TB8B
Activated in response to the clock designation signals BAA and BAB,
The inverted and amplified data is transmitted to the output buffer. Next
Data reading of SDRAM shown in FIGS.
The operation will be described with reference to the operation waveform diagram of FIG.
I will tell. In FIG. 48, the latency is 3,
The data read operation waveforms when the loop length is 4 are shown. here
The latency is the effective data after the column access
Is a data input / output terminal DQ (in FIG.
Clock cycles required before appearing at
Is a number. Start of column access is clocked by signal / CAS
Set to “L” at the rising edge of signal CLK
Is specified by This column access cycle is shown in FIG.
And the configuration of the SDRAM shown in FIG.
The same is true for Therefore, the signal / RAS is not shown.
No. The signal / RAS is applied to the column
Set before access specification. In the first cycle (clock number 1)
Signal / CAS falls to "L". Light rice
Signal / WE is at "H" and data read is designated.
You. At this time, address signals Ya and
Bank #A is designated according to bank address BA.
Row access has already been executed by signal / RAS.
You. According to this column access instruction (column selection operation instruction),
In column #A, a column selection operation is performed, and the selected
The data of the memory cell is a global IO line pair GIO0 to GI
It is transmitted on O7. On global IO line pair GIO0-GIO7
Is determined, the preamplifier enable signal PA
EA rises to "H". This preamplifier enable signal
The PAEA generation timing is also set according to the latency.
Of the clock of the third cycle (clock number 3)
Generated in synchronization with the rise. As a result,
Global IO line pairs corresponding to the registers RG0A to RG7A
The upper data is latched. Next, the wrap address from the wrap address generation circuit
Address RWYi is the third clock according to a predetermined sequence.
The clock signal corresponding to the lap length sequentially from the lock cycle
Generated between cycles. In this third clock cycle
Similarly, according to the bank address BA, the bank designating signal
BAA rises to "H", and inverter buffer TB8
A is activated. Activated by wrap address
From the inverter buffers TB0A to TB7A
Data is transmitted to output buffer 702. Output buffer
The signal OEM (not shown in FIG. 48)
Is generated at the same timing as the bank designation signal BAA.
It is. This ensures that the valid data is in the fourth clock cycle
Are output sequentially. In the fifth clock cycle, signal / C
AS falls to "L" and the address given at that time is
According to the data signal Add and the bank address BA.
Column selection for bank #B where row access is being performed
The operation is performed. In bank #B in the seventh cycle
The corresponding preamplifier enable signal PAEB is set to "H".
Up, global IO line pair GIO in bank #B
0B to GIO7B to read registers RG0B to RG7
Data transfer and latch for B are performed. Seventh
Wrap addresses are generated sequentially from the clock cycle,
Data of the read register of the selected bank #B is output
It is transmitted to the buffer. As a result, reading from bank #B
The data b1 to b4 output from the eighth clock cycle
Output sequentially. Thus, bank A and bank B
By alternately accessing B, both banks #A and
Data can be read at high speed from $ B. This van
Continuous access to queries #A and $ B is
If the SDRAM is of the loose type, it can be easily realized.
Wear. Bank #A and bank #B
However, even if a configuration using separate signals / RAS is used,
Good. Preamplifier enable signal PAEA (also
Is PAEB) and wrap address RWYi, respectively.
By generating the signal in synchronization with the clock signal CLK,
Data reading from a memory array can be pipelined.
Data can be read at high speed. [Bank Designation Signal Generation System] FIG.
2 shows a circuit configuration for generating designation signals BAA and BAB.
FIG. Referring to FIG. 49, a bank designating signal generating system
Is the signal / C at the time of rising of the clock signal CLK.
A latch circuit 710 for latching AS, and a clock signal C
Lack of bank address BA at rising edge of LK
Output signal from the latch circuit 711 and the latch circuit 710
(One column having a predetermined width in response to (column selection operation instruction)
One-shot pulse generation cycle for generating shot pulse φr
From the path 712 and the one-shot pulse generation circuit 712.
The latch circuit 711 responds to the one-shot pulse φr.
And a latch circuit 713 for latching the latch data of FIG.
Latch circuits 710 and 711 output the latch data.
Updated according to the rising edge of clock signal CLK.
You. The latch circuit 713 is a one-shot pulse generation circuit
712 according to the one-shot pulse φr.
The data is updated. The bank designating signal generating system further includes
A latency storage circuit 714 for storing the system information;
A wrap length storage circuit 716 for storing long data,
One-shot pulse from shot pulse generation circuit 712
Activated in response to φr, the latency storage circuit 714
And the latency held in the lap length storage circuit 716
Performs count operation according to data and lap length data.
Counter circuit 718 and the counter circuit 718
An output signal is selected according to the latch data of the latch circuit 713.
B which generates the bank designation signal BAA or BAB
A generation circuit 715 is included. The counter circuit 718 has a one-shot pulse
It is started in response to signal φr, and latency storage circuit 71
The number of clocks indicated by the latency data included in
A signal which counts the tension-1) and then becomes active
Occurs. The counter circuit 718 further includes the activation signal.
After being generated in the wrap length storage circuit 716.
The active state during the clock cycle indicated by the tap length data
To maintain. The specific configuration of this counter circuit 718 will be described.
Will be described in detail later. Output enable signal OEM
Is generated from the counter circuit 718. This output enable
Bull signal OEM generates BA from this counter 718 circuit
Generated by a signal applied to the circuit 715 as a trigger.
You. Next, the operation of the bank designating signal generation system shown in FIG.
The operation will be described with reference to FIG.
You. First clock cycle (number in FIG. 50)
At the rising edge of the clock signal CLK
The signal / CAS falls to "L". This state is
From this cycle.
A column selection operation is performed. Latch circuit 710 is a clock
Latch signal / CAS at rising edge of signal CLK
You. Latch circuit 711 rises clock signal CLK.
The bank address BA is latched at the leading edge. Wanshi
The output pulse generating circuit 712 is provided by the latch circuit 710.
One-shot pulse signal in response to "L" signal from
The signal φr is generated. The latch circuit 713 performs this one-shot operation.
Latch bank address BA according to pulse signal φr
(Provided by the latch circuit 711). The counter circuit 718 has the one-shot
Count operation of the clock signal in response to the
Start. The count value is stored in the latency storage circuit 714.
Clock cycles indicated by the latency information stored in the
Counter circuit 718 when (latency-1) matches
Generates a signal which rises to "H". At this time the counter
718, the one-shot pulse signal φr
Clock signal.
No. Also, the counter circuit 718 has a one-shot pulse signal.
After the signal φr is given, the latency storage circuit 714
Latency number to remember It is the number of clock cycles indicated by the data
Of the rising edge of the clock signal CLK that is less than two
It may be configured as follows. In FIG. 50, the latency
When the status of “3” is indicated and the bank #A is designated
A match is indicated. The BA generation circuit 715 includes the counter circuit 7
18 in accordance with the activation signal from bank control signal BAA.
appear. At this time, the counter circuit 718 again
Output enable signal O triggered by the
Generates EM. The output signal of the counter circuit 718
The activated state is the wrap stored in the wrap length storage circuit 716.
It is maintained for the clock cycle indicated by the length. Figure 50
The lap length is 4 and the third clock
7th clock after 4 clock cycles have elapsed
Bank designation signal BAA and output enable in cycle
A state where signal OEM shifts to “L” is shown. [Read Register] FIG.
FIG. 47 shows a specific configuration of the read register shown in FIG. 47.
is there. In FIG. 51, read registers RG0A to RG0R
G7A and RG0B to RG7B are indicated by reference numeral RG.
You. These read registers have the same configuration.
You. Referring to FIG. 51, read register RG
Is a preamplifier enable signal PAE (PAEA or
PAEB) and the global IO lines GIOi and
/ Amplifier for amplifying signal potential on GIOi
And latch the data amplified by the preamplifier PRA
Including a latch circuit LRG. The preamplifier PRA
Reamplifier enable signal PAE (PAEA or PAE
Complementary connected p-channel MOS receiving B) at its gate
Transistor 750 and n-channel MOS transistor
Between the transistor 754 and the ground potential.
Connected to the global IO line / GIOi
An n-channel MOS transistor 756 connected to
Complementary receiving amplifier enable signal PAE at its gate
Connected p-channel MOS transistor 752 and
n-channel MOS transistor 755 and transistor
755 and ground potential, the gate of which is
N-channel MOS transistor connected to global IO line GIOi
And a transistor 757. The preamplifier PRA further includes a transistor
P-channel MOS transistor provided in parallel with 750
751 and p provided in parallel with transistor 752.
It includes a channel MOS transistor 753. Transis
Gates 751 and 753 have their gates and drains crossed
Are combined. The latch circuit LRG has two two-input NANs.
D circuits 760 and 762 are included. NAND circuit 760
Has one input connected to the node N30 (one of the preamplifiers PRA).
Output node) and the other input is NAND
It is coupled to the output of path 762. The NAND circuit 762 is
Is input to node N32 (the other output of preamplifier PRA).
Input and the other input is a NAND circuit 7
60 output nodes N34. NAND circuit 7
Storage of read register RG from output node N34 of 60
Data is output. Next, the lead register shown in FIG.
The operation of the star will be described with reference to FIG.
I will tell. When a column selection instruction is applied (signal / CAS)
Falls to "L") in the selected bank.
The data of the memory cell that has been set is stored in the global IO line GIOi.
And / GIOi on the global IO line pair G
The signals on IOi and / GIOi correspond to the read data.
Changes to the potential. In FIG. 52, the global IO
Data “1” (corresponding to potential “H”) is read on line GIOi.
Is output and data “0” is output on the global IO line / GIOi.
(Corresponding to potential "L") is shown. Next, global IO lines GIOi and
When the potential on / GIOi is determined, the preamplifier enable
Signal PAE is generated (trigger clock signal CLK).
Moth). While signal PAE is at "L", preamplifier PR
In A, p-channel MOS transistors 751 and 751
And 752 are on and n channel MOS transistors
The transistors 754 and 755 are off. For this reason
Nodes N30 and N32 are precharged to the "H" potential.
Have been In this state, the latch circuit LRG
Latch data remains unchanged, read in previous access cycle
Holding the signal. Preamplifier enable signal
When PAE rises to "H", transistors 750 and
And 752 are off, transistors 754 and 755
Is turned on. Transistors 756 and 757
The gate is connected to the global IO line that has already been
GIOi and the signal potential of GIOi are transmitted. Now, the signal on the global IO line GIOi
The order is “1”. Therefore, the conduction of transistor 757
The electrical conductivity becomes higher than the conductivity of the transistor 756,
Node N30 is connected by transistors 755 and 757.
The discharge is performed at a higher speed than that of the node N32. Node N30
Transistor 751 is turned on when the potential of
And the node N32 is charged. Node N32
Rises, the transistor 753 is turned off.
Transition. Thereby, the potentials of nodes N30 and N32
To high speed global IO lines GIOi and / GIOi
It has a corresponding potential. That is, the potential of the node N30 becomes
“L” and the potential of the node N32 becomes “H”. Depending on,
The output of the NAND circuit 760 becomes “H”, and the node N3
4 is read from the memory cell selected in the memory cell.
Is touched. When the signal potential of global IO line GIOi is
"L" and signal potential on global IO line / GIOi
Is “H”, the potential of the node N30 is “H”,
The potential of the node N32 becomes “L” and the NAND circuit 760
Become "H" at both inputs, so that the node N34 has
The “L” signal potential is latched. [Preamplifier Enable Signal Generation System] FIG.
3 is for generating a preamplifier enable signal PAE
FIG. 3 is a diagram showing a circuit configuration of FIG. In FIG. 53, the PAE signal
The signal generation system receives a signal at the rising edge of the clock signal CLK.
Signal / CAS, a latch circuit 710 for latching
A one-shot pulse in response to the output signal of
A one-shot pulse generation circuit 712 that generates
One-shot pulse from shot pulse generation circuit 712
Clock signal CLK in response to
Counts according to 14 stored information, and reaches a predetermined count value.
Generates preamplifier enable signal PAE when it reaches
And a counter circuit 720 for performing the operation. Next, as shown in FIG.
The operation of the preamplifier enable signal generation system
This will be described with reference to FIG. A signal is generated at the rising edge of clock signal CLK.
When the signal / CAS is set to "L", the column selection operation (column
Seth) begins. At this time, the output of the latch circuit 710 is
Falls to "L" and the one-shot pulse generation circuit 71
2 generates a one-shot pulse. This one-shot
The one-shot pulse from the pulse generator circuit 712.
This indicates that the column selection operation has been started. Counter times
The path 720 is connected to the one-shot pulse generation circuit 712.
Clock signal CLK according to these one-shot pulses.
Count. This count value is stored in the latency storage circuit 7
14 has reached one less than the stored latency
When the clock signal CLK at that time is used as a trigger,
The counter circuit 720 generates a one-shot pulse signal
I do. The one shot pulse from the counter circuit 720 is
The loose signal becomes the preamplifier enable signal PAE. The output from counter circuit 720
The re-amplifier enable signal PAE is output from the BA shown in FIG.
With the same configuration as the raw circuit 715, the selected bank
Generated only for read registers provided for
You. Counter circuit 720 is provided for each of banks #A and #B
Selected according to the bank address BA
Only the counter circuit corresponding to the activated bank is activated.
A configuration such as that described above may be used. Here, FIG.
The case where the intensity la is 3 is shown as an example. And
Therefore, the second clock signal after the column selection operation has started
Signal (clock number 3) as a trigger
A bull signal PAE is generated. FIG. 55 shows the counter circuit 720 shown in FIG.
FIG. 3 is a diagram showing an example of a specific configuration of FIG. In FIG. 55,
The counter circuit 720 is a one-shot pulse generation circuit.
Activated in response to the one-shot pulse φr given by
Falling to count the falling of the clock signal CLK
From the falling counter 770 and the falling counter 770
Has a predetermined pulse width in response to the count-up signal
A pulse generation circuit 772 for generating a pulse signal PA1,
Latency data from the latency storage circuit indicates 1
Is activated when the
In response, a pulse signal PAE0 having a predetermined pulse width is generated.
A pulse generation circuit 774 and a pulse generation circuit 772
And 774 pulse signals PAE1 and PAE0
OR circuit 776 that takes the logical sum of Preamplifier enable from OR circuit 776
A signal PAE is generated. The falling counter 770
The latency la stored in the latency storage circuit is 2 or more.
In such a case, the counting operation is performed. Pulse generation circuit 774
Indicates that the latency la stored by the latency storage circuit is 1
If activated. Next, the counter times shown in FIG.
The operation of the road 720 is described with reference to FIG.
Will be explained. At the rising edge of clock signal CLK,
When the signal / CAS is low, the signal has a predetermined pulse width.
A one-shot pulse signal φr is generated. Leyte
If the response is 2 or more, the falling counter 770 is activated.
It is sexualized. The falling counter 770 uses this one-shot
Is activated in response to the rise of the pulse signal φr,
The falling of the lock signal CLK is counted. Layten
If the value is 3, the pulse generation circuit 772 outputs the clock
The counter 77 responds to the second falling of the signal CLK.
A predetermined time is determined by a count-up signal generated from 0.
After the elapse, a pulse signal PA1 having a predetermined pulse width is generated.
Live. On the other hand, the pulse generation circuit 774 has a latency of 1
, The one-shot pulse signal φr
A predetermined pulse width after a predetermined time in response to the rise of
Is generated. OR circuit 77
6 is one of the pulse signals PAE1 and PAE0
Generates a preamplifier enable signal PAE.
The pulses required by the pulse signals PAE0 and PAE1
Even if the width is the same as the pulse width of clock signal CLK,
Good. FIG. 57 shows another example of the counter circuit shown in FIG.
FIG. 3 is a diagram showing the configuration of FIG. In FIG. 57, a counter circuit
720 is a frequency dividing circuit 78 for dividing the frequency of the clock signal CLK.
0 and the clock signal CLKV from the frequency dividing circuit 780.
Counter 782 to count
Has a predetermined pulse width according to the count-up signal φu
A pulse generating circuit 784 for generating a pulse signal PAE is included.
No. The counter 782 outputs the one-shot pulse signal φr
Activated in response to count clock signal CLKV
The count value is the count specified by the latency data.
Count-up signal when the count value is reached
You. Next, the operation of counter circuit 720 shown in FIG.
The operation will be described with reference to FIG. 58 which is an operation waveform diagram. In FIG. 58, the frequency dividing circuit 780
Clock signal CLK is divided by 、 and its frequency is doubled.
Is shown as an example. In this case, the counter times
The path 782 is one-shot for the latency data la.
Clock signal CL after receiving pulse signal φr
The falling of KV is counted 2 (la-1) times. Cow
When the count value reaches 2 (la-1), the count-up signal
The signal φu is generated. The pulse generation circuit 784 uses this counter.
One-shot pulse signal in response to the
Occurs. In FIG. 58, the pulse signal PAE
The pulse width is shown as being equal to the pulse width of the clock signal CLK.
Is done. The counter circuit 782 has a latency la of 1
, The divided clock signal CLKV
Generates a count-up signal in response to the first falling edge of
I do. Therefore, in this case, the pulse generation circuit 784
At the beginning of the column access cycle of the clock signal CLK.
The preamplifier responds to the rise of the clock signal CLK.
It can be said that the enable signal PAE is generated. [0307] For the wrap address RWYi, the column selection
1st latency from the start of selection operation
Wrap address in response to the rise of the clock signal CLK
Set and then for the clock cycle indicated by the wrap length
Generate wrap address in response to sequential clock signal
You. This corresponds to the wrap address generation time shown in FIG.
Setting timing of the output of the path decoder (see FIG. 28)
Reset signal) according to the latency data la
Clock signal specified by the latency data la.
Clock cycle defined by wrap length data from cycle
During this time, the wrap address is generated by the clock signal CLK sequentially.
Provided to the circuit. [Lap Address Generation System] FIG.
FIG. 2 is a diagram illustrating an example of a configuration of an address generation system. In FIG.
In this case, the wrap address generating system uses the clock signal CLK.
Latch that latches signal / CAS at the rising edge of
Path 790 and a column selection operation start finger from the latch circuit 790.
In response, three-bit addresses A0, A1 and A
2 and decodes the decoded result.
From the address decoder 791 and the latch circuit 790
Is activated in response to the column selection operation instruction of
To count the clock signal CLK in accordance with the data
Latency counter 794 and latency counter 794
Address in accordance with the count-up signal φls from
Wrap address the decoder latched by the
A transfer circuit 792 for transferring the data to the
In response to the count-up signal from the
Clock signal according to the wrap length data wr
Wrap length counter 79 for counting the falling edge of CLK
5 and the output φlw of the lap length counter 795.
Wrap address by selectively passing lock signal CLK
A gate circuit 796 applied to generation circuit 793 is included. The wrap address decoder 791 is shown in FIG.
This corresponds to the configuration shown in FIG. Lap address generation circuit
793 is the clock signal CLK from the gate circuit 796
wrap given via transfer circuit 792 according to a
The addresses are sequentially shifted (see FIG. 28). This transfer times
A path 792 receives a reset signal shown in FIG.
This corresponds to the register 236. The gate circuit 796 is, for example,
It is composed of an AND circuit and outputs the wrap length counter 795
The clock signal CLK is passed only when φlw is “H”.
Let Next, the operation of the wrap address generation system shown in FIG.
The operation will be described with reference to the operation waveform diagram of FIG. At the rising edge of clock signal CLK,
Signal / CAS is set to "L" and a column selection operation is instructed.
You. This state is latched by the latch circuit 790,
Address decoder 791 and latency counter
794 becomes active. Wrap address decoder 79
1 is in accordance with the column selection operation instruction from latch circuit 790.
Address A0, A1 and A2 given by
And latch the decoding result. to this
1 out of 8 wrap addresses RWY0 to RWY7
A decode signal for activating one of them is generated. Leyte
The counter 794 performs a column selection operation from the latch circuit 790.
Started according to instruction and counts clock signal CLK
And the number of clock signals (the number
Counts up at the rising edge of 3 clock cycles)
Generates a loop signal φls. The latency counter 794 includes a latch circuit
In response to the column selection operation instruction from 790, clock signal CL
It may be configured to count the fall of K.
In FIG. 60, the latency la is set to 3.
Therefore, from the latency counter 794, the latency
The number of clocks that is one less than la, ie, clock number 3
The signal which becomes “H” at the rising of the clock signal is
Generated (the first clock signal is not counted). this
As a result, the transfer circuit 792 becomes conductive and the wrap address
Decoded and latched by the decoder 791
The transmitted information is transmitted to the wrap address generation circuit 793.
You. The wrap address generation circuit 793 has the configuration shown in FIG.
Is provided with a shift register configuration as shown in FIG.
In each of the 8-bit shift registers,
Address is set and the wrap address RWY of 8 bits
1-bit wrap address selected from 0 to RWY7
State ("H"). [0312] The lap length counter 795 uses this latency.
Synchronous with count-up signal φls from counter 794
Is activated and the falling edge of the next clock signal CLK is
Clock cycle specified by wrap length data wr
Count the number of files. This wrap length data wr is specified
Wrap length counter 7 until the next clock cycle elapses
95 sets the signal φlw to “H”. This makes the fourth
Clock signal CLK wrapped from clock cycle
To the address generation circuit 793. [0313] The wrap address generation circuit 793 is
Clock signal CLKa provided through a gate circuit 796
According to the wrap address RWYi. Luck
The output φlw of the wrap length counter 795 is the wrap length data w
The falling edge of the clock designated by the lap length counter 7
After it has counted 95, it falls to "L" (clock signal
In response to the falling edge of CLK). This makes the gate 79
6 is turned off, and the wrap address generation circuit 793
The change of the wrap address RWYi is prohibited. As described above, wrap address generating circuit 793
Sequentially stores the held data in accordance with the clock signal CLK.
Transfer the initial wrap address in
Set the timing according to the clock signal, and
Changing the address according to the clock signal CLK
Thereby, accurate data reading is performed. Here, the wrap address generation circuit 793 is
A configuration different from the configuration of the shift register may be used.
No. As shown in FIG. 61, this wrap address
The decoder and the wrap address generating circuit are provided with the WCBR section.
Of the wrap address according to the address bit A6 in the
The generation order is set, and then a column selection operation instruction is given.
The three-bit address A0, A1 and A2
Therefore, wrap addresses are generated in the set order.
Configurations may be utilized. In this configuration,
Generated wrap address generation timing and change
The timing is determined in response to the clock signal. This structure
Configuration can be realized using a normal sequence setting circuit.
it can. [Output Buffer] FIG. 62 shows the output buffer.
FIG. 3 is a diagram illustrating an example of a specific configuration. Referring to FIG.
The output buffer 702 is output from the inverter buffer TB8.
Transmitted data Qout and output enable signal OEM
Receiving two-input NAND circuit 801 and read data Qo
ut and an output enable signal OEM.
Response to the output of the NAND circuit 802 and the NAND circuit 801.
And the data input / output terminal DQ is at the power supply potential Vcc level.
P-channel MOS transistor 803 for charging
Conducted in response to the output of gate circuit 802, and data input / output
N-channel MO for discharging force terminal DQ to ground potential level
S transistor 804 is included. The gate circuit 802 is
Receive the output enable signal OEM at the false input of the
Receiving the read data Qout. Next, the operation is briefly described.
Just explain. When output enable signal OEM is at "L" level,
In this case, the output of the NAND gate 801 is “H” and the gate circuit
The output of 802 is "L". This allows the transistor
803 and 804 are both turned off, and the output battery
The fa 702 enters an output impedance state. The output enable signal OEM rises to "H"
Then, the NAND circuit 801 functions as an inverter
The gate circuit 802 also functions as an inverter.
You. For example, when data Qout is set to “1” (potential “H”).
), The outputs of gates 801 and 802 are both
Becomes “0” (corresponding to the potential “L”), and the transistor 8
03 is turned on, and the transistor 804 is turned off.
You. As a result, data “1” is applied to the data input / output terminal DQ.
Is read. [Second Embodiment of Data Reading System] FIG. 63
Is another example of the data read system of the SDRAM of the present invention.
FIG. In FIG. 63, the SDRAM has two
Includes banks #A and #B. Bank #B is also the same as bank #A,
Amplifier enable signal PAEB and transfer instruction signal TL
Corresponding global IO line pair GIO0B-G according to RB
Read for amplifying and latching data on IO7B
Registers RG0B to RG7B and wrap address RWY
0B, / RWY0B to RWY7B, / RWY7B
To invert and amplify the latch data of the corresponding read register
Three-state inverter buffers TB0B to TB7B and this
Activated 3 states among these 3 state inverter buffers
Circuit L for latching the output of the active inverter buffer
AB and the data latched by the latch circuit LA-B are
Includes a three-state inverter buffer TB8B for inverting and amplifying. Bank #A and bank #A shown in FIG.
♯ In the configuration of B, the read registers RG0A to RG7A and
And RG0B to RG7B are the preamplifier enable signals P
Transfer instruction signal TL in addition to AEA and PAEB
Data latch transfer is controlled according to RA and TLRB
Is different from the read register configuration shown earlier.
You. In FIG. 63, this SDRAM is further
The output from bank #A and bank #B (tristate
Latching the output of the buffer TB8A and TB8B).
Output from the latch circuit 820 and the latch circuit 820.
To the data input / output terminal DQ according to the cable signal OEM
Output buffer 702. Output buffer 702
The configuration is the same as that shown in FIG. The latch circuit 820 outputs the control signal DOT and
-State inverter bar activated in response to / DOT
Buffer 821 and the output of the three-state inverter buffer 821.
A latch circuit 822 for latching a force is included. [Read Register] FIG. 64 is shown in FIG.
FIG. 3 is a diagram showing a specific configuration of a read register. In FIG.
The read register RG shown is the read register shown in FIG.
In response to the preamplifier enable signal PAE,
And corresponding global IO lines GIOi and / G
A preamplifier PRA for amplifying data on the IOi;
A latch for latching the data amplified by the amplifier PRA.
Switch LRG and transfer instruction signals TLR and / TLR.
In response to the transfer of the latch data of the latch circuit LRG,
Transfer register RGTR and transfer gate RGT
A latch circuit SLRG for latching the output signal of R is included. The latch circuit SLRG includes a transfer gate RGT
An inverter 824 for inverting the output of R, and a transfer instruction signal
Activated in response to TR and / TR, inverter 8
24 is inverted and transmitted to the input of inverter 824.
A three-state inverter buffer 826. Transfer gate
RGTR is composed of a three-state inverter buffer. Turn
Transmission gate RGTR and three-state inverter buffer 826
Is complementary to output high impedance state and operation
State. In the first clock cycle, the clock
Signal / CAS goes low at rising edge of signal CLK
Is set and the start of column selection operation is instructed.
It is specified). The address Ya given at this time is
As an address, a column selection operation is performed. Also at this time
Bank address A is set, and bank #A is selected.
You. The row selection operation is based on the previously applied signal / RAS and the signal / RAS.
Execute according to the bank address given at the time of
Have been. This bank address A is therefore
Of the data reading system, that is, the circuit related to the signal CAS.
It has a function to specify the link. In the second clock cycle, the clock
When the signal CLK rises, the preamplifier enable signal P
Set AEA to “H”. That is, preamplifier rice
Cable signal PAEA is (latency-2) clock cycle.
Activated during cruising. Valid data is entered
Two clock cycles before appearing on output terminal DQ
In the read register RG and
The latch (by the latch circuit LRG) is executed. In the second clock cycle, the clock
The transfer instruction signal is triggered by the rise of the clock signal CLK as a trigger.
The signal TLRA is raised to “H”. As a result, FIG.
Transfer gate RGTR indicates output high impedance state
From the active state and is latched by the latch circuit LRG.
Data (the memo read by the current access cycle)
Recell data) to the next-stage latch circuit SLRG
You. The data transferred by this transfer gate RGTR
When the signal TLR rises to "L", the latch circuit SLRG
(The three-state inverter buffer 826 is
It becomes active). In this second clock cycle,
Wrap with the rising edge of the clock signal CLK as a trigger
A wrap address is generated from the address generation circuit. This
Thereby, the three-state inverter buffers TB0A to TB7A
One becomes active, and the latch circuit SLRG is latched.
3-state inverted data is provided at the output unit
The latch circuit LA-A at the previous stage of the buffer
Is touched. As with the generation of this wrap address RWYiA,
The clock signal CLK of the second clock cycle.
With the rising edge as a trigger, the bank designation signal BAA is
It becomes "H". This latches the lap circuit LA-A.
The transferred data is passed through the three-state inverter buffer TB8A.
And transmitted to the preceding stage of the look-ahead latch circuit 820 of the output unit.
You. Subsequently, the third clock cycle (valid data
Is one clock cycle longer than the clock cycle at which
Before rising edge of the clock signal CLK)
As a result, the control signal DOT becomes “H” for a predetermined period. This
As a result, the prefetch latch circuit 820 has already been transmitted.
Acquire and latch data. Generation of this control signal DOT
Output enable signal OEM rises to “H” in synchronization with
To As a result, output buffer 702 is activated.
The data transmitted from the prefetch latch circuit 820.
To the data input / output terminal DQ. In the third clock cycle, the clock
The rising edge of the clock signal CLK as a trigger
Changes. In the fourth clock cycle, the output buffer
The output data of the file 702 is determined as valid data. [0334] Thereafter, wrap add
RWYiA changes, a control signal DOT is generated,
Four bytes of data are sequentially output from the output buffer 702.
It is. In the fifth clock cycle, bank #
B column selection is specified. In this case as well,
Preamplifier enable signal in 6 clock cycles
PAEB is set to "H" and selected in bank #B
Amplification and latching of data in memory cells are performed
(In bank #B, row is already selected by signal / RAS
Is running). That is, bank {A and bank}
B can be activated in parallel in a pipeline manner
You. In bank #B, the preamplifier enable signal
When the signal PAEB is generated, at the sixth clock cycle
A transfer signal TLRB is generated in the current access cycle.
Memory cell data read in the latch circuit S
Latched by LRG. Then wrap address RWYi
B are sequentially generated, and data is generated according to the wrap address.
Is transmitted to the input section of the look-ahead latch circuit 820. Or later
Control signals DOT and OEM from the next clock cycle
Are sequentially read out according to the following. Control signal DOT outputs valid data.
To the wrap length (4 in the configuration shown in FIG. 65)
It becomes "L" when the number of clock signals is counted. When the latency is 1, read-ahead cannot be performed.
No. Column access if latency is set to 1
(Column select operation start) clock cycle specified
The wrap address RWYi is changed by the lock signal as a trigger.
To Latency of output control signal DOT also
In the case of 1, in the clock cycle at the start of column access
It is set to “H”. That is, FIGS.
In the configuration shown in FIG.
Data transfer and output buffer
Data reading up to the previous stage of the buffer is executed. FIG. 66 shows FIGS. 63 and 64.
FIG. 3 is a diagram showing a data flow in a data reading system. Figure
At 66, in the first clock cycle,
LRG (the first latch of the read register) is
Access cycle data is latched. Remaining latch
The same applies to The output buffer is the output high impedance.
-Dance state. In the first clock cycle,
A signal PAE is generated, and in response to the signal PAE,
LRG latch data is the memory of the current access cycle.
Changes to cell data QA. At this time, the latch SLR
The data held in G is data from the previous access cycle.
You. In the second clock cycle, signal TLR
Is generated, and the data of the latch SLRG is transferred to the latch LRG.
The data is changed to the latched data. Next, a wrap address RWYi is generated.
Selected from the data latched by the latch SLRG.
The selected three-state buffer becomes active and is set in the output section.
Latch LA-A is set at the beginning of the current access cycle.
Changes to data. At this time, the bank designation signal B
A is in the determined state, and the input of the prefetch latch circuit 820 is
This first data is transmitted to the force. In the third clock cycle, control signal D
OT is generated and the latch data of the prefetch latch circuit 820 is output.
Becomes the current cycle data QAi. Subsequently, according to the signals DOT and OEM,
The output data of the output buffer 702 changes. Layten
Confirmed data is sequentially output from the fourth clock cycle after
Is output. In the read register, the transfer signal TLR
In order to perform data transfer, the same bank is continuously
Access, the data from the previous access cycle
Before all are read, the memory cells of the current access cycle are read.
The contents of the read register are destroyed by the
This is to prevent the situation. Next, the specific circuit configuration
And will be described sequentially. [Lap Address Generation System] FIG.
FIG. 3 is a diagram illustrating a functional configuration of a address generating system; Figure 67
In the wrap address generation system, the preamplifier enable
One signal in response to the
Pulse generating circuit 8 for generating a pulse signal φrw
50 and a one-shot pulse from the pulse generation circuit 850
Falling of the next clock signal CLK in response to the
Lap length counter 852 that counts the lap
Selective clock signal in response to output of length counter 852
A gate circuit 856 for passing the signal CLK and a one-shot
The first wrap address in response to the pulse signal φrw
Occurs and then the clock provided from gate circuit 856.
Wrap address is sequentially changed in response to the clock signal CLKa.
Wrap address generating circuit 854. The pulse generation circuit 850 has a latency data
If la indicates two or more latencies,
When the re-amplifier enable signal PAE is generated
One shot in response to rising of clock signal CLK
Is generated. Latency data la
Indicates the latency 1, the pulse generation circuit 85
0 is one in response to the preamplifier enable signal PAE.
A shot pulse signal φrw is generated. The wrap address generation circuit 854 is shown in FIG.
Wrap address decoder and wrap address generation
Circuits 791 and 793 are included. In response to a column selection instruction
Performs a decoding operation and one-shot
Transfer in response to a pulse signal and the first wrap address
Occurs. [0347] The wrap length counter 852 is
Of the clock signal CLK in response to the
The period (wr + 2) cow whose fall time is indicated by the lap length data
To Instead, the lap length counter 852
After the shot pulse signal φrw is generated, the next clock
The rising edge of the clock signal CLK is counted as the wrap length + 1
Configurations may be utilized. The lap length counter 852
Until the count of the specified count value of the gate is completed
The circuit 856 is turned on. Gate circuit 856 is conductive
The clock signal CLK is transmitted when the state is reached. This
This causes the wrap address generation circuit 854 to
Wrap address is sequentially changed in accordance with the clock signal CLKa.
You. FIG. 68 shows the wrap address shown in FIG.
4 shows operation waveforms of the generation circuit. In FIG.
The operation in the case where the wrap length is 3 and the wrap length is 4 is shown. Second
In the clock cycle, the preamplifier enable signal
PAE is generated, and pulse generation circuit 850 generates a clock signal.
One-shot pulse signal in response to the rise of signal CLK
The signal φrw is generated. This one-shot pulse signal φ
rw, the wrap address generation circuit 854 generates the first line.
Generates a top address. Lap length counter 852
Is activated in response to the one-shot pulse signal φrw of
You. The gate circuit 856 is the counter of the lap length counter 852.
The clock signal CLK is passed during the operation period. The wrap address generation circuit 854 operates as a gate circuit.
In accordance with the clock signal CLKa from the
Address is sequentially changed. This reduces latency to 3
, The wrap address in the second clock cycle
Can occur. The lap length counter 852
After the completion of the count operation, the wrap address generation circuit 854
Set the output to "L". Lap address generation circuit 85
4 is operated only when necessary,
Aim for reduction. Output state of wrap address generation circuit 854
May be used. Instead of the structure shown in FIG.
The pulse generation circuit 854 generates a one-shot pulse signal φrw
Not the first wrap-up according to the clock signal CLKa.
Configuration that generates wrap addresses sequentially from the address
It may be. In this case, the one-shot pulse signal
The address is not supplied to the address generation circuit 854. Wrap length
The counter 852 follows the one-shot pulse signal φrw
To pass the clock signal CLK. From lap address
The raw circuit 854 generates the first line according to the clock signal CLKa.
Are generated sequentially from the top address. In this case, as shown in FIG.
In the waveform diagram, the clock is
Clock signal CLKa is generated and the second clock cycle
Address in accordance with clock signal CLKa at
Is generated. In the operation waveform diagram shown in FIG. 68,
The wrap address RWYi has a rising edge of the clock signal CLK.
The edge changes as a trigger. Clock signal C
Wrap address is triggered by falling edge of LK
Modified configurations may be used. FIG. 69 shows a wrap-around when the latency is 1.
It is a figure which shows the generation mode of a dress. In FIG.
If the intensity is 1, column access (column selection operation)
When starting, responds to the rising of this clock signal CLK
As a result, a preamplifier enable signal PAE is generated. This
Response to the preamplifier enable signal PAE
A reset pulse signal φrw is generated. This one shot
First wrap address RWY according to pulse signal φrw
i is generated. At this time, the transfer control signal TLR and the output
The force control signal DOT is fixed to “H” when the latency is 1.
Is determined. Therefore, preamplifier enable signal PA
The data read according to E is the wrap address RWYi
Is transmitted to the output buffer 702. Out
In the output buffer 702, the output enable signal OE
Clock signal sequentially from the second clock cycle according to M
, Valid data is output. In the operation waveform diagram shown in FIG.
When the intensity is 1, the one-shot pulse signal φrw
In response, the wrap address RWYi becomes the clock signal CL
It may be configured to change at the falling edge of K.
No. [Data Read Control System] FIG.
FIG. 3 is a diagram illustrating a configuration of a control signal generation system related to output. Figure
At 70, the data read control signal generation system outputs a signal / W
E and / CAS at the falling edge of clock signal CLK.
Latch to detect whether a data read operation has been specified.
Read detection circuit 860 and signals / WE, / CAS
Rising edge of / RAS clock signal CLK
And whether the WCBR mode is specified or not
WCBR detection circuit 862 for detecting clock signal C
Address bits A0, A1, A at the rising edge of LK
2, an address latch 864 for latching A4 and A5,
Responds to WCBR detection from WCBR detection circuit 862
Address bit latched by the address latch 864.
Latency data is generated in accordance with
Latency decode latch 868 and WCBR
In response to WCBR detection from detection circuit 862,
Decode address bits A1 and A2 from latch 864
Wrap length decoder to load wrap length data
Switch 870, clock signal CLK and signal / CAS
Therefore, the latch circuit 86 for latching the bank address BA
6 and various control signals PAE, TLR, BA, OEM and
And an output control circuit 880 for generating DOT. The output control circuit 880 comprises a latch circuit 866
To the bank specified by the bank address latched in
Only generate necessary control signals. In FIG. 70,
Output control circuit 8 is applied to banks #A and #B.
It is shown that a control signal is generated in common from 80. The control signal generating system shown in FIG.
SDRAM shown in FIG. 44 or SDRAM shown in FIG.
It is applicable also in. Each applied signal is buffered
It may be considered that the internal signal has been processed. FIG. 71 shows the structure of the read detection circuit shown in FIG.
It is a figure showing an example of composition. In FIG. 71, lead detection
The circuit 860 receives the signal / CAS at the false input and outputs the signal / W
A gate circuit 901 receiving E at its true input;
The output of gate circuit 901 is latched at the rising edge of CLK.
D-type flip-flop 902 and D-type flip
It receives the output Q of the flop 902 and the clock signal CLK.
And an AND circuit 903. The gate circuit 901 receives a signal
/ CAS is at "L" and signal / WE is at "H"
Only outputs an "H" signal. Next, this lead detection
FIG. 72 is an operation waveform diagram of the operation of the road 860.
It will be described with reference to FIG. At the time of reading, the clock signal CLK is
At the rising edge, the signal / CAS becomes “L” and the signal / WE becomes
It is set to “H”. This makes the D-type flip-flop
The output Q of 902 rises to "H". AND circuit 903
Is high when both input signals are high.
Output a signal. As a result, the signal φr specifies the read mode.
Having the same width as the clock signal CLK when
It becomes a one-shot pulse signal. FIG. 73 shows an example of the configuration of the WCBR detection circuit.
FIG. In FIG. 73, WCBR detection circuit 8
62 receives signals / RAS, / CAS and / WE
The NOR circuit 904 and the rising edge of the clock signal CLK
D-type flip latch latching the output of the NOR circuit 904
The output of the flip-flop 905 and the D-type flip-flop 905
AND circuit 906 receiving force Q and clock signal CLK
including. The NOR circuit 904 has all three inputs.
An "H" signal is output only when the signal becomes "L". Next
The operation of the WCBR detection circuit shown in FIG.
This will be described with reference to FIG. 74 which is a waveform diagram. At the rising edge of clock signal CLK,
Signals / RAS, / CAS and / WE are set to "L"
You. As a result, the WCBR mode is designated. D type
The output of the flip-flop 905 is the clock signal CLK.
Rises to "H" at the rising edge of
Signal φWCBR output from path 906 also rises to “H”
To Thereafter, clock signal CLK falls to "L".
Signal WCBR also falls to "L". Next clock
In the cycle, the rising edge of clock signal CLK
The output of the NOR circuit 904 is “L”.
Therefore, the signal φWCBR maintains “L”. With this configuration
Only when the WCBR mode is designated.
BR is generated. FIG. 75 shows the latency decoding shown in FIG.
FIG. 3 is a diagram illustrating a configuration of a latch. In FIG.
WCBR detection signal φWC
Activated in response to BR, applied address bit
A decoder 907 for decoding A4 and A5;
Delay circuit for delaying BR detection signal φWCBR for a predetermined time
909 and a decoder in response to the output of the delay circuit 909.
And a latch circuit 908 for latching the output of 907.
In FIG. 75, when the latencies are 1, 2, 3 and 4,
A state in which four types are prepared is shown. Decoder 907
Decodes these 2-bit addresses A4 and A5
Then, one of the four latencies is activated.
Latch 908 responds to the output of delay circuit 909 to decode
The output of the latch 907 is latched. This causes the latch 908
Output LAT1E to LAT4E is active
And the latency data la is set. FIG. 76 shows the wrap length decoding shown in FIG.
FIG. 3 is a diagram illustrating a configuration of a latch. In FIG. 76, the wrap
The long decode latch 870 outputs the WCBR detection signal φWCB
Decode 3-bit addresses A0-A2 in response to R
And a WCBR detection signal φWCBR.
A delay circuit 912 that delays by a predetermined time;
A latch that latches the output of decoder 910 in response to the output.
Switch circuit 911. Decoder 910 receives the given address.
Decode the dress and select one of the eight wrap lengths
select. The latch circuit 911 outputs the output of the decoder 910.
Latch force. As a result, the output L of the latch circuit 911 is
EN1E, LEN2E, LEN4E, ... LENAE
One of them is selected. This allows lap length day
Is set. In FIG. 76, wrap length decoder
Switch 870 includes a WCBR detection signal.
Signal to perform decoding operation in response to signal φWCBR
Have been. This decoder 910 operates as a column selection operation start finger.
Address (column access start instruction)
It may be used also as a decoder for generating the data. Also, the delay circuit 909 shown in FIGS.
And 912 ensure the outputs of decoders 907 and 910
Provided for latching force. [PAE Signal Generation System] FIG.
FIG. 2 is a diagram illustrating a configuration of a enable signal generation system. Figure 77
, The preamplifier enable signal generation system
In response to the detection signal φR, corresponding to a predetermined latency
Latency counter 914 that counts the number of clocks
And the count-up signal from the latency counter 914.
Signal having a predetermined pulse width in accordance with the signal φu.
PAE generation circuit 916 for generating enable signal PAE
Including. The preamplifier PAE generation circuit 916 has a latency
When the count-up signal φu from the counter 914 is given
The delay circuit 913 that delays for a while and the output of the delay circuit 913
In response, a one-shot pulse with a predetermined pulse width
A one-shot pulse generation circuit 915 for generating
No. Next, the operation of the circuit shown in FIG. 77 will be described with reference to its operation waveform diagram.
This will be described with reference to FIG. The latency counter 914 detects the read
Count clock signal CLK in response to signal φR
You. The latency counter 914 stores the latency data 1
a (latency setting signals LAT1E to LAT4E).
And execute the count operation, and the count value
Counts up when it becomes equal to the value corresponding to data la
The signal φu is generated. In the PAE generation circuit 916
Means that the delay circuit 913 outputs the count-up signal φu at a predetermined time.
Delay for a while. One-shot pulse generation circuit 915 is
The predetermined pulse width (for example, clock
Pulse signal having substantially the same pulse width as the clock signal CLK)
Occurs. When the latency is 1 or 2, PA
E generation circuit 916 outputs the first clock signal CLK.
Pre-trigger triggered by rising edge (rising edge of signal φR)
An amplifier enable signal PAE is generated. Latency is
In the case of 3 or more, 2 clock support
Check the falling edge of the clock signal before the cycle (la-2).
The preamplifier enable signal PAE is generated as
You. This preamplifier enable signal PAE is generated
Later, a wrap address RWYi is generated. Delay circuit 9
13 and the one-shot pulse generation circuit 915
The delay time and delay time are set according to the set latency data.
And the pulse width may be adjusted. FIG. 79 shows the latency count shown in FIG.
FIG. 14 is a diagram illustrating an example of a specific configuration of the data 914. In FIG. 79
The latency counter 914 is connected in series in four stages.
The connected flip-flops FF1 to FF4 and the flip
Three-state buffer 92 receiving output Q1 of flop FF1
1 and 3 states receiving the output Q2 of the flip-flop FF2
State buffer 922 and output Q of flip-flop FF4
4 including a three-state buffer 923. First stage flip
The input of the flip-flop FF1 is connected to the read detection signal φR and
Complementary read detection signal / φR is applied. Flip flow
FF1 and FF3 respond to the clock signal CLK.
Input and output the given signal
You. Flip-flops FF2 and FF4 are complementary clocks.
Applied to the input in response to the rise of the clock signal / CLK.
The latched signal is taken in and latched. The three-state buffer 921 includes the AND circuit 92
When the output of “0” is “L”, it is activated. AND circuit
920 is a latency setting indicating latency 1 and 2 respectively.
Receives constant signals / LAT1E and / LAT2E. 3 states
State buffer 922 indicates latency 3 at its control input.
Receives latency setting signal / LAT3E. 3-state battery
Fa 923 is a control input whose latency indicates a latency of four.
Receives tension setting signal / LAT4E. Latency is 1
Or in case of 2, the 3-state buffer 921 is active
And in the case of latency 3, a 3-state buffer 922
Is activated, and in the case of latency 4, the 3-state
The buffer 923 is activated. FIG. 80 shows the flip-flop shown in FIG.
FIG. 3 is a diagram illustrating a specific configuration example. Referring to FIG.
The flip-flop FF (representing FF1 to FF4)
Receiving the input signal IN and the clock signal K (CLK or / CLK).
The two-input NAND circuit 926 and the complementary input / IN
N-input NAND circuit 925 receiving lock signal K, N
NAND circuit receiving the output of AND circuit 926 at one input
Path 928 and the output of NAND circuit 925 to one of its inputs.
, And a two-input NAND circuit 927 to be received. NAND times
Roads 927 and 928 have their outputs crossed by the other input
Are combined. The output of NAND circuit 928 is connected to output Q.
And the output of the NAND circuit 927 is connected to the output / Q.
You. In the configuration of the flip-flop shown in FIG.
When the clock signal K is "H", the inputs IN and
And / IN are applied to outputs Q and / Q, respectively.
Given. When the clock signal K is "L",
The output does not change regardless of the state of the force IN and / IN.
No. That is, the flip-flop shown in FIG.
In response to the rise of lock signal K, it goes through
The input IN and / IN are taken in and the rising of the clock signal K.
The latch state is entered in response to the fall. Next, FIG. 79 and
The operation of the latency counter shown in FIG.
This will be described with reference to FIG. Rising of clock signal CLK in first cycle
A read detection signal φR is generated in response to the deflection. this
In response to the rise of signal φR to “H”, flip-flop
The output Q of the flip-flop FF1 rises to “H” (in the initial state).
Means that all outputs Q1 to Q4 are reset to "L".
). The output Q1 of this flip-flop FF1 is
Flip-flop FF2 at the falling of lock signal CLK
Is taken in. The output Q2 of the flip-flop FF2 is
In response to the rising of clock signal CLK in two cycles
Fetched by flip-flop FF3. This flip
The output Q3 of the flip-flop FF3 is the flip-flop FF4
Falling of clock signal CLK in the second cycle
It is taken in response to the beam. That is, as shown in FIG.
The outputs Q1 to Q4 of the FFs FF1 to FF4 are clock signals.
Clock signal CLK having a pulse width twice that of the clock signal CLK.
Is a signal whose half cycle is shifted. Latency is 1
Or in the case of 2, the output Q1 of the flip-flop FF1
Preamplifier enable signal PAE is generated in response to
You. If the latency is 3, flip-flop FF
2 in response to the output Q2 of the preamplifier enable signal PA
E is generated. If latency is 4, flip
Preamplifier enable in response to output Q4 of flop FF4
A bull signal PAE is generated. [TLR Signal Generation System] FIG. 82 shows the transfer control signal.
FIG. 3 is a diagram showing a circuit configuration for generating a signal TLR. Figure
At 82, the TLR generator generates the clock signal CLK.
Preamplifier enable signals PAE and / PA
A flip-flop 930 that takes in the E
A three-state buffer 932 for receiving the output Q of the
Three-state buffer receiving reamp enable signal PAE
934 and the output of the 3-state buffer 932 or 934
A delay circuit 936 for delaying a predetermined time and a three-state buffer
932 or 934 and the output of delay circuit 936
Gate circuit 93 receiving intensity setting signal / LAT1E
8, the output of the gate circuit 938 and the latency setting signal L
An OR circuit 940 for receiving AT1E is included. The flip-flop 930 is shown in FIG.
It has the same configuration as that shown. Clock signal C
The signal PAE or the signal applied to the input at the rising edge of LK
And / PAE, falling of clock signal CLK
Latch. The 3-state buffer 932 has a latency setting.
When the constant signal LAT2E is “L”, the operation state is set. 3
The state buffer 934 includes a latency setting signal / LAT2
When E is "L", it is activated. Latency to 2
When set, the setting signal LAT2E becomes “H”.
You. Otherwise, the latency setting signal LAT2
E becomes "L". The gate circuit 938 includes a delay circuit 936
Is at "L" and the buffer 932 or 93
4 is at "H" and the signal / LAT1E is at "H".
The signal of "H" is output only at the time of. Latency is 1
In this case, the signal / LAT1E becomes "L",
Outside, the signal / LAT1E becomes "H". The OR circuit 940 outputs the signal φp (gate circuit).
938) and the setting signal LAT1E. Leyte
When the threshold is 1, the signal LAT1E is "H". This
In this case, the transfer control signal TLR is fixed at "H".
When the latency is 2 or more, the transfer control signal TLR becomes
It changes according to the output φp of the gate circuit 938. Gate
The output φp of the circuit 938 is output when the signal / LAT1E is “L”.
Sometimes it is fixed to "L". The gate circuit 938 is
It is activated only when the intensity is 2 or more. Game
In the active state, the buffer circuit 938
Or from the rising edge of the output of 934 to the delay circuit 93
One-shot pulse with delay time "H" given by 6.
Generate a signal. Next, the TLR generation circuit shown in FIG.
Will be described with reference to the operation waveform diagram of FIG.
You. When the latency is 1 or 2, the first
Clock cycle CLK as a trigger
The enable signal PAE is generated. Latency is 1
, The signal LAT1E is set to “H” and the transfer signal
TLR is fixed at "H". When the latency is 2,
The buffer 934 is activated and the preamplifier
A predetermined pulse width in response to the rise of the
Is generated from gate circuit 938.
It is. When the latency is 3 or more, the buffer
The one-shot pulse signal φp is generated according to the output of 932
Be born. At this time, the flip-flop 930
Signals PAE and / P at the rising edge of clock signal CLK.
Incorporating AE. Output Q of flip-flop 930
Rises to “H” in synchronization with the rise of clock signal CLK.
Go up. Therefore, if the latency is 3 or more,
The pulse signal φp from the gate circuit 938 is
"H" for a predetermined period triggered by the rise of signal CLK
Become. In FIG. 83, the pre-processing when the latency is 3
The generation mode of the amplifier enable signal PAE is shown as an example.
Is done. In the case of the latency 3, the second clock
Cycle (clock number 2) of the clock signal CLK
The one-shot pulse signal φp is triggered by the rising edge
Generated. As a result, the preamplifier enable signal PA
E is generated and the data on the global IO line pair is amplified.
Data is latched in the first latch of the read register.
After that, the final data is transferred to the next latch (SLRG).
It is. Thus, the preamplifier enable signal PAE is activated.
The transfer control signal TLR is generated after the
Data transfer between latches inside the
And read data by continuously accessing the same bank
If the data held in the read register is
Is prevented. [OEM / DOT Signal Generation System] FIG.
For generating data output control signals OEM and / DOT
FIG. 3 is a diagram showing a circuit configuration for the second embodiment. Referring to FIG.
The data output control signal generation system responds to the read detection signal φR.
Clock signal according to the set latency data.
A latency counter 1000 for counting CLK,
Count-up signal from latency counter 1000
Is activated in response to the
Lap length counter 100 for counting clock signal CLK
2 in response to the latency setting signal / LAT1E
And passes the preamplifier enable signal PAE
3-state inverter buffer 1004 and latency cow
Count-up signal from inverter 1000 or Invar
Set according to the signal from the data buffer 1004 and
For the count-up signal from lap length counter 1002
Therefore, it includes the OEM generation circuit 1006 to be reset. The latency counter 1000 is set
The number of clocks equal to the latency
(When latency is 2 or more). Lap length counter 10
02 counts the number of clocks equal to the set lap length.
Generates a count-up signal when counting. OEM
Output enable signal OEM is generated from generation circuit 1006
Is done. Further, the output enable signal OEM and the clock
Output control signal in response to signal CLK and signal / LAT1E
Signal / DOT generating gate circuit 1008 is provided.
You. Gate circuit 1008 includes a three-input NAND circuit.
Output enable signal OEM, latency setting signal /
LAT1E and clock signal CLK are both "H".
At this time, the signal / DOT is set to “L”. FIG. 85 shows the latency count shown in FIG.
FIG. 2 is a diagram showing a specific configuration of the data 1000. Fig. 85
The latency counter 1000 outputs the read detection signal φ
Shift for counting clock signal CLK in response to R
Counter 1009 and latency setting signal / LAT1E
~ / LAT4E, the output of shift counter 1009 is output.
Three-state inverter buffer 10 for selectively passing power
10, 1012, 1014 and 1016 and wrap length
To start the counter and reset the OEM generation circuit
Three-state inverter buffers 1018, 1020, 1
022 and 1024. The shift counter 1009 has eight stages in series.
Including connected flip-flops FF11 to FF18.
No. These flip-flops FF11 to FF18 are shown in FIG.
It has the same configuration as the flip-flop shown in
Of the rising clock signal CLK or / CLK
Capture the input. 3-state inverter buffer 1
010 is activated according to the latency setting signal / LAT1E.
And inverts the output Q1 of the flip-flop FF11
And transmits it on the signal line 1026. 3-state inverter bar
Buffer 1012 receives the latency setting signal / LAT2E.
In response, the flip-flop FF12 is activated.
The output Q2 is inverted and transmitted on the signal line 1026. The inverter buffer 1014 has a latency
Activated in response to the system setting signal / LAT3E,
The output Q4 of the flip-flop FF14 is inverted and the signal line 102
6 on. The inverter buffer 1016
Activated in response to the tension setting signal / LAT4E,
The output Q6 of the flip-flop FF16 is inverted and the signal line 1
026. This inverter buffer 1010
To be transmitted on signal line 1026 from
Is used to reset the lap length counter 1002
Can be The inverter buffer 1018 has a latency
It is activated in response to the system setting signal / LAT1E,
Output Q2 of flip-flop FF12 on signal line 1028
To communicate. Inverter buffer 1020 outputs signal / L
AT2E is activated in response to flip-flop
The output Q3 of the FF 13 is inverted and the signal lines 1030 and 1
028. The inverter buffer 1022 is
Activated in response to signal / LAT3E, flip
The output Q5 of the flop FF15 is inverted and the signal line 1030
And 1028. Inverter buffer 10
24 is activated in response to the signal / LAT4E,
The output Q7 of the flip-flop FF17 is inverted and the signal line 10
28. The signal on signal line 1030 originates from OEM
Used to reset the raw circuit. Signal line 102
8 drives the lap length counter 1002
Used for Next, the latency counter shown in FIG.
Referring to FIG. 86 which is an operation waveform diagram,
Will be explained. Inverter buffers 1010 to 1024
Can be selectively selected according to preset latency data.
Activated state. For example, if the latency is 1,
Operates the inverter buffers 1010 and 1018
State. Before the read detection signal φR is given
In this case, the signal lines 1030 and 1028 and 10
The potential of 26 is at "L". Clock signal of first cycle
In response to the rise of signal CLK, read detection signal φR
Generated. In response, the flip-flop FF1
1 output Q1 rises to "H". After that, flip flow
The flip-flops FF12 to FF18 output the given clock signal.
The signal applied to its input on the rising edge of
No. Therefore, the flip-flops FF11 to FF18
Of the clock signal CLK has a half cycle phase.
Is output. According to the set latency, this free
One of the outputs of flip-flops FF11 to FF17 is selected.
Selected. Therefore, the signal on signal line 1030 is
Rising edge of lock signal CLK (inverter 102
0 to 1024 are given according to the clock signal CLK.
Connected to the flip-flop that captures the signal)
Change. On the other hand, the signal on the signal line 1026 is
The inverted signal of the clock signal CLK except for the case of the tension 1.
It changes in response to the rise of / CLK. Latency is
In the case of 1, the signal on the signal line 1026 is a clock signal
It changes in response to the rise of CLK. That is, the signal
The signal potential on line 1028 is the signal potential on signal line 1026
It changes after a half cycle. In FIG. 86, signal lines 1026,
On 1028 and 1030, the clock signal CLK
Only one pulse signal with twice the pulse width appears
You. Signals on signal line 1030 are specified by latency
Active one clock cycle before clock cycle
State. The OEM generation circuit therefore operates on this signal line 1
Set according to the signal on 030 to generate signal OEM
(Except when the latency is 1). Latency is 1
In the case of, as shown in FIG.
The inverted signal of signal PAE is a three-state inverter buffer 100
4, the three-state inverter buffer 100
OEM generation circuit 1006 is set according to the output of 4
It is said. If the latency is 1, you can look ahead
It is not possible. If the latency is 1, the game
The output / DOT is inactive by the gate circuit 1008
Is set to “H”. FIG. 87 shows the wrap length counter shown in FIG.
FIG. 10 is a diagram illustrating an example of a specific configuration of the device 1002. FIG. 87
Referring to the wrap length counter 1002, the signal line 102
8 is activated in response to a signal on clock signal CLK
For executing a count operation in response to and / CLK
Lap length data / LEN1E,
According to / LEN2E, / LEN4E and / LEN8E
Then, the output of the shift counter is selected and the signal line 105 is selected.
0, an OEM generation circuit reset signal RST is generated.
The selector circuit 1042 is included. The shift counter 1040 has a 16-stage serial
Flip-flops FF21 to FF36 connected to
No. Each of the flip-flops FF21 to FF36 is shown in FIG.
Has the same configuration as the flip-flop shown in FIG. Frizz
The flip-flops FF21 to FF36 alternately receive the clock signal /
CLK and CLK are provided. Whether the selection circuit 1042 is in the driving state
Count the number of clocks according to the lap length data
Period equal to the number of clock cycles specified by the
To generate a reset signal when the time has elapsed.
The output of the shift counter 1040 is selected. The selection circuit 1042 calculates the wrap length data / L
In response to EN1E, the output of flip-flop FF22 is
Three-state inverter that inverts and transmits on signal line 1050
Buffer 1043 and flip-flop FF (not shown)
3 state inverter buffer 1 for inverting and amplifying 24 outputs
044 and the output of a flip-flop FF28 not shown
Is activated in response to lap length data / LEN4E
Three-state invar that inverts and amplifies and transmits to signal line 1050
Buffer 1045 and the output of flip-flop FF36.
Includes a three-state inverter buffer 1046 to select the force
No. The inverter buffer 1046 stores the wrap length data /
Activated in response to LEN8E, flip-flop F
Inverts and amplifies the output of F36 and transmits it on signal line 1050
You. The three-state inverter buffers 1043-
The flip-flop FF selected by 1046 has a clock
The output state changes according to signal CLK. Layten
Lap length after serial counter generates count-up signal
Number of clock cycles specified by data (wrap length + 1)
The OEM generation circuit is reset after
You. The lap length counter 1002 further outputs a signal
An inverter 1052 for inverting the signal on line 1028;
The output of the inverter 1052 and the signal on the signal line 1026 are
Receiving two-input NOR circuit 1055 and on signal line 1026
An inverter 1054 for inverting the signal of
2 which receives the signal on 8 and the output of inverter 1054
NAND circuit 1056 and the output of NOR circuit 1055
Gate circuit 105 receiving output of NAND circuit 1056
7 inclusive. The gate circuit 1057 includes a NOR circuit 1055
Is "H" or the output of NAND circuit 1056
Generates a reset signal RESET when is low.
You. In response to this reset signal RESET, the shift camera
Counter 1040 resets all its output states to "L".
Is The configuration of this reset corresponds to the flip shown in FIG.
In the flop, the reset signal RE is applied to the output Q.
A transistor that couples output Q to ground potential in response to SET
It is sufficient that one star is provided. Next, the rack shown in FIG.
The operation of the length counter is shown in FIG.
It will be described in the light of the above. In FIG. 88, when the latency is 2 or more,
The operation waveform in the case is shown. Falling of clock signal CLK
When the potential of the signal line 1026 falls to “L” at the edge,
Next, at the next rising of clock signal CLK, signal line 10
The signal potential of signal 28 falls to "L". In response,
The output of inverter 1052 rises to "H". On the other hand, the NOR circuit 1055 includes an inverter
1052 and the signal on signal line 1026
You. Therefore, clock signal CLK of clock number 0
Clock signal C of clock number 1 from the falling edge of
The output of the NOR circuit 1055 continues until the rising edge of LK.
It becomes "H". Similarly, the output of NAND circuit 1056 is
It becomes “L”. The output of gate circuit 1057 is NOR
According to the output of circuit 1055 and gate circuit 1056
Becomes “H”, a reset signal RESET is generated,
The reset of the output of the shift counter 1040 is executed.
After this reset, the falling edge of the clock signal CLK
The output of the inverter 1052 is flip-flop FF
21 and the output Q21 becomes "H". Responds to next falling of clock signal CLK
Then, the output Q22 of the flip-flop FF22 becomes "H".
Stand up. After that, every other flip-flop
A signal delayed by a clock cycle is output. Frizz
The output Q22 of the flip-flop FF22 is the wrap length data wr
Shows the case where the lap length is 1. The input of buffer 1044 is
The case where the wrap length is 2 is shown. Therefore, latencyica
The lap length data
After a lapse of a clock cycle equal to
2 generates a reset signal RST, and generates an OEM signal.
Is reset. FIG. 89 shows the wrap length when the latency is 1.
It is a figure showing operation of a counter. In FIG. 89, the ray
When the latency is 1, the clock signal of the first clock cycle is output.
The read detection signal φR is generated in response to the rise of the signal CLK.
When generated, the potential of signal line 1026 falls to "L" in response.
Go down. Then, in response to the falling edge of the clock signal, the signal
The potential of the line 1028 falls to "L". In the first clock cycle, the
NOR circuit 1055 and N
The output of the AND circuit 1056 is “H” and
It becomes “L”. As a result, the output of the gate circuit 1057 becomes
Becomes “H”, and the reset of the shift counter 1040 is executed.
Is performed. Clock signal CLK of first clock cycle
The flip-flop FF21 is turned on at the falling edge of
Capture signals applied to forces IN and / IN. This and
The output of the inverter 1052 is still "H".
Therefore, the output Q21 of the flip-flop FF21 is
The state of “L” is maintained. In the second clock cycle, the clock
When the signal CLK falls to "L", the flip-flop F
F21 takes in the output of this inverter 1052,
An "H" signal is output. Flip-flop FF22
Outputs the output Q21 of the flip-flop FF21 to the next
Captured at the rising edge of clock signal CLK,
Rising edge of clock signal CLK in lock cycle
Generates a signal which becomes "H". Hereinafter, the clock signal C
At the rising edge of LK, the required lap length
Output disabled after indicated clock cycle
A signal is generated to bring the state to a bull state. As described above, after the elapse of the latency,
Reset the OEM generation circuit after the elapse of the length cycle
Is generated. FIG. 90 is a circuit diagram of the OEM generation circuit shown in FIG.
It is a figure showing an example of composition. In FIG.
The raw circuit consists of two 2-inputs whose output and one input are cross-coupled.
Power NAND circuits 1060 and 1062. NAN
The other input of D circuit 1060 is a three-state inverter buffer
The output of 1004 and signal line 1030 are coupled. N
The other input of AND circuit 1062 is coupled to signal line 1050
Is done. Inverter circuit at output of NAND circuit 1062
1064 is provided. Out of inverter circuit 1064
A force enable signal OEM is generated. Next, in FIG.
FIG. 10 is an operation waveform diagram showing the operation of the OEM generation circuit shown in FIG.
This will be described with reference to FIG. The clock signal CL in the second clock cycle
In response to the rise of K, the potential of signal line 1030 becomes “L”.
(Latency count completed). But Leyte
This is the case when the number is 2 or more. In response to this,
In the raw circuit 1006, the output of the NAND circuit 1060 is output.
The force changes to "H". The signal potential on the signal line 1050 is
Since it is “H”, the output of the NAND circuit 1062 is
It becomes “L” and is generated from the inverter circuit 1064
Output enable signal OEM rises to "H". This out
The gate circuit 100 is responsive to the power enable signal OEM.
8, an output control signal synchronized with the clock signal CLK.
/ DOT is generated. When a predetermined lap length cycle is completed, a signal
Signal potential on line 1050 rises to "L" (nth
Cycle in response to the rising edge of the clock signal CLK).
As a result, the output of the NAND circuit 1062 becomes “H”.
You. Output enable signal via inverter circuit 1064
No. OEM falls to “L” and output disabled
It is said. In the case of latency 1, in FIG.
A signal waveform shown by a broken line appears. In this case,
Enable preamplifier by inverter buffer 1004
Output enable signal OEM is generated according to the signal PAE
Is done. Timing of falling of output enable signal OEM
Is the same as in the case of latency 2 or more. At this time,
The gate circuit 1008 outputs a signal because the latency is 1.
/ LAT1E is "L" and the output control signal / DOT is
It is fixedly maintained at “H”. When the latency is 1
Are output control signals DOT and / DOT for prefetching.
Is not necessary. [BA signal generation system] FIG. 92 shows the generation of BA signal.
It is a figure showing composition of a system. In FIG. 92, the BA signal is
The raw system responds to the read detection signal φR by a predetermined number of clocks.
Count and the count value reaches a predetermined value.
Counter circuit that generates a count-up signal when
1100 and the output of the counter circuit 1100.
A BA generation circuit 1106 for generating a control signal, and a BA generation circuit
Receiving the signal from the path 1106 as a set signal SET,
Lap length counter 110 for counting a predetermined lap length
4 and the bank address given during column access
BA latch 1108 that touches
Specify bank output of BA generation circuit 1106 according to power
Generated as signal BAA or bank designation signal BAB
A selection circuit 1110 is included. Lap length counter 1104
A structure similar to that shown in FIG. 87 is provided.
The latency storage circuit 1102 is the same as that shown in FIG.
It has the same configuration as the above. [0407] Counter circuit 1100 responds to signal φR.
Clock signal to shift
Latency counter for counting clock signal CLK
1112 and the output of the latency shift counter 1112
Is stored in the latency storage circuit 1102.
And an output selection circuit 1114 for selecting according to the information. Ray
The tension shift counter 1112 has a shift counter shown in FIG.
It has the same configuration as the counter. The output selection circuit 1114 is
Similarly, a three-state inverter buffer shown in FIG.
Two clock cycles before the specified latency
Latency shift counter to generate
The output of the counter 1112. If the specified latency is 1, the resource
Mode detection signal φR is selected by output selection circuit 1114.
And supplied to the BA generation circuit 1106. BA generation circuit
1106 has the same configuration as the OEM generation circuit shown in FIG.
And the output of the output selection circuit 1114 is used as a set signal.
To generate an active control signal. Lap head cow
The counter 1104 receives the signal from the BA generation circuit as a set signal.
As a signal, a predetermined lap length is counted. Predetermined
BA is issued when the lap length reaches the specified value.
The raw circuit 1106 is disabled. From BA
Raw circuit 1106 responds to falling of clock signal CLK
To generate an activation signal. The selection circuit 1110
According to the bank address BA latched by the latch 1108,
Therefore, one of the outputs BAB and BAB is selected.
The bank designation signal is sent only to the bank selected in this way.
The signal BAA (or BAB) is generated. The bank specifying signal generating system shown in FIG.
The configuration is based on the latency shift selected by the output selection circuit 114.
Only the output selection position of the
85, 87 and 90.
It can be realized by using. FIG. 93 shows the bank designation signal BAA (and
Shows an operation waveform diagram for generating BAB). Figure 93
In the case of latencies 1 and 2,
Signal φSO is generated from output selection circuit 1114 at the time of imaging
Is shown. If the latency is 2,
Activation signal φSO in response to the falling of clock signal CLK.
Is generated, and when the latency is 1, this read detection
In response to signal φR, a timing earlier than the timing shown in FIG.
Activation signal φSO from output selection circuit 1114
May be used. This is illustrated earlier
As shown in FIG. 85, when the latency is 1,
Generates signal φSO in response to contact signal φR,
In the case of 2, the signal φR at the falling of the clock signal CLK
And a structure for generating signal φSO may be used.
No. [Data Writing Circuit System] FIG. 94 shows the present invention.
Shows another configuration of the data write circuit system of the SDRAM according to FIG.
FIG. The data write circuit shown in FIG. 94 has been described above.
As in the case of the data read circuit system shown in FIG.
Applicable to both AM and SDRAM shown in FIG.
be able to. Therefore, in the following description, the signal /
RAS is not specified. Signal / RAS is applied SDR
It is set according to the AM operation method. Referring to FIG. 94, the data write circuit system includes:
Divided into bank #A and bank #B. Bank No. A
And bank #B have the same data write circuit system.
I can. In FIG. 94, one data is stored in bank #A.
Data write circuit provided for the data input terminal D
Show. Data writing system of banks #A and #B
Are commonly coupled to an input buffer 1200. Input battery
The fa 1200 receives data input according to the clock signal CLK.
Fetches data applied to terminal D to generate write data
You. Bank #A is connected to data input terminal D
Eight pairs of global IO line pairs GIO0 to GIO7
Write registers WG0-WG provided for each
G7 and write circuits WR0-WR7. The operation of the data write circuit system is controlled.
For example, the signals / CAS and / WE and the clock signal C
LK, the data write mode is specified
Write detection circuit 1204 for detecting, and write detection circuit 1
Activated in response to write detection signal φw from
Write wrap address in synchronization with the clock signal CLK.
Wrap address generating circuit 1202 for generating WWY
And the write detection signal φw from the write detection circuit 1204
Activated in response to clock signal CLK
To the wrap address WWY from the dress generation circuit 1202
Therefore, the corresponding global I from the write circuits WR0 to WR7
A document for controlling data writing to the O line pair GIO0 to GIO7
Control circuit 1206 is provided. [0415] Wrap address generation circuit 1202 and write
The write control circuit 1206 controls the bank address BA
Therefore, the wrap address only for the specified bank
And a write control signal. Wrap
Address generation circuit 1202 and write control circuit 1206
Each is provided for bank #A and bank #B
To the selected bank according to the bank address BA.
The corresponding wrap address generation circuit and write control circuit
An activated configuration may be used. The wrap address generation circuit 1202
Is a read wrapper to select the read register.
It may be shared with a circuit that generates a dress. The wrap address generation circuit 1202
Address BA and 3-bit addresses A0-A2.
Wrap to code and select write registers sequentially
Generates address WWY. This lap address is
It changes sequentially in synchronization with the clock signal CLK. Light Regis
The wrap address generation circuit 12
02 according to the wrap address given from
The write data given from the file 1200 is stored. [0418] The write control circuit 1206 operates the
And a predetermined number of write circuits WR0 to WR7 according to the
Activate each. That is, the write control circuit 1206
Indicates that data is written to all the write registers WG0 to WG7.
When it is inserted (in the case of wrap length 8), the write circuits WR0 to WR0
It does not activate WR7 at the same time. Write control circuit 1
206 is, for example, two bits of valid data written
When the corresponding write circuit is activated, the corresponding global I
The write data is transmitted onto the O line pair. This predetermined bit unit
Has the following advantages. [0419] The number of data specified by the lap length is always given.
Not always. For example, when the lap length is 8, 4
In some cases, only valid data is given. this
When operating with lap length 8, necessary data is written
Only after a predetermined clock cycle has passed since
No data is written to the memory cell. Accordingly
Write operation until the specified number of clock cycles elapses
Can not be stopped. Smell during data write operation
To stop writing data in the middle of the
), Write data is written only to the write register
Data is not written to the memory cell
It is. However, writing data in units of multiple bits
By writing from the register to the memory cell,
Even if a data loss occurs, data memory
Since the data is being written to the
A lap stop can be executed every cycle,
Fast access is possible. FIG. 95 is a block diagram of the write control circuit shown in FIG.
It is a figure showing an active composition. In FIG. 95, the write control
The path 1206 is a lap length setting for storing lap length data.
Circuit 1212 and a lap stop
Press length setting circuit 1214 and write detection signal φw
Is activated in response to the command and specified by the lap length setting circuit 1212.
Count the number of clocks one greater than the lap length
And a counter circuit 1210 for switching. Counter circuit 12
10 outputs the output WDE in response to the write detection signal φw.
Activated and specified by the lap length setting circuit 1212
In response to a number of clock cycles one greater than the length,
Activate. The write control circuit 1206 further includes a counter
Output WDE from circuit 1210 and lap stop length setting
Transfer in response to the wrap length data from circuit 1214
Transfer timing that generates transfer timing signal to enable
And the transfer timing generation circuit 121.
6 and the wrap address WWY in response to the
Write register (write circuit) specified by dress WWY
Generates a transfer control signal WEE that enables transfer to
Transfer control signal generation circuit 1218 and transfer control signal generation circuit
Transfer control signal WEE from path 1218 and counter circuit 1
210, in response to output WDE of write circuit WR0-WR
7 includes a transfer control circuit 1220 for controlling data transfer.
No. The transfer timing generation circuit 1216 outputs the signal
When WDE is active, lap stop length setting circuit 1
Inactive state for each lap stop length specified by 214
The transfer timing signal. That is, wrap
Stop length data defines one data transfer cycle
You. The transfer control signal generation circuit 1218 has a wrap address
Write to the write register (write circuit) specified by WWY
When the output of the transmission timing generation circuit 1216 is active
From the corresponding write circuit to the global IO line pair GIO
Write enable signal WEE that enables data transfer
I do. The transfer control circuit 1220
When output WEE is active, this transfer control signal
Transfer control signal from path 1218 (write enable signal)
Execute data transfer in response to WEE. [Write Register / Write Circuit] FIG.
Specific structures of the write register and the write circuit shown in FIG.
FIG. In FIG. 96, the transfer shown in FIG.
The transmission control circuit 1220 is also shown. In FIG. 96
Is a one-bit data register WGi and a write circuit WR
i is representatively shown. Write registers WG0-WG7
And write circuits WR0-WR7 have the same configuration as that shown in FIG.
It is prepared. Referring to FIG. 96, transfer control circuit 1220
Is a two-input NAND receiving signals WEEi and WDE
Circuit 1246 and an output of NAND circuit 1246
An inverter circuit 1245 is included. Signals WEEi and WDE are both at "H"
Becomes “L” when the output of the NAND circuit 1246 becomes “L”.
And onto global IO lines GIOi and / GIOi
Data transfer. The write register WGi has a wrap address
/ WWYi, the input buffer (see FIG. 94)
First taking in write data WD and / WD applied from
Output of the latch circuit 1300 and the inverter circuit 1245.
In response to the force, the latch data of the first latch circuit 1300 is
And a second latch circuit 1310 for receiving data. The first la
Switch circuit 1300 writes the wrap address / WWYi.
2-input OR circuit 1230 receiving data WD, wrap
2 inputs for receiving address / WWYi and write data / WD
OR circuit 1232 and OR circuits 1230 and 1232
-Input NAND circuit receiving the output of each of them at one input
1231 and 1233. NAND circuit 1231
And 1233 are cross-coupled at the other input and output
You. The second latch circuit 1310 has an inverter
The output of the circuit 1245 and the output of the NAND circuit 1231 are received.
-Input OR circuit 1234 and inverter circuit 124
5 receiving the output of the NAND circuit 1233
Power OR circuit 1236 and OR circuits 1234 and 123
6-input NAND receiving the outputs of 6 at one input
It includes circuits 1235 and 1237. NAND circuit 12
35 and 1237 are cross-coupled to the other input and output
Is done. [0428] The first latch circuit 1300 is
When the address / WWYi is “L”, the write data WD and
/ WD and the wrap address / WWYi changes to "H"
Then, the latched state of the fetched signal is established. Second
The latch circuit 1310 outputs the output of the inverter circuit 1245.
Is low, the output of the first latch circuit 1300 is taken.
And the output of the inverter circuit 1245 becomes “H”.
Then, a data latch state is set. The write circuit WRi is the NAND circuit 1246
Of the second latch circuit 1310 in response to the output of
A transfer circuit 1320 for transmitting data, and a transfer circuit 132
Amplifying the output of the global IO line GIOi and / or
Includes a preamplifier 1330 for transmitting onto GIOi. transfer
The circuit 1320 includes the NAND circuit 12 of the first latch circuit.
35 and the NAND circuit 12 of the transfer control circuit 1220
46, a two-input NOR circuit 1238 receiving the output of
Output of ND circuit 1237 and output of NAND circuit 1246
And a two-input NOR circuit 1239 receiving the following. Transfer circuit
1320 indicates that the output of the NAND circuit 1246 is “L”.
Then, the second latch circuit 131 functions as an inverter.
0 latch data is transmitted. Of the NAND circuit 1246
When the output is “H”, NAND circuits 1238 and 1238
The outputs 39 are both "L". The preamplifier 1330 is connected between the power supply node and ground.
N-channel MOS connected in series between potential node
The transistors 1240 and 1241 and the power supply node
Channel connected in series between the ground and the ground potential node.
MOS transistors 1242 and 1243.
Transfer times to the gates of transistors 1240 and 1243
The output of NOR circuit 1238 on path 1320 is transmitted.
Transfer times to the gates of transistors 1241 and 1242
The output of NOR circuit 1239 on path 1320 is provided.
Preamplifier 1330 connects to nodes Q64 and Q65.
When the potentials are both "L", transistors 1240-12
43 are all turned off and output high impedance
State. Next, the operation of the circuit shown in FIG. 96 will be described.
The operation will be described with reference to FIG. 97 which is an operation waveform diagram. First, when a write operation is designated, signal WD
E rises to "H". While this signal WDE is “H”
Is the number of clock cycles specified by the wrap length data wr
One clock cycle longer. During this period, the write data
Data WD rises to "H" (when data "1" is written).
H). After this, the wrap address / WWYi is selected
And falls to "L". Wrap address / WWYi
In response to the fall, the latch of the first latch circuit 1300
Node Q60 has a value obtained by inverting write data WD.
The data is latched. Until then, the previous access
The data written in the cycle is latched.
You. Next, the signal WEEi is output from this wrap address.
SW WWYi, the state becomes selected, and rises to “H”.
You. As a result, the second latch circuit 1310 operates as the first latch.
Latch data latched by the latch circuit 1300, and latch
The potential of the node Q62 becomes "H". In parallel with this
As a result, the transfer circuit 1320 becomes conductive, and the node Q64
Is determined to be “L”. Here, the signal WEEi is
Until “H”, both outputs of the transfer circuit 1320
It has been reset to "L". This allows Transis
Transistors 1240 and 1243 are off, transistor 1
242 and 1241 are turned on, and the global I
The potential on the O line GIOi rises and data "1" is written.
It is. Here, in FIG. 97, the global IO line G
IOi potential is read from memory cell from precharge potential
Changes according to data, then changes according to write data
Is shown. Global IO line GIOi and
/ GIOi floats at precharge potential
Yes, before connecting to the local IO line pair,
The pump 1330 may be activated. [WDE Signal Generation System] FIG.
Specific configuration of lap length setting circuit and counter circuit shown
It is a figure showing an example. In FIG. 98, the lap length setting circuit
And the counter circuit according to the wrap data wr.
(Wr + 1) count to count the number of locks (wr + 1)
1350 and a write detection circuit 1204
Set in response to output signal φw, and (wr + 1) count
Reset in response to the count-up signal of
Including a flip-flop 1360. Flip-flop
1360 receives write detection signal φw at one input.
Input two-input NOR circuit 1361 and (wr + 1) count
Input N receiving the output from the data 1350 at one input
An OR circuit 1362 is included. NOR circuits 1361 and 1
Reference numeral 362 indicates that the other input and output are cross-coupled. NO
Signal WDE is output from R circuit 1362. The (wr + 1) counter 1350 is shown in FIG.
It has the same configuration as the shift counter shown
The clock signal CLK is counted in response to the signal φw.
The count value is greater than the wrap length indicated by the wrap data wr.
A reset signal is generated when the value of the counter is also increased by one. this
(Wr + 1) counter 1350 includes a wrap length setting circuit.
No. FIG. 99 is a signal wave showing the operation of the circuit shown in FIG. 98.
FIG. The count shown in FIG. 98 with reference to FIG.
The operation of the data circuit will be described. In the first clock cycle, signal / C
AS and / WE are set to “L” and the write mode is
It is specified. In response, the light detection circuit 1204
Generates a write detection signal φw. In response to this
As a result, the flip-flop 1360 is set, and N
The output signal WDE of the OR circuit 1362 rises to “H”
You. The (wr + 1) counter 1350 detects this write detection signal.
Count operation of clock signal CLK in response to signal φw
Execute. If the lap length is n, (wr + 1) counter
1350 is the rise of the clock signal in the (n + 1) th cycle
The reset signal φRES is generated in response to the resetting. FIG.
9, the (n + 1) th cycle of the clock signal
Reset signal φRES is generated in synchronization with falling
The status is indicated. Thereby, the flip-flop 136
0 is reset, and the signal WDE falls to "L". In the configuration shown in FIG.
Set NOR type flip-flop in response to signal φw
The (wr + 1) counter 1350 outputs the clock signal C
Generates reset signal φRES in synchronization with falling of LK
are doing. Instead, the flip-flop 1360
A delay signal of write detection signal φw is applied to set input S.
You may be. Also, the (wr + 1) counter 1350
Generates an activation signal in synchronization with the rise of the lock signal,
A signal obtained by delaying this activation signal for a predetermined time is flip-flopped.
Configuration applied to the reset input R of the
May be used. [WEE signal generation system] FIG.
FIG. 3 is a diagram showing a specific configuration of a transfer control signal generation circuit shown in FIG.
You. In FIG. 100, transfer control signal generation circuit 1218
Is a two-input NA receiving signal / WERSTf at one input
ND circuit 1370, mask data MD and wrap address
WWYi, a two-input NOR circuit 1372, and N
The output of the OR circuit 1372 is received at one input, and the NAND circuit
Gate circuit 137 receiving the output of path 1370 at the other input
4 and two inputs receiving signal / WERST at one input
NAND circuit 1376 and output of NAND circuit 1370
At one input, and the other input of NAND circuit 1376
Includes two-input NAND circuit 1375 receiving an output. The NAND circuit 1370 has a gate connected to the other input.
The output of the NAND circuit 1376
Receives the output of NAND circuit 1375 at the other input
You. Inverter receiving output of NAND circuit 1376
Signal WEEi is generated from path 1377. Signal / WE
RST is a delayed signal of the signal WERSTf. The signal MD is write mask data.
When the data MD attains “H”, the
A mask is applied (see FIG. 27). This mask day
When the data MD is “H”, the output of the NOR circuit 1372 is
Fixed to “L”. Signals / WERSTf and / WE
NAND circuit 137 regardless of "L" or "H" of RST
5 is fixed at “L”, and the signal WEEi changes to “L”.
Become. That is, this mask data MD is in an active state.
If data writing is masked,
No data transfer is performed. Next, the transfer shown in FIG.
FIG. 4 is an operation waveform diagram of the operation of the control signal generation circuit.
This will be described with reference to FIGS. In FIG. 101, the wrap length is 4,
Indicates the operation waveform when the stop bit length is set to 2.
You. The mask data MD is “L”. In the first clock cycle, signal / C
AS falls to "L" and the start of column selection operation is specified.
At the same time, a data write operation is designated. In response to this
Wrap address / WWYi is generated, and signal W
DE rises to "H". Responds to rising edge of signal WDE
Signal / WERSTf rises to an inactive state of "H"
After a predetermined delay time, the signal / WERST is
It rises to “H”. At this time, the wrap address / WWY
When i is at “L”, the output of the NOR circuit 1372 is
The output of the gate circuit 1374 rises to “H”,
It rises to “H”. The signal / WERSTf becomes “H”
And the output of the NAND circuit 1370 changes to “L”,
Then, the output of the NAND circuit 1375 becomes “H”. signal
/ WERST then rises to "H", and the NAND circuit
The output of 1376 becomes “L” and the inverter circuit 137
7 rises to "H". During the period when signal / WERSTf is at "H",
The wrap address / WWYi changes from "L" to "H".
To the false input of the gate circuit 1374
And the output of NAND circuit 1370
Does not change. That is, the signal / WERSTf becomes “H”.
Changes to the active state,
Address is latched. The signal / WERSTf is shown in FIG.
In the embodiment shown, the clock is latched every two clock cycles.
Address WWY is latched. Signal WERST is higher than signal / WERSTf
The active state is also delayed
This is to secure the data write time of the data. That is, the figure
In the embodiment shown in FIG.
In the third clock cycle
Data can be written to memory cells, and sufficient
Data writing time can be secured. 2 bit unit
2 clock cycles
A lap stop can be performed for each file. For example, in the configuration shown in FIG.
Start column access in 6 clock cycles
When writing is performed, the
With a stop and a new column access started
think of. At this time, signals WEE0 and WEE1 are active.
State, and the write registers corresponding to these signals
Data is written from the master to the 2-bit memory cell.
Has been done. Therefore, a new column access in this state
Even if it is started, the previously written 2-bit data is
It has been written to the memory cell. FIG. 102 shows data when the lap length is 1.
FIG. 4 is a signal waveform diagram showing a write operation. When the lap length is 1
, Only one bit of external data is input.
Therefore, data is written to the selected memory cell bit by bit.
Must be included. Therefore, as shown in FIG.
In addition, the signal / WERSTf is larger than when the wrap length is 2 or more.
Also set to inactive state ("H") one clock cycle earlier
I do. The signal / WERST is in the second clock cycle
Maintain the inactive state. In this state,
Data has been written to the selected memory cell from the
You. That is, in the case shown in FIG. 102, the first clock cycle
Signals, / WERSTf and / WERST
Becomes inactive ("H" state) and the second clock cycle
Signal starts, the signal / WERSTf becomes active,
Falling of clock signal CLK in second clock cycle
Signals / WERST and WE0 go low.
Go down. [Transfer Timing Generation System] FIG.
Control signal / WERSTf and / WERST
FIG. 3 is a diagram showing a circuit configuration for the second embodiment. The circuit shown in FIG. 103
Corresponds to the transfer timing generation circuit 1216 shown in FIG.
Respond. Referring to FIG. 103, transfer timing generating circuit
1216 is the clock signal CLK in response to the signal WDE.
Counts and generates a timing signal.
Path 1380 and the tie from this timing circuit 1380.
Logic processing of the ming signal to generate signals / WERSTf and /
A logic gate 1382 for generating WERST is included. FIG. 104 is a timing chart of FIG.
It is a figure showing an example of the composition of a road. Referring to FIG.
Timing circuit 1380 provides signals WDE and / WDE
Flow in response to the clock signal / CLK
FF79, signal WDE and flip-flop FF7
9 and the stop bit length are specified (actual
In the embodiment, the stop bit length is 2) the signal is flipped
3-input NAND received from complementary output of flop FF81
Circuit 1395 and the output of the NAND circuit 1395 are inverted.
Inverter circuit 1397 and NAND circuit 1395
The output and the output of the inverter circuit 1397 are connected to the signal CLK.
A flip-flop FF80 that takes in in synchronization with the rise,
Clock the outputs A and / A of flip-flop FF80.
Flip-flop that is captured in synchronization with the rise of the
Output of flip-flop FF81 and flip-flop FF81.
Flip-flip taken in in synchronization with lock signal CLK
And the output B of the flip-flop FF82
And / B in response to the rising of clock signal / CLK.
And a flip-flop FF83 to be loaded. The flip-flops FF80 to FF83 are
It has the same configuration as the flip-flop FF79. Flip
The flop FF79 includes four NAND circuits 1390, 1
392, 1394 and 1396. This flip
The configuration of the flop FF79 is similar to the flip-flop shown in FIG.
It has the same configuration as the
Performs an operation to capture a given signal in response to
You. Next, the operation of the timing circuit shown in FIG.
This will be described with reference to FIG. 105 which is a waveform diagram. In clock cycle 1, signal WDE
Rises to “H”. At this time, the complementary signal / WDE becomes
It becomes “L”. Synchronized with the falling of the clock signal CLK
As a result, the output Q80 of the flip-flop FF79 becomes “H”.
Get up. The clock signal C of this first clock cycle
The flip-flop FF81 responds to the fall of LK.
Signal power of outputs A and / A of flip-flop FF80
Pass the rank. At this time, the flip-flop FF80
Is "H". Therefore, the NAND circuit
All the outputs of 1395 become “H” and the NAND circuit 1
395 becomes “L” and the inverter 1397
Becomes "H". In the second clock cycle, the clock
In response to the rise of signal CLK, flip-flop F
F80 is the inverter circuit 1397 and the NAND circuit
The output of the path 1395 is taken. This allows flip-flops
The potential of the output A of the flip-flop FF80 rises to "H". This second
Responds to the falling edge of the clock signal in two clock cycles
And the flip-flop FF81 is
80 outputs A and / A, and a flip-flop F
The potential of the output Q82 of F81 becomes "H". In the third clock cycle, flip
Since the output Q82 of the flop FF81 is "H", NA
The output of the ND circuit 1395 becomes “H”,
The output of the path 1397 becomes “L”. Therefore this third
In the clock cycle, the flip-flop FF80
Output A falls to "L". On the other hand, output B of flip-flop FF82
Rises to "H". The clock of this third clock cycle
Flip-flop FF in response to the falling edge of the clock signal.
83 is the output B and / B of the flip-flop FF82
Therefore, the output C of the flip-flop FF83 is
It rises to “H”. On the other hand, the flip-flop FF81
Fetch outputs A and / A of flip-flop FF80
Therefore, the output of node Q82 falls to "L". Less than
This operation is repeated while the signal WDE is at "H". In FIG. 105, when the wrap length is four
Are shown, and the signal WDE is changed in the fifth clock cycle.
Rise or fall of clock signal CLK
Falls to "L". This allows flip flip
FF80, FF81, FF82 and FF83
Outputs are sequentially shifted by 1/2 clock cycle each
Fall to "L". Flip-flops FF80 to F
F83 responds to the signal WDE, and the phase is
Clock signal CLK is shifted by サ イ ク ル cycle, and
A pulse signal whose pulse width is twice the clock signal CLK
Has occurred. Flip-flops FF80 to FF83
The signal / WERSTf and the output signal
And / WERST as stop bit length 2
be able to. Since the stop bit length is 2,
The output of the flip-flop FF81 is the NAND circuit 139
5 has been fed back. Stop bit length
If it extends further, connect this flip-flop further.
Then, the output of the subsequent flip-flop is the NAND circuit 1
395. FIG. 106 shows the logic gate 1 shown in FIG.
FIG. 382 is a diagram showing a specific configuration of the 382. Referring to FIG.
Therefore, the logic gate 1382 operates at the timing shown in FIG.
And the complementary output / A of the flip-flop FF80 of the circuit.
OR circuit 140 receiving output C of flip-flop FF83
0, the signal WDE and the output of the OR circuit 1400
An input NAND circuit 1402 and a wrap length designating signal LEN
1E and / LEN1E, the NAND circuit 14
Three-state inverter buffer 1 for inverting and amplifying the output of F.02
408 and the flip-flop FF82 shown in FIG.
Receiving inverted output / B and output C of flip-flop FF83
Circuit 1404, the signal WDE and the OR circuit 140
4, a two-input NAND circuit 1406 receiving the output of
Delay circuit for delaying output of ND circuit 1406 for a predetermined time
1410 and the output of NAND circuit 1406
Activated in response to constant signals LEN1E and / LEN1E
Three-state inverter buffer 1409
including. [0455] The signal LEN1E is output when the wrap length is one.
It becomes "H". That is, when the lap length is specified as 1
The inverter buffer 1408 is activated.
You. If the wrap length is 2 or more,
1409 is activated. Next, the logic shown in FIG.
The operation of the gate will be described with reference to FIG.
Will be explained. When signal WDE rises to "H", NAN
D circuits 1402 and 1406 serve as inverter circuits
Function. Nodes / A and / B are still "H" at this time.
Of the NAND circuit 140.
2 and 1406 at the rising edge of this signal WDE.
In response, it falls to "L". Wrap length designation signal LEN1
Regardless of whether E is "H" or "L", the signal
The potential of / WERSTf rises to "H". This
Signal / WERST from delay circuit 1410 is delayed for a predetermined time.
Rises to “H”. If the lap length is 1,
The barter buffer 1408 is activated. Second black
Node / A falls to "L" in the clock cycle
And the output of the OR circuit 1400 becomes "L".
The output from the inverter buffer 1408 falls to "L".
You. Use of Write Control Circuit Having the Above Structure
Lap stop operation can be realized
Obtaining SDRAM that can be accessed at high speed
it can. [Global IO Line Precharge / Equal
Control of Rise Timing] See FIGS. 18 and 19.
As shown, the global IO line pair GIO
A transistor GEQ is provided. Global IO
The wire pair GIO is connected as shown in FIGS.
The internal data is connected to the register and the write register.
Select memory cell and read register / write register
To communicate with. The speeding up and consumption of transmission of this internal data
In order to reduce the current, the global IO line pair
Equalize transistor responding to rise signal φGEQ
Each global IO line of a global IO line pair by GEQ
Equalized to the intermediate potential (the logic high level
(A potential between the logic low level). Choice
Local IO line provided for memory block
It is necessary to equalize for LIO as well
You. Rows provided for unselected memory blocks
Internal data is transmitted to the Cal IO line pair LIO.
Therefore, the standby state is maintained. In the following description, the global IO line
The equalizing operation for pairs will be described.
For the local IO line pair provided for the memory block,
Even the same as the global IO line pair
Control is executed. Hereafter, this equalization timing system
I will explain. (I) Control Method 1 FIG. 108 shows the first internal data line equalizing timing.
FIG. 4 is a timing chart illustrating a control method. The following
In the description, the internal data line is a global IO line
And a local I provided for the selected memory block.
Includes both O lines. The equalize timing shown in FIG.
The writing control is performed according to the write control method shown in FIGS.
Corresponding. As shown in FIGS. 97 to 99, external
When the lock signal CLK (ext.CLK) rises,
External column address strobe signal / CAS (ext /
CAS) is at the low level, the start of the column selection
Is shown. Write enable signal / WE is low at that time
If it is at the level, data write is specified and write enable
Data read is specified if the bull signal / WE is at high level
Is done. As shown in FIG. 99,
The write circuit includes a write enable signal WEEi and a signal WD.
Write data to the internal data line according to E. This writing system
Control signal WDE is latched after data write instruction is given.
After the elapse of a clock cycle equal to the
Inactive in the cycle. FIG. 108
In the data write operation sequence when the wrap length is 4,
Indicates Kens. In addition, four gross
Only the global IO line pairs GIO1 to GIO4 are shown. Next
The operation will be described below. During standby (column select instruction is given)
In the previous), the equalizing signal φGEQ is at a high level.
It is in. In this state, global IO line pair GI
Oi are all equalized (precharged) to an intermediate potential.
Have been. In clock cycle 1, external clock
Signal ext. External column address at the rise of CLK
The dress strobe signal ext / CAS is set to low level.
Column selection start instruction (column access start
Shown). Now, not shown in the figure,
Enable signal / WE is also at low level, and data write
Is assumed to be specified. In this state, data input / output terminal D
/ Q is the wrap address / WWY
(See FIG. 96).
At this time, internal write control signal WDE indicates data writing again.
Set to the active high level in response to a write command.
Is determined. This write control signal WDE is a write command
Is counted and the lap length is counted.
Inactive state in the clock cycle. At this time, a column selection start instruction signal (write
Command), the equalizing signal φGEQ
Becomes inactive and becomes low level. This allows
Global IO line pairs GIO1 to GIO4 are floating
State. At the same time, respond to the column selection start instruction signal.
In response, the column selection signal CSL is internally set to a high level,
Memory cell block selected by the column selection signal CSL of
Data in the global I / O
It is transmitted on the O line. Next, in the first clock cycle,
Data D1 is transmitted to global IO line pair GIO1.
Is reached. Thereafter, in each clock cycle, the data
Data D2 and D3 applied to data input / output terminals D / Q and
And D4 are stored in the write register.
Internal data line, ie, global I
Transmitted on O line pair GIO2, GIO3 and GIO4
You. The wrap length data D1 to D4 are internal data lines
GIO1 to GIO4 are transmitted on the local IO line pair.
Is written to the selected memory cell via
Clock cycle is the column selection start instruction (write command
C), the next clock cycle
In this case, the column selection signal CSL becomes inactive. Ma
At this time, the equalizing signal φGEQ
It is activated in synchronization with the signal and goes high. This
Global IO line pairs GIO1 to GIO4
It is precharged / equalized to the right. At this time
In addition, when the write enable signal WDE is
It becomes. As described above, a column selection start instruction is given.
Then, the equalize signal φGEQ is deactivated and the column is selected.
A clock signal equal to the wrap length given the start instruction signal
Cycle, the next clock cycle
The equalizing signal φGEQ of the
Before writing data by setting the level (active state)
After the global IO line pair is equalized,
Write data at high speed without the need to write data
Can be. When the lap length is changed, the lap length is changed.
The equalize signal φGEQ is activated according to the data.
It is. Therefore, equalization is always performed at the optimal timing.
The signal φGEQ can be generated. FIG. 109 shows an equalizer in data reading.
FIG. 4 is a diagram illustrating a noise control method. In FIG. 109, C
Equalization when AS latency is 3 and lap length is 4
The control operation is shown. Now, referring to FIG. 109, at the time of data reading,
The equalizing timing control operation in
You. In clock cycle 1, external clock
Signal ext. External column at rising edge of CLK
Address strobe signal / CAS is set to low level.
It is. The write enable signal / WE (not shown) is high.
Set to bell. This gives a column selection start instruction.
And the data read is specified (read command
Is given). In response to this column selection start instruction,
The rise signal φGEQ is set to the inactive low level.
You. As a result, the global IO line pair GIO is
Floating state at the noise potential. [0477] Column select signal CSL rises to a high level.
And the note on the corresponding column in the selected memory cell block
Recell data is lost via local IO line pair LIO.
Is transmitted to the global IO line pair GIO1 to GIO4. This global IO line pair GIO1 to GIO
4 appear in parallel, as shown in FIG.
It is transmitted to the read register (via the preamplifier). This global IO line pair GIO1 to GIO
After transferring the data on 4 to the read register, equalize
The signal φGEQ is set to the active high level, and the global
The potential of the IO line pair GIO1 to GIO4 is equal to the intermediate potential.
Be raised. Data stored in this read register
Is the clock cycle (CAS) at which the CAS latency has elapsed.
Cycle 4) to the clock signal ext. Synchronous with CLK
Output data Q1, Q2, Q3 and Q4.
Is transmitted to the data input / output terminal D / Q. As shown in FIG. 109, global IO lines
The data on GIO1 to GIO4 is transferred to the read register.
After being sent, the global IO line pair GIO1 to GIO4
Since the global IO line pair is
Data need not be equalized before being read there.
Data can be read at high speed. FIG. 110 shows the state shown in FIGS.
FIG. 3 is a diagram showing a configuration for generating an equalizing signal.
You. In FIG. 110, the equalizing signal generation unit
External signals / CS, / CA synchronized with clock signal CLK
S and / WE are taken in, column selection disclosure instruction
Column access judgment times to judge read / write mode
Signal in synchronization with the path 2000 and the external clock signal CLK.
/ WE, CAS and address signal Add, and
When the CBR condition is designated, the address signal A at that time
dd is decoded and stored as wrap length data.
Length setting circuit 2003 and column access determination circuit 20
Activated in response to the column selection start instruction detection signal from 00
And counts the external clock signal CLK.
Lap length set in the lap length setting circuit 2003
Counter that generates a count-up signal when equal to
2001 and the output of the column access determination circuit 2000
Preamplifier enable signal PAE (see FIGS. 63 to 65)
Response) and the counter 2001 count-up signal.
Signal equalizing signal φGEQ
Including a raw circuit 2002. Equalize signal generation circuit 200
2 from the global IO line
Equalize transformer provided for GIOi and / GIOi
It is provided to the gate of the register GEQ. The structure of the counter 2001 is as follows.
For example, use the same configuration as the latency counter shown in FIG.
can do. The counter 2001 is shown in FIG.
A configuration similar to the configuration shown in 79 may be used. Luck
The length setting circuit 2003 detects the WCBR detection time shown in FIG.
Path 862 and wrap length decode latch 870.
You. FIG. 111 shows the column access shown in FIG.
Of the configuration of the source determination circuit and the equalization signal generation circuit
FIG. In FIG. 111, the column access
The constant circuit 2000 is synchronized with the internal clock signal CLK.
Capture signals / CS, / CAS and / WE and write
Command to detect whether a command has been given
In synchronization with the output circuit 2010 and the external clock signal CLK.
To capture signals / CS, / CAS and / WE
Read command that detects whether or not a command has been given
In synchronization with the detection circuit 2012 and the external clock signal CLK,
Signal / CS, / CAS, / WE and / RAS
To detect whether a prechart command has been given
Precharge command detection circuit 2014
Write command detection signal from command detection circuit 2010
Set in response to the precharge command detection circuit
In response to the precharge command detection signal from 2014
And reset flip-flop 2
016 and the lead from the read command detection circuit 2012.
Is set in response to the
Precharge command from the command detection circuit 2014
Set / reset reset in response to the load detection signal
And a flip-flop 2018. The flip-flops 2016 and 2018
Outputs a high-level signal from its Q output when set
Output a low level signal from the Q output at reset.
You. Write command detection circuit 2010, read command
Detection circuit 2012 and precharge command detection circuit
FIG. 39 shows how each of the commands 2014 detects a command.
Please refer to the combinations of states of the external control signals shown in FIG. The Q output of flip-flop 2016 is shown in FIG.
Count start instruction signal to the counter 2001 shown in FIG.
(Counter activation signal). Counter 2
001 is the Q output from the flip-flop 2016
When the external clock signal CLK is
And the count value is included in the lap length setting circuit 2003.
When the wrap length is reached, it responds to the next clock signal.
In response, a count-up signal φCNT is generated. [0488] The equalizing signal generation circuit 2002 operates according to the structure shown in FIG.
From the counter 2001 shown in FIG.
Count-up signal φ that indicates the
CNT and set / reset flip-flop 2016
AND circuit 2020 receiving the Q output from
Q output of reset flip-flop 2018
FIG. 64, FIG. 55 and FIG.
7) and an AND circuit
OR circuit 202 receiving outputs of 2020 and 2022
4 and the outputs of the command detection circuits 2010 and 2012
Circuit 2026 receiving the output and the output of the OR circuit 2024
And is set in response to the output of the OR circuit 2026.
/ Reset flip-flop reset by reset
2028. Set / reset flip-flop 202
8 receives the output of the OR circuit 2026.
Output of the one-shot pulse generation circuit 2027
Can be The signals φCNT and PAE are pulse signals.
The set signal is output from the OR circuit 2024 only during a predetermined period.
Generated. Reset pulse is a pulse with a predetermined time width
One-shot pulse generation circuit 2027 is provided for
Can be This set / reset flip-flop 202
8 generates an equalize signal φGEQ. Then work
Will be described briefly. A write command or a read command is given.
If so, flip-flop 2016 or 2
018 becomes high level, and the OR circuit 20
26 output becomes high level and the one-shot
From the pulse generation circuit 2027 having a predetermined time width.
A reset pulse is generated and a set / reset flip
It is applied to the reset input R of the flop 2028. this
Output from the Q output of the flip-flop 2028
The equalizing signal φGEQ attains a low level. When a write command is given,
The output Q of the flip-flop 2016 becomes high level.
Accordingly, counter 2001 shown in FIG. 110 is activated.
The internal clock signal CLK is counted. Cow
The counter value of the counter 2001 is set to the wrap length shown in FIG.
One greater than the lap length data stored in the constant circuit 2003
When the threshold value is reached, the count-up signal φCNT is generated.
It is. Accordingly, the output of the AND circuit 2020 becomes high.
Level and set / reset via the OR circuit 2024.
Flip-flop 2028 is set and the equalizer
Signal φGEQ attains a high level. When a read command is given,
The Q output of the lip flop 2018 becomes high level.
At this time, the flip-flop 2016 is not set.
Therefore, the Q output is at a low level and the counter 20
01 does not execute the count-up operation. Preampui
The enable signal PAE rises to a high level for a predetermined period.
And the output of the AND circuit 2022 becomes high level,
Set / reset flip-flop via R circuit 2024
2028 is set, and the equalizing signal φGEQ is
High level. When one memory cycle is completed,
When a flip command is given, the flip-flop 201
6 and 2018 are reset and their Q outputs are both
Low level. At this time, the set / reset
The lip flop 2028 is in the set state.
Therefore, during standby, equalizing signal φGEQ is high.
Maintain a level. In addition, one memory cycle, that is,
Read command when the active command is given
Operation when a write command is given and then a write command is given
Modes are possible. In this case, the precharge command
Are not given, so flip-flop 2016 and
2018 are both set. However,
If the write operation is performed after the read operation, the pre-
Enable signal PAE is not generated at the time of writing.
The equalizer according to the signals PAE and φCNT, respectively.
Noise signal φGEQ can be set. Ma
The one-shot pulse generation circuit 2027
Command according to the write command and write command.
Rise signal φGEQ can be set to low level
You. A read operation is performed next to a write operation.
In this case, the counter 2001 operates even during the read operation.
Maintain the activated state. In this case, the counter 20
01 is the count-up signal φCN even when reading.
It is possible to generate T. To prevent this
Indicates that the Q output of the flip-flop 2018 is at a high level.
Sometimes, AND circuit 2020 is disabled.
And the output Q of the flip-flop 2016 is at a high level.
In this case, the AND circuit 2022 is disabled.
Of the flip-flops 2016 and 2018
Connect the Q output to the inputs of AND circuits 2022 and 2020.
You can continue. FIG. 112 equalizes the local IO line.
For generating equalizing signal φLEQ for
It is a figure showing a road composition. In FIG. 112, the local I
The equalizing signal φLEQ generation system for the O line
Signals / RAS and / CS in synchronization with clock signal CLK.
To detect whether an active command has been given
An active command detection circuit 2030 and an active command
Active command detection from command detection circuit 2030
Address signal given at that time in response to the signal
Latches a predetermined bit (block address) of the
A block address decode latch 2032 to be loaded,
The block from the block address decode latch 2032
Clock instruction signal φBKS and inverted equalize signal / φGEQ
Receiving NAND circuit 2034. Block address decode latch 2032
Connects the local IO line to the global IO line
Selection control signal φB for
Memory block to connect lock to sense amplifier
Selection control signal φA is generated. Block selection signal φB
KS is a signal similar to these block selection control signals.
You. Equalization of local IO line pair from NAND circuit 2034
Rise signal φLEQ is generated. Next shown in FIG.
The operation of the circuit will be described with reference to FIG.
explain. At the rise of clock signal CLK, the signal
If / RAS and / CS are both at low level,
Active command to access the memory array.
The cycle is specified. However, in FIG. 113,
Signals CLK and / CS are not shown. This acty
Block address decode latch according to the
Block selection signal φB at a predetermined timing from 2032
KS is generated. This block selection signal φBKS is
High level only for the selected memory block
Low level for unselected memory blocks.
You. During standby, block select signal φBK
Since S is at the low level, the NAND circuit 2034 outputs
The generated equalize signal φLEQ is at high level.
Therefore, the local IO line pair is equalized. A read command or a write command is given.
Then, at a predetermined timing, the global IO line pair
Equalize signal / φGEQ rises to high level. This
The global IO line pair equalize signal / φGEQ
Global IO line pair equalize signal φGE shown at 111
Q, for example, flip-flop 202
Generated from 8 complementary outputs / Q. Block selection signal φ
Equalize according to BKS high level and low level
Signal φLEQ becomes high level and low level. [0496] For the selected memory block, the block
Since the selection signal φBKS is at a high level, the global
IO line pair equalize signal / φGEQ goes high
And the local IO line pair equalizing signal φLEQ is low.
And the local IO line pair equalization is prohibited
You. In an unselected memory block, signal φBKS is
Since this is low level, the local IO line pair equalize signal
The signal φLEQ is at a high level. Global IO line pair equalize signal / φG
When the EQ goes low, the local IO line pair equalizes
Signal φLEQ goes high, causing the local IO line pair
Is performed. With the above configuration, the selected memory block
Only at the same timing as the global IO line pair.
Activate / deactivate local IO line pair equalization
be able to. FIG. 114 shows the first equalizing timing.
It is a figure which shows the example of a change of the control method. In FIG. 114
Is when the equalizing signal φGEQ is in standby
When writing data in the inactive low level
The manner in which the equalizing control signal is generated in this case is shown. FIG.
In the equalization timing control method shown in FIG.
When a selection start instruction signal (write command) is
After a clock cycle equal to the loop length, the next
In response to the clock signal, the equalize signal φGEQ
It is generated in the form of a shot pulse. Therefore, the data
Equalization is performed only during a predetermined period after data writing
It is. In such a standby mode,
When the signal φGEQ is in the low level inactive state
However, after writing data, the equalize signal
Signal φGEQ in the form of a one-shot pulse
Ensures that global IO line pairs are equalized
Can be. Global IO line before writing data
Write data at high speed without the need to equalize pairs
Can do it. FIG. 115 shows the first equalization timing.
Equalization at the time of data reading in a modification of the
FIG. 4 is a diagram illustrating a noise signal generation mode. Ikora shown in FIG. 115
In the timing control method,
In addition, the equalizing signal φGEQ is inactive low level.
In Column selection start instruction signal when reading data
(Read command) is given and the data of the selected memory cell is
Appears on global IO line pair GIO1-GIO4
You. Appears on global IO line pair GIO1-GIO4
After the transferred data is transferred to the read register,
Equalizing signal φGEQ is generated in the form of
You. In this case as well, the global IO line pair
Global IO line pair after data transfer to
Since the local IO line pair is equalized, the selected memory
Before the cell data appears on the global IO line pair,
Internal data lines (global IO line pairs and local IO
No need to equalize both line pairs)
Data can be read at high speed. Equalization shown in FIGS. 114 and 115
The signal control method is the flip-flop 2 shown in FIG.
028 in response to the output of the OR circuit 2024.
One-shot pulse generation for generating one-shot pulses
It can be realized using a circuit. In this case, FIG.
OR circuit 2026 shown in FIG.
The raw circuit 2027 need not be used. (Ii) Second Equalization Timing System
FIG. 116 shows a second equalizing timing control method.
FIG. 4 is a timing chart. In the configuration shown in FIG.
In this case, the column selection start instruction signal is
When given (when a write command is given)
First, the equalizing signal φGEQ is set to a low level in an inactive state.
And Next, a predetermined period is synchronized with each clock signal CLK.
The inter-equalization signal φGEQ is activated. This
Global IO line pairs GIO1 to GIO4 are equalized
Is done. Clock cycle equal to lap length has elapsed
Then, an equalizing signal synchronized with this clock signal CLK
Disable activation of φGEQ. Next clock of lap length
In the cycle, the value from the counter (see FIG. 110) is read.
Equalization in response to the
Signal φGEQ is at an active high level. As described above, when writing data,
Global IO line pair and local for each lock cycle
Equalize IO line pairs (internal data lines)
Lap stop operation.
Seth. Now, as shown in FIG. 117, the wrap length is 4
And two data are written, and the third clock cycle
Lap stop
Consider the case where is specified. In this case, as shown in FIG.
Thus, in clock cycle 1, the write command
Is given, the data D1 and D1 given at that time are given.
Data D2 given in clock cycle 2
Sequentially transmitted to the VAL IO line pair GIO1 and GIO2
You. Equalize signal φGEQ for each clock cycle
Are activated, and the global IO line pair GIO1 to GIO1 to G
IO4 is equalized. In the third clock cycle, the wrap length
Has not yet been counted up,
Signal φGEQ is activated to a high level,
Equalization of IO line pairs GIO1 to GIO4 is performed.
You. In clock cycle 3, read command
Command and the equalizing signal
φGEQ is deactivated. Also this lead command
Column select signal CSL rises to high level according to
Columns are selected. At this time, the data read on the selected column
Memory cell data is transferred to the global IO line pair GIO1
GIO4, but first the equalize signal φGEQ
Data at high speed
Can be transmitted to the global IO line pair GIO1 to GIO4.
Wear. Therefore, the lap stop operation is performed
Data can be read at high speed. Lead
After a command is given, the data is
Transferred from GIO1 to GIO4 to the read register
Thereafter, this equalizing signal φGEQ is activated at a high level.
State. First, a read command is given.
When the lap stop operation is performed,
The lap stop operation can be executed at the timing shown in
You. When reading external data, the
Equalization of global IO line pair GIO1 to GIO4
Because it is being done. FIG. 118 shows the equalizer shown in FIG. 117.
FIG. 3 is a diagram illustrating a circuit configuration for performing an imaging control.
In FIG. 118, the same portions as those in FIG.
Reference numbers are assigned. In FIG. 118, the column access determination cycle
The path 2000 is the output of the write command detection circuit 2010.
And the output of the precharge command detection circuit 2014
Circuit that resets the flip-flop 2018
2013 and the output of the read command detection circuit 2012
Receiving the output of the precharge command detection circuit 2014
OR circuit 20 for resetting flip-flop 2016
15 is further included. Other configurations are the same as those shown in FIG.
The same is true. In the configuration shown in FIG.
The flip-flop 2016 receives a read command.
Or when a precharge command is given
Reset. The flip-flop 2018 is a write
When a command is given or a precharge command
Is reset when given. This allows
When the counter command is given, the counter 2001
Equalizing signal according to the count-up signal φCNT
Control of the signal is prohibited. Similarly, if the write command
When given, the preamplifier enable signal PAE
Control of activation / inactivation of equalization signal φGEQ by
It is forbidden. [0511] The equalizing signal generation circuit 2002
Clock of the reset / reset flip-flop 2016
Cycle transmitted with a half cycle delay of the clock signal CLK
Of the delay circuit 2021 and the output of the flip-flop 2016
(Lap from force and counter 2001 (see FIG. 110)
Length + 1) AND receiving count-up signal φCNT
Circuit 2020 and the Q output of flip-flop 2018
AND circuit 2 receiving preamplifier enable signal PAE
022 and the outputs of AND circuits 2020 and 2024
Receiving OR circuit 2024 and flip-flop 2016
And an OR circuit 2026 receiving the outputs of
A predetermined time in response to the rise of the output of R circuit 2026
One-shot pulse with one-shot pulse width
And the output of the OR circuit 2024
And one-shot pulse generation circuit 20
Set / reset free reset by output of 27
Including flip-flop 2028. This flip-flop 2
028 is the signal Q shown earlier with reference to FIG.
It changes like φGEQ. [0512] The equalizing signal generation circuit 2002 further includes
Lap length count-up signal from the counter 2001
Signal φwu is delayed by a half cycle of clock signal CLK.
A half-cycle delay circuit 2029 for transmitting
The output of step 2018 and the output of half cycle delay circuit 2029
OR circuit 2023 receiving force and half cycle delay circuit 2
021 in response to the rising edge of the output,
Reset in response to rising of output on road 2023
Set / reset flip-flop 2025 and flip-flop
Activated when Q output of flip-flop 2025 is active
And responds to the rise of the clock signal CLK.
One-shot that generates a one-shot pulse with a time width
Shot pulse generation circuit 2030 and one-shot pulse
The output of the generation circuit 2030 and the output of the flip-flop 2028
An OR circuit 2031 receiving the output is included. OR circuit 203
1 generates an equalize signal φGEQ. [0513] The wrap length count-up signal φwu is
Counter 2001 when a write command is applied.
Occurs when counting the loop length. That is, this
Lap length count-up signal φwu counts up
Generated one clock cycle before signal φCNT
You. Next, the operation of the circuit shown in FIG.
This will be described with reference to FIG. In clock cycle 1, column selection instruction
That is, when a write command is given, the set / reset
Flip-flop 2016 is set and its output
Q rises to high level. Half cycle delay circuit 202
1 clocks the Q output of the flip-flop 2016
Half a clock cycle of the clock signal CLK
You. This half-cycle delay circuit 2021 has
Input when the clock signal CLK is high level.
Latched when the clock signal goes low.
Is used to output the latched data. did
Therefore, the output of the half-cycle delay circuit 2021 is a clock
The flip-flop 20 responds to the fall of the signal CLK.
It rises according to the output of 16. With this, set / reset
Flip-flop 2025 is set,
The cut pulse generation circuit 2030 is enabled. this
When the clock signal CLK is already at the low level,
A pulse is generated from shot pulse generation circuit 2030.
Not. The counter 2001 has the flip-flop 2
166 is activated in response to the Q output of clock signal C
LK is counted. On the other hand, the output of OR circuit 2026
The force responds to the rising of the Q output of the flip-flop 2016.
In response, the rising one-shot pulse generation circuit 2027
Generates a one-shot pulse from the flip-flop
2028 is reset and its Q output goes low.
Fall. As a result, the equalizing signal φGEQ is OR times
Falling to low level through road 2031. In clock cycle 2, the clock signal
When the signal CLK rises to a high level, this clock signal
In response to the rise of CLK, flip-flop 202
One-shot pulse activated by output of 5
One-shot having a predetermined time width from the raw circuit 2030
Pulse is generated. Thereby, the OR circuit 2031
Signal equalizes to a high level via
You. A clock cycle equal to wrap length 4 passes
Lap length count-up from the counter 2001
Signal φwu is generated. This lap length count-up
Signal φwu is transmitted through a half cycle delay circuit 2029.
Delayed by half a clock cycle and applied to OR circuit 2023
Can be Therefore, the output of OR circuit 2023 is
Falling of clock signal CLK in cycle 4
In response, it rises to the high level and flip-flop 2
025 is reset. This allows one shot
Loose generation circuit 2030 is deactivated. At clock cycle 5, the count
When the counter signal φCNT is generated from the counter 2001,
(In clock cycle 5), flip-flop 2
028 is an AND circuit 2020 and an OR circuit 2024.
And the Q output rises to a high level.
You. As a result, the equalize signal φGEQ is
It rises to a high level in response to the top signal φCNT. Up
By the series of operations described above, data of wrap length 4 is written.
After that, the equalizing signal φGEQ is changed to a high level.
And an equalizing signal φG every clock cycle.
The EQ can be raised to a high level. [0519] In clock cycle 11, the write operation is performed again.
Flip command is given in the same way
The output of the flip-flop 2016 rises to the high level,
The output of flop 2028 falls to low level,
As a result, the equalizing signal φGEQ falls to a low level. Ma
Flip-flop 2025 is set after half a cycle has passed.
And the one-shot pulse generation circuit 2030 is set.
Is done. At clock cycle 12, the clock signal
Signal CLK, one-shot pulse generation circuit
One-shot pulse having a predetermined time width from 2030
Is generated, and the equalizing signal φGEQ is
Stand up. In clock cycle 13, laps
Top operation is performed and read command is given
Then, the flip-flop 2016 is reset. this
When the counter 2001 is still performing the counting operation
You. However, the Q output of flip-flop 2018
Is set by the output of the read command detection circuit 2012
And a flip-flop correspondingly via an OR circuit 2023
Step 2025 is reset. In clock cycle 13, the clock has already been
In response to the rise of the lock signal CLK, the one-shot
The one-shot pulse signal from the
And the equalizing signal φGEQ is
It has become level. In the read operation, the preamplifier rice
When the cable signal PAE is generated, the flip-flop 20
28, and the equalizing signal φGEQ is
Stand up to I-level. [0524] As described above, each clock cycle
And the equalizing signal φGEQ is set to the high level for a predetermined period.
By doing so, when a write command is given,
The lap stop operation can also be performed. Lead
If a command is given, the global IO line
Preamplifier after data transfer from pair to read register
Equalization is performed according to the cable signal PAE.
Therefore, lap stop operation increases access time
It can be performed without. [0525] It should be noted that FIGS.
In the method of controlling the rise signal, the local IO line pair L
For the IO, the selected control is performed in the same manner as the first control method.
Of local IO line pairs only for
Sex / inactivity is performed. For unselected memory blocks
The local IO line pair LIO maintains the standby state
You. (A) Modification 1 FIG. 120 shows a first example of the second equalizing signal control method.
FIG. 9 is a timing chart showing a modification example of FIG. FIG.
In the standby mode, the equalizing signal
φGEQ (the same applies to the local equalize signal φLEQ).
) Is set to a low level. Ie global
Of internal data lines including IO line pairs and local IO line pairs.
Equalization is not performed during standby. Column
Only when a selection start instruction is given, equalize signal φG
Activation of EQ and φLEQ is performed. In the operation shown in FIG.
In cycle 1, when a write command is given,
Rise of next clock signal CLK (clock cycle 2)
Equalize signal φGEQ is activated in response to the
(Becomes high level). Next, clock cycles 3 and 4
In response to the rising edge of the clock signal CLK in each case.
Therefore, the equalizing signal φGEQ is kept at the high level for a predetermined period.
It is. When the lap length counter counts the lap length,
The clock of the next clock cycle (clock cycle 5)
In response to the rise of the clock signal CLK, the equalizing signal φ
GEQ is activated for a predetermined period. FIG. 121 shows the equalized signal shown in FIG.
FIG. 1 is a diagram illustrating an example of a circuit configuration for implementing a signal control method.
is there. In FIG. 121, column access determination circuit 20
00 has the same configuration as the circuit configuration shown in FIG.
You. Column access determination circuit 200 shown in FIG.
0, the parts corresponding to the components shown in FIG. 118
Have the same reference numbers. The equalizing signal generation circuit 2002
Delays flip-flop 2016 output by half a clock cycle
Half-cycle delay circuit 2021 and flip-flop
Receiving the count-up signal φCNT and the output of
OR circuit 2035 and half-cycle delay circuit 2021
Set in response to the rise of the output, the OR circuit 203
5 is reset in response to the rise of the output of
Reset flip-flop 2025, flip-flop
2018 and the preamplifier enable signal PAE
Receiving AND circuit 2022 and the output of AND circuit 2022
One-shot pal with predetermined time width in response to force
Pulse generating circuit 2036 for generating a pulse signal
And the Q output of the flip-flop 2025 is at a high level.
Activated when the clock signal CLK rises.
In response, a one-shot pulse signal having a predetermined time width
A one-shot pulse generation circuit 2030 for generating
Output of the one-shot pulse generation circuits 2036 and 2030
An OR circuit 2037 for receiving a force is included. OR circuit 2037
Generates an equalize signal φEEQ. Next,
explain about. When a write command is given, a half
The output of the cycle delay circuit 2021 is
The rise of clock signal CLK in a given clock cycle
Rising to high level in response to falling, flip-flop
Step 2024 is set. With this, one shot
The pulse generation circuit 2030 is activated. At this time
The clock signal CLK falls to a low level,
From the one-shot pulse generation circuit 2030 to FIG.
In the first clock cycle shown, one shot pulse
Is not generated. In clock cycles 2, 3 and 4
One-shot in synchronization with the rise of the clock signal CLK.
A predetermined time width from the reset pulse generation circuit 2030
One shot is generated. In response,
Signal φGEQ is synchronized with the clock signal CLK for a predetermined period.
To a high level. When the lap length data is written,
The next clock after a clock cycle equal to the
Clock in response to the rising edge of the clock signal
Counter 2001 generates a count-up signal φCNT.
It is. As a result, the output of the OR circuit 2035 becomes high level.
Output Q of the flip-flop 2025 goes low
Bell. The output Q of this flip-flop 2025 is
Before falling to a low level, the clock signal CLK is
High level, one-shot pulse generation circuit
A pulse signal with a predetermined time width is generated from 2030
Is done. Accordingly, clock cycle 5 (FIG. 120)
In response to the rising of the clock signal CLK in FIG.
The rise signal φGEQ rises to a high level for a predetermined period.
You. Note that this count-up signal φCNT is
High level, flip-flop 2025 resets
The one-shot pulse generation circuit 2030
Inactive state. However, this one shot
The pulse generation circuit 2030 includes a flip-flop 2025
When the output Q of the
If you have a transmission gate to
The one-shot pulse generation circuit 2030 includes a flip-flop
The output Q of the loop 2025 becomes low level at reset.
Even a one-shot pulse with a certain duration
Can occur. When a read command is given,
One shot in response to reamp enable signal PAE
A pulse generator 2036 has a one-shot having a predetermined time width.
To generate a pulse of the set. This allows the equalizing signal
φGEQ is set to a high level for a predetermined time by the OR circuit 2037.
It becomes. When a write command is given,
When the flip-flop operation is designated, the flip-flop 202
5 is reset by the OR circuit 2035. This place
The lap stop operation
Clock cycle, one-shot pulse generation circuit
One shot pal with a predetermined time width from 2030
Is generated in response to the clock signal CLK. This
This ensures that even if the lap stop action is specified,
Set equalizing signal φGEQ to high level for a predetermined period
Can be (B) Modification 2 In the equalizing signal control method shown in FIG.
Only one data line DB is used (8 bits
Width data line). The equalize signal IOEQ is
Activate the equalizing transistor provided on the data line DB
/ Deactivate. Equalize signal IOEQ is high level
, The internal data line DB is equalized,
When the colize signal IOEQ is at low level, the internal data
The equalization of the data line DB is not performed. [0538] As shown in FIG.
Where the internal data line DB is equalized
In the standby mode, the equalize signal IOEQ
Is high level. In clock cycle 1, the column
When a selection instruction signal (write command) is given,
The rise signal IOEQ becomes low level. Later, wrap
The length is counted and the clock signal is
The equalizing signal IOEQ is synchronized with the rise of CLK.
It rises to a high level for a predetermined period. Number of wraps
After the clock cycle has elapsed, the next clock cycle
In response to the rise of clock signal CLK at
The rise signal IOEQ becomes high level. If a data read instruction is given,
After the load command is given, the equalize signal IOEQ
Is inactive low level. To internal data line DB
When data appears, these are sequentially transmitted to the data output unit
Is done. Therefore, the data split transfer architecture
In the case where a read command is given,
Is a preamplifier enable signal indicating transfer of read data.
No. PAE signal is used for read data transfer
Generated. Therefore, this preamplifier enable signal
No. PAE as a trigger
To set the equalize signal IOEQ to a high level for a predetermined period.
You. This allows write and read commands
Whichever is given, each data transfer is
DB can be equalized. As shown in FIG.
The control method of the equalizing signal is as follows.
It can be realized using. In FIG. 123, when the standby mode is
Therefore, the equalization signal IOEQ is at a low level,
The data line DB is in a floating state. As shown in FIG.
In clock cycle 1, a column selection instruction (write command
Command), the next clock cycle
The equalizing signal I in synchronization with the rise of the clock signal CLK.
OEQ is at the high level for a predetermined period. Equal to lap length
After the clock cycle has elapsed, the next clock cycle
Equalization in response to the rising of clock signal CLK
The signal IOEQ is at a high level for a predetermined period. This FIG.
In the timing control method shown in FIG.
If the read data is supplied, the data bus
After the transfer to the data output unit, the equalize signal
High level for a fixed period. Even in this case,
A signal corresponding to the amplifier enable signal PAE is generated.
The equalizing signal IOEQ is triggered by this signal.
It is at a high level for a predetermined period. In the timing control shown in FIG.
Occurs after all the wrap length data has been written.
The timing of the equalizing signal IOEQ
Equalized signals generated in Equles 2, 3 and 4
Seems to be slightly behind the timing of the issue
Is shown in This configuration corresponds to the circuit configuration shown in FIG.
, Instead of flip-flop 2028, OR times
One-shot pulse in response to the output of road 2024
Implemented by using a pulse generator circuit
Can be. In the case of this configuration, the OR circuit 2026 and the
The one-shot pulse generation circuit 2027 is not used. As described above, every clock cycle
Internal data line DB or global IO line pair and low
Data transfer by equalizing the Cal IO line pair
Lap stop operation without adversely affecting
And high-speed access can be realized. (Iii) Third equalization signal timing
FIG. 124 shows a third equalizing timing control method.
FIG. 4 is a timing chart. The system shown in FIG.
In the control method, when writing the lap data,
Equalize signal φGEQ is activated every clock cycle
State. Internal data line, ie global IO
Line pairs GIO1 to GIO4 are output every two clock cycles.
Globalized from write register because equalized
Data transfer to IO line pairs and data transfer to memory cells
Writes are performed during two clock cycles. Accordingly
Therefore, even if the clock cycle becomes shorter,
Global IO line pair from write register with margin
Transfer data to memory cells and write data to memory cells.
Operation with a high-speed clock
It becomes. In FIG. 124, in the standby state
The equalize signal φGEQ is at the active high level.
You. In clock cycle 1, column selection starts
When an instruction signal (write command) is given,
Signal φGEQ is at a low level in an inactive state. K
In response to lock signal CLK, data is written and sequentially
It is transmitted on the global IO line pair. Write command
And two clock cycles after the column selection operation is specified.
Responds to the rising edge of the clock signal CLK
As a result, the equalizing signal φGEQ becomes high level for a predetermined period.
Is done. Thereby, the global IO line pair GIO1 to GIO
IO4 is equalized. [0546] After the column selection start instruction signal is given,
After the elapse of a clock cycle equal to the
In the clock cycle (cycle 5), the equalizing signal
φGEQ rises to the active high level. As described above, every two clock cycles
The equalizing signal φGEQ is activated at a high level for a predetermined time.
To equalize global IO line pairs
Is sufficient for short clock cycles.
Write data and global IO line pairs and
And local IO line pairs can be equalized.
Can operate in synchronization with a high-speed clock signal.
You. Referring to FIG. 125, an equalize signal is generated.
The circuit 2002 includes a write control signal WDE and a read command
The detection signal (the flip-flop 2018 shown in FIG.
Circuit 2040, which is provided with an OR circuit 2040)
It has a predetermined time width in response to the rise of the output of 2040.
One-shot pulse that generates a one-shot pulse
98 and a reset signal φRES (FIG. 98).
OR) that receives the preamplifier enable signal PAE
Circuit 2044 and the rising edge of the output of OR circuit 2044
Set in response to the one-shot pulse generation circuit 20
Flip-flop reset in response to the output of 42
2046 and the falling edge of the write control signal / WERST.
In response, a one-shot pulse signal having a predetermined time width
A one-shot pulse generation circuit 2048 for generating
Q output of lip flop 2046 and one shot pulse
An OR circuit 2049 receiving the output of the generation circuit 2048
Including. The equalizing signal φGEQ is output from the OR circuit 2049.
Generated. The reset signal φRES is shown in FIG.
After the write command is given, the lap length + 1
High level for a predetermined period when the clock signal
Driven by The write enable signal WDE is a write command.
After the reset signal φRES is applied.
Maintain the high level active state until The write control signal / WERST is shown in FIG.
As is clear from the operation waveform diagram shown, the write command
When given, every two clock cycles a predetermined period of time
-Level. The rise of this write control signal / WERST
A one-shot pulse of a predetermined width is generated for each
Drives the rise signal φGEQ to a high level active state.
You. Next, the operation will be briefly described. When a write command is given, a write
Signal WDE attains a high-level active state, and an OR circuit
2040 via one-shot pulse generation circuit 2042
Is driven to generate a one-shot pulse. to this
In response, flip-flop 2046 is reset,
The Q output is set to low level. When write enable signal WDE is at a high level,
In the sexual state, two clocks after the write command is given
Signal / WERST is low for a predetermined period every clock cycle.
Fall to the bell. One shot in response to this fall
The pulse generation circuit 2048 has a one-shot having a predetermined time width.
Generates the pulse signal of the boat. Thereby, the OR circuit
2049, the equalizing signal φGEQ is supplied for a predetermined period of time.
It is set to the active state of level I. [0556] Lap length after write command is given
After a clock cycle equal to
Reset in response to the rising edge of the clock signal
Signal φRES is driven to a high level for a predetermined period. This
In response, flip-flop 2046 is set.
The Q output becomes high level, and the equalizing signal φ
GEQ is set to high level. Thus, equalization is performed every two clocks.
The signal φGEQ can be driven to a high level for a predetermined period.
Reset when all lap length data has been written.
The equalizing signal φGEQ in accordance with the reset signal φRES.
It can be maintained at a level. When the wrap length is 4, the write control signal
/ WERST is the clock signal C of the fifth clock cycle
Driven to low level in response to the rise of LK,
Similarly, a reset signal φRES is generated. in this case,
In particular, the equalizing signal φG according to the reset signal φRES
To activate the EQ, a write command is applied.
Clock cycle equal to the wrap length
The one-shot pulse generation circuit 2048
What is necessary is just to use the structure which prohibits operation | movement. Thereby, the fifth
Of write control signal / WERST in clock cycle
Ignore the falling edge and reset according to the reset signal φRES.
The rise signal φGEQ can be activated to a high level.
Wear. In place of the control signal / WERST, FIG.
01 and the like, the control signal / WERSTf is used.
You may. FIG. 126 shows an equalizing signal during standby.
When the signal φGEQ is maintained at the low level inactive state
FIG. 4 is a diagram showing a timing control method of FIG. Shown in FIG. 126
In the configuration, the column selection start instruction signal (write command)
), The clock after two clock cycles elapses
Equalizing signal φGE for a predetermined period in clock cycle 3
Q is raised to a high level. Black equal to lap length
When the clock cycle elapses, the next clock signal CLK
In response to the rise, equalizing signal φGEQ is
It is started to a high level. Realization of the configuration of FIG. 126
To do this, in the configuration shown in FIG.
A one-piece having a predetermined time width in place of the flop 2046
One-shot pulse generation circuit that generates the pulse of the shot
May be used. To realize the configuration of FIG.
First, in the configuration shown in FIG.
One shot with a predetermined time width in place of step 2046
Used by a one-shot pulse generation circuit
It should be done. In this case, one-shot pulse generation circuit
2042 and OR circuit 2040 are not used. Also, one-shot receiving signal / WERST
And a one-shot response to the signal PAE.
One-shot pulse generation circuit that generates cut-off pulses
And the output of these one-shot pulse generation circuits
Equalize from this OR gate using an OR gate
Signal φGEQ may be configured to be generated. This
In the case of, burst (lap) stop is a light frame
Command is executed every even clock cycle after the command is given.
Is required. As described above, the first to third equalizers
If you use the write signal timing control method,
Or equalize internal data lines before reading
And input / output of data at high speed.
Also, after transfer of read data to the output section or write data
After writing to the memory cell of the
After) Since the internal data lines are equalized,
Equalize signal can be activated at timing
You. Write Mask Circuit Below "Write Mask Circuit"
Of the write circuit control shown in FIGS.
This will be described with reference to the configuration of the system. In the following description,
When the lap length is 2 or more, the lap stop length is 2
An example of how the write control signal is generated when it is set to
Shown. This lap stop length is set to 2
In some cases, after the column access is started,
The third clock after two clocks have passed since the
Responds to rising of clock signal CLK in lock cycle
As a result, the signal / WERSTf falls to a low level. Less than
When writing down and lap length data,
Signal / WERSTf goes low every clock cycle.
Fall for a fixed period. Signals / WERSTf and / WERS
Wrap address / WWY when T is both high level
i is latched, and the latched wrap address / W
In accordance with WYi, fetching of write data of write circuit and
Data transfer to global register and global IO line
Data transfer to GIO is performed. Detailed Configuration of Write Circuit and Write Register
Please refer to FIG. 96. When the signal WEEi is at a high level
At this time, as shown in FIG. 96, the signal WDE goes high.
If there is, the write circuit WGi sends the write
Data transfer and data on global IO line pair GIO
Data transfer is performed. At this time, as shown in FIG.
If the internal write mask signal MD is at a high level,
Wrap address / WWYi is ignored and internal write instruction signal
The signal WEEi maintains the low level. The internal write mask signal MD
High level indicating data write prohibition for a predetermined period in the cycle
The bell is kept active. Rising of the clock signal CLK
At the rising edge, the external write mask signal DQM goes high.
If it is at the bell, the internal write mask signal MD
Keep on the bell. This prohibits data writing.
You. For data writing, the internal write mask signal MD is low level.
This is executed when the file is inactive. As described above, each clock cycle
The internal write mask signal MD to the active high level.
When the light mask is not applied
After a predetermined period has elapsed, the internal write mask signal MD is set to low level.
Write data as a file. This configuration has the following advantages:
Give points. [0564] External write mask signal DQM is at high level.
Active or low-level inactive state
After the determination, the internal write mask signal MD is activated.
Level, the judgment result of the light mask is determined
It is necessary to wait until internal data is written. This place
In this case, the write control signal is determined by the internal write mask signal MD.
Must be delayed until finalized. Also at this time,
Of internal write mask data MD to prevent data write
Between the generation of the internal write instruction signal (signal WEEi, etc.)
It is necessary to have a timing margin. Because of this
Data cannot be written quickly. However, at each clock cycle,
To set the internal write mask signal MD to a high level for a predetermined period.
In the meantime, during this time, the external write mask signal DQM is activated /
Inactivity is determined and the internal light mass is determined according to the determination result.
Control of maintaining and deactivating the active state of the lock signal MD.
For example, the generation timing of the write control signal / WERSTf, etc.
Can be constant at all times, and data can be written at high speed.
Can be. Therefore, external write mask signal DQM
Data is written at high speed if
Can be included. FIG. 128 generates an internal write mask signal.
FIG. 3 is a diagram showing an example of a circuit configuration for performing the above. See FIG.
In contrast, the internal write mask generation system
ext. CLK externally provided in response to CLK
Screen signal ext. Dynamic latch 2 that takes in DQM
050 and the external clock signal ext. CLK rise
One-shot pulse having a predetermined time width in response to
One-shot pulse generation circuit 2052 for generating a signal
And the output of the one-shot pulse generation circuit 2052
A delay circuit 2054 for delaying the time T by
Output OUT of latch 2050 and output of delay circuit 2054
And a one-shot pulse
Set in response to the output of the generation circuit 2052, the gate
Set / reset in response to the output of circuit 2056 /
And a reset flip-flop 2058. Set / Re
Set flip-flop 2058 to internal write mask
A signal MD is generated. This internal write mask signal MD
Is provided to a circuit 1218 shown in FIG. The one-shot pulse generation circuit 2052
Internal clock signal ext. CLK is delayed for a predetermined time
A delay circuit 2053, an output of the delay circuit 2053, and an external clock.
Lock signal ext. Gate circuit 2055 receiving CLK
including. Gate circuit 2055 is connected to the output of delay circuit 2053.
When the power is low and the external clock signal ex
t. Outputs a high-level signal when CLK is high.
Power. Therefore, the delay from gate circuit 2055
A circuit having a time width equal to the delay time of the circuit 2053
A one-shot pulse is generated. This delay circuit 205
3 is the delay time of the delay circuit 2054
The interval T is made smaller. To flip-flop 2058
High level simultaneously to the set input S and reset input R
This is to prevent the application of a signal of the same type. Gate
The output of the delay circuit 2054 is at a high level
And the output OUT of the dynamic latch 2050 is low.
Outputs a high-level signal when the signal is low. FIG. 129 shows the dynamics shown in FIG.
FIG. 3 is a diagram illustrating an example of a specific configuration of a latch. In FIG. 129, the dynamic latch 2
050 is the power supply potential node 2063 and the output node 206
1 and is provided in response to a clock signal CLK.
P-channel MOS transistor 2060 through which
Provided between potential node 2063 and output node 2061
P channel M which is turned on in response to output signal OUT
Between the OS transistor 2062 and the output node 2061
And the input signal IN (external)
N channel M conducting in response to external mask signal DQM)
Between the OS transistor 2064 and the output node 2061
And the output signal OUT
N-channel MOS transistor 206 which is rendered conductive in response
6, internal node 2069, ground potential node 2065,
And is turned on in response to the clock signal CLK.
N channel MOS transistor 2076. Tiger
Transistors 2062 and 2066 are conductive complementarily to each other
State. [0570] The dynamic latch 2050 further includes
Between source potential node 2063 and output node 2067
And the p channel is turned on in response to the clock signal CLK.
And a complementary output signal / O.
P that conducts in response to UT (potential on node 2061)
Channel MOS transistor 2068 and output node 2
067 and the internal node 2069.
N channel MOS transistor receiving reference potential Vref
Transistor 2074, output node 2067, and internal node
2069, and responds to the complementary output signal / OUT.
N channel MOS transistor 2072 which conducts in response
including. Reference potential Vref is applied to power supply potential node 2063.
Between the applied potential and the potential applied to the ground node
It is a potential between. Next, the dynamic latch shown in FIG.
Will be described with reference to the operation waveform diagram of FIG.
I do. When the clock signal CLK is at low level,
Both transistors 2060 and 2070 are on
In this state, the transistor 2076 is off. This state
In, the dynamic latch is in the precharge state
Yes, output nodes 2061 and 2067 are both powered
Preset to power supply potential level applied to potential node 2063
Charged. When the clock signal CLK is at the high level,
Both transistors 2060 and 2070 are off
State, the transistor 2076 is turned on. input signal
When IN is at a low level lower than the reference potential Vref,
The conductance of the transistor 2064 is a transistor
2074, which is smaller than the conductance.
Node 2067 is discharged faster than output node 2061.
You. When the potential of the output node 2067 decreases, the transistor
The star 2062 is on and the transistor 2066 is off
State, and the output node 2061 is driven at high speed by the power supply potential level.
Charged to the bell. On the other hand, when the potential of output node 2061 rises
Transistor 2068 is turned off in response to
The transistor 2072 is turned on, and the output node 206
7 rapidly drops to a low level. This allows the output signal
Signal OUT is low level, complementary output signal / OUT is high level.
Keep the bell. Once the output signals OUT and / OUT
The potential level is determined to be low level and high level
The input signal IN goes from low to high on the way
Even if it rises, its state does not change. Transistor 20
Current drive strength of 62, 2066, 2068 and 2072
Is the current driving capability of transistors 2064 and 2074
It is because it is made larger. Next, the clock signal CLK is again set to the low level.
Output nodes 2061 and 2067
The transistors 2060 and 2070 supply the power supply potential.
Charged to the bell. At this time, the transistor 2076
Is in the off state, and the nodes 2061 and 206
7 does not exist, the output node 20 is operated at high speed.
61 and 2067 are charged. When the input signal IN is at the high level, the clock
When the clock signal CLK rises to a high level, the output node 2
067, the signal OUT output from the high level
The signal / OUT output from the node 2061 is at a low level.
It becomes. According to the above configuration, the clock signal CLK is
Capture and latch input signal IN on rising edge
be able to. Next, the operation of the circuit shown in FIG.
This will be described with reference to FIG. 131 which is a waveform diagram. Dynami
The output OUT of the clutch 2050 is an external clock signal.
ext. When CLK is low, it is pulled high.
Recharged. Rise of clock signal CLK
An external mask applied to the input IN of the latch 2050 at the edge
Scatter data ext. The state of DQM is latched. Outside
Mask signal ext. DQM receives the external clock signal ext.
Latch if low at rising edge of CLK
In the output signal OUT of 2050, the clock signal CLK is high.
It goes low during the level. The one-shot pulse generation circuit 2052
External clock signal ext. At the rising edge of CLK
Generates a one-shot pulse signal with a fixed time width
ing. From this one-shot pulse generation circuit 2052
In response to the one-shot pulse of the flip-flop 2
Since 058 is set, it is output from its Q output.
The internal write mask signal MD rises to a high level. From one-shot pulse generation circuit 2052
A predetermined time T has passed since the one-shot pulse was generated
Then, a one-shot pulse is output from the delay circuit 2054.
Generated. At this time, the dynamic latch 2050
If the signal from the output OUT is at a low level, the gate circuit
Path 2056 passes the output of delay circuit 2054.
This resets flip-flop 2058.
The internal write mask signal M output from the output Q
D goes low. The external clock signal ext. CLK is high
In the case of a bell, the output O of the dynamic latch 2050 is output.
UT goes high. In this state, the gate
The output of path 2056 is at a low level. [0580] External clock signal ext. CLK rises
External write mask signal DQM
When set to bell, the dynamic latch 2050
The force OUT changes even when the clock signal CLK rises.
Keep high level without doing. In this state, the game
The output of the gate circuit 2056 is fixed at a low level. did
Therefore, the one-shot pulse generation circuit 2052 outputs
A shot pulse is generated and the flip-flop 205
Even if 8 is set, in this cycle,
Flip-flop 2058 is not reset. But
Is the internal write mask signal MD.
High level during the clock cycle given to DQM
maintain. One shot generated by delay circuit 2054
The pulse signal was ignored by the gate circuit 2056.
It is. In the next cycle, the external write mask
The signal ext. When DQM is low, one-shot
One-shot pulse from cut pulse generation circuit 2052
After the flip-flop 2058 is set,
A delay circuit is provided via a delay circuit 2054 and a gate circuit 2056.
Set. With the above configuration, each clock cycle
The internal write mask signal MD is generated at
Unit mask signal ext. DQM is active and write
When the mask is specified, the internal write mask signal MD
Prohibits resetting of the internal
All of the rising edges of the internal clock signal CLK
Data can be set at high speed by setting the period from the edge.
Can be written. In addition, other write control signals
Activation timing is also determined by the delay given by delay circuit 2054.
Between the internal write control signal and the internal write control signal.
Consider the timing margin with the write mask signal MD
It is not necessary to write data at high speed.
You. Also, due to manufacturing process fluctuations, etc.
Even if the pulse width of the light mask signal MD is different,
Both the internal write control signal and mask signal MD write data
Since data writing is performed when the status is indicated,
It is necessary to provide a margin for the timing of the internal write control signal
There is no. FIG. 133 shows a modification of the dynamic latch.
FIG. In FIG. 132, the dynamic
Enable transistor 207 included in switch 2050
6 and the ground potential node 2065, the array active
N channel that conducts in response to command instruction signal φAA
A MOS transistor 2080 is provided. ARRAY ACT
Active instruction signal φAA is used to access the memory cell array.
Is active only during the designated period. Therefore
This dynamic latch 2050 provides access to the array.
Is activated only when the command is specified. Dynamic
In the clutch 2050, the transistor 2080 is turned off.
In this case, since there is no discharge path, its output OUT and
And / OUT both maintain a high level. This
Lower current consumption in the dynamic latch 2050.
To reduce. FIG. 133 is a diagram showing a free area for generating an internal write mask.
One-shot pulse generation for flip-flop setting
It is a figure which shows the example of a change of a raw part. In FIG. 133,
Inactive detection signal φAA and external clock signal ex
t. The AND circuit 2081 receiving the CLK
It is provided in a stage preceding the pulse generation circuit 2052. AND
The circuit 2081 detects that the array active detection signal φAA is high.
Only when the external clock signal ext. CLK
Let it pass. The array active detection signal φAA is low.
In the case of a bell, the AND circuit 2081 outputs a low level signal.
Is output. With this, the one-shot pulse generation circuit
From 2052, only during array active operation
A one-shot pulse is generated and the flip-flop
Set / reset is executed. With this, one-shot
The pulse generation operation from the reset pulse generation circuit 2052.
Reduced current consumption by limiting only to the lay-active operation period
Plan. FIG. 134 shows a one-shot pulse generation circuit.
It is a figure which shows the example of a change of. In FIG.
The reset pulse generation circuit 2052 detects the array active state.
P channel MO receiving inverted signal / φAA of signal φAA
S transistor 2090 and the output of delay circuit 2053
P-channel MOS transistor 209 receiving an inverted signal
1 and an inverted signal / CLK of the clock signal CLK.
Includes p-channel MOS transistor 2092. Tran
The transistors 2090 to 2092 are connected to the power supply potential node 20.
63 and the output node 2096 are connected in series. The one-shot pulse generation circuit 2052 is
In addition, n gates receiving inverted clock signal / CLK at their gates
Channel MOS transistor 2093 and delay circuit 205
N-channel MOS receiving gate of inverted signal of output 3
Transistor 2094 and inverted array active detection signal
-Channel MOS transistor receiving signal / φAA at its gate
A star 2095. Transistors 2093 to 20
95 is an output node 2096 and a ground potential node 2065
Are connected in parallel with each other. The inverted signal of the output of the delay circuit 2053 is
The extension circuit 2053 is formed by cascade connection of inverters.
The number of inverters is odd.
Generated. One-shot pulse generation shown in FIG.
In the circuit configuration, the array active detection signal φA
A is at high level and array active command
In this case, the signal / φAA becomes low level,
Transistor 2090 is on, transistor 209
5 is turned off. As a result, the delay circuit 2053
The inverted output signal and inverted clock signal / CLK are both
When the signal goes low, a high-level signal is output.
It is. [0590] On the other hand, in the precharge state,
The inactivity detection signal φAA is at low level,
The array active detection signal / φAA goes high.
You. In this state, the transistor 2090 is off,
Transistor 2095 is turned on, and output node 2
096 is fixed to the ground potential level. [0591] Note that the transistor 2090 is turned off.
Sometimes, the transistor 2090 and the transistor 2090
Connection node and transistor 2091 and transistor
The connection node of the data 2092 is in a floating state.
Output node 2096 and these nodes
N channel that conducts in response to signal / φAA
A MOS transistor may be provided. FIG. 135 shows an array active detection signal φ.
FIG. 3 is a diagram illustrating a circuit configuration for generating AA. FIG.
In 5, the array active detection signal generating system
Active command given according to / RAS and / WE
Active command detection circuit 2 for detecting that
085 and the row address strobe signal / RAS
Precharge command according to the enable signal / WE
Precharge command detection to detect that
Circuit 2086 and active command detection circuit 2085
Is set according to the output of the
Set / reset reset according to the output of circuit 2086
Set flip-flop 2087 is included. Flip flow
Array active detection signal from Q output from
The signal φAA is output. Active command detection circuit 2
085 and precharge command detection circuit 2086
Is a set of states of signals / RAS and / WE shown in FIG.
Active command and precharge command
It is determined whether a command has been given. In the configuration shown in FIG. 135,
The chip select signal / CS may be used. signal/
RAS and / WE may be internal signals,
The signal may be a partial signal. When these signals are external signals
The active command detection circuit 2085 and the pre-
The charge command detection circuit 2086 outputs the clock signal C
Capture the state of these signals on the rising edge of LK,
The state is determined. In this configuration, the detection circuit
2085 and 2086 do not require a latch circuit.
Not. Can be configured using only logic gates
You. A flip-flop 2087 is used,
Signal to set / reset flip-flop 2087
This is because the set can be performed. If there is a margin in the timing,
This flip flow only when a write command is given.
Step 2058 may be configured to operate. FIG. 136 shows the internal mask data generation circuit.
It is a figure which shows the example of a change, and its operation waveform. Referring to FIG. 136 (A), the internal mask
Data generation circuit outputs the external clock signal ext. CLK rising
The pulse signal φ which becomes “H” for a predetermined period in response to the rise
One-shot pulse generation circuit 2100 for generating CK
And enable the one-shot pulse signal φCK
The external write mask signal ext. DQM
And a dynamic latch 2102 receiving the
Inverter circuit for inverting one shot pulse signal φCK
2106 and the output OUT of the dynamic latch 2102
Circuit 2104 for delaying a predetermined time
In response to the fall of signal / φCK from circuit 2106
Is set, and the output signal DQM from the delay circuit 2104 is
Flip-flop 210 reset when "L"
8 inclusive. Internal from the Q output of flip-flop 2108
A write mask signal MD is output. The dynamic latch 2102 has been described with reference to FIG.
29 has the same configuration as the circuit shown with reference to FIG.
Signal φCK applied to switch enable input LE
The external lightma given to the input IN when it is “H”
Screen signal ext. Take in DQM from output node OUT
Output. When signal φCK is “L”, dynamic
The output OUT of the clutch 2102 becomes high level. H
The lip flop 2108 provides its set input / S
When the output signal / φCK goes low, the output MD
To a high level. Flip-flop 2108
Indicates that the signal DQM applied to the reset input / R is low.
Reset when the internal write mask signal MD
To a low level. Next, FIG.
The operation of the internal write mask signal generation circuit
This will be described with reference to FIG. [0598] The internal clock signal ext. CLK is high
After rising to the bell, respond to this rise for a predetermined time.
Width (the delay included in the one-shot pulse generation circuit 2100)
High level determined by the delay time of the extension circuit)
The signal φCK is generated. This allows the dynamic latch
2102 is the external light mask given at that time
The signal ext. Capture DQM. Inverter circuit 2106
Generates signal / φCK by inverting signal φCK. This
As a result, the flip-flop 2108 is set, and the internal
The write mask signal MD rises to a high level. Delay times
The path 2104 is the output OU of the dynamic latch 2102.
The signal generated from T is delayed for a predetermined time. Outside
Write mask signal ext. Signal when DQM is low level
When the signal φCK is at a high level, the dynamic latch 21
02 is at a low level. The signal / φCK is
When rising to a high level, the output from the delay circuit 2104 is output.
Signal DQM is low level,
Resets the internal write mask signal M
D falls to a low level. [0599] External write mask signal ext. DQM is outside
Unit clock signal ext. High level at the rise of CLK
, The output DQM of the delay circuit 2104 is
Maintain high level for the cycle period. Therefore,
The flip-flop 2108 is not reset and the internal light
The disk signal MD maintains a high level. With the above structure, the external write mask signal e
xt. Internal write mask according to DQM activation / inactivation
The activation / inactivation of the signal MD can be determined. As described above, the internal write mask signal is utilized.
And a write mask signal is given from outside.
Only when the internal write mask signal is activated
The internal write mask signal and other write control
There is no need to consider the timing relationship of
Data can be written at a high speed. [Reference Voltage Generating Circuit] FIG. 137 shows an SDR
FIG. 3 is a diagram illustrating a configuration of an AM data output unit. FIG. 137
Output buffers for data output terminals Q0-Q7.
OB circuits OB0 to OB7 are provided. This output
The buffer circuits OB0 to OB7 correspond to the output buffer shown in FIG.
The output buffer shown in FIG.
702 and as shown in FIGS. 46 and 47.
Latch circuit LA and three-state inverter buffer TB8
And an output buffer.
Latch circuit LA and look-ahead latch circuit 820 shown in FIG.
And an output buffer 702. The output buffer circuits OB0 to OB7 output the output signals.
In response to the enable signal φOE, it becomes active and the internal data
Data from the data output terminal Q
The generated read data is transmitted to 0 to Q7. The output buffer circuits OB0 to OB7 are
Internal voltage that generates an internal voltage in response to a clock signal CLK
Using boosted voltage from generation circuit 1500 as operating power supply voltage
Operate. Is this internal voltage generation circuit 1500 a power supply terminal?
In response to clock signal CLK.
To boost. Output buffer circuits OB0 to OB7 are boosted
Output buffer circuit OB0
OB7 operate at high speed. FIG. 138 shows the specific structure of the output buffer circuit.
It is a figure showing an example of composition. In FIG. 138, the data
Only a circuit portion connected to the output terminal Qi is shown. FIG.
8, the output buffer circuit OBi outputs the output enable signal.
Signal OE in response to internal read data I
A preamplifier stage 1502 for inverting and amplifying Qi;
Is activated in response to the
02 is inverted and amplified and transmitted to the data output terminal Qi.
And output stage 1504. This preamplifier stage 1502
The internal power generation voltage shown in FIG.
The power supply voltage Vc transmitted from the path 1500 is supplied. The preamplifier stage 1502 supplies the boosted power supply voltage.
Node Vc (the power supply voltage is the same as the signal line
Between the output node 1518).
P channel which is turned on in response to internal read data IQi.
MOS transistor 1510 and transistor 151
0 is provided in parallel with the output enable signal
P-channel MOS transistor 1512 receiving φOE
And one output terminal (drain) to output node 1518.
), And the internal read data IQi is connected to its gate.
Receiving n-channel MOS transistor 1514
The other conduction terminal (source) of the transistor 1514 and the ground potential
Between the supply node and its gate.
N-channel MOS transistor receiving bull signal φOE
1516. Output stage 1504 has a complementary output at its gate.
Receiving the enable signal / φOE, while one of the conduction terminals
P-channel MOS connected to source voltage supply node Vcc
Transistor 1520 and output enable on its gate
Signal φOE, one of the conduction terminals of which is connected to the ground potential supply node.
N-channel MOS transistor 152 connected to node
6 and the complement between transistors 1520 and 1526
Connected to the output of the preamplifier stage 1502 at its gate.
MOS transistor 1522 and n-channel MOS transistor
Including a channel MOS transistor 1524. Next,
This will be briefly described. When output enable signal φOE is at "L" level,
If data output is prohibited,
1516 is off, transistor 1512 is on
It is a state. In this state, in preamplifier stage 1502
Is the output signal regardless of the state of the internal read data IQi.
Mode 1518 is charged to the power supply voltage (boost voltage) Vc level
Is done. In the output stage 1504, the transistor 15
20 and 1526 are both in the off state and output high.
It is in an impedance state. When signal φOE rises to "H", data
Output is enabled. In this state, Transis
1516 is on, transistor 1512 is off
And preamplifier stage 1502 functions as an inverter
And inverts and amplifies internal read data IQi to output node
1518. In the output stage 1504,
Transistors 1520 and 1526 are both turned on.
Function as an inverter circuit, and a preamplifier stage 1502
Inverts and amplifies the signal applied to output node 1518 from
To the data output terminal Qi. MOS transistor
Operating speed depends on the power supply voltage, especially the level of its gate voltage.
Dependent. The voltage boosted from internal voltage generation circuit 1500
By supplying the voltage Vc as the operating power supply voltage, the output
The stage 1504 operates at high speed and drives the data output terminal Qi at high speed.
To charge and discharge. FIG. 139 shows another example of the output buffer circuit OBi.
FIG. 3 is a diagram showing the configuration of FIG. In FIG. 139, the output buffer
The output circuit OBi receives the output enable signal φOE and the internal readout signal.
A two-input NAND circuit 1530 receiving data IQi,
Inverter circuit for inverting the output of NAND circuit 1530
1531, boosted power supply voltage node Vc and transistor 1
P-channel MOS transistor provided between the MOS transistor
Transistor 1533a, boosted power supply voltage node Vc and transistor
P channel MOS transistor provided between the
And a transistor 1533b. The gate of transistor 1535a has an NA
An output signal of ND circuit 1530 is applied, and n channel M
An inverter is connected to the gate of the OS transistor 1535b.
The output of path 1531 is provided. Transistor 1533
a and 1533b are cross-connected drains and gates.
Thus, a latch circuit is formed. The output buffer OBi further includes a transistor
The signal of the connection node of the star 1533b and 1535b is
An inverter circuit 1537 for inverting and amplifying and an inverter circuit
N-channel MO receiving at its gate the output signal of path 1537
S transistor 1534 is included. Transistor 1534
Is between the operating power supply voltage supply node Vcc and the output node.
Is provided. The inverter circuit 1537 includes a step-up power supply.
It operates using the voltage Vc as the operating power supply voltage. The output buffer OBi further includes an output rice
Cable signal φOE and internal read data IQi
Output of the gate circuit 1532 and the gate circuit 1532 at a predetermined time.
Including a cascaded inverter at the next stage
Buffer circuit 1539 and the output of the buffer circuit 1539.
N-channel MOS transistor 153 which is rendered conductive in response
6 inclusive. Transistor 1536 is connected between the output node and ground.
Provided between the order node. The gate circuit 1532
The false input receives the output enable signal φOE,
Input receives internal read data IQi. Gate circuit 15
32 indicates that the output enable signal φOE is at a low level
Or when internal read data IQi is at a high level,
Output a low-level signal. [0614] A buffer circuit 1539 is provided.
Is a NAND circuit 1530 and an output drive transistor.
An inverter circuit provided between the
The delay time given by the inverter latch is determined by the gate circuit 15.
32 and the output drive transistor 1536
This is to make the delay time equal. Next, simple operation
Will be described. [0615] Output enable signal φOE is at low level.
(“L”), the output of the NAND circuit 1530 is
“H”, the output of the gate circuit 1532 becomes “L”. This
In the state of, the transistor 1535a is turned on.
And the transistor 1533b is turned on. G
The transistor 1535b has an inverter circuit at its gate.
Since it is receiving the output signal of 1531, it is in the off state.
Therefore, the transistor 1533a is turned off accordingly.
It becomes. Thereby, the inverter circuit 1537 outputs
An “L” signal is output, and the n-channel MOS transistor is output.
The data 1534 is turned off. Similarly, the “L” level from gate circuit 1532 is
The signal causes n-channel MOS transistor 1536 to
The state is turned off, and the output becomes a high impedance state. [0617] Output enable signal φOE attains "H".
And the NAND circuit 1530 functions as an inverter,
Gate circuit 1532 also functions as an inverter.
You. When the internal read data IQi is “H”, NAN
The output of the D circuit 1530 is “L”,
The output becomes "L" again. In this state,
The transistor 1536 is off. Meanwhile, Transis
The transistor 1535a is turned off, and the transistor 1535 is turned off.
b is turned on, and the transistor 1533b is accordingly turned on.
The transistor is turned off and the transistor 1533a is turned on.
Thereby, transistors 1533b and 1535b
Of the connection node is high by the transistor 1535b.
Discharges quickly. From the inverter 1537, a boost power supply
A signal “H” at the voltage Vc level is output. this
As a result, the n-channel MOS transistor 1534 is
Output terminal without loss of threshold voltage
To generate an output signal Qi at the operating power supply potential Vcc level.
You. [0618] When the internal read data IQi is "L"
Of the NAND circuit 1530 and the gate circuit 1532
Both outputs become "H". This allows the transistor
1536 is turned on. On the other hand, the transistor 153
5a is on, and transistor 1535b is off.
Transistor 1533b is turned on and the transistor
The transistor 1533a is turned off. This allows
The input node of converter 1537 is connected to boosted power supply voltage Vc level.
The bell signal is transmitted through the transistor 1533b.
You. The output of inverter 1537 is at the ground potential level.
"L", and n-channel MOS transistor 1534
Is turned off. Transistor 1536 is a gate circuit
It is turned on by the “H” signal from
An output signal Qi at the ground potential level is generated. In the structure shown in FIG.
Use of the power supply voltage Vc to generate an internal signal at high speed
Output data Qi at high speed.
Can be. Also, the output stage transistor 1534 and
1536 are both composed of n-channel MOS transistors
In this case, the inverter circuit 1537
Since the operating power supply voltage is the boosted power supply voltage Vc, this drive
The threshold voltage loss in the active transistor 1534 is
A signal of the operating power supply voltage Vcc level without causing
Can be output. FIGS. 138 and 139 show either
Even in the case of the configuration, the boost
By using the source voltage Vcc, high-speed internal data
The internal node can be charged according to the
Data can be read. FIG. 140 shows the internal voltage generation shown in FIG.
FIG. 3 is a diagram illustrating a configuration of a circuit. In FIG. 140, the internal
The pressure generation circuit 1500 divides the frequency of the clock signal CLK,
Internal clock signals CL having the same frequency and shifted in phase from each other
Frequency dividing circuit 1600 for generating K1 to CLK4, frequency dividing circuit
Clock signals CLK1, CLK2, C
Charge pump in response to LK3 and CLK4 respectively
Charge pump circuit that generates boost voltage by performing
Roads 1602a, 1602b, 1602c and 1602
d. Charge pump circuits 1602a to 1602d
Are commonly transmitted to output node 1603. FIG. 141 shows the internal voltage shown in FIG.
FIG. 4 is a waveform chart showing an operation of the generation circuit. Hereinafter, FIG.
The operation will be described with reference to 142. The frequency dividing circuit 1600 generates the clock signal CLK
Clock signal whose frequency has been reduced to 1/4 by dividing
CLK1 to CLK4 are generated. Clock signal CLK1
To CLK4 also have a phase of 1/4 cycle (clock).
(One cycle of the lock signal CLK). these
The internal clock signals CLK1 to CLK4 are
It is provided to dipump circuits 1602a to 1602d. Inside
Clock signals CLK1 to CLK4
Phase is 1/4 cycle (1 cycle of clock signal CLK)
Le) It is out of alignment. Therefore, the charge pump circuit 160
From 2a to 1602d, the phase is 1/4 cycle from each other
A shifted boosted voltage is generated. Internal clock signal CLK
1 to CLK4 are phase-synchronized with the clock signal CLK.
You. The boosted voltage is synchronized with the rising of the clock signal CLK.
Is generated. Each cycle of the clock signal CLK
In either case, one of the charge pump circuits
Voltage is being generated. Therefore, the clock signal CL
A stable boost voltage is always generated at the rising edge of K
Can live. The rising edge of the clock signal CLK
Valid data is read out by the printer. Therefore always stable
The output buffer circuit can output data at high speed.
Wear. A ring in which ordinary inverters are connected in odd number stages
Generates internal clock signal using oscillator
When the dipump circuit is driven, the following disadvantages occur. Rin
The cycle time of the clock signal generated by the clock oscillator is
It changes according to the power supply voltage and the operating temperature. Accordingly
Of the boosted voltage generated from the charge pump circuit
The timing changes, and the boost voltage can be supplied stably.
Can not. Therefore, the data output by the output buffer circuit
The potential level of the data fluctuates, and the effective data is
It cannot output continuously. However, the present invention as shown in FIG.
According to the configuration of the embodiment, as described above, valid data is always
It is safe when the output clock signal CLK rises.
A constant boost voltage can be supplied. This allows
Data can be continuously output at high speed. next
The specific configuration of each circuit will be described. FIG. 142 shows components of the frequency dividing circuit shown in FIG. 140.
It is a figure showing an example of a physical configuration. In FIG. 113, the minute
The circuit 1600 includes four stages of flip-flops connected in series.
Ropp FF100, FF101, FF102 and FF
103 is included. Output Q9 of flip-flop FF103
4 is the complementary input / I of the first stage flip-flop FF100
N and via inverter circuit 1650
Connected to the input IN of this flip-flop FF100
Is done. Flip-flops FF100 and FF102
Clock signal CLK is applied to clock input K of
You. The flip-flops FF101 and FF103
The lock input K is connected via the inverter circuit 1652.
A clock signal CLK is provided. This frequency dividing circuit 1600
A quaternary ring counter circuit is configured. flip flop
FF100 to FF104 have the configuration shown in FIG.
You. In FIG. 143, the flip-flop FF
(FF100 to FF103) are four NAND circuits 1
660, 1662, 1664 and 1666. N
AND circuits 1660 and 1662 are connected to clock input K
Is high when the clock signal applied to the
And the signal applied to / IN is inverted and passed.
NAND circuits 1664 and 1666 are NAND circuits
The outputs of 1660 and 1662 are inverted and latched.
The flip-flop FF shown in FIG.
It has the same configuration as the flip-flop, and has a clock input
Signal in response to the rise of the signal applied to K
Signal to the clock input K.
Given to inputs IN and / IN in response to the falling edge of the signal
Outputs the previously applied signal regardless of the signal potential
It becomes a latching state to push. Next, FIG. 142 and FIG.
FIG. 143 is an operation waveform diagram showing the operation of the frequency divider circuit 143.
This will be described with reference to FIG. [0628] Flip-flops FF100 to FF103
Clock signal CLK is applied to clock input K of
I have. Therefore, the output of flip-flop FF100
Of each flip-flop is delayed by one clock cycle.
The signals are transmitted to the outputs of the FFs 101 to 103. clock
When the signal CLK rises to "H", the flip-flop F
F100 and FF102 enter the through state,
Pass signals applied to forces IN and / IN. This
As a result, the output Q91 of the flip-flop FF100 becomes
It rises to “H”. The flip-flop FF102 is
The output Q92 of the flip-flop FF101 is "L"
Therefore, the output does not change. When the clock signal CLK falls, a flip occurs.
The flip-flops FF101 and FF103 go through
Become. In response, the flip-flop FF101
The output Q92 rises to "H". Flip-flop FF
The output Q94 of 103 is the output of flip-flop FF102.
Since the force Q93 is "L", there is no change. Next, the clock signal CLK changes to "H" again.
When rising, the output Q93 of the flip-flop FF102
According to the output Q92 of the flip-flop FF101
It rises to “H”. Output of flip-flop FF103
Since Q94 is still "L", flip-flop FF
The output Q91 of 100 keeps "H". Clock signal
When CLK falls again, flip-flop FF103
Is output Q94 of the flip-flop FF102.
It rises to “H” according to 93. In response, the
The output of the barter circuit 1650 changes to "L". But
Therefore, in response to the next rising of the clock signal CLK,
Output Q91 of flip-flop FF100 is set at "L".
Falling, then １ ／ cycle of clock signal CLK
The outputs Q92 to Q94 sequentially fall to "L" with a shift. In this frequency dividing circuit 1600, the output Q9
1 and Q93 to internal clock signals CLK1 and CL
Use as K2 and flip-flop FF100
And the complementary outputs / Q91 and / Q93 of the FF102.
Used as internal clock CLK3 and CLK4 respectively
Then, internal clock signals CLK1 to CLK shown in FIG.
The signal waveform of LK4 is obtained. Use such a divider circuit
By using this, any size of the clock signal CLK can be used.
Activate the two clock signals in the
A large pump operation can be performed. FIG. 145 shows the charge pump shown in FIG.
FIG. 4 is a diagram illustrating a specific configuration example of a loop circuit. Figure 145
The four charge pump circuits 160 shown in FIG.
2a to 1602d are typically represented by reference numeral 1602.
Show. In FIG. 145, the charge pump circuit 1
602 is a clock signal K (internal clock signal CLK1
To CLK4).
0 and the output of the inverter circuit 1670 are connected to the node N100
A capacitor 1672 capacitively coupled to the clock signal K
For transmitting to the node N102 by capacitive coupling
1674 and the clock signal K are connected to the node N by capacitive coupling.
Capacitor 1676 to transfer to node 104
A diode-connected n-channel that charges 0 to a predetermined potential
MOS transistor 1678 and node N100
In response to the signal potential, nodes N104 and N102 are
N-channel MOS transistors 168 to be charged respectively
0 and 1682, one of which is connected to node N10
4 and its gate is connected to node N102.
And the other conduction terminal is connected to the output node OUT
Includes n-channel MOS transistor 1684. Next
The operation of the charge pump circuit shown in FIG.
This will be described with reference to FIG. 146 which is a waveform diagram. [0634] The node N100 is connected to the transistor 1678.
And the potential level is Vcc-VTH
It becomes. Where VTH is the threshold of transistor 1678
Value voltage. In the following description, transistor 1
680, 1682 and 1684 have the same threshold voltage V
TH is provided. Potential Vc on node N100
With c-VTH, transistors 1680 and 168
2 conducts and connects nodes N102 and N104 respectively.
It is charged to Vcc-2 · VTH. The clock signal K is
When it falls to “L”, the potential of node N100 becomes 2 Vcc
-Rise to the level of VTH. This allows the transition
Stars 1680 and 1682 connect power supply voltage Vcc to a node.
N102 and N104. Clock signal K
In response to the fall, nodes N104 and N102
The potential level is applied via capacitors 1672 and 1674
Lower. This decrease in potential is caused by transistors 1682 and
And 1680, to the power supply potential Vcc level.
To recover. [0635] The transistor 1684 is connected to the node N104.
Is transmitted to output node OUT. Output node OU
T is initially at the level of Vcc-3 · VTH
Charged. Responds to the rise of clock signal K
And the potential level of nodes N102 and N104 is Vc
c level, the potential of the output node OUT
The level rises to the Vcc-2 · VTH level. When clock signal K rises to "H",
The potential of the node N100 temporarily drops, and then Vcc-
Recover to VTH level. This allows the transistor
The voltage level transmitted by 1680 and 1682 is Vcc
-2 VTH potential level. This clock signal K
N102 and N104 in response to the rise of
Rises to the 2Vcc-2VTH level. This
As a result, the potential level of the output node OUT becomes 2Vcc-3
The potential level becomes VTH. Next, clock signal K falls to "L" again.
Then, the potential level of node N100 rises again by Vcc.
The potential levels of nodes N102 and N104 are
The current is supplied from the supply node to the power supply potential Vcc level.
To recover. By repeating this operation, node N
102 and N104 are 2 Vcc
And the level of Vcc. In this stable state
Therefore, the output node OUT has a potential level of 2 Vcc-VTH.
To stabilize. As the clock signal K rises,
Charge from the node N104 through the transistor 1684
Is supplied to the output node OUT, and the output node OUT
To compensate for the potential drop. Nodes N102 and N104
Is at the power supply voltage Vcc level,
Level is 2 Vcc-VTH level,
The gate 1684 has the same voltage at the gate and drain,
It functions as a mode and is turned off. Accordingly, the charge pump shown in FIG.
If the internal voltage is generated using the
Charged in response to rising of signals CLK1 to CLK4
A pump operation is performed, and the internal clock signal is set to "H".
Of charge to the output node of the charge pump circuit during
Replenishment is performed, and the internal boost voltage is generated stably
be able to. Also, one precharge pump circuit
In the cycle in which the charge pump operation is completed,
Another charge pump circuit clocks the charge pump operation.
Is executed in response to the rising edge of the
Clock signal CLK defining data read timing
A stable boost voltage on the rising edge of
Can be achieved. [Second Embodiment of Internal Voltage Generating Circuit] FIG. 1
Reference numeral 47 denotes the configuration of the second embodiment of the internal voltage generation circuit.
FIG. In FIG. 147, internal voltage generation circuit 180
0 is a frequency dividing circuit 1600 for dividing the frequency of the clock signal CLK.
In response to the output bit size selection signal / BS
The internal clock signal output from the circuit 1600 is selectively disabled.
Switch circuit 1802 to be activated and switch circuit
Internal clock signals CLK1 to C
Execute the charge pump operation according to LK4 to increase the boosted voltage.
Charge pump circuits 1602a to 1602d for generating
including. Dividing circuit 1600 and charge pump circuit 1
602a to 1602d are first shown in FIG.
It has a configuration similar to that shown. Switch circuit 180
2 according to the output bit size selection signal / BS.
Some of the internal clock signals CLK1 to CLK4 are inactive
State. In SDRAM, usually in units of 8 bits
Is configured to input and output data. Wai
SDRAM with × 4 bit configuration
can do. In the case of this × 4 bit configuration,
An operating output buffer is associated with the four data output terminals.
Only things. The remaining output buffers did not work
Therefore, there is no need to supply a boosted voltage. Internal voltage generation circuit
The 1800 has a low output buffer for a × 8-bit configuration.
The drive capacity is determined so that the
Have been. Therefore, when changed to × 4 bit configuration,
In that case, the driving capability is too large, and unnecessarily
It can be said that it consumes power. Therefore, as shown in FIG.
A switch circuit 1802 is provided as shown in FIG.
The drive capability of internal voltage generation circuit 1800 is adjusted according to the
Adjust. That is, for example, a × 4 bit configuration is specified.
In this case, the operation of the two charge pump circuits is prohibited.
This reduces power consumption. FIG. 148 shows the switch circuit shown in FIG.
FIG. 3 is a diagram showing an example of a specific configuration of FIG. Figure 148
Thus, the switch circuit 1802 outputs the output bit size selection signal.
/ BS and the internal clock signal CLK2 from the frequency divider circuit.
Receiving AND circuit 1810 and output bit size selection signal
/ BS and the internal clock signal CLK4 from the frequency divider circuit.
Receiving circuit 1812. Internal from frequency divider
Clock signals CLK1 and CLK3 are gated.
Pass without. The clock from this switch circuit 1802
Are transmitted to the corresponding charge pump circuits.
You. When the output bit size selection signal / BS is "L",
AND circuits 1810 and 1812 both output their outputs.
Fixed to “L”. In that case, the charge pump circuit
The obtained internal clock signals CLK2 and CLK4 are
Since it is “L”, the charge pump circuit 1602b and
And 1602d do not execute the charge pump operation. Cha
Only the pump circuits 1602a and 1602c alternate
To perform a charge pump operation. Clock signal CLK
The stability of the boosted voltage at the time of rising is guaranteed. [0641] The output bit size selection signal / BS is "H".
In this case, AND circuits 1810 and 1812
Functions as a circuit. In this case,
Circuits 1602a to 1602d are charge pumps, respectively.
Perform a loop operation. FIG. 149 shows the output bit size selection signal generation.
FIG. 3 is a diagram illustrating a configuration of a raw circuit. In FIG. 149, the output
The bit size selection signal generation circuit 1820
The potential of the output pad 1822 is detected and the output bit size is selected.
Select signal / BS is generated. The circuit 1820 uses the power supply voltage V
provided between cc supply node and internal node 1829
Of the high-resistance resistor 1824 and the internal node 1829
An inverter circuit 1826 for inverting and amplifying the signal potential;
Inverter circuit that inverts and amplifies the output of barter circuit 1826
Road 1828. Pad 1822 is typically a float
State. In this case, the output bit size is
For example, set to × 8 bits and the maximum output bit size
It is. When the pad 1822 is in a floating state,
Section node 1829 is connected to the
Maintained at source potential Vcc level. So in this case
The selection signal / BS becomes "H". The output bit size is as small as 4 bits, for example.
In this case, the pad 1822 is connected to the ground potential Vss.
Bonded by bonding wire 1830. This state
In the state, the potential level of internal node 1829 is
"L", and the selection signal / BS becomes "L". Resistor
Reference numeral 1824 denotes a high resistance, and the power supply voltage Vcc supply node
From the high resistance body 1824 and the bonding wire 18
The current flowing through 30 is negligible and can be ignored
It is about. The output bit size is 8 bits.
The case of 4 bits is shown, but what bit size
May be combined. Also, the logic of the selection signal / BS
May be reversed. Also, without using a high-resistance resistor
And pad 1822 is at power supply voltage Vcc level or ground.
Connect to potential Vss level according to its output bit size
A configuration may be used. [Third Embodiment of Internal Voltage Generating Circuit] FIG. 1
Reference numeral 50 denotes a third embodiment of the internal voltage generating circuit of the present invention.
FIG. 3 is a diagram illustrating a configuration. In FIG.
The circuit 1900 includes a clock signal CLK and a read mode instruction.
An AND circuit 1902 receiving signal φread, and FIG.
Internal having the same configuration as the internal voltage generating circuit shown in 40
A voltage generation circuit 1500 is included. Read mode instruction signal φr
read is active only in data read mode.
It is. Therefore, the internal voltage generation circuit shown in FIG.
The path 1900 has a boosted voltage only during the data read operation.
Vc. The output buffer circuit operates only when the data
Data reading only. Therefore, the internal voltage
The operation of the raw circuit 1500 is controlled by the read mode instruction signal φread.
Charge only when necessary by controlling according to
Pump operation can be performed, reducing power consumption.
Can be. FIG. 151 shows a read mode instructing signal φrea.
FIG. 3 is a diagram illustrating a circuit configuration for generating d. FIG.
, The read mode instruction signal generating circuit
Read mode in response to signal CLK and signals / CAS and / WE.
Read detection circuit 190 for detecting that a code has been designated.
4 and the read detection signal φ from the read detection circuit 1904.
In response to R, generates a signal that is active for a predetermined period.
Including a signal generation circuit 1906. Signal generation circuit 1906
Generates read mode instruction signal φread. this
FIG. 1 is an operation waveform diagram showing the operation of the circuit shown in FIG.
This will be described with reference to FIG. First, at the rising edge of clock signal CLK
Signal / CAS falls to "L" and signal / WE
It is set to "H" and the read mode is designated. In response
In response, the lead detection circuit 1904 outputs a one-shot pulse
Signal φR. The signal generation circuit 1906
Generates clock signal CLK in response to read detection signal φR
Live. Period during which signal φread is activated
Shows only the period necessary for data output, and FIG.
The read mode detection signal φread is inactive.
Is equal to the sum of latency and lap length.
The cycled state is shown as an example. Destination
The signal OEM shown in FIG. 84 is the read mode detection signal.
It may be used as φread. [Fourth Embodiment of Internal Voltage Generating Circuit] FIG. 1
53 is a fourth embodiment of the internal voltage generating circuit according to the present invention.
FIG. 3 is a diagram showing the configuration of FIG. In FIG. 153, internal voltage generation
Circuit 1910 includes an internal power supply provided for bank #A.
Provided for voltage generation circuit 1914 and bank #B
The internal voltage generation circuit 1916 and the bank selection signals BAA and
Clock signal CLK generates internal voltage according to BAB
Switches selectively transmitting to circuits 1914 and 1916
Switch 1912. The SDRAM shown in FIG.
出力 A and bank ♯B have separate output buffers
Have been killed. Therefore, for the selected bank
Only when necessary by supplying the internal boost voltage.
Reduce power consumption. This internal voltage generation circuit
To supply the power supply voltage to drive the
Instead of boosting the word line as explained later.
When used to generate drive signals, bank #A
And the optimum boosting of the internal boosted voltage according to the operation mode of ΔB.
It can be generated with power consumption. For example, bank #A
Banks #B overlap each other in a pipelined fashion
When activated, each of the banks #A and #B
Internal voltage generating circuits 1914 and 191
6 drives multiple banks simultaneously.
Can supply the required internal voltage stably
You. FIG. 154 shows the switching circuit 1 shown in FIG.
FIG. 912 is a diagram showing the configuration of 912. In FIG.
Switch circuit 1912 outputs the bank selection signal BAA and the clock.
AND circuit 1920 receiving signal CLK, and clock signal
Circuit 1 receiving signal CLK and bank select signal BAB
922. The output of the AND circuit 1920 is the bank #A
To internal voltage generating circuit 1914. AND circuit
Output of 1922 is internal voltage generating circuit 191 for bank #B
Given to 6. The bank selection signals BAA and BAB are
When bank #A and bank #B are specified, respectively
At an active state. For unselected banks
Indicates that the output of the AND circuit is fixed at "L" and the corresponding internal
Since no clock signal is supplied to the voltage generation circuit,
No charge pump operation is performed. [0655] The bank selection signals BAA and BAB
Are generated by internal voltage generation circuits 1914 and 1916.
The internal voltages VCA and VCB supplied to the output buffer
If it is the source voltage, the
This is generated by latching the link address BA.
This internal voltage generating circuit generates a voltage for driving the word line.
When used for the bank selection signal BAA and
And BAB are applied to the bank address at the fall of signal / RAS.
Generated by latching the data BA. Explained earlier
The bank designation signal may be used. [Other Applications of Internal Voltage Generating Circuit] FIG.
Shows an example of application of the internal voltage generation circuit according to the present invention.
FIG. In FIG. 155, internal voltage generating circuit 1
950 is a selected word in the memory cell array 1958
Used to generate word line drive signals to the lines.
To raise the potential of the word line above the power supply voltage Vcc
Access to memory cell data from selected memory cell
Without signal loss due to transistor threshold
High-speed reading is possible. In particular, in recent years, semiconductor memory devices
Aiming for large storage capacity, high-speed operation, and low power consumption
The level of the operating power supply voltage Vcc is 3.3 V,
Or, it has been lowered to 1.25V. Such a place
In this case, it is possible to read a sufficient read voltage onto the bit line at high speed.
Required for correct memory operation. Because of this,
Using a word line drive signal with a further boosted source voltage
Is performed. In FIG. 155, the memory cell array
In 1958, one word line WL and one bit
Line BL and one of the members arranged corresponding to their intersections.
A typical example of a Morisel MS is shown. In memory cell array 1958, word
Decorate X address (row address) to select line
X decoder circuit 1954 for loading
Word line selected according to the output of
Word line drive circuit 1956 for transmitting a word line drive signal
Is provided. In FIG. 155, the X decoder circuit
Provided corresponding to one word line in path 1954
The configuration of an AND-type decoder circuit is shown as an example. NA
An ND type decoder circuit may be used. Word line dora
Eve circuit 1956 is also a circuit element related to one word line.
Are representatively shown. This word line drive circuit 195
6 is connected to the boosted word line via the high voltage generation circuit 1952.
A drive signal is transmitted. The high voltage generation circuit 1952
The internal power supply responds to the
The boosted voltage Vc generated by the voltage generation circuit 1950 is connected to the word line
It is transmitted as a drive signal. [0654] The word line drive circuit 1956 is
As a resistor to pass the output from the code circuit 1960
A functioning gate transistor 1962 and a gate transistor
Conduction occurs in response to the output of the
Related to the boosted word line drive signal given from
N-channel MOS transistor transmitted onto word line WL
The output of the unit decode circuit 1960 and the output of the
Inverter circuit 1964 and inverter circuit 19
64, the potential of the word line WL is changed to the ground potential level.
N-channel MOS transistor 1968 discharging to bell
including. Next, the operation will be briefly described. [0655] The internal voltage generating circuit 1950
Signal CLK and internal power supply voltage (may be internal step-down voltage
Operates according to Vcc (according to the configuration of the aforementioned embodiment).
Operates) to generate the boosted voltage Vc. X decoder times
In path 1954, unit decode circuit 1960 selects
Then, the output signal becomes "H" level. to this
Transistor 1966 is turned on, and the transistor
The star 1968 is turned off. High voltage generation circuit 195
2 at the boosted voltage Vc level according to the timing signal φX.
A word line drive signal is generated. Transistor 1966
Is the boosted word line drive from this high voltage generation circuit 1952.
Upon receiving the operation signal, the signal is transmitted to the word line WL. At this time,
For the self-bootstrap effect of transistor 1966
As a result, the gate voltage rises to the boost voltage level,
The boosted word line drive signal is transmitted to the selected word line WL.
Is reached. The access transistor of the memory cell MS is high.
Conduction at a high speed, and the information stored in the memory cell capacitor.
Is transmitted to the corresponding bit line BL. [0656] The gate transistor 1962 is
Due to the self-bootstrap effect of transistor 1966
The boosted voltage of the gate is bad for the unit decode circuit 1960.
It is provided so as not to affect. others
The gate of the gate transistor 1962 is the operating power supply voltage.
Vcc level voltage is supplied. For unselected word lines
As a result, the transistor 1966 is turned off and the transistor
1968 is turned on, and the potential level of the
It is held at the order level. In the above configuration, the internal voltage generation
First to Fourth Embodiments Shown as Circuit 1950
By using the internal voltage generation circuit shown in
Generates a boost word line drive signal and drives the selected word line
Can move. [Modification of Charge Pump Circuit] FIG. 156
FIG. 4 is a diagram showing a modification of the charge pump circuit. FIG.
The charge pump circuit 1980 shown in FIG.
appear. Normally, in a semiconductor memory device, software
Error, reducing the junction capacitance of the MOS transistor,
For the purpose of preventing generation of raw MOS transistors, P
Negative voltage is applied to the mold substrate region or P-type well region
You. The circuit for generating such a negative voltage has the first
Or the configuration of the internal voltage generating circuit of the fifth embodiment is applied.
Can be In FIG. 156, the charge pump
The path 1980 is a capacitor receiving the clock signal CLK.
1982 and one electrode node 19 of the capacitor 1982
85 and a grounded potential.
N-channel MOS transistor 1984 and node 1
DIO provided between output terminal 985 and output node 1987
N-channel MOS transistor 1986
including. The transistor 1986 is connected to the node 1987
Is conductive when the potential of the node is higher than the potential of the node 1985.
State. Transistor 1984 is connected to the node 1985
Is higher than the ground potential level (exactly
(Above the threshold voltage). As shown in FIG.
Brief description of operation of charge pump circuit 1980
I do. [0660] Clock signal CLK rises to "H"
Then, the potential of the node 1985 rises to "H". This
The potential of the node 1985 is released through the transistor 1984.
The threshold voltage of the transistor 1984.
It becomes the pressure VTH level. Clock signal CLK goes low
When the voltage falls, the potential of node 1985 becomes VTH-Vcc level.
Drops to the bell. Thereby, the transistor 198
6 conducts, lowering the potential of output node 1987.
Next, when the clock signal CLK falls to "H",
1985, the potential of the transistor 1986 rises again.
Is turned off. The potential of this node 1985 is
Discharged by the transistor 1984. Clock signal C
When LK falls to “L”, the potential of node 1985 is restored again.
Drops, transistor 1986 conducts, and node 19
The potential of 87 drops again. By repeating this operation
Output node 1987 has a potential of-(Vcc-2VT).
H) level. Generate such a negative voltage
The internal voltage circuit using a charge pump circuit
In this case, the substrate bias potential VBB can be stabilized.
And a stable operating semiconductor memory device can be obtained.
You. The structure of this internal voltage generating circuit is S
It does not apply only to DRAM. Repeat from outside
In the case of a semiconductor memory device to which a signal is given,
The configuration of the voltage generation circuit is applicable. As described above, according to the present invention, each bus
The internal potential can be generated according to the operating status of the link.
Control the increase of current consumption and stabilize each bank
An internal potential can be generated and supplied.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an overall configuration of a first type SDRAM to which the present invention is applied; FIG. 2 is a timing chart showing a standard operation of the SDRAM shown in FIG. FIG. 3 is a diagram showing a memory array arrangement of an SDRAM according to the present invention. FIG. 4 is a diagram showing a standard DRAM array arrangement. FIG. 5 is a diagram for explaining a problem when the SDRAM is applied to a standard DRAM array structure. FIG. 6 shows an arrangement of a memory array of the SDRAM according to the present invention. FIG. 7 is a diagram showing an arrangement of one memory mat shown in FIG. 6; FIG. 8 is a diagram for explaining a word line shunt region. FIG. 9 is a diagram for explaining a word line shunt region. FIG. 10 is a diagram showing a specific structure of a memory array of an SDRAM according to the present invention. FIG. 11 is a diagram for illustrating connection between a local IO line and a global IO line in an SDRAM according to the present invention; FIG. 12 is a diagram showing a connection mode between a local IO line and a global IO line in an SDRAM according to the present invention. FIG. 13 is a diagram illustrating a dummy bit line. FIG. 14 is a diagram showing a configuration for precharging a dummy bit line and a local IO line in an SDRAM according to the present invention; FIG. 15 is a diagram showing a connection mode between a local IO line and a global IO line in an SDRAM according to the present invention. FIG. 16 shows a configuration of a bit line pair, a local IO line pair, and a global IO line pair in an SDRAM according to the present invention. FIG. 17 is a diagram showing a signal change in the configuration shown in FIG. 16; FIG. 18 is a diagram showing a detailed structure of an SDRAM array according to the present invention. FIG. 19 is a diagram showing a detailed structure of an SDRAM array according to the present invention. FIG. 20 is a diagram showing a correspondence relationship between one column select line and a global IO line pair in the SDRAM according to the present invention; FIG. 21 is a diagram showing the correspondence between global IO lines related to one column selection line and data input / output terminals. FIG. 22 is a diagram showing another example of the correspondence relationship between global IO line pairs and data input / output terminals. FIG. 23 is a timing chart showing a masked write operation of the SDRAM according to the present invention. 24 is a diagram showing a configuration for realizing the masked light shown in FIG. FIG. 25 is a signal waveform diagram representing an operation of the circuit shown in FIG. 24. 26 is a diagram showing a specific configuration of a write register shown in FIG. FIG. 27 is a diagram showing a specific configuration of the mask data register shown in FIG. FIG. 28 is a diagram showing a specific configuration of the wrap address generating circuit shown in FIG. FIG. 29 is a diagram showing a specific configuration example of the write buffer shown in FIG. 1; FIG. 30 is a diagram showing a list of correspondences between frequencies and latencies. FIG. 31 is a diagram for describing a definition of each access time in the SDRAM. 32 is a diagram showing a circuit configuration for realizing the frequency-latency correspondence shown in FIG. 30; FIG. 33 is a diagram for explaining a wrap length. FIG. 34 is a diagram showing a circuit configuration for realizing the wrap length shown in FIG. 33; FIG. 35 is a diagram showing a configuration of a circuit portion related to column selection in the SDRAM. FIG. 36 is a timing chart showing an internal operation when the wrap length is 16; FIG. 37 is a diagram showing the appearance and pin arrangement of a package accommodating the first type SDRAM according to the present invention. FIG. 38 is a diagram showing the appearance and pin arrangement of a package accommodating the second type SDRAM according to the present invention. FIG. 39 is a view showing a list of correspondences between external signal states of the second type SDRAM and operation modes designated at that time; FIG. 40 is a timing chart showing an example of the operation of the second type SDRAM. FIG. 41 is a timing chart showing another operation mode of the second type SDRAM. FIG. 42 is a diagram showing a configuration of an external signal input section of a second type SDRAM. FIG. 43 is a diagram showing a configuration of an address buffer unit of a second type SDRAM. FIG. 44 is a block diagram showing an overall configuration of a second type SDRAM. FIG. 45 is a diagram schematically showing a configuration of an output unit of the SDRAM according to the present invention; FIG. 46 shows a structure of a data output unit of bank #A shown in FIG. 45. FIG. 47 shows a configuration of a data output unit of bank #B shown in FIG. 45. FIG. 48 is a timing chart showing an operation of reading data from the banks shown in FIGS. 46 and 47. FIG. 49 is a diagram showing a circuit configuration for generating a data output control signal. 50 is a signal waveform diagram representing an operation of the circuit shown in FIG. 49. FIG. 51 is a diagram showing an example of a specific configuration of the read register shown in FIGS. 46 and 47; FIG. 52 is a signal waveform diagram representing an operation of the read register shown in FIG. 51. FIG. 53 is a diagram showing a circuit configuration for generating a preamplifier enable signal shown in FIG. 51. FIG. 54 is a signal waveform diagram representing an operation of the circuit shown in FIG. 53. FIG. 55 is a diagram showing a specific configuration example of the counter circuit shown in FIG. 53; FIG. 56 is a signal waveform diagram representing an operation of the counter circuit shown in FIG. 55. FIG. 57 is a diagram illustrating another configuration example of the counter circuit illustrated in FIG. 54; 58 is a signal waveform diagram representing an operation of the circuit shown in FIG. 57. FIG. 59 is a diagram showing a circuit configuration for generating a wrap address. FIG. 60 is a signal waveform diagram representing an operation of the wrap address generation circuit system shown in FIG. 60. FIG. 61 is a diagram showing an example of a wrap address generation sequence. FIG. 62 is a diagram illustrating a specific configuration example of the output buffer illustrated in FIG. 45; FIG. 63 is a diagram showing another configuration example of the data output unit of the SDRAM. FIG. 64 is a diagram showing a specific configuration of the read register shown in FIG. 63; FIG. 65 is a timing chart showing a data read operation of the data output unit shown in FIG. 63; FIG. 66 is a diagram showing a data flow of the data output unit shown in FIG. 63. FIG. 67 is a diagram showing a configuration of a wrap address generation circuit system. FIG. 68 is a signal waveform diagram representing an operation of the circuit system shown in FIG. 67. FIG. 69 shows an operation of the circuit system shown in FIG. 67. 70 is a diagram showing a configuration of an output control unit for controlling the operation of the data output unit shown in FIG. 63. FIG. 71 shows a structure of the read detection circuit shown in FIG. 70; FIG. 72 is a signal waveform diagram representing an operation of the read detection circuit shown in FIG. 71. FIG. 73 is a diagram showing a configuration of the WCBR detection circuit shown in FIG. 70; 74 is a signal waveform diagram representing an operation of the circuit shown in FIG. 73. FIG. 75 shows a structure of the latency decode latch shown in FIG. 70. FIG. 76 is a diagram showing a configuration of a wrap length decode latch shown in FIG. 70; FIG. 77 is a diagram showing a circuit configuration for generating a preamplifier enable signal. FIG. 78 is a signal waveform diagram representing an operation of the circuit shown in FIG. 77. FIG. 79 is a diagram showing an example of the configuration of the latency counter shown in FIG. 77; FIG. 80 illustrates an example of a configuration of the flip-flop illustrated in FIG. 79; FIG. 81 is a signal waveform diagram representing an operation of the circuit shown in FIG. 79. FIG. 82 is a diagram showing a circuit configuration for generating a read register transfer instruction signal. FIG. 83 is a signal waveform diagram representing an operation of the circuit shown in FIG. 80. FIG. 84 is a diagram showing a circuit configuration for generating an operation control signal for an output buffer. FIG. 85 shows a specific configuration of the latency counter shown in FIG. 84. 86 is a signal waveform diagram representing an operation of the latency counter shown in FIG. 85. 87 is a diagram showing a specific configuration of a wrap length counter shown in FIG. 84. FIG. 88 is a signal waveform diagram representing an operation of the wrap length counter shown in FIG. 87. FIG. 89 is a diagram showing another operation of the wrap length counter shown in FIG. 87. FIG. 90 shows a structure of the OEM generation circuit shown in FIG. 84. FIG. 91 is a signal waveform diagram representing an operation of the OEM generation circuit shown in FIG. 90. FIG. 92 is a diagram showing a circuit configuration for generating a bank address designating signal. 93 is a signal waveform diagram representing an operation of the bank address generation circuit system shown in FIG. 92. FIG. 94 is a diagram showing a configuration of a data writing unit of the SDRAM. FIG. 95 shows a structure of the write control circuit shown in FIG. 94. 96 is a diagram showing a specific configuration of a write register and a write circuit shown in FIG. 94; 97 is a signal waveform diagram representing an operation of the write register and the write circuit shown in FIG. 96. FIG. 98 is a diagram showing an example of the configuration of the operation of the counter circuit shown in FIG. 95; FIG. 99 is a signal waveform diagram representing an operation of the circuit system shown in FIG. 98. 100 is a diagram illustrating an example of a configuration of a transfer control signal generation circuit illustrated in FIG. 95; FIG. 101 is a timing chart showing the operation of the write control circuit shown in FIG. 95; FIG. 102 is a timing chart showing an operation of the write control circuit shown in FIG. 95; 103 is a diagram showing a functional configuration of the transfer timing generating circuit shown in FIG. 95; FIG. 104 is a diagram showing a configuration of the timing circuit shown in FIG. 103; 105 is a timing chart showing the operation of the timing circuit shown in FIG. 104. 106 is a diagram showing a configuration of a logic gate shown in FIG. 103. 107 is a signal waveform diagram representing an operation of the logic gate shown in FIG. 106. FIG. 108 is a timing chart showing a first equalize signal control timing operation. FIG. 109 is a timing chart showing a first equalize signal timing control method at the time of data reading. FIG. 110 is a diagram schematically showing a configuration of an equalization signal generation system; 111 is a diagram showing an example of a configuration of a column access determination circuit and an equalize signal generation circuit shown in FIG. 110. FIG. 112 is a diagram showing a configuration of an equalizing signal generation system for a local IO line pair. 113 is a signal waveform diagram representing an operation of the configuration shown in FIG. 112. FIG. 114 is a diagram showing a modification of the first equalize signal timing control method. FIG. 115 is a diagram showing a modification of the first equalize signal timing control method at the time of data reading. FIG. 116 is a timing chart showing a second equalize signal timing control method during data writing. FIG. 117 is a timing chart showing a lap stop operation in the second equalize signal timing control method. FIG. 118 is a diagram showing a configuration of a column access determination circuit and an equalize signal generation circuit for realizing a second equalize signal timing control method. 119 is a signal waveform diagram representing an operation of the circuit shown in FIG. 118. FIG. 120 is a diagram showing a modification of the second equalize signal timing control method at the time of data writing. FIG. 121 is a diagram showing a configuration of an equalize signal generation circuit for realizing the timing control shown in FIG. 120; FIG. 122 is a diagram showing a modification of the second equalize signal timing control method. FIG. 123 is a diagram showing a modification of the second equalize signal timing control method. FIG. 124 is a timing chart showing a third equalize signal timing control method during data writing. FIG. 125 is a diagram showing a circuit configuration for implementing third equalize signal timing control. FIG. 126 is a view showing a modification of the third equalize signal timing control method. FIG. 127 is a signal waveform diagram showing a method of generating an internal write mask signal. 128 is a diagram showing an example of a configuration of an internal write mask signal generation system shown in FIG. 127. FIG. 129 is a diagram showing an example of the configuration of the dynamic latch shown in FIG. 128. 130 is a signal waveform diagram representing an operation of the dynamic latch shown in FIG. 129. 131 is a signal waveform diagram representing an operation of the circuit shown in FIG. 128. FIG. 132 is a diagram showing a modification of the dynamic latch. FIG. 133 is a diagram showing a modification of the one-shot pulse generator for setting the flip-flop for generating an internal write mask. 134 is a diagram showing a modification of the gate circuit included in the one-shot pulse generation circuit shown in FIG. 128. FIG. 135 is a diagram showing a configuration of an array active detection signal generation system used in FIGS. 132 to 134; FIG. 136 is a diagram showing another configuration and operation waveforms of the internal write mask signal generation circuit. FIG. 137 is a diagram showing a configuration of a data output unit of the SDRAM. FIG. 138 is a diagram illustrating an example of a configuration of a data output unit of the output buffer circuit illustrated in FIG. 137; FIG. 139 is a diagram illustrating another configuration example of the data output unit of the output buffer circuit illustrated in FIG. 108; FIG. 140 shows a structure of the internal voltage generation circuit shown in FIG. 137. FIG. 141 is a signal waveform diagram representing an operation of the internal voltage generation circuit shown in FIG. 140. FIG. 142 is a diagram showing an example of the configuration of the frequency dividing circuit shown in FIG. 140; FIG. 143 is a diagram illustrating a configuration of the flip-flop illustrated in FIG. 142; FIG. 144 is a timing chart showing an operation of the frequency dividing circuit shown in FIG. 142. FIG. 145 is a diagram showing the configuration of the charge pump circuit shown in FIG. 140; FIG. 146 is a signal waveform diagram representing an operation of the charge pump circuit shown in FIG. 145. FIG. 147 is a diagram showing another configuration example of the internal voltage generation circuit. FIG. 148 is a diagram illustrating an example of a configuration of the switch circuit illustrated in FIG. 147; FIG. 149 is a diagram showing a circuit configuration for generating output bit size selection signal / BS shown in FIG. 148. FIG. 150 is a diagram showing another configuration of the internal voltage generation circuit. FIG. 151 is a diagram showing a circuit configuration for generating the read mode detection signal shown in FIG. 121. FIG. 152 is a signal waveform diagram representing an operation of the circuit system shown in FIG. 150. FIG. 153 is a diagram showing still another configuration of the internal voltage generation circuit. FIG. 154 is a diagram showing a specific configuration of the switch circuit shown in FIG. 153; FIG. 155 is a diagram showing another application example of the internal voltage generation circuit. FIG. 156 is a diagram illustrating another configuration example of the charge pump circuit. [Description of Signs] GIO Global IO line pair, LIO local IO line pair, BS connection circuit, MK 32K bit memory array, MSA 2M bit memory array (activation section),
MA 256K bit memory array, DBL dummy bit line, DEQ dummy bit line and transistor for local IO line connection, 700 SDRAM, 702 output buffer, RG read register, TB0A to TB8A
3-state inverter buffer, TB0B to TB8B 3
State inverter buffer, 714 latency storage circuit,
715 BA generation circuit, 716 Wrap length storage circuit, 7
18 counter, PRA preamplifier, LRG latch circuit, 720 counter circuit, 793 wrap address generation circuit, 820 look-ahead latch circuit, SLRG latch circuit, 852 wrap length counter, 854 wrap address generation circuit, 860 read detection circuit, 862 WCB
R detection circuit, 868 latency decode latch, 87
0 wrap length decode latch, 880 output control circuit,
1000 latency counter, 1002 lap length counter, 1006 OEM generation circuit, 1008 look-ahead latch control signal generation circuit, 1100 timing pulse generation circuit, 1102 latency storage circuit, 1104 lap length counter, 1106 BA generation circuit, 1108 BA
Latch, 1110 selection circuit, WG0-WG7 write register, WR0-WR7 write circuit, 1200 input buffer, 1202 wrap address generation circuit, 1204
Write detection circuit, 1206 write control circuit, 1210
Counter circuit, 1212 lap length setting circuit, 121
4 Lap stop length setting circuit, 1216 transfer timing generation circuit, 1218 transfer control signal generation circuit, 12
20 transfer control circuit, OB0 to OB7 output buffer circuit, 1500 internal voltage generation circuit, 1600 frequency divider circuit, 1602a to 1602d charge pump circuit,
802 switch circuit, 1820 output bit size selection signal generation circuit, 1900 internal voltage generation circuit, 190
2 AND circuit, 1910 Internal voltage generation circuit, 191
2 Switch circuit, 1914 Bank #A internal voltage generator, 1916 Bank #B Internal voltage generator, 1
950 Internal voltage generation circuit, 1952 High voltage generation circuit, 1954 X decode circuit, 1956 word line drive circuit, 1958 memory array, 2000 column access determination circuit, 2001 counter, 2002
Equalize signal generation circuit, 2003 wrap length setting circuit, 2010 write command detection circuit, 2012 read command detection circuit, 2014 precharge command detection circuit, 2020 AND circuit, 2022 AND
Circuit, 2024 OR circuit, 2026 OR circuit, 20
27 one-shot pulse generation circuit, 2028 set / reset flip-flop, 2030 active command detection circuit, 2032 block address decode latch, 2021 half-cycle delay circuit, 2034 half-cycle delay circuit, 2025 set / reset flip-flop, 2030 one-shot pulse generation circuit,
2031 OR circuit, 2036 one-shot pulse generation circuit, 2037 OR circuit, 2040 OR circuit, 2
042 one-shot pulse generation circuit, 2044 OR
Circuit, 2046 set / reset flip-flops,
2048 One-shot pulse generation circuit, 2049 O
R circuit, 2050 dynamic latch, 2052 one-shot pulse generation circuit, 2054 delay circuit, 20
56 gate circuit, 2058 set / reset flip-flop, 2080 switching transistor, 2
081 AND circuit, 2085 active command detection circuit, 2086 precharge command detection circuit, 2
087 Set / reset flip-flop, 2100
One-shot pulse generation circuit, 2102 dynamic latch, 2104 delay circuit, 2108 flip-flop.

Continuation of front page    (72) Inventor Hisashi Iwamoto             Mitsubishi Electric Corporation 4-1-1 Mizuhara, Itami-shi, Hyogo             ULS Inc. Development Research             Inside (72) Inventor Yasuhiro Konishi             Mitsubishi Electric Corporation 4-1-1 Mizuhara, Itami-shi, Hyogo             ULS Inc. Development Research             Inside (72) Inventor Naoya Watanabe ▼             Mitsubishi Electric Corporation 4-1-1 Mizuhara, Itami-shi, Hyogo             ULS Inc. Development Research             Inside (72) Inventor Seiji Sawada             Mitsubishi Electric Corporation 4-1-1 Mizuhara, Itami-shi, Hyogo             Kita Itami Works Co., Ltd. F term (reference) 5F038 BG05 BG07 DF01 DF05 DF08                       DF17 EZ20                 5M024 AA04 AA16 AA24 AA45 BB04                       BB29 BB33 DD42 DD45 DD47                       DD83 FF03 FF13 FF15 FF25                       GG01 GG06 HH09 HH11 JJ02                       JJ12 JJ20 JJ53 JJ60 LL09                       PP01 PP02 PP03 PP05 PP07                       PP10

Claims (1)

Claims: 1. A plurality of banks each having a plurality of memory cells, and a plurality of banks are provided corresponding to each of a plurality of precursor banks, each of which receives a corresponding driving clock signal and performs a charge pump operation. Receiving a clock signal and a plurality of bank identification signals, each of which is activated according to the selected bank address, and corresponding the clock signal to the selected bank. A switch circuit for transmitting the internal potential generation circuit as a driving clock signal.