JP2003274674A - Zero-voltage switching mode inverter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To maintain voltage of a switching element at a zero voltage by utilizing an operation of inductance before turning on the switching element in an inverter, to reduce a switching loss in switching, at the same time, to restrain rising of current, and hence to achieve the inverter having increased efficiency and low noise. <P>SOLUTION: In the inverter circuit, the two switching elements have opposite continuity characteristics that have a dead time and are opened and closed without simultaneously turning on, and are connected to an input power supply in series. Further, inductances L1 and L2 are connected in series to both polarities of the input power supply, the switching elements having the opposite continuity characteristics that have a capacitor C and the dead time and are opened and closed without simultaneously turning on are provided ahead, and power is supplied to a load from the center point of each switching element. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to inverter soft switching.

[0002]

2. Description of the Related Art FIG. 1 shows an inverter circuit called a full bridge inverter. In principle, this circuit is characterized by the fact that no voltage higher than the power supply voltage is applied to the switching element, and the effective value of the current flowing through the switching element is small, making it an indispensable circuit system for an inverter with high power. However, in this inverter circuit, a voltage corresponding to the power supply voltage is applied to the switching element immediately before the switching element is turned on, and the charge accumulated between the terminals of the switching element is rapidly discharged at the moment when the switching element is turned on. Therefore, not only transient voltage and current changes at the switching element switching moment are a major cause of noise generation, but also the product of voltage and current corresponding to the loss at the switching switching point becomes large, which reduces the inverter efficiency. Was the cause.

Furthermore, when a switching element such as an FET or an IGBT is used, the reverse recovery time of the built-in diode becomes long, and during this reverse recovery time, the ON-OF is alternately turned on.
Excessive pulse current flows in the series circuit of the switching elements that perform F, and this current may increase loss and generate noise. When the power supply voltage is high, not only the loss may increase, but also the switching element may be destroyed. It was

[0004]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention

In FIG. 1, the conversion efficiency was poor and there were many switching noises. To solve these problems,

As shown in FIG. 2, inductances L1 and L2 are provided between a pair of series switches, and a current flowing through the inductances biases the interrupted switching element in the reverse direction to make the voltage of the interrupted switch almost zero. keep. As a result, not only ideal zero voltage switching operation is possible, but also the rise of the current when the switch is turned on is limited by the action of the inductance, and the reverse recovery time of the switching element or the rectifier and the charge accumulation effect are caused. It is intended to realize a high-efficiency and low-noise inverter by preventing problems such as a decrease in efficiency and noise generation.

[0005]

[Means for Solving the Problem] As shown in FIG. 2, two switching elements S1 and S2 having a reverse conduction characteristic that have a dead time and open and close under the condition that they do not turn on at the same time are connected in series to an input power source. , A switching element S3 having two reverse conduction characteristics, in which inductances L1 and L2 are connected in series for both polarities of the input power source, and there is a dead time with the capacitor C at the end of the input power supply, and the switching elements S2 and C2 are opened and closed under the condition that they are not turned on at the same time. S4 is provided to supply power to the load from the middle point of each switching element. By this method, the current of L1 or L2 is made to flow in the reverse direction while the switching element is OFF, and the operation of maintaining the voltage of the switching element at substantially zero is performed.

[0006]

First, when the switches S2 and S3 are turned off in FIG. 2 and the switches S1 and S4 are turned on at the same time, current flows from S1 to the load (Load), S4 and L2 in this order, and A voltage value approximately equivalent to the power supply voltage is added. When S1 and S4 are turned off when the ON time has passed, the current flowing in L2 is changed to the diode D2, Load,
It flows in the order of D3 and C to become the charging current of the capacitor C,
The current of L2 flowing immediately before the interruption of S1 and S4 is maintained, and the energy accumulated in the coil L1 is effectively recovered to the power supply side. As a result, the diodes D2 and D3 are forward biased, and the voltage value thereof is maintained at substantially zero.

In the next cycle, the switches S3 and S2 are turned off.
When set to N, the current flows in the order of L1, S3, Load, S2. Since the voltage has already become zero at the moment when S3 and S2 are turned on for the reason described above, the switching loss becomes minimum. When the ON time has elapsed, turn S3 and S2 off.
When FF, the current flowing in L1 is the diode D1, L
The current flows in the order of 1 and C, the charging current of the capacitor C, the current of the diode D4 and the load, and the current of L1 flowing immediately before the interruption of S3 and S2. As a result, the diodes D1 and D4 are forward biased,
Its voltage value is kept near zero. When the switches S1 and S4 are turned on in the next cycle, the current is S1 and Loa.
d and S4 L2 flow in this order. S1 and S
Since the voltage has already become zero at the moment when 4 is turned on, the switching loss is minimized here as well.

Since the voltage when all the switching elements are cut off is kept substantially zero by the same repetition as the above, the switching loss at the moment when the switching elements are turned on becomes the minimum. Moreover, since there is no voltage change at the moment when the switching element is turned on, no noise is generated and the problem of reverse recovery current of the diode does not occur. Further, the current rising speed at the moment when the switching element is turned on can be arbitrarily delayed by L1 and L2, and the transient switching loss applied to the switching element can be greatly reduced. Typically,
It is easy to reduce the loss by delaying the rising of the current flowing through the switching element by the action of the inductance. However, even if the transitional switching loss is reduced due to the delay in the rising of the current, the energy stored in the inductance for suppressing the rising of the current cannot be effectively used in many cases, and the expected efficiency is improved. In many cases, the improvement is not made. In the present invention, the energy stored in the inductance operates to charge the capacitor C as described above and is effectively returned to the power supply side, so that no loss occurs and extremely high efficiency is realized. You can

[0009]

EXAMPLE FIG. 3 shows an example of using a FET as a switching element. Due to the structure of the FET, the voltage-current characteristic in the reverse direction often has a diode characteristic.
D1 to D4 corresponding to (4) utilize this diode characteristic. Generally, the built-in diode of FET has a relatively long reverse recovery time and cannot be used at a high frequency. For this reason, when used at a high frequency, a Schottky diode having a fast recovery time is serially connected to the FET to block the reverse current, and a high speed diode is externally attached. This method has a large number of parts, increases the cost, and increases the loss due to the voltage drop of the diode connected in series. In the present invention, the switching element is ON
At that moment, since the voltage is originally zero voltage and there is no voltage change, current does not flow due to the influence of the reverse recovery time of the diode, and such troublesome measures are unnecessary.

In FIG. 3, Pv1 to Pv4 are pulse voltages FE
It is supplied to the gate of T to control the timing of turning on the FET. The conditions of the pulse voltage applied here are S1 and S2.
Or, the condition that S3 and S4 are not turned on at the same time, the period from when S1 or S2 is turned off until S3 or S4 is turned on, and the time when S3 or S4 is turned off and S1 or
Insert an appropriate dead time until 2 turns ON. This dead time is adjusted so that the upper and lower switches do not turn on at the same time according to the switching speed of the FET. If the above conditions are observed, the gate timing of the FET has much more freedom than the other zero voltage switching methods. The output of the inverter can be freely adjusted by changing the timing of turning on the switches S1 to S4, and zero voltage switching is performed in a wide range.

FIG. 4 is an example of a DC-DC converter utilizing the present invention. If this output voltage or current is compared with a reference voltage and Pv1 to Pv4 are controlled as feedback signals, a constant voltage or constant current power supply with high efficiency and low noise can be realized. The capacitor Cc is inserted for the purpose of preventing a DC bias from being generated in the transformer when the positive and negative cycles of the output voltage of the inverter are different from each other in terms of the voltage integration value, and thus biasing the transformer. Also, the diode Dd
1, Dd2 and Rd clamp the peak value of the primary voltage of the transformer. In order to reduce the rising speed of the voltage when each switch is turned off, a capacitor can be added in parallel with each switching element. When the zero voltage switching operation is not performed, the energy stored in this capacitor becomes a loss and the efficiency is reduced. Even if the capacitor is not added, the efficiency is lowered even by the amount accumulated in the inter-terminal capacitance of the switching element. However, since the present invention does not have this loss, an inverter with high efficiency and low noise can be realized.

[0012]

As described above, by utilizing the current flowing through the inductance, the voltage can be kept at zero voltage and the transient switching loss at the moment when each switching element is turned on can be made zero. Furthermore, the current rising speed after the switching element is turned on can be freely controlled by the value of the added inductance.
The rising speed of the voltage at the instant of F can be freely set without lowering the efficiency by the method of inserting a capacitor in parallel with the switching element, and it is possible to increase the efficiency and realize an inverter with low noise. The inductances L1 and L2, which are the key points of the present invention, have an epoch-making effect even with a very small value, and have almost no influence on the size of the device. In addition, the value is more flexible and easier to design than other methods. It is also possible to wind the inductances L1 and L2 around the same magnetic core to further reduce the size.

[Brief description of drawings]

]

FIG. 1 is a principle diagram of a conventional full-bridge type inverter. S1 to S4 are switches, and D1 to D4 are rectifiers for reverse voltage elements. Ei is an input power source, and Load is a load.

FIG. 2 is a principle diagram of an inverter according to the present invention. S1
S4 are switches, D1 to D4 are rectifiers for reverse voltage elements. Ei is an input power source, and Load is a load. L
1 and L2 use this current to adjust the action of keeping the switching element at zero voltage during the OFF period and the current rising speed after the switching element is turned ON.

FIG. 3 is an example of the present invention, in which the switching element is an FET
This is an example of using. S1 to S4 are FETs, and Pv1 to Pv4 are drive circuits, respectively. (The rectifier for the reverse voltage element utilizes the diode characteristic of the FET.) Ei is the input power supply and Load is the load. L1 and L2 utilize this current to adjust the action of keeping the switching element at zero voltage during the OFF period and the current rising speed after the switching element is turned ON.

FIG. 4 is a diagram illustrating an example of the present invention in which the inverter of FIG.
It is an implementation circuit diagram at the time of applying to a DC converter. S
1 to S4 are FETs, and Pv1 to Pv4 are drive circuits, respectively. (The rectifier for the reverse voltage element utilizes the diode characteristics of FET) Dd1, Dd2 diode, R
d is a resistor that clamps the peak value of the primary voltage of the transformer. Ei is an input power supply, and L1 and L2 utilize this current to adjust the action of keeping the switching element at zero voltage during the OFF period and the current rising speed after the switching element is turned ON. T is a transformer, Rec is a rectifier, Lf is a choke coil for filters, Co is a capacitor for filters, and Cc is a DC blocking capacitor.

Claims (2)

[Claims] 1. As shown in FIG. 2, two switching elements S1 and S2 having a reverse conduction characteristic that open and close under the condition that they have no dead time and do not turn on at the same time are connected in series to an input power source, and further, an input power source. Inductors L1 and L2 are connected in series for both polarities of, and two switching elements S3 and S4 having a dead time and a reverse conduction characteristic that opens and closes under the condition that they do not turn on at the same time with the capacitor C are provided. An inverter circuit that supplies power to the load from the middle point of each switching element. 2. As shown in FIG. 2, two switching elements S1 and S2 having a reverse conduction characteristic which have a dead time and open / close under the condition that they do not turn on at the same time are connected in series to an input power source, and further, an input power source. Inductors L1 and L2 are connected in series for both polarities of, and two switching elements S3 and S4 having a dead time and a reverse conduction characteristic that opens and closes under the condition that they do not turn on at the same time with the capacitor C are provided. An inverter device that has the function of controlling the ON time of each switching element and adjusting the output with an inverter circuit that supplies power from the midpoint of each switching element to the load.