JP2003271260A - Computer system and its operation control system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To assert STPCLK# at fixed intervals so as to reduce an apparent CPU speed and electric current consumption. <P>SOLUTION: By asserting STPCLK# at fixed intervals, the apparent CPU speed and the electric current consumption are reduced. On the occurrence of system event (INTR, NMI, SMI, SRESET, INIT), the assertion of STPCLK# is prohibited for a given length of time, making it operate at high speed. On ISA refresh cycle, STPCLK# is asserted in stead of a conventional HOLD/HLDA cycle, thereby permitting to execute a refresh cycle in a stop grant state. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system such as a personal computer, and more particularly to a computer system realizing an energy saving mode using a stop clock function in the system and an operation control method thereof.

[0002]

2. Description of the Related Art In recent years, various notebook-type or laptop-type portable personal computers which are easy to carry and can be operated by a battery have been developed. In this type of computer, various measures have been taken to save power in order to make the battery drive time as long as possible.

For example, in order to reduce the power consumption of the CPU, measures have been taken to slow down the operating speed of the CPU and reduce the current consumption of the CPU. On the other hand, CPU (cent
Ral processing unit) is getting faster year by year. For example, Intel Corporation 80286-8
0386, 80486, Pentium, ... Continued to be speeded up, the CPU internal clock speeded up, and the CPU bus width expanded.

By the way, for example, when the above Pentium is mounted as a CPU in a portable computer such as a notebook computer, there is a problem of how to suppress heat generation because the power consumption is large. Since the current consumption of the CPU is almost proportional to the input clock, if the CPU is operated at a low speed (the clock is dropped), the current consumption will be reduced, and as a result, heat generation can be suppressed. Basically, it is conceivable to use the stop clock function of the CPU to switch the clock so that the clock is slowed down when the CPU temperature rises.

The stop clock function is an interrupt mechanism (STPCLK # signal) for controlling the power consumption of the CPU by stopping the internal clock to the CPU, and is a function possessed by, for example, the Intel 80486 or Pentium. The low power state is called a stop grant state. Further, the STPCLK # interrupt can change the input frequency within a certain range or completely stop the CLK input frequency. When the CLK input is completely stopped, the CPU can be in the stop clock state, that is, the lowest power state.

However, in the clock switching using the stop clock function, since the CPU does not operate normally for 1 ms after the clock switching, there is a restriction that the switching cannot be performed dynamically.

In addition, conventionally, the refresh cycle (IS
There are two methods of executing the A bus refresh cycle) and switching the CPU clock, and lengthening the refresh cycle to apparently reduce the CPU speed. The conventional refresh cycle is executed by stopping the CPU so that the CPU does not access during this period. That is, as shown in FIG. 16, the HOLD signal is issued and the refresh operation is performed once every 15 μS. When the HOLD signal is output, the CPU stops operating completely. If this refresh cycle is extended and extended as shown by the broken line in the figure, and the refresh cycle is set to, for example, 7 μS, the CPU apparently appears to operate at ½ speed. However, the CPU does not execute the program,
The current consumption of the CPU does not change. In this case, the user can set the operating speed of the CPU to HIG in
When switching from H to LOW, the operation speed of the CPU is apparently slowed by the extension of the refresh cycle as described above. However, as described above, the current consumption of the CPU does not change during this HOLD period. Therefore, even if the operating speed of the CPU is apparently slowed down, the operating time does not change, and it does not contribute to prolonging the driving time of the battery.

By the way, as a system specification, there is a computer system having a setting function of CPU high speed / low speed. Conventionally, such a computer system has the above-mentioned problems, so that the clocks are not actually switched, and only the hold cycle at the time of refresh is extended to slow the apparent operation speed. Absent. That is, as shown in FIG. 15, the microprocessor does not slow down, but the refresh hold time is extended by the slowdown timer.
Holds the microprocessor longer than normal. The processor appears to be slow because it cannot fetch and execute the program.

In this case, the current consumption of the CPU does not change even if the CPU is operated at low speed. Therefore, it is desired that the apparent speed is reduced and the current consumption is also reduced. Also,
In this low speed mode, it is desired to perform the refresh cycle by using the stop clock function instead of the hold cycle.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a computer system and its operation control method capable of efficiently reducing current consumption by using a stop clock function. It is to be.

[0011]

In order to solve the above problems and achieve the object, the present invention uses the following means.

The computer system of the present invention includes a CPU capable of receiving an instruction signal indicating an instruction to stop the internal clock and an interrupt signal indicating an instruction for interrupt processing, and the CP.
A means for asserting the instruction signal to U, an interrupt means for generating the interrupt signal when a system event occurs, and an interrupt signal generated by the interrupt means while the instruction signal is asserted to the CPU. In this case, the interrupt signal is held, and the interrupt signal is asserted to the CPU after the instruction signal is deasserted.

The computer system of the present invention can efficiently reduce current consumption by using the stop clock function.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. FIG. 1 is a schematic block diagram showing an embodiment of a computer system having an energy saving mode function using a stop clock function of the present invention. As shown in the figure, the CPU 1 is, for example, SL Enhanced 80486 or Pentiu manufactured by Intel Corporation of the United States.
It is a 32-bit CPU corresponding to m (P54C). CPU
Reference numeral 1 is connected to the CPU control gate array 3 and the main DRAM 7 via the CPU bus 5. CP
The U control gate array 3 is composed of a data bus drive block, a CPU control block, a DRAM mapper, a DRAM control block, and a CPU cycle check block. The CPU controller controls the CPU cycle (controls the end of the cycle for the CPU based on the signals from the DRAM controller and the VL bus), CPU address decode (internal memory (64
Bit), extended memory (32 bits), memory, ext
Ended memory, 000C0000H-000FFF
FFH window of 16 KB, SM-RAM, write protect area, cache area), control signal output to data bus driver (latch signal, byte lane swap signal), output of I / O buffer enable signal, etc. are controlled. . DRAM mapper is used for DRAM mapping (address conversion from CPU address to DRAM address, generation of DRAM logical address, conventi
DRAM logical address generation corresponding to the internal area, DRAM logical address generation corresponding to the extended area, and DRAM corresponding to the SM-RAM area
Logical address generation). DRAM controller is D
RAM control (DRAM access (CPU and external master / DMA) control, L1 write back cache support control, shadow refresh control, 32-bit extended DRAM access cycle conversion (64x3)
2)) is performed. In addition, selectors for register data from the above blocks, delay control circuit for ADS #, CP
A clock output delay control circuit to U, a clock / reset / suspend control circuit, an additional circuit for testing, and the like are provided. The CPU control gate array 3 also includes an ISA controller gate array 11, an expansion DRAM 13, and a VGA via a VL bus 9.
It is connected to the controller 15. The ISA controller 11 includes the VGA controller 15 and the extended DR.
It controls the AM 13 and the CPU 1 and VGA controller 1 via the CPU control gate array 3.
5 and the extended DRAM 13 are interfaced.

FIG. 2 shows an interval stop clock (S
An example of a circuit for asserting TPCLK #) at regular intervals is shown. Although the circuit shown in FIG. 2 is provided in the ISA control gate array 11 of FIG. 1, it may be provided in the CPU control gate array 3. For the interval stop clock (STPCLK #) function, for example, 1
"Intel 486 Micropro, published in 993
cesor Family Data Book Add
endum: SL Enhanced Intel 486
Microprocessor Family, and 1994 Issued "Pentium Process"
or Family User's Manual ". In the figure, the counter A17 is shown in FIG.
It is a counter for counting the request period of the request signal (ISRQ1) shown in (a). The request period is set by the interval stop clock enable register (REGA) 19. The counter B23 has a stop clock signal (STPCLK) shown in FIG.
#) Is a counter for counting the hold period. The hold period is set programmable by the interval stop clock hold register (REGB) 25.

The function of the interval stop clock enable register 19 is as follows. After sending a stop clock request to the CPU1 at a fixed interval for a set time, and when the CPU1 accepts it (only when the CPU1 has generated a stop grant cycle), after continuing the stop grant state for another set time , STPCLK # are deasserted (to HIGH).

INTERVAL STOP CLOCK ENABLE REG.bit7-1: I
NTSC (INTERVAL STOPCLOCK ENABLE) Enables the interval stop clock function.

When 0: The interval stop clock function is disabled.

When 1: The interval stop clock function is enabled.

The counter A17 starts operating by setting this bit to 1, and stops (clears) the counter when it becomes 0.

Bit6-3: INH3-0 (INTERVAL STOPCLOCK INHIB
IT TIME) SMI, NMI, INTR, INIT, VGA Only when access comes in, fixed time interval stop clock (STPCLK #)
Prohibit When INH3-0 are all 0, the function of prohibiting the interval stop clock (STPCLK #) does not operate.

DIS3 2 1 0 Interval stop clock prohibition period 0 0 0 0 0 Not prohibited 0 0 0 1 1ms 0 0 1 1 0 2ms 0 0 1 1 3ms ··· 1 1 1 1 1 15ms bit 2-0: INTB2-0 (INTERVAL TIMER BIT2-0) Specifies the interval for asserting STPCLK #. bit
Effective only when 7 = 1.

BIT 2 1 0 STPCLK # Assertion Interval 0 0 0 8 μs 0 0 1 16 μs 0 1 0 32 μs ··· 1 1 0 512 μs 1 1 1 1024 μs The bit assignment and function of the interval stop clock hold register 25 are as follows. On the street.

Bit7-6: IRQ0SL, VGASL The condition for prohibiting the interval stop clock is changed.

IRW0SL = 0: IRQ0 by timer interrupt
INTR (Interrupt Requests)
In t), a certain time interval is prohibited.

IRQ0SL = 1: IRQ0 by timer interrupt
The specified time interval is prohibited by the INTR including the above.

VGASL = 0: Access to VGA prohibits a fixed time interval.

VGASL = 1: Access to VGA does not prohibit intervals.

Bit5-0: HTIM5-0 (HOLD TIMER 5-0) STPC
Designate the time (hold time) during which LK # is asserted. Start of Stop Grant Cycle (ADS #)
The counter starts operating 10 CLKs after, and STPCLK # is deasserted (HIGH) when the value set by this bit is reached. The counter B23 is set to S depending on whether the interval stop clock function is disabled, this bit setting value is set, or an interrupt factor or the like.
When TPCLK # is broken, it is cleared and the operation is stopped.

BIT 5 4 3 2 1 0 STPCLK # hold period 0 0 0 0 0 0 0 0 μs 0 0 0 0 0 1 1 μs 0 0 0 0 0 2 0 2 μs ·· 1 1 1 1 1 1 1 0 62 μs 1 1 1 1 1 63μ In FIG. 2, the comparison circuit 21 compares the counter output of the counter A17 with the counter set value of the register A19,
When they match, a clear signal is supplied to the clear terminal of the counter A17 to clear the counter A17. The comparison circuit 29 compares the counter output of the counter B23 with the counter set value of the register B25, and if they match, the AND gate 27
Is supplied to the clear terminal of the counter B23 via. The decode circuit 31 is a circuit that decodes the CPU status and detects the stop grant state.
Although the stop grant state is input to the PLL in the CPU 1 as a clock, the output of the PLL is stopped, and the current consumption of the CPU is reduced (Icc = 20 or 50).
It is in the high-speed wakeup state. For details, see "Intel 486 Microprocess" above.
or FamilyData Book Addend
um] and “Pentium Processor F
aimy User's Manual]. The AND gate 27 outputs the clear signal from the comparison circuit 29 to the counter B in the stop grant state.
23.

31 is a snap mode (usually, STPCLK # is asserted at a constant interval to reduce the apparent operation speed, and when a factor such as an interrupt occurs, the assertion of STPCLK # is prohibited for a certain period of time to achieve high speed. This is an inhibit timer circuit for realizing an operating mode). Counter 33, register 19, comparison circuit 37
Is a circuit for setting the interval stop clock prohibition section shown in FIG. 4A, and the counter 33 is an event (for example, INTR (Interrupt Requests).
t), NMI (Non-Maskable Inter
RUPT), SMI (System Management)
nt Interrupt), SRESET (System
em Reset), INIT (Initializ)
e) etc., these signals are referred to as “SL Enhan” described above.
ced Intel 486 Microprocess
or Family ”and“ Pentium Pro
cesor Family User's Manual
start counting in response to the occurrence of 1). The above interval stop clock prohibited section is set in bit 6-3 of the register 19 for 1 ms to 15 ms.
It is set in the range of. The comparator circuit 37 compares the counter output of the counter 33 with the counter set value of the register 35, and outputs the interval stop clock prohibition signal to the AND gate 39 until the two coincide with each other, and the AND gate 39, as shown in FIG. Does not output the interval stop clock (STPCLK #).

The arbitration circuit 41 operates while the interval stop clock (STPCLK #) is operating, INTR, SMI,
This is a circuit that performs processing when there is NMI, SRESET (INIT), or VGA access, and performs processing as shown in FIG.

As shown in the table of FIG. 6, 1) when the interval stop clock is output and the CPU is operating, 2) when the interval stop clock is output and STPCLK # = 0, and 3 ) There are three states when the interval stop clock is output and the CPU 1 is in the stop grant state. In the IRQ0 due to the timer interrupt, the inhibit timer 31 does not operate in any of the above states 1) to 3).

In the state of 1), INTR (IRQ0 to IRQ15), SMI, NMI, SRESET (INI
T) and VGA access, the inhibit timer 31 is started. In the state of 2), INTR (IR
Q0 to IRQ15), SMI, NMISRESET
When (INIT) and VGA are accessed, the inhibit timer is started and the CPU waits for the stop grant cycle. Furthermore, in the state of 3), INTR (I
RQ0 to IRQ15), SMI, NMI, SRESE
When T (INIT) is present, the stop grant state is broken and the inhibit timer 31 is started. In addition, when the CPU 1 is in the stop grant state, V
GA access does not occur.

FIG. 7 shows the detailed timing of the interval stop clock. When the interval stop clock request (ISRQ1) is output as shown in FIG. 9A, sTPCLK # is asserted as shown in FIG. (However, INTR, NMI, S
If there is MI, SRESET, INIT, STP
Do not assert CLK #. ) In the figure (b), STPCL
When K # is asserted, the CPU enters the stop grant state as shown in FIG. The CPU enters the stop grant state, and the halt break timer (counter 2) 10 CLK after ADS # (a signal indicating the start of a new bus cycle) of the stop grant cycle.
3, when the register 25 and the comparison circuit 290 start to operate and count for a period designated by the register 25, FIG.
The hold timer is terminated as shown in FIG. 3 and the interval stop clock request (ISRQ shown in FIG.
1) is withdrawn.

FIG. 8 shows the interval stop clock (S
TPCLK #) is asserted and the CPU is in the stop grant state, and is a timing chart when another break factor occurs. When another break factor occurs as shown in (e) of the same figure, (b) of the same figure
STPCLK # is deasserted, and the interval stop clock request (ISRQ1) and the hold timer (counter 23, register 25, comparison circuit 29) are cleared as shown in FIGS.

Next, the stop clock refresh function will be described. The stop clock refresh function is used in the conventional HOL during the ISA bus refresh cycle.
By asserting the STPCLK # signal instead of the D / HLDA cycle, the refresh cycle is performed in the stop grant state.

With the ISA bus refresh function, for example, when a desk station is connected via an expansion connector of a notebook computer, a DRAM expansion memory card may be connected to the slot of the desk station. In this case, the refresh signal is defined as the bus specification as the CPU interface signal. C
The PU is configured to refresh the extended memory card when this refresh signal is active.

This function is provided in the ISA control gate array 11 shown in FIG. 1, for example. However, C
It may be in the PU control gate array 3. I
In the SA control gate array 11, when a stop clock request for refresh is generated, INT
The assertion of R, NMI, SMI # and INIT and whether or not it is a halt cycle are monitored, and if these factors have already occurred, the refresh is switched to the normal HOLD / HLDA cycle. in this case,
Do not assert STPCLK #. STPCLK # is asserted and INTR, NMI, SMI #, and INIT are blocked at the same time only when the above factors do not occur. When a halt cycle occurs after STPCLK # is asserted, STPCLK # is deasserted.
However, INTR, NMI, SMI #, and INIT remain blocked so that the halt cycle is not broken.

The halt cycle and the stop grant state are the same in terms of current consumption.
Is in a stopped state. Therefore, it does not make sense to break the halt cycle and then shift to the stop grant state and refresh. Therefore, the ISA control gate array is STPCLK #
If a Holt cycle occurs after outputting
It is assumed that a stop grant cycle has occurred (STPCLK # is not deasserted), and is originally supported (in the stop clock state).
/ HLDA shoulder replacement circuit enables HL inside the gate array
A DA signal (hold acknowledge signal) is generated. HLDA is deasserted when the hold request by the hold extension circuit at the time of refresh is cut off, and INTR,
The blocks of NMI, SMI #, and INIT are released. In this case, the refresh cycle is performed when the CPU is in the halt state. The hold extension time at the time of refreshing by this hold extension circuit is set programmable by designating with a register.

If a halt cycle occurs after STPCLK # is asserted, the HOLD that was blocked is blocked.
A signal may be output to the CPU to switch to normal HOLD / HLDA refresh.

Next, the stop clock refresh function will be described. The bit assignments of the stop clock refresh control register and their functions are as follows.

STOP CLOCK REFERESH CONTROL REG. Bit7: Enable / disable stop clock refresh.

When 0, normal refresh When 1, the STPCLK # is controlled at the time of refresh.

Conventional ISA refresh is performed by HOLD /
Use STPCLK # instead of controlling with HLDA.
During ISA refresh, the CPU is placed in the stop grant state to reduce power consumption. If the refresh hold time is set long, the time during which the CPU is in the stop grant state also becomes long, and power consumption can be further suppressed.

STPCLK # is controlled only when a HOLD request by ISA refresh occurs. In the HOLD request by the DMA / master, STPC
LK # does not become LOW.

When stop clock refresh is enabled, HOLD due to ISA refresh is not transmitted to the CPU. HLDA shoulder replacement is performed in the gate array.

Stop grant state by ISA refresh is SMI, NMI, INTR, INIT, S
Not break by RESET. SMI, NM during Stop Grant state by ISA refresh
I, INTR, and SRESET are blocked, and are reissued at the first rise of ADS # after the end of the stop grant.

In the CPU, SMI, even during the grant state,
Do not block NMI, INTR and INIT.

Bit6-1: Not used STPCLK # due to ISA refresh is SRESE
Arbitrate with T. ISA refresh by STPCL
The SRESET request is blocked while K # = LOW, and SR when STPCLK # = HIGH.
Reissue ESET. SRES (don't wait for ADS #)
During ET, STPCLK # is not asserted to LOW even if there is a HOLD request due to ISA refresh. If there is a HOLD request due to refresh, this is passed through to the CPU without blocking. The CPU accepts HOLD even during SRESET.

The stop clock function and the stop clock refresh function may be enabled at the same time. HA
When STPCLK # = LOW in LT stop clock or register read stop clock, ISA
Break events are masked during HOLD due to refresh. (At this time, in the HOLD / HLDA processing, the gate array takes over and HOLD does not convey to the CPU.) The mask is released after the refresh, and the break event (INTR, NMI, SMI, INIT, SRESE) is released.
T) is accepted.

FIG. 9 is a timing chart showing the stop clock refresh timing. When the hold request signal (HDRQ) in FIG. 9D is output,
As shown in FIG. 6C, a signal (RFSTS) indicating that the hold request signal is due to active refresh is output. As a result, the stop clock signal (STPCLK #) shown in FIG. As a result, as shown in FIG.
Enters the stop grant state, and the ADS # signal indicating the start of the stop grant cycle is output as shown in FIG. In addition, as shown in FIG.
Even if LK # is asserted, the HOLD signal is not output to the CPU, and the hold acknowledge signal (CGHLDAZ) shown in (g) of the figure by the HOLD / HLDA shoulder substitute circuit is output.

As shown in FIG. 14, the HOLD / HLDA shoulder substitute circuit is assumed that the refresh control circuit issues a HOLD request to the HOLD / HLDA shoulder substitute circuit in response to the interrupt signal from the timer. At this time, if C
If it is assumed that the PU has just switched the clock, it takes 1 ms until the internal PLL stabilizes due to the specifications of the CPU, so the CPU does not operate during this period. On the other hand, since DRAM refresh must be performed every 15 μS, DRAM refresh cannot be performed. Therefore, the HOLD / HLDA shoulder replacement circuit is as if the CPU
Outputs the HLDA signal as if the HOLD request was accepted.

Then, a signal (RFMD3) indicating the refresh mode is output as shown in FIG. 9K, and the refresh cycle is executed. Figure 10 shows STPCLK #
6 is a timing chart showing a relationship between a stop clock refresh and an interrupt when an interrupt has already occurred when asserting.

Since the hold request signal (HDRQ) is output as shown in FIG. 7E and the interrupt request (INTR) is issued as shown in FIG.
K # is not asserted, and as shown in FIG.
The D signal is output to the CPU 1. The result, the figure (g)
As shown in, the CPU 1 is in the hold state and the normal refresh cycle is executed.

FIG. 11 shows S when the CPU is 80486.
9 is a timing chart showing timings of various signals when an interrupt occurs after asserting TPCLK #. A hold request signal (HDRQ) is output as shown in FIG. 11 (f), and a signal (RFSTS) indicating that the hold request signal is due to active refresh is output as shown in FIG. 11 (e).
As a result, when an interrupt factor occurs as shown in FIG. 3D, it is blocked and is not output to the CPU 1. During that time, the CPU 1 is in the stop grant state as shown in (h) of the figure, and the refresh cycle is executed as shown in (i) of the figure. Thereafter, it is not shown as shown in FIG. The block (blocking) of INTRO is released by the output of ADS #.

FIG. 12 is a timing chart showing the timing of various signals when an interrupt occurs after asserting STPCLK # when the CPU is the Pentium.

When the hold request signal (HDRQ) is generated as shown in FIG. 12 (f) and the active refresh signal (RFSTS) shown in FIG. 12 (e) is output, STPCLK # is output as shown in FIG. 12 (d). Is asserted.
After that, when the interrupt signal (INTR) shown in FIG. 9B is output, the ISA control gate array 11 does not block this signal and outputs it to the CPU 1 through as shown in FIG. Then, as shown in (h) of the figure, the CPU 1 enters the stop grant state, and as shown in (i) of the figure, a signal (R
FMD3) is output and the refresh cycle is executed.

FIG. 13 is a timing chart showing the relationship between the stop clock refresh and the HALT when the HALT comes. H when the CPU is Pentium
It is designed so that you cannot enter the stop grant from the ALT state. If a HALT cycle comes after asserting STPCLK #, the CPU remains in the HALT state. In 80486, there is no problem because a stop grant cycle occurs from the HALT state, but P
In the entium, the grant cycle does not occur unless the HALT state is exited. Since an interrupt (INTR, NMI, SMI #) is required to exit the HALT state, it is necessary to make an interrupt through even during the stop grant. When HALT comes after STPCLK # is asserted as shown in FIG. 13B, the CPU 1 stays in the HALT state as shown in FIG. And ISA
The control gate array 11 sends the HOLD signal shown in FIG.
Output to. The CPU 1 outputs a hold acknowledge signal (HLDA) as shown in (h) of FIG.
The refresh cycle is executed as shown in. After that, an interrupt signal (INTR) is generated as shown in (j) of the figure, and the CPU 1 exits the HALT state and enters the stop grant state as shown in (h) of the figure. When the CPU 1 completes the stop grant state cycle, as shown in FIG.
1 deasserts STPCLK #.

Stop clock arbitration circuit 41 shown in FIG.
The functions of are as follows.

SMI # request, INIT (SRESET)
Request, NMI request, INTR request, STPCLK request,
Arbitrate for HOLD requests. As a CPU, Pen
"P54 mode" when targeting the equivalent of titanium, S
For the case of L Enhanced 486 equivalent, refer to "E48
Control is distinguished by calling it "6 modes".

1. Priority (A> B indicates that A has a higher priority than B) The priority when a plurality of requests overlap is determined as follows.

SMI #> INIT (SRESET)> STPCLK # NMI, INTR> STPCLK # SMI, INIT (SRESET) and NMI, INT
There is no ranking among Rs.

There is no influence from the other. S
TPCLK # is generated by multiple factors. There are the following six factors.

1) Request by clock change 2) Clock stop request by I / O read 3) Stop grant request by I / O read 4) Clock stop request by HALT 5) Interval stop grant request 6) Refresh stop grant request These, Priorities are also determined for the six factors.

Clock change> I / O read clock stop> I / O read grant> HALT clock stop>
Interval Grant> Refresh Grant P54C
In the mode, the stop grant cycle does not occur from the HALT state state due to the CPU specifications.
Does not support clock stop itself. Clock change, I / O read clock stop, HALT clock stop, and STPCLK # request due to refresh grant arbitrate with HOLD request.

Clock change> I / O read clock stop> HALT clock stop> Refresh grant>
HOLD request It is not necessary to arbitrate between the stop grant request, the interval stop grant request and the HOLD request by the I / O read.

The control corresponding to the STPCLK # factor is ST
This is performed by controlling the 6 states of ATE1 to STATE6.

STATE1: A state in which the CPU can accept STPCLK #.

STATE2: ST due to any factor
PCLK # is asserted, but the stop grant cycle is incomplete.

STATE3: The state in which the stop grant cycle is completed. Actually, this state is brought about when the waiting time of several clocks at which STPCLK # can be deasserted is completed after the completion of the stop grant cycle. STA
There are also cases where it moves from TE3 to STATE6.

STATE4: Shoulder shoulder processing AND / OR
Assign to clock operation processing.

STATE5: Assigned to the STPCLK # deassertion process when a transition is made via STATE4.

STATE6: A state in which the precharge time from the deassertion of STPCLK # to the assertion of the next STPCLK # is maintained.

(I) Clock change Each STATE processing STATE1 ... Clock change request and other STPCL
K # request, SMI # request, INIT request, NMI / IN
There are no cancellation conditions for arbitration with TR requests, HOLD requests, and HALT. Assert STPCLK #.

STATE2 ... Another STPCLK # request,
SMI # request, INIT request, NMI / INTR request,
Block HOLD requests. If the occurrence of HALT is monitored and detected, SMI # request, INIT request, N
Release the block of MI / INTR request and HOLD request. STATE upon completion of the stop grant cycle
Move to 3.

STATE3 ... If HALT is not generated, the process proceeds to STATE4. If HALT has occurred, the request latch F / F is not cleared and STPCLK #
Deassert. (Clear only the synchronization F / F) S
TPCLK # deasserts to move to STATE6.

STATE4 ... Performs HLDA processing on behalf of the shoulder (enables CGHLDAZ).

Clock switching processing is performed. When the clock switching process is completed, the process moves to STATE5.

STATE 5 ... Shoulder HLDA processing is performed. When the HLDA for the shoulder is finished, the request latch F /
Clear F and sync F / F. When STPCLK # is deasserted, the process moves to STATE6.

STATE6 ... Clears detection of HALT. The block (blocking) of the SMI # request, the INIT request, the NMI / INTR request, and the HOLD request is released. ST
STATE1 when PCLK # precharge is completed
Move to. At the same time as moving to STATE1, another STPCLK
# The request is unblocked.

(II) I / O read clock stop Each S
TATE processing STATE1 ... I / O read clock stop request and other S
TPCLK # request, SMI # request, INIT request, NM
Arbitration with I / INTR request, HOLD request, and HALT. There are no cancellation conditions. Assert STPCLK #.

STATE2 ... Another STPCLK # request,
SMI # request, INIT request, NMI / INTR request,
Block HOLD requests. If the occurrence of HALT is monitored and detected, SMI # request, INIT request, N
Release the block of MI / INTR request and HOLD request. STATE upon completion of the stop grant cycle
Move to 3.

STATE3 ... If HALT has not occurred, the process proceeds to STATE4. If a HALT has occurred, the request latch F / F is not cleared and STPCLK #
Deassert. (Clear only the synchronization F / F) S
TPCLK # deasserts to move to STATE6.

STATE4 ... Performs HLDA start processing for shoulder replacement. Perform clock stop processing (enable CGHLDAZ). Watch for break events. Break event: SMI required, INIT (SRESE
T) Requested, NMI requested and NMISL = 1, I
4 conditions of NT request and INTSL = 1. When the break event is detected, the clock start processing is started.
When the clock starting process is completed, the process proceeds to STATE5.

STATE5: HLDA end processing for shoulder replacement is performed. If HLDA is finished on behalf of the shoulder, request latch F /
Clear F and sync F / F. When STPCLK # is deasserted, the process moves to STATE6.

STATE6 ... Clears detection of HALT. The blocks of SMI # request, INIT request, NMI / INTR request, and HOLD request are released. STPCLK
# When the precharge time is over, move to STATE. Simultaneously with the shift to STATE 1, the block of another STPCLK # request is released.

(III) I / O Lead Grant Each STA
TE processing STATE1 ... I / O read grant request and other STP
CLK # request, SMI request, INIT request, NMI / I
Arbitrate with NTR request. There are no cancellation conditions. S
Assert TPCLK #.

STATE2 ... Blocks other STPCLK # requests. Upon completion of the Stop Grant Cycle, move to STATE3.

STATE3 ... Monitors a break event. Break event: SMI # required, INIT
(SRESET) request, NMI request and NMI
4 conditions of SL = 1, INT request and INTSL = 1. If a break event is detected, request latch F
/ F and F / F for synchronization are cleared. When STPCLK # is deasserted, the process moves to STATE6.

STATE6 ... STPCLK # When the precharge time is over, the process moves to STATE1. STAT
Simultaneously with the shift to E1, the block of another STPCLK # request is released.

(IV) Interval Grant Each STA
TE processing STATE1 ... Interval grant request and other STP
CLK # request, SMI # request, INIT request, NMI /
Arbitration with INTR request. If you lose the mediation, cancel the interval grant request. (Clear the request latch F / F and the synchronization F / F). STPCLK
Assert #.

STATE2 ... Blocks another STPCLK # request. Upon completion of the Stop Grant Cycle, move to STATE3.

STATE3: Issues an interval break enable. Watch for break events. Break event ... SMI # requested, INIT (SRE
SET) request, NMI request, and NMISL =
Five conditions of 1, INT request, INTSL = 1, interval stop clock hold timeout. When a break event is detected, the request latch F / F and the synchronization F / F are cleared. When STPCLK # is deasserted, the process moves to STATE6.

STATE6 ... Cancels the interval break enable. When the STPCLK # precharge time is completed, the operation moves to STATE1. Simultaneously with the shift to STATE 1, the block of another STPCLK # request is released.

(V) Refresh Grant Each STAT
E processing STATE1 ... Refresh grant request and other STP
CLK # request, SMI # request, INIT request, NMI /
Performs INTR request and arbitration with HALT. If the arbitration is lost, the refresh grant request is canceled.
(Clear request latch F / F and synchronization F / F) ST
Assert PCLK #.

STATE2 ... Another STPCLK # request,
Block HOLD requests. The occurrence of HALT is monitored, and if detected, the block of the HOLD request is released. STATE upon completion of the Stopbrand cycle
Move to 3.

STATE3 ... If HALT has not occurred, the process proceeds to STATE4. If a HALT has occurred, the request latch F / F and the synchronization F / F are cleared. S
TPCLK # deasserts to move to STATE6.

STATE4 ... Performs HLDA start processing for shoulder replacement. (Enable CGHLDAZ). The break event is monitored (= HDRQ deassertion of refresh). If a break event is detected, ST
Move to ATE5.

STATE5 ... Shoulder HLDA end processing is performed. If HLDA is finished on behalf of the shoulder, request latch F /
Clear F and sync F / F. When STPCLK # is deasserted, the process moves to STATE6.

STATE6: Clears detection of HALT. Unblock the HOLD request. STPCLK
# When the precharge time is over, move to STATE1. Simultaneously with the shift to STATE 1, the block of another STPCLK # request is released.

[0102]

As described above, according to the present invention,
The power consumption of the computer system can be efficiently reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a computer system having an energy saving mode function using a stop clock function of the present invention.

2 is a circuit diagram showing a circuit provided in the ISA controller 11 shown in FIG. 1 for realizing an energy saving mode function using a stop clock function.

FIG. 3 is a timing chart showing basic timing of an interval stop clock.

FIG. 4 is a timing chart for explaining a snap mode.

FIG. 5 is a timing chart showing the timing when the interval stop clock is prohibited.

FIG. 6 shows that when the interval stop clock is operating, I
NTR, SMI, NMI, SRESET (INIT),
The figure which shows the process when there is a VRAM access.

FIG. 7 is a timing chart showing detailed timing of interval stop clock timing.

FIG. 8: Other break factors (INTR, NM
I, SMI, SRESET, INIT) is a timing chart showing the timing of the interval stop clock.

FIG. 9 is a timing chart showing stop clock refresh timing.

FIG. 10 is a timing chart showing the relationship between a stop clock refresh and an interrupt when an interrupt has already occurred when STPCLK # is asserted.

FIG. 11 is a timing chart showing a relationship between a stop clock refresh and an interrupt when an interrupt occurs after asserting STPCLK # when the 80486 is used as the CPU.

FIG. 12 is a timing chart showing a relationship between a stop clock refresh and an interrupt when an interrupt occurs after asserting STPCLK # when a Pentium is used as a CPU.

FIG. 13 is a timing chart showing the relationship between stop clock refresh and HALT when HALT comes when a Pentium is used as the CPU.

FIG. 14 is an explanatory diagram for explaining a HOLD / HLDA shoulder substitute circuit.

FIG. 15 is a diagram showing an example of a circuit for apparently delaying the operating speed of the CPU by prolonging the refresh cycle.

FIG. 16 is a conceptual diagram for explaining the extension of the HOLD signal when the operation speed of the CPU is apparently delayed by extending the refresh cycle.

[Explanation of symbols]

1 ... CPU, 3 ... CPU control gate array, 5
... CPU bus, 7 ... Main DRAM, 9 ... VL bus, 1
1 ... ISA control gate array, 13 ... extended DR
AM, 15 ... VGA controller, 17 ... Interval stop clock request counter, 19 ... Interval stop clock enable register, 21 ... Comparison circuit, 23 ... Interval stop clock signal hold period counter, 25 ... Interval stop clock hold register, 27 ... AND gate, 29 ...
Comparing circuit, 31 ... Inhibit timer, 33 ... Snap mode counter, 37 ... Snap mode comparing circuit,
41 ... Arbitration circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Koichi Senuma             Toshiba, 3-3-3 Shinmachi, Ome-shi, Tokyo             Digital Media Engineering Stock Association             In-house (72) Inventor Takeyuki Iguchi             Toshiba, 3-3-3 Shinmachi, Ome-shi, Tokyo             Digital Media Engineering Stock Association             In-house F-term (reference) 5B079 BA06 BA11 BB04 BC01

Claims (15)

[Claims] 1. A CPU capable of receiving an instruction signal indicating an instruction to stop an internal clock and an interrupt signal indicating an instruction for interrupt processing, a means for asserting the instruction signal to the CPU, and a system event when the system event occurs. Interrupt means for generating an interrupt signal, and when the interrupt signal is generated by the interrupt means while the instruction signal is asserted to the CPU,
A means for holding the interrupt signal, and asserting the interrupt signal to the CPU after the assertion of the instruction signal is released, the computer system comprising: 2. A CPU that shifts to a power-saving state in response to receiving an instruction signal indicating an instruction to stop the internal clock, a unit that asserts the instruction signal to the CPU, and an interrupt signal when a system event occurs. And an interrupt signal generated by the interrupt means while the CPU is in the power saving state, the interrupt signal is held and the interrupt signal is output after the power saving state is released. A means for asserting to the CPU, and a computer system. 3. The stop signal (STPC
LK) signal. 3. The computer system according to claim 1, wherein the computer system is a LK) signal. 4. The computer system according to claim 3, wherein input of the stop clock signal is prohibited for a predetermined time after asserting the interrupt signal to the CPU. 5. The timer according to claim 4, further comprising timer means for counting a time during which the assertion of the stop clock signal is prohibited in response to the deassertion of the stop clock signal. Computer system. 6. A CPU capable of receiving a signal indicating an instruction to stop the internal clock, means for asserting the signal to the CPU, and interrupt means capable of generating a system event for causing the CPU to perform processing. If a system event is generated by the interrupt means while the signal is asserted to the CPU,
A computer system, comprising: holding means for holding the system event and not notifying the CPU. 7. An operation control method for a computer system comprising a CPU capable of receiving an instruction signal indicating an instruction to stop an internal clock and an interrupt signal indicating an instruction for interrupt processing, wherein the instruction signal is asserted to the CPU, When an event occurs, the interrupt signal is generated, and when the interrupt signal occurs while the instruction signal is asserted to the CPU, the interrupt signal is held and the instruction signal is deasserted. An operation control method characterized by asserting the interrupt signal to the CPU later. 8. A method of controlling the operation of a computer system comprising a CPU that shifts to a power saving state based on reception of a signal indicating an instruction to stop the internal clock, wherein the signal is asserted to the CPU, and a system event occurs. In this case, an interrupt signal indicating an instruction for interrupt processing is generated to the CPU, and when the interrupt signal is generated while the CPU is in the power saving state, the interrupt signal is held and the CPU is released from the power saving state. And then asserting the interrupt signal to the CPU. 9. A computer system comprising a CPU that receives a stop clock signal for stopping an internal clock of the CPU, wherein a stock clock signal for asserting the stock clock signal for causing the CPU to enter a stock grant state in which the CPU is set to a low power state is asserted. A computer for executing a refresh cycle when the CPU is in a stop grant state, and a means for designating whether or not to execute a refresh cycle when the CPU is in a stop grant state. system. 10. When the CPU is designated to execute a refresh cycle while in the stop grant state, the CP is transmitted without transmitting a HOLD request to the CPU.
10. The computer system according to claim 9, further comprising means for issuing a HOLD acknowledge signal (HLDA) instead of U. 11. The computer system according to claim 9, further comprising means for switching a cycle length of the refresh cycle. 12. A computer system comprising a CPU that receives a stop clock signal for stopping the internal clock of the CPU, wherein the stock clock signal is asserted for a certain period of time to reduce the operating speed of the CPU and save power consumption. Means for outputting a HOLD signal to the CPU without asserting a stop clock if an interrupt has already been generated when the stop clock signal is asserted,
A computer system in which the CPU is set to a hold state and executes a refresh cycle. 13. A computer system comprising a CPU that receives a stop clock signal for stopping the internal clock of the CPU, wherein the stock clock signal is asserted for a certain period of time to reduce the operating speed of the CPU and save power consumption. And an interrupt is generated after the stop clock signal is asserted, the interrupt is prohibited from being generated to the CPU, the CPU is set to a stop grant state set to a low power state, and refreshed. A computer system comprising means for performing a cycle. 14. A computer system comprising a CPU that receives a stop clock signal for stopping an internal clock of the CPU, wherein the stock clock signal is asserted for a certain period of time to reduce the operating speed of the CPU and save power consumption. And an interrupt is generated after the stop clock signal is asserted, the interrupt is passed to the CPU,
A computer system comprising: means for setting the CPU to a stop grant state set to a low power state and executing a refresh cycle. 15. A computer system comprising a CPU that receives a stop clock signal for stopping the internal clock of the CPU, wherein the stock clock signal is asserted for a certain period of time to reduce the operating speed of the CPU and save power consumption. And HAL after the stop clock signal is asserted
A T signal is generated, means for setting the CPU to a HALT state, means for outputting a HOLD signal to the CPU during assertion of the stop clock signal, and causing the CPU to execute a refresh cycle, and a refresh cycle A means for issuing an interrupt signal to the CPU to set the CPU to a stock grant state in which the CPU is set to a low power state, and causing the CPU to execute a stop grant cycle when the CPU is in the stock grant state; A computer system having means for deasserting the stock clock signal after the CPU completes the stock grant cycle.