JP2003264458A - Superconducting single magnetic flux quantum multi- input exclusive or circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a superconducting single magnetic flux quantum multi-input exclusive OR circuit which can be operated at high speed without increasing the number of logic stages. <P>SOLUTION: In the conventional superconducting single magnetic flux quantum two input exclusive OR circuit having a function that performs arithmetic operations of exclusive OR to a first input signal and a second input signal and outputs the result to an output end, it is constituted so that it has functions that perform arithmetic operations of exclusive OR to the first, second and third input signals and output the results on the output end by further providing an input circuit for inputting at least one or more third input signals in addition to the first and second input signals and providing the input circuit with a function that delays the phase of the third input signal to the phases of the first and second input signals in a desired time. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a basic gate of a superconducting integrated circuit which operates at a cryogenic temperature, and more specifically, performs an exclusive OR operation on at least three or more input signals. The present invention relates to a superconducting single-flux quantum multi-input exclusive OR circuit.

[0002]

2. Description of the Related Art A multi-input exclusive OR circuit is used, for example, as a basic gate of a full adder which is a basic constituent element of a digital signal processing circuit. More specifically, the full adder is a circuit that generally adds two binary numbers (addend and augend), but the input signal is a signal of the same digit as the addend and augend. It is necessary to calculate the three input signals of the carry signal from the lower digit.

Therefore, the full adder is a circuit (SUM circuit) for calculating the same digit of the addend and the augend from these three signals.
And a circuit that generates a carry signal to the upper digit (CARRY
Circuit) and. The SUM circuit has three signals (addend signal, addend signal, carry signal from lower digits).
It is sufficient to calculate the exclusive OR of

Conventionally, a single flux quantum (also referred to as SFQ) that takes an exclusive OR of two input signals
Superconducting circuit using the (Reference: IEEE Trans. On Applied
Superconductivity. Vol. 1, p. 10, March 1991 Fi
Although g.13) is well known, there was no circuit that takes the exclusive OR of three or more input signals at once. Therefore, a method is known in which the two-input exclusive-OR circuits are combined in multiple stages to perform a logical operation of a multiple-input exclusive-OR.

As an example, FIG. 7 shows a block diagram of a three-input exclusive OR circuit according to this conventional technique, and FIG.
The block diagram of the exclusive OR circuit of 5 inputs is shown in FIG.
These multi-input exclusive OR circuits are configured with a 2-input exclusive OR circuit (2XOR) as a basic block. Therefore, in order to explain the operation of these multi-input exclusive OR circuits, the operation of the basic block, the 2-input exclusive OR circuit (2XOR), will be described first.

FIG. 9 shows an equivalent circuit diagram of a conventional superconducting single-flux-quantum 2-input exclusive OR circuit. Further, FIG. 10 shows a truth table in which the logical states of the inputs and outputs of the exclusive OR of the two inputs are described.

This circuit includes a plurality of Josephson junctions (J1A, J2A, J1B, J2B, J3, J4, J).
5) Two inductances (L1A, L1B), a signal input end (InA, InB), a signal output end (OUT), and a DC bias input end (Ib1, Ib2). As shown in the truth table of FIG. 10, when the input signal of only one is “1”, the exclusive OR of two inputs becomes “1”, and both input signals are “0” or When it is "1", the output signal is "0".

In order to realize this logical operation, this circuit uses two superconducting loops (J1A, J2A, L1A, J3, and J4) capable of holding a single magnetic flux quantum and J1B, J2B, and L1B. , J3, J4 superconducting loop 2) are combined,
Only one of the two superconducting loops holds a single flux quantum, but both superconducting loops have two
The single flux quanta are designed not to be retained.

Therefore, when the SFQ pulse is input to only one of the signal input terminals InA or InB, the single flux quantum is held in the superconducting loop on the input side, and the Josephson junction J4 is biased. The state (a single magnetic flux quantum is held, a permanent current flows in the superconducting loop, and this permanent current flows in the Josephson junction J4, which is a part of the superconducting loop). Therefore, when the clock signal (Clock) is input thereafter, the Josephson junction J4 causes the magnetic flux quantum transfer to generate the SFQ pulse at the output end.

S is applied to both the signal input terminals InA and InB.
If the FQ pulse is not input, the single flux quantum is not held in the superconducting loop, so that the Josephson junction J4 is not biased. Therefore, even if a clock signal is subsequently input, the Josephson junction J4 does not undergo the flux quantum transition and the SFQ pulse is not generated at the output end.

SFQ is applied to both the signal input terminals InA and InB.
When a pulse is input, a single magnetic flux quantum is first held in one superconducting loop and a persistent current flows in the superconducting loop. Try to hold the magnetic flux quantum. However, at this time, since the superconducting current has already flowed due to the first SFQ pulse, the currents are added and flow into the Josephson junction J3, and the Josephson junction J3 undergoes the flux quantum transition and is held in the superconducting loop. Eliminate one magnetic flux quantum. Therefore, since the Josephson junction J4 is not in the bias state, even if a clock pulse is input thereafter, the magnetic flux quantum transfer does not occur and the SFQ pulse is not generated at the output end.

With the above operation, it is possible to perform the exclusive OR operation of two inputs as shown in the truth table of FIG.

Next, referring again to FIGS. 7 and 8, the operation of the superconducting single-flux quantum multi-input exclusive OR circuit will be briefly described. As for the 3-input exclusive OR, the 2-input exclusive OR circuit is connected in two stages as shown in FIG.
The exclusive OR of nA and the input signal InB is calculated by the 2-input exclusive OR circuit (2XOR1), and the exclusive OR of the output signal and the input signal InC is calculated by the 2-input exclusive OR circuit (2XOR2). It can be obtained by calculation.

As for the exclusive OR of 5 inputs, an exclusive OR circuit of 2 inputs is connected in 4 stages as shown in FIG. 8, and first, an exclusive OR of the input signal InA and the input signal InB is exclusive by 2 inputs. Is calculated by the logical OR circuit (2XOR1), the exclusive OR of the output signal and the input signal InC is calculated by the 2-input exclusive OR circuit (2XOR2), and the output signal and the input signal I are calculated.
2D exclusive OR circuit (2X
OR3), and the exclusive OR of the output signal and the input signal InE is 2-input exclusive OR circuit (2XOR4).
It can be obtained by calculating with.

As described above, a multi-input superconducting single-flux-quantum exclusive-OR circuit can be constructed by connecting two-input exclusive-OR circuits in multiple stages according to the number of input signals. .

[0016]

However, the conventional superconducting single-flux-quantum multi-input exclusive OR circuit described above has the following problems. That is, since two-input exclusive-OR circuits are connected in multiple stages in order to form a multi-input exclusive-OR circuit, the number of logical stages increases and high-speed operation as a whole is difficult.

Further, it is necessary to supply a clock signal to each stage of the 2-input exclusive OR circuit, which causes a problem that the number of clock input signals increases in accordance with the number of input signals.

Further, since the two-input exclusive OR circuits are connected in multiple stages, there is a problem that the circuit scale becomes large and power consumption also increases.

[0019]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an exclusive OR circuit which solves the problems of the prior art. That is, an object of the present invention is to provide a superconducting single-flux-quantum multi-input exclusive OR circuit that can operate at high speed without increasing the number of logic stages.

In order to achieve the above object, the present invention provides:
It has a first signal input end, a second signal input end and a signal output end, is composed of a plurality of Josephson junctions and a plurality of inductances, and is input to the first and second signal input ends, respectively. A conventional superconducting single-flux-quantum exclusive OR having a function of performing an exclusive OR operation on the first input signal and the second input signal, and outputting the result to the signal output terminal. The circuit further comprises an input circuit for inputting at least one or more third input signals in addition to the first and second input signals, the input circuit including the first and second input signals. By having a function of delaying the phase of the third input signal by a desired time with respect to the phase of the input signal, an exclusive OR operation is performed on the first, second and third input signals. , Has a function of outputting the result to the output terminal Was Unishi.

Here, the delay function of the input circuit can be realized by using a signal propagation delay of a Josephson transmission line composed of a Josephson junction and an inductance.

Alternatively, the delay function of the input circuit can be realized by using the signal propagation delay of the microstrip line.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION First, the operation when a three-input exclusive OR circuit is constructed by the conventional technique will be described.

The prior art two-input exclusive OR circuit shown in FIG. 9 can operate normally even if SFQ pulses are inputted to the two signal input terminals with a time difference or simultaneously. Is. In the above description of the conventional technique,
The case where the SFQ pulses are sequentially input to the two signal input terminals with a time difference has been described.

In this case, the first SFQ pulse is transmitted from the signal input terminal InA to the superconducting loop 1 (J1A, J2A, L1).
A single magnetic flux quantum is first retained in the superconducting loop 1 by being input to the loop composed of A, J3, and J4). After that, the second SFQ pulse is transmitted from the signal input terminal InB to the superconducting loop 2 (J1B, J2B, L1B, J3, J).
4), the Josephson junction J3 undergoes a flux quantum transition, so that the single flux quantum held in the superconducting loop is eliminated. By this series of operations, the quantum state of the superconducting loop returns to the initial state (state “0”) (reset).

On the other hand, when the SFQ pulse is simultaneously input to the two signal input terminals, the quantum state of the superconducting loop is in the initial state (state "0") only by the magnetic flux quantum transition of the Josephson junction J3 from the beginning. It doesn't change. In both cases, the final quantum states are the same. Therefore, in the case of two inputs, the order in which SFQ pulses are input did not matter.

However, if the conventional 2-input exclusive-OR circuit is simply made to have 3 inputs, a normal logical operation of 3-input exclusive-OR cannot be performed. This is because the final quantum state of the superconducting loop is different when the three SFQ pulses are sequentially input and at the same time. When three SFQ pulses are sequentially input, the quantum state of the superconducting loop changes from the initial state (“0”) to the “1” state by the input of the first SFQ pulse, and the quantum state of the second SFQ pulse The "1" state is reset to the "0" state by the input, and the "0" state is changed to the "1" state again by the input of the third SFQ pulse. Therefore, when the clock signal is input thereafter, the SFQ pulse is generated at the output end. The result of this calculation is normal.

On the other hand, when three SFQ pulses are simultaneously input, the Josephson junction J3 only undergoes magnetic flux quantum transition from the beginning, and the quantum state of the superconducting loop changes in the initial state (state "0"). do not do. The calculation result in this case is not normal. Alternatively, when one SFQ pulse is input and the remaining two SFQ pulses are input at the same time, the quantum state of the superconducting loop is initially in the initial state (“0”) due to the input of the first SFQ pulse. To the "1" state, and then the second and third SFQ pulses are simultaneously input to reset the "1" state to the "0" state. Also in this case, the final state of the superconducting loop becomes the "0" state, which is different from the final quantum state ("1" state) when three SFQ pulses are sequentially input, resulting in malfunction.

Therefore, a feature of the invention is a means for ensuring that at least one or more third input signals are input to the superconducting loop with a desired time difference with respect to the first and second input signals. Is in the point of having. As a result, it is possible to execute the exclusive OR operation of at least three or more input signals in one clock at a time.

Next, regarding the first embodiment of the present invention,
Description will be made with reference to FIGS. 1 to 3.

FIG. 1 is an equivalent circuit diagram of a 3-input exclusive OR circuit showing a first embodiment of a superconducting single-flux-quantum multi-input exclusive OR circuit of the present invention. FIG. 2 is a truth table of the superconducting 3-input exclusive OR circuit.

First, the structure and function of this circuit will be described. This circuit consists of multiple Josephson junctions (J1A, J1
2A, J1B, J2B, J3, J4, J5), two inductances (L1A, L1B), signal input end (In
A, InB), a signal output terminal (OUT), and a DC bias input terminal (Ib1, Ib2), in addition to the structure of the conventional 2-input exclusive OR circuit, a third signal input terminal (InC). ) And Josephson junction (J1C, J2C, Jd
1, Jd2) and inductance (L1C, Ld1, Ld
2) and DC bias input terminals (Ib3, Ib4, Ib)
5) is connected. Josephson junction (Jd1, Jd2) and inductance (Ld1, Ld
2) and the DC bias input terminals (Ib4, Ib5) are used for the Josephson transmission line (JTL), the signal input to the signal input terminal (InC) is transferred to another signal input terminal (InC).
A, InB) has a function of delaying a signal input thereto by a desired time.

In the exclusive OR of three inputs, as shown in the truth table of FIG. 2, when the number of input signals being "1" is odd, the output becomes "1", and the input signal becomes When the number of "1" is zero or even, the output is "0". In other words, three signal input terminals (InA, InB, In
When a "1" signal is input to any one of C),
When the "1" signal is input to all three, the output is "
When the three input signals are "0" or only the two input signals are "1", the output signal is "0".

In order to realize this logical operation, in this circuit, three superconducting loops (superconducting loop 1 consisting of J1A, J2A, L1A, J3, J4 and J1B, J2B, L1B) capable of holding a single flux quantum are used. , J3, J4 superconducting loop 2, J1C, J2C, L1C, J3, J
The superconducting loop 3) composed of 4 is combined, and only one of the three superconducting loops holds a single magnetic flux quantum. The single flux quantum is designed not to be retained.

In addition, the input circuit having the delay function, which is a feature of the present invention, is composed of the Josephson transmission line (JTL), and the third input circuit is input to the signal input terminal (InC).
Is input to the superconducting loop 3 with a delay of the propagation delay time of the Josephson transmission line (JTL).

FIG. 3 shows the superconducting single magnetic flux quantum 3 of this embodiment.
The schematic of the operation waveform of an input exclusive OR circuit is shown. The operation of this circuit will be described based on this operation waveform. In the figure, the input signal, the clock signal (Clock), and the output signal (OUT) input to the signal input ends InA, InB, and InC are shown from the top. The horizontal axis is the time axis. This circuit is a circuit that performs a logical operation with an SFQ pulse, and an input signal, a clock signal, and an output signal are all SFQ pulses. In the SFQ pulse logic circuit,
A state in which the SFQ pulse is input between clock pulses is a signal "1" state, and a state in which no SFQ pulse is input between clock pulses is a signal "0" state.

The SFQ pulse of each input signal is shown at the timing when the input signal is input to the corresponding superconducting loop.

The input signal pattern corresponds to the truth table of FIG. 2, and the eight logic states of the truth table ((1)
(8)) to (8)). The quantum state of the superconducting loop changes according to the input signal input during the clock pulse, and at the time when the clock pulse is input, the output terminal (OU) is output according to the quantum state of the superconducting loop at that time.
An SFQ pulse is generated at T). At the same time, the quantum state of the superconducting loop is reset to the initial state "0". In other words, an output pulse is generated after the clock signal is input, corresponding to the input signal pattern before the clock pulse is input. That is, the output signal is generated with a delay of one clock.

Three signal input terminals (InA, InB, In)
When there are two or less "1" states of the input signal input to C), the operation is almost the same as that described in the prior art. Therefore, here, the input signals are all in the "1" state in FIG. The operation in the case of the logic state (8) will be described. In addition, the three input signals are assumed to be input to the respective signal input terminals almost at the same time.

When the first SFQ pulse and the second SFQ pulse are simultaneously input to the corresponding superconducting loops 1 and 2 at the two signal input terminals InA and InB, respectively, the Josephson junction J3 is magnetic flux quantum from the beginning. Only the transition occurs, and the quantum state of the superconducting loop remains the initial state (state "0"). Therefore, Josephson junction J4 is not biased.

After that, Josephson transmission line (JTL)
When the third SFQ pulse delayed by the propagation delay time is input to the corresponding superconducting loop 3, the superconducting loop 3
The single flux quantum is held at and the Josephson junction J4 is biased again. Therefore, when a clock pulse is input thereafter, the Josephson junction J4 undergoes magnetic flux quantum transition, and an SFQ pulse is generated at the output end.

Here, the first SFQ pulse and the second SFQ pulse
Although the SFQ pulse of 1 is input to the corresponding superconducting loop at the same time, the second SFQ pulse may be input after the first SFQ pulse. In this case, in order for the operation to be performed normally, the single flux quantum is first retained in the superconducting loop by the input of the first SFQ pulse, and the superconductivity is then input by the input of the second SFQ pulse. After the quantum state of the loop is reset, the third SFQ
A pulse needs to be input.

Because if the second SFQ pulse and the third SFQ pulse
This is because, when the SFQ pulse of 1 is input to the superconducting loop at the same time, the single magnetic flux quantum retained in the superconducting loop is eliminated by the first SFQ pulse at this time. Therefore, the Josephson junction J4 is not biased, so that even if a clock signal is subsequently input, the Josephson junction J4 does not undergo the flux quantum transition and the SFQ pulse is not generated at the output end. This operation is a malfunction.

Therefore, after the second SFQ pulse is input to the superconducting loop (first SFQ pulse and second SFQ pulse).
When the pulses are input simultaneously, after the input), the normal operation is not performed unless the third SFQ pulse is input to the superconducting loop with a desired delay. More specifically, the third SFQ pulse needs to be input to the superconducting loop 3 with a delay of time t _{0 in} FIG. Time t ₀ is
It is the time required for the second SFQ pulse to be input to the superconducting loop 2 and to reset the quantum state of the superconducting loop. The Josephson transmission line of the present embodiment has a function of sending the time when the third SFQ pulse is input to the superconducting loop for this time t ₀ . With the above operation, Table 1
It is possible to perform an exclusive OR operation of three inputs as shown in the truth table of.

Further, in FIG. 1, concrete circuit constants can be set as follows, for example.

J1A = 0.0926 mA, J1B = 0.0926 mA, J1
C = 0.0926 mA, J2A = 0.0824 mA, J2B = 0.0824 m
A, J2C = 0.0824 mA, J3 = 0.0848 mA, J4 = 0.0781
mA, J5 = 1.123 mA, L1A = 6.5 pH, L1B = 6.5 pH, L
1C = 6.5 pH, Jd1 = Jd2 = 0.1mA, Ld1 = Ld2 = 10p
H.

Here, each Josephson junction is set to operate in an overdamping state with a Mackamba constant β = 1. Also, the critical current density 2500A
In a circuit simulation assuming a Nb / AlOx / Nb junction of / cm ² , it was confirmed that it is sufficient to set a time difference of about 5 picoseconds as t0. This value greatly depends on circuit constants such as junction characteristics.

In the present embodiment, the three input signals input to the three signal input terminals (InA, InB, InC) are the signals in the preceding stage of the present three-input exclusive OR circuit. It is supposed to occur at about the same time. S
Since the FQ circuit is generally used like a micropipeline, such an assumption is valid.

Further, in this embodiment, a JTL (Josephson junction Jd1 and inductance Ld) having a two-stage structure as a Josephson transmission line (JTL) for realizing the delay function is used.
1, Josephson junction Jd2 and inductance Ld2)
However, depending on the size of the desired delay time t ₀ ,
The same effect can be obtained even if it is configured in one or multiple stages. The delay time can also be adjusted by the value of the bias current (Ib4, Ib5) of the Josephson transmission line.

In the following embodiments, the delay circuits for delaying the third and subsequent SFQ pulses are shown, but if it is possible to delay by the time t _0, it is not necessary to limit to this. Absent.

As described above, the superconducting single-flux-quantum 3-input exclusive OR circuit of the present embodiment delays and inputs the third input signal to obtain the exclusive OR of 3 inputs. The operation can be realized by one clock operation. As a result, the number of elements can be reduced as compared with the conventional technique at the same time as the speed is increased, so that the circuit size can be reduced and the power consumption can be reduced.

Next, with reference to FIG. 4, a superconducting single-flux-quantum multi-input exclusive-OR circuit according to a second embodiment of the present invention will be described.

FIG. 4 is an equivalent circuit diagram of a three-input exclusive OR circuit showing the second embodiment. The configuration of this circuit is, in the first embodiment, a Josephson transmission line (JTL) which plays a role of delaying the third input signal in time.
Is replaced with a microstrip line.

The microstrip line is set to have a characteristic impedance of an appropriate value so as to match the impedance with the Josephson junctions at the front and rear. Therefore, the delay time t ₀ is determined by the signal propagation time of the microstrip line and is proportional to the length of the microstrip line. The desired delay time can be realized by adjusting the length of the microstrip line.

The operation of the circuit of this embodiment is the same as that of the first embodiment. Therefore, the same effect as that of the first embodiment can be obtained. Further, unlike the Josephson transmission line, a Josephson junction is not used for the delay means, so that the number of elements can be further reduced and the power consumption can be reduced as compared with the first embodiment.

Next, a superconducting single-flux-quantum multi-input exclusive-OR circuit according to the third embodiment of the present invention will be described with reference to FIGS.

FIG. 5 is an equivalent circuit diagram of a 5-input exclusive OR circuit showing the third embodiment. FIG. 6 shows a truth table of this superconducting 5-input exclusive OR circuit.

First, the structure and function of this circuit will be described. This circuit consists of multiple Josephson junctions (J1A, J1
2A, J1B, J2B, J3, J4, J5), two inductances (L1A, L1B), signal input end (In
A, InB), a signal output terminal (OUT), and a DC bias input terminal (Ib1, Ib2), in addition to the structure of the conventional 2-input exclusive OR circuit, a third signal input terminal (InC). ), A delay circuit (Delay1), a Josephson junction (J1C, J2C), an inductance (L1C) and a DC bias input end (Ib3), a fourth signal input end (InD), a delay circuit (Delay2), and a Josephson junction (Delay2). J1D, J2D), inductance (L1D), DC bias input terminal (Ib4), fifth signal input terminal (InE), delay circuit (Delay3), Josephson junction (J1E, J2E), inductance (L1E), and DC bias. The input terminal (Ib5) is connected.

Delay circuits (Delay1, Delay2,
Delay 3) is shown here as a box, but specifically, the Josephson transmission line (JTL) shown in the first embodiment or the microstrip line shown in the second embodiment can be used. . of course,
As described above, the present invention can be configured using other delay circuits.

Each delay circuit (Delay1, Delay)
2, the delay time 3) is set to be different from each other by the time t ₀ described in the first embodiment. Further, in the present embodiment, each signal input terminal (InA, InB, InC, InD,) is provided as a circuit in the preceding stage which generates five input signals to the five-input exclusive OR circuit.
A superconducting single magnetic flux quantum RS flip-flop circuit (RS-FF) is connected before InE). The superconducting single-flux-quantum RS flip-flop circuit is a well-known circuit and has been published in the IEEE Trans.
conductivity. Vol.1, p. 7, March 1991, Fig.7).

As shown in the truth table of FIG. 6, the exclusive OR of the five inputs is such that when the number of input signals is "1", the output is "1" when the number is odd, and the input signal is When the number of "1" is zero or even, the output is "0". In order to realize this logical operation, this circuit uses five superconducting loops (J1A, J2) capable of holding a single magnetic flux quantum.
Superconducting loop 1 and J1 consisting of A, L1A, J3, and J4
B, J2B, L1B, J3, J4 superconducting loop 2, J1C, J2C, L1C, J3, J4 superconducting loop 3, J1D, J2D, L1D, J3, J4 superconducting loop 4, J1E, J2E, L1E, J3,
The superconducting loop 5) composed of J4 is combined, and only one of the five superconducting loops holds a single magnetic flux quantum, but the five superconducting loops have the same structure. The single flux quantum is designed not to be retained.

In addition, the delay circuits (Delay1, Delay2, Delay3), which are the features of this embodiment, can delay the signals input to the superconducting loop by different times. This makes it possible to delay the third input signal, the fourth input signal, and the fifth input signal in order.

Five signal input terminals (InA, InB, In
When the input signal input to C, InD, InE) has three or less “1” states, the operation is almost the same as that described in the related art and the first embodiment. The operation when all the input signals are in the "1" state (state shown in the bottom row of the truth table of FIG. 6) will be described.

First, when an SFQ pulse is input to the signal input terminal InA, a single magnetic flux quantum is held in the superconducting loop 1 and the Josephson junction J4 is biased (the single magnetic flux quantum is held). As a result, a permanent current flows in the superconducting loop, and this permanent current flows in the Josephson junction J4 which is a part of the superconducting loop.)
become.

After that, the SFQ pulse is input to the signal input terminal InB, and the superconducting loop 2 tries to hold the single magnetic flux quantum. However, at this time, since the superconducting current has already flowed due to the first SFQ pulse, the currents are added and flow into the Josephson junction J3, and the Josephson junction J3 undergoes the flux quantum transition and is held in the superconducting loop. By eliminating one magnetic flux quantum, the superconducting loop is reset to the initial state (“0” state). Therefore, the Josephson junction J4 is no longer in the biased state.

Here, the InA and InB SFQ pulses may be simultaneously input to the corresponding superconducting loops.

After that, when the third SFQ pulse is input, the single flux quantum is held in the superconducting loop 3, and the Josephson junction J4 is biased again. After that, the SFQ pulse is input to the signal input terminal InD, and the superconducting loop 4 tries to hold the single magnetic flux quantum. However, at this time, since the superconducting current is already flowing due to the third SFQ pulse, the currents are added up and the Josephson junction J
3, the Josephson junction J3 is subjected to magnetic flux quantum transition and eliminates the single magnetic flux quantum held in the superconducting loop, thereby resetting the superconducting loop to the initial state (“0” state). Therefore, the Josephson junction J4 is no longer in the biased state.

After that, when the fifth SFQ pulse is input, the single flux quantum is held in the superconducting loop 5, and the Josephson junction J4 is biased again. for that reason,
Then, when a clock pulse is input, the Josephson junction J4 undergoes magnetic flux quantum transition to generate an SFQ pulse at the output end.

In order for the above-described series of operations to be performed normally, each time a SFQ pulse is input, a single magnetic flux quantum is held (set) in any one of the five superconducting loops, and the next SFQ is generated. The single flux quantum held by the input of the pulse is removed from the superconducting loop and reset to the initial state. After that, it is necessary to normally repeat setting and resetting according to the number of SFQ pulse inputs. This condition is
This is satisfied by setting the third to fifth input signals to be input to the superconducting loop at different times. The time difference between the signals may be set to be different from each other by the time difference t0 described in the first embodiment (at the time t0, the SFQ pulse is input to one of the superconducting loops and becomes “1”). It is the time required to reset the quantum state of the superconducting loop that was in the state).

By the above operation, the 5-input exclusive OR operation as shown in the truth table of FIG. 6 can be performed. In this way, by setting desired delays for the third to fifth input signals, the superconducting single-flux-quantum 5-input exclusive-OR operation that operates as a whole with one clock (one logical stage) A circuit can be realized.

Further, in FIG. 5, specific circuit constants can be set as follows, for example.

J1A = J1B = J1C = J1D = J1E = 0.0926 m
A, J2A = J2B = J2C = J2D = J2E = 0.0824 mA, J3 = 0.
0848 mA, J4 = 0.0781 mA, J5 = 1.123 mA, L1A = L1B
= L1C = L1D = L1E = 6.5 pH.

Here, each Josephson junction is set to operate in the overdamping state with the Mackamba constant β = 1.

In this embodiment, the five input signals input to the five signal input terminals (InA, InB, InC, InD, InE) are the superconducting single-flux-quantum RS flip-flops of the preceding stage. It occurs at almost the same time in the circuit (RS-FF). That is, when a clock signal is input to the five RS flip-flop circuits, SFs are almost simultaneously generated according to the internal state (quantum state) of the RS flip-flops.
The Q pulse is output.

As described above, the effect that the superconducting single-flux-quantum 5-input exclusive-OR circuit of the present embodiment can realize the 5-input exclusive-OR operation in one clock operation. is there. As a result, the number of elements can be reduced as compared with the conventional technique at the same time as the speed is increased, so that the circuit size can be reduced and the power consumption can be reduced.

In this embodiment, the superconducting single-flux-quantum five-input exclusive OR circuit for five input signals is constructed, but more input signals are added in the same manner as in this embodiment. By inputting an input signal with a delay, a superconducting single-flux-quantum multi-input exclusive OR circuit having the same effect can be realized.

[0077]

As described above, according to the present invention, a superconducting single-flux-quantum multi-input exclusive-OR circuit that can operate at high speed with one clock can be realized. The superconducting single-flux-quantum multi-input exclusive-OR circuit of the present invention, even if the number of input signals increases,
Since it is not necessary to have a multi-stage configuration unlike the multi-input exclusive OR circuit of the conventional technique, there is an effect that the circuit size can be reduced and the power consumption can be reduced. Further, by using the superconducting single-flux-quantum 3-input exclusive OR circuit of the present invention, there is an effect that a full adder, which is a basic block of a digital signal processing circuit, can be easily configured.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram for explaining a first embodiment of a superconducting single-flux-quantum multi-input exclusive OR circuit of the present invention.

FIG. 2 is a truth table for explaining the first embodiment of the superconducting single-flux-quantum multi-input exclusive OR circuit of the present invention.

FIG. 3 is a schematic view of operating waveforms for explaining the operation of the first embodiment of the superconducting single-flux-quantum multi-input exclusive OR circuit of the present invention.

FIG. 4 is an equivalent circuit diagram for explaining a second embodiment of a superconducting single-flux-quantum multi-input exclusive OR circuit of the present invention.

FIG. 5 is an equivalent circuit diagram for explaining a third embodiment of a superconducting single-flux-quantum multi-input exclusive OR circuit of the present invention.

FIG. 6 is a truth table for explaining a third embodiment of the superconducting single-flux-quantum multi-input exclusive OR circuit of the present invention.

FIG. 7 is a block diagram for explaining a conventional superconducting single-flux-quantum 3-input exclusive OR circuit.

FIG. 8 is a block diagram illustrating a conventional superconducting single-flux-quantum 5-input exclusive OR circuit.

FIG. 9 is an equivalent circuit diagram for explaining a conventional superconducting single-flux-quantum two-input exclusive OR circuit.

FIG. 10 is a truth table for explaining a conventional superconducting single-flux-quantum two-input exclusive OR circuit.

[Explanation of symbols]

J1A, J1B, J1C, J1D, J1E, J2A, J
2B, J2C, J2D, J2E, J3, J4, J5, J
d1, Jd2 Josephson junctions L1A, L1B, L1C, L1D, L1E, Ld1, L
d2 Inductances Ib1, Ib2, Ib3, Ib4, Ib5 DC bias currents InA, InB, InC, InD, InE Signal input terminals 2XOR1, 2XOR2, 2XOR3, 2XOR4 2
Input exclusive OR circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shuichi Nagasawa             Foundation law, 1-14-3 Shinonome, Koto-ku, Tokyo             International Superconductivity Technology Center             Institute of Electrical Engineering (72) Inventor Kazuhiro Takahashi             Foundation law, 1-14-3 Shinonome, Koto-ku, Tokyo             International Superconductivity Technology Center             Institute of Electrical Engineering (72) Inventor Kazuki Miyahara             Foundation law, 1-14-3 Shinonome, Koto-ku, Tokyo             International Superconductivity Technology Center             Institute of Electrical Engineering (72) Inventor Yoichi Enomoto             Foundation law, 1-14-3 Shinonome, Koto-ku, Tokyo             International Superconductivity Technology Center             Institute of Electrical Engineering F-term (reference) 4M113 AD11 AD23                 5J042 AA04 BA14 CA26 DA02 DA03

Claims (6)

[Claims] 1. A first Josephson junction having one end connected to a first connection point and the other end connected to an output point, and a second Josephson junction having one end connected to the output point and the other end grounded. A Son junction, a third Josephson junction having one end connected to the output point and the other end connected to a control signal input point, and a fourth Josephson junction having one end connected to the first signal input point and the other end grounded. And a fifth junction having one end connected to the first bias current input point and the other end connected to the first signal input point.
A Josephson junction, a first inductance having one end connected to the first bias current input point and the other end connected to the first connection point, and one end connected to a second signal input point A sixth Josephson junction whose end is grounded; a seventh Josephson junction whose one end is connected to a second bias current input point and whose other end is connected to the second signal input point; A superconducting single-flux-quantum exclusive-OR circuit configured with a second inductance connected to a second bias current input point and the other end connected to the first connection point. Point and a third bias current input point, one end of which is connected to the third signal input point and the other end of which is the second
A delay circuit having a predetermined delay time connected to a connection point of, an eighth Josephson junction having one end connected to the second connection point and the other end grounded, and one end of the third bias current A ninth Josephson junction connected to the input point and the other end connected to the second connection point; and one end connected to one of the third bias current input points and the other end connected to the first connection A superconducting single-flux-quantum multi-input exclusive-OR circuit comprising at least one circuit composed of a third inductance connected to a point. 2. The predetermined delay time commonly includes the first Josephson junction and the second Josephson junction, and the first to third inductances and the fourth to ninth Josephson junctions. 2. The superconducting single-flux quantum poly according to claim 1, wherein the superconducting loop formed through the ground and the ground has a time longer than the time required to reset the quantum state of the superconducting loop. Input exclusive OR circuit. 3. The delay time of at least one delay circuit connected to the at least one third signal input point is sequentially different from each other by the predetermined delay time. The superconducting single magnetic flux quantum multi-input exclusive OR circuit according to claim 1. 4. The superconducting single-flux-quantum poly according to claim 1, wherein the delay circuit is realized by using a signal propagation delay of a Josephson transmission line composed of a Josephson junction and an inductance. Input exclusive OR circuit. 5. The superconducting single-flux-quantum multi-input exclusive-OR circuit according to claim 1, wherein the delay circuit is realized by using a signal propagation delay of a microstrip line. 6. The superconducting single-flux-quantity multi-input exclusive-OR circuit according to claim 1, wherein the control signal is a periodic clock signal.