JP2003263888A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a delay time for generating a sense amplifier driving signal. <P>SOLUTION: In a device having hierarchical word line structure having main word lines and sub-word lines and having a dummy pattern for holding continuity of a shape at a memory cell mat end, this dummy pattern is pre-charged to a power source voltage level making source sides of cell transistors 1A, 1B, 1C,... connected to the dummy pattern of the sub-word line SWL end as a ground potential, when any of sub-word lines is selected and started, the corresponding dummy pattern is made a 'L' level, a signal from the dummy pattern through an inverter 3 is made a sense amplifier driving signal. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more specifically, it has a hierarchical word line structure in which a word line has a main word line and a sub word line and maintains shape continuity at the end of a memory cell mat. The present invention relates to a technique for reducing the generation time of a sense amplifier drive signal in a semiconductor memory device such as a dynamic RAM (hereinafter referred to as DRAM) having a dummy pattern.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of high integration DRAMs, a hierarchical word line structure has been proposed as a word line selection method for relaxing the pitch of metal wiring. An example of this hierarchical word line structure is “A 29-ns 64-Mb
DRAM with Hierarchical Array Architecture ”IEEE JOU
RNAL OF SOLID-STATE CIRCUITS, Vol.31 (1996) pp.1302-1
There is 307.

In the above DRAM, the memory cell array a is divided into a plurality of sub-arrays b as shown in FIG. The sub-arrays b arranged in the same row direction form a block, and a plurality of blocks 0, 1, 2, 3, ... A plurality of main word lines MWL (only one in the block 0 is shown in the figure) is used as a plurality of sub-arrays b in the same row.
Pass over.

These main word lines MWL are driven by a row decoder (not shown) selected by a predetermined address signal.

The sub word line PDX is arranged orthogonal to the main word line MWL. These sub word lines PDX are commonly used by the sub arrays b arranged in the same column direction. Each sub-word line PDX is made up of a plurality of lines (for example, 4 lines) as shown by the bold line in the figure, and one of the plurality of lines is selected by a common address signal of several bits (for example, 2 bits).

Each of the selected main word line MWL and sub word line PDX selects one of a plurality of sub word drivers (not shown). The selected sub-word driver drives one of a plurality of sub-word lines (not shown), and these sub-word lines are each connected to a memory cell.

The operation of the DRAM will be described below.

When a row address is input, any one row decoder is selected, and one main word line MWL connected to this row decoder is selected and activated.

On the other hand, any one of the plurality of sub-word selection lines is selected and activated by a row address different from the row address for selecting the main word line MWL.

When one main word line and one subword selection line are activated in the subarray, one subword driver (not shown) is selected, and one subword connected to this selected subword driver. The line is selected and activated, and the information of the memory cell connected to this sub word line is read.

Now, the internal structure of the word line driver of the DRAM will be described with reference to FIG. still,
FIG. 3 shows an example in which a word line driver is composed of NMOS type transistors.

The word line driver of FIG. 3 has first and second NMOS type transistors 10 and 11 connected in series, and the connection point is connected to the word line WL12 as an output point.

A sub-word selection line PDX13 is connected to the first NMOS type transistor 10, and a main word line MWL15 is connected to the gate of the sub word selection line PDX13 via a third NMOS type transistor 14.

The second NMOS type transistor 11 is grounded, and an inverted voltage QPDX of the voltage of the sub word selection line 13 is applied to its gate.

Further, a high voltage VPP is applied to the gate of the third NMOS type transistor 14.

Reference numeral 16 denotes a fourth NMOS transistor 16, which is connected between the main word line 15 and the output point and has its gate at the sub word selection line. 13 is connected.

Here, in the generation of the sense amplifier drive signal of the DRAM, a sense amplifier drive signal is created by setting an appropriate delay from the confirmation of the row address to drive the word line and further setting an appropriate delay. is doing.

That is, as shown in FIG. 4, after the input signal An is input to the row address buffer 20 and the row address signal is fixed, an appropriate delay is set by using the delay circuit (delay) 21 to drive the word line. Generate a signal. Then, after the word line drive signal is determined, the delay circuit 22 is used to further set an appropriate delay to create the sense amplifier drive signal.

[0019]

As described above, regarding the delay for generating the sense amplifier drive signal, from the rise of the word line to the generation of a minute potential on the bit line according to the cell information. The delay circuits 21 and 22 are arranged by estimating the delay corresponding to time.

However, it is general to give a margin to this delay in order to perform a stable operation.

As a result, extra delay is generated and the access time is wasted.

[0022]

In view of the above problems, the semiconductor memory device of the present invention has a hierarchical word line structure having a main word line and a sub word line and maintains shape continuity at the end of the memory cell mat. Of the sub-word line, the source side of the cell transistor connected to the dummy pattern at the end of the sub-word line is set to the ground potential, and the dummy pattern is precharged to the power supply voltage level, and the sub-word line is selected and raised. When it goes up, the dummy pattern becomes "L" level, and the signal passing through the inverter from this dummy pattern is used as a sense amplifier drive signal.

When the sub-word line is selected and rises, the dummy pattern becomes "L" level, and this signal is used as a sense amplifier drive signal.

As a result, the sense amplifier drive signal is generated in response to the rise of the word line in the memory cell mat, so that no extra delay occurs.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a semiconductor memory device of the present invention will be described below with reference to the drawings.

Here, the feature of the present invention is that, as shown in FIG. 1, in the structure having a hierarchical word line structure and having a dummy pattern for maintaining the continuity of the shape at the end of the memory cell mat, the end of the sub word line SWL is formed. The source side of the cell transistors 1A, 1B, 1C ... Connected to the dummy pattern (hereinafter, friendly bit line FBL) is set to the ground potential, and the dummy pattern is precharged to the power supply voltage Vcc level via the transistor 2. By generating the sense amplifier drive signal in response to the rise of the word line in the memory cell mat, an extra delay as in the conventional case is not generated.

That is, the cell transistor 1 connected to the friendly bit line FBL at the end of the sub word line SWL.
If the source side of A, 1B, 1C ... Is set to the ground potential and this friendly bit line FBL is precharged to the power supply voltage Vcc level, when any sub word line (SWL) is selected and rises. , The friendly bit line FBL becomes "L" level.

Then, this friendly bit line F
The signal SN from BL through the inverter 3 is used as the sense amplifier drive signal.

As described above, according to the present invention, the source side of the cell transistor 1 connected to the friendly bit line FBL for maintaining the shape continuity at the end of the memory cell mat has a hierarchical word line structure, and this friendly bit is used as the ground potential. By precharging the line FBL to the power supply voltage Vcc level, one of the sub word lines SWL
Is selected and rises, the friendly bit line FBL becomes "L" level, and since the signal SN from the friendly bit line FBL through the inverter 3 is used as the sense amplifier drive signal, an extra delay as in the conventional case occurs. Absent.

Further, since the friendly bit line FBL is effectively used as described above, there is also an advantage that there is little pattern loss.

Furthermore, the peripheral control circuits such as the conventional delay circuits 21 and 22 are not required, so that the pattern area can be reduced and the cost can be reduced.

As the sense amplifier drive signal, even if the signal SN from the friendly bit line FBL through the inverter 3 is used as it is, the logical product of the upper bit of the address which also serves as the memory cell mat selection and the bit signal is obtained. It doesn't matter.

Furthermore, from the signal obtained by inverting the signal SN that has passed through the inverter 3 from the friendly bit line FBL,
A restore signal for the sense amplifier 4 can also be generated.

[0034]

According to the present invention, since the sense amplifier drive signal is generated in response to the rise of the word line in the memory cell mat, no extra delay occurs.

Further, since the friendly bit line FBL is effectively used, the pattern loss is small.

Furthermore, the peripheral control circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional semiconductor memory device.

FIG. 3 is a circuit diagram showing a conventional semiconductor memory device.

FIG. 4 is a circuit diagram showing a conventional semiconductor memory device.

[Explanation of symbols]

1A cell transistor 1B cell transistor 1C cell transistor 3 inverter 4 sense amplifier

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F083 GA01 KA03 LA05 ZA28                 5M024 AA50 BB12 BB14 BB35 CC39                       CC40 CC46 CC82 GG01 PP01                       PP03

Claims (3)

[Claims] 1. A semiconductor memory device having a hierarchical word line structure having a main word line and a sub word line, and having a dummy pattern for maintaining shape continuity at a memory cell mat end, wherein a dummy pattern at the end of the sub word line is provided. A semiconductor memory device characterized in that the dummy pattern is precharged to the power supply voltage level with the source side of the cell transistor connected to the ground potential as ground potential. 2. When the sub-word line is selected and rises, the dummy pattern becomes “L” level, and a signal passing through the inverter from the dummy pattern is used as a sense amplifier drive signal. The semiconductor memory device described. 3. The semiconductor memory device according to claim 2, wherein a signal obtained by inverting the sense amplifier drive signal is used as a restore signal for the sense amplifier.