JP2003263105A - Block encryption circuit and its method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speed up data transfer processing even when encrypting data from an interface having optional data width. <P>SOLUTION: When a power supply is turned on, the bus width of an input data register 220 and the byte order of the register 220 are set up by the initializing operation of a CPU 11. A block encryption circuit 120 inputs unencrypted data from an internal bus 114, encrypts the inputted data and outputs the encrypted data. An endian selection circuit 240 executes byte order conversion processing of input data and stores the processed input data in an input data register 220 of which byte width is 8 bytes, so that a ciphering block 210 is ciphered by using a block of 8 bytes. Since conventional byte order conversion processing to be executed by the CPU 101 is unnecessary and the processing load of the CPU 101 can be reduced, the speedup of data transfer processing can be realized. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a block cipher circuit and method for dividing input data into predetermined lengths (block lengths) and encrypting the data in block units.
In particular, the present invention relates to a configuration that speeds up data transfer processing when data from an interface having an arbitrary data width is encrypted.

[0002]

2. Description of the Related Art Generally, in this type of block encryption,
When input data is encrypted in block length units such as 4 bytes or 8 bytes, the result of encryption changes depending on the data order in each byte unit, so it is necessary to input data in an appropriate byte unit order. . In the past, the interface between such a block cipher circuit and the CPU was conventionally performed in units of 1 byte (8 bits), but in recent CPUs, the bus width is often wider than 8 bits. In order to transfer data at a higher speed, it is necessary to match the bus widths of the block cipher circuit and the CPU.

FIG. 5 shows a CD-R or CD-RW (hereinafter referred to as CD-R) equipped with such a conventional block cipher circuit.
FIG. 3 is a block diagram showing an example of a schematic configuration of a recording / reproducing device (referred to as R / RW). This recording / reproducing apparatus includes a CPU 1 that controls the entire apparatus, a disk drive 3 that writes and reads data to and from a CD-R / RW 2, a RAM 4 that stores reproduced data and recorded data, and a reproduced data and recorded data. And a block encryption circuit (encryption block) 5 for performing encryption. In this device, the bus width between the CPU 1 and the disk drive 3 is 1 byte, and the bus width between the CPU 1 and the RAM 4 and the block encryption circuit 5 is 2.
It has become a byte. Further, the encryption processing unit (block length) of the block encryption circuit 5 is 8 bytes (64 bits).

FIG. 6 is a flow chart showing an encryption process at the time of reproducing data in such a recording / reproducing apparatus, and FIG. 7 is an explanatory diagram showing a data transition in the encryption process. First, the CPU 1 controls the disk drive 3 to read data from the CD-R / RW 2,
This is transferred to the RAM 4 and stored (FIG. 6; S1). At this stage, as shown in FIGS. 7A and 7B, CD-R /
Each byte data A, B, C, ... Read from RW2
Are stored in the storage area of the RAM 4 in units of words, and are stored in the order of byte data B, A, D, C, ....

Therefore, the CPU 1 performs byte-order conversion processing for block encryption on the data stored in the RAM 4 (FIG. 6; S2). This is shown in Figure 7.
As shown in (C), the data order stored in the RAM 4 is changed in byte units, and the byte data order at the time of reading is A,
Change to B, C, .... Note that such a byte-order conversion process is described in, for example, Japanese Patent Laid-Open No. 2000-3.
It is disclosed in Japanese Patent No. 30760. Then, this converted data is transferred to the block encryption circuit 5 with a 16-bit width (FIG. 7 (D)), and after block encryption is performed (FIG. 6;
S3), the encrypted data is loaded into the CPU 1 (FIG. 6; S4).

[0006]

As described above, in the system using the conventional block cipher circuit, the CPU needs to perform byte-order conversion processing in consideration of the interface with the block cipher circuit. However, there is a problem that the data transfer process becomes long and the process cannot be speeded up.

Therefore, an object of the present invention is to provide a block cipher circuit and method capable of realizing high speed data transfer processing even when data from an interface having an arbitrary data width is encrypted. .

[0008]

In order to achieve the above-mentioned object, the present invention provides a block cipher circuit for inputting data from an input interface having an arbitrary bus width and performing block encryption. An input data register to be stored, a bus width setting means for setting a bus width of the input data register, an endian setting means for setting an endian of data to be stored in the input data register, and a set value of the bus width setting means. And a byte order selecting means for controlling the bus width of the input data register on the basis of the input data register and controlling the byte order of the data input from the input interface on the basis of the set value of the endian setting means and storing the data in the input data register. Stored in the input data register And having a block encryption unit performs block encryption over data.

Further, according to the present invention, in a block cipher method for inputting data from an input interface having an arbitrary bus width and performing block encryption, the block width is set from the input interface based on the bus width set value set by the system control means. Controlling the bus width of the input data register for storing the data of, and controlling the byte order of the data input from the input interface based on the endian setting value set by the system control means and storing the data in the input data register. It is characterized by having a byte order selection step.

In the block cipher circuit of the present invention, the bus width of the input data register is controlled based on the setting value of the bus width setting means, and the byte order of the input data is controlled based on the setting value of the endian setting means. A byte order selecting means for storing in the input data register is provided. Therefore, when encrypting data from an interface with an arbitrary data width, the CP on the system side
To reduce the burden of changing byte order in U etc.,
It is possible to speed up the data transfer process.

In the block cipher method of the present invention, the bus width of the input data register is controlled based on the preset bus width setting value, and the byte order of the input data is determined based on the preset endian setting value. And a byte order selecting step for controlling and storing in the input data register. Therefore, when the data from the interface having an arbitrary data width is encrypted, it is possible to reduce the load of the byte order changing process on the CPU and the like on the system side and realize the high speed data transfer process. .

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a block cipher circuit and method according to the present invention will be described below. Figure 1
FIG. 6 is a block diagram showing a configuration example of a CD-R / RW recording / reproducing apparatus equipped with a block cipher circuit according to an embodiment of the present invention. FIG. 5 is a block diagram showing components of the recording / reproducing apparatus from FIG. It is a little concrete. This recording / reproducing apparatus includes a CPU 101, a ROM 102, a key input section (KEY) 103, a RAM 104, a liquid crystal display section (LCD) 105, an EEPROM 106, a microphone (MI).
C) 107, speaker (SP) 108, A / D / D /
It has an A interface (I / F) 109, a disk drive 110, a disk interface 111, a USB interface 112, a power switch 113, a block cipher circuit 120, and an internal bus 114 connecting the above blocks.

A CPU 101 controls the entire apparatus as a system control means, and a ROM 102 stores a C
A control program executed by the PU 101 and the like are provided. The RAM 104 is for storing various data, and the EEPROM 106 is for storing data to be saved even when the power is off. A key input unit (KEY) 103 is used by a user to input various keys, and a liquid crystal display unit (LCD) 105.
Displays various data. The microphone 107 is for inputting various types of voice, and the speaker (SP) 108 is for outputting various types of voice. The A / D / D / A interface 109 is an interface for performing analog / digital conversion between the microphone 107 or the speaker 108 and the internal bus 114. The disk drive 110 writes and reads data to and from the CD-R / RW, and the disk interface 111 includes a disk drive 11
0 and the internal bus 114.
Also, the USB interface 112 is an interface for connecting a PC or other external processing device 130, and the power switch 113 is a switch for turning on / off the power of the present device.

The block encryption circuit 120 is for performing block encryption of data, and has an encryption block 210, an input data register 220, a bus width selection circuit 230, and an endian selection circuit 240. . The encryption block 210 includes the input data register 22.
Block encryption is performed on the data stored in 0, and the input data register 220 stores the data subjected to byte order conversion by the endian selection circuit 240. In addition, the bus width selection circuit 230
Is a bus width setting means for setting the bus width of the input data register 220, and is a register for setting the bus width according to an instruction from the CPU 101. Specifically, the bus width of 2 ⁿ bytes (n = 1, 2, 3, ...) Is selectively set. The endian selection circuit 240 controls the endian setting means for setting the endian of the input data and the byte order of the input data to control the input data register 23.
It includes a byte order selecting means for storing in 0, and performs byte order conversion processing corresponding to the bus width of the CPU 101.

FIG. 2 is a block diagram showing the functional arrangement of the endian selection circuit 240. Here, the entire block of the endian selection circuit 240 is a byte order selection unit, and the Little setting register 241 in this block is an endian setting unit. The Little setting register 241 is set with identification data indicating either big endian (Little = 0) or little endian (Little = 1) according to an instruction from the CPU 101. In addition, the endian selection circuit (byte order selection means) 240 receives the input data register 220 based on the set value of the bus width selection circuit 230.
The bus width is set, the byte-order conversion processing is performed on the input data based on the setting value of the Little setting register 241, and the result is stored in the input data register 220.

The setting value of the bus width selection circuit 230 and the setting value of the Little setting register 241 of the endian selection circuit 240 are determined by the specifications of the CPU 101, etc. It is set and will not disappear when the power is turned off. Then, in the initial setting operation when the power is turned on, these set values are read by the CPU 101 and set in the block cipher circuit 120 under the control of the CPU 101.

FIG. 3 is a flow chart showing an encryption processing method of the block encryption circuit 120 in the present embodiment, and FIG. 4 is an explanatory diagram showing data transition in the encryption processing method. First, when the power is turned on (FIG. 3; S11), the setting value of the bus width selection circuit 230 is determined by the initial setting operation of the CPU 101, and the bus width of the input data register 220 is set based on this setting value (FIG. 3). S12). Next, the endian selection circuit 240
The setting value of the Little setting register 241 is determined, and the byte order for the input data register 220 is set based on this setting value (FIG. 3; S13). Thereafter, when the data reproducing operation is instructed by the recording / reproducing apparatus, the CPU 101, as shown in FIGS.
The disk drive 110 is controlled to read the data from the CD-R / RW, transfer it to the RAM 104, and store it. Then, the data stored in the RAM 104 is transferred to the block cipher circuit 120 through the internal bus 114.

As a result, the block cipher circuit 120 inputs unencrypted data from the internal bus 114 (FIG. 3; S14), performs encryption (FIG. 3; S15), and outputs the encrypted data (FIG. 3). S16). At this time, the endian selection circuit 240 performs byte order conversion processing as shown in FIGS. 2 and 4C on the byte order of the input data, and the input data register 220 having a byte width of 8 bytes (64 bits). By storing (Fig. 4
(D)) The encryption block 210 is encrypted in units of 8 bytes. Therefore, in the block cipher circuit according to the present embodiment, the C
The byte order conversion process by the PU (the process shown in S2 of FIG. 6) is unnecessary, and the processing load on the CPU can be reduced, so that the data transfer process can be speeded up.

In the above, the example in which the block cipher circuit and method of the present invention is applied to a CD-R / RW recording / reproducing apparatus has been described, but the present invention is not limited to this, and various data can be recorded. It can be similarly applied to a system that performs block encryption. Further, the specific numerical values such as the byte width described above are merely examples, and needless to say, various changes can be made.

[0020]

As described above, according to the block cipher circuit of the present invention, the bus width of the input data register is controlled on the basis of the set value of the bus width setting means, and the set value of the endian setting means is used. By providing the byte order selection means for controlling the byte order of the input data and storing it in the input data register, when the data from the interface having an arbitrary data width is encrypted, the byte order in the CPU etc. on the system side It is possible to reduce the load of the change processing and realize the speedup of the data transfer processing.

Further, according to the block cipher method of the present invention, the bus width of the input data register is controlled on the basis of the preset bus width setting value and the input data of the input data register is controlled on the basis of the preset endian setting value. By providing the byte order selection step of controlling the byte order and storing it in the input data register, when the data from the interface having an arbitrary data width is encrypted, the byte order changing process in the CPU of the system side can be performed. It is possible to reduce the burden and realize the speedup of the data transfer process.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a CD-R / RW recording / reproducing apparatus equipped with a block cipher circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a functional configuration of an endian selection circuit in the block cipher circuit shown in FIG.

FIG. 3 is a flowchart showing an encryption process of the block cipher circuit shown in FIG.

FIG. 4 is an explanatory diagram showing a transition of data in the encryption processing shown in FIG.

FIG. 5: CD-R / equipped with a conventional block cipher circuit
It is a block diagram which shows the example of a schematic structure of the recording / reproducing apparatus of RW.

6 is a flowchart showing an encryption process at the time of reproducing data in the recording / reproducing apparatus shown in FIG.

FIG. 7 is an explanatory diagram showing a data transition in the encryption processing shown in FIG.

[Explanation of symbols]

101 ... CPU, 102 ... ROM, 103 ... Key input section (KEY), 104 ... RAM, 105 ... Liquid crystal display section (LCD), 106 ... EEPROM, 107 ...
… Microphone (MIC), 108… Speaker (SP), 1
09 ...... A / D / D / A interface (I / F),
110 ... Disk drive, 111 ... Disk interface, 112 ... USB interface, 1
13 ... power switch, 114 ... internal bus, 120 ...
... Block encryption circuit, 210 ... Encryption block, 22
0 ... Input data register, 230 ... Bus width selection circuit, 240 ... Endian selection circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tsutomu Ichinose             Aiwa Co., Ltd. 1-2-11 Ikenohata, Taito-ku, Tokyo             Inside the company F-term (reference) 5J104 AA18 NA22

Claims (7)

[Claims] 1. In a block cipher circuit for inputting data from an input interface having an arbitrary bus width and performing block encryption, an input data register for storing data from the input interface, and a bus width of the input data register. A bus width setting means for setting, an endian setting means for setting an endian of data to be stored in the input data register, and a bus width of the input data register based on a set value of the bus width setting means, Byte order selection means for controlling the byte order of the data input from the input interface based on the set value of the endian setting means and storing it in the input data register, and block encryption of the data stored in the input data register Block cipher hand doing Block cipher circuit, characterized in that it comprises a and. 2. The block cipher circuit according to claim 1, further comprising system control means for setting the bus width setting means and the endian setting means. 3. The block cipher circuit according to claim 1, further comprising system control means for inputting data from the input interface. 4. The block cipher circuit according to claim 1, wherein the endian setting means is a register for setting either big endian or little endian. 5. The bus width setting means is 2 ⁿ bytes (n
2. The block cipher circuit according to claim 1, wherein the block cipher circuit is a register for setting a bus width of = 1, 2, 3 ,. 6. A block cipher method for inputting data from an input interface having an arbitrary bus width and performing block encryption, wherein an input for storing data from the input interface based on a preset bus width setting value. Controlling the bus width of the data register and controlling the byte order of the data input from the input interface based on a preset endian setting value, and storing the byte order in the input data register. Characteristic block cipher method. 7. The block cipher method according to claim 6, wherein the bus width setting value and the endian setting value are set by the system control means after the power is turned on.