JP2003260824A - Imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging apparatus having reduced power consumption and improved user's usability by cutting a time required for initializing an integrated circuit for a peripheral control unit by a control program, and shortening a system return time. <P>SOLUTION: The imaging apparatus has a main control means 3 for controlling entirely, and a integrated circuit 32 for the peripheral control unit for controlling each part in accordance with an instruction of the main control means 3. A function block 41 for realizing a predetermined mechanism, a register block 42 for storing setting data to the function block 41, and a nonvolatile memory 44 for storing an initial value of the setting data to the function block 41 separately from the register block 42 are incorporated in the integrated circuit 32. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus such as a digital copying machine or a digital printer using a non-volatile memory.

[0002]

2. Description of the Related Art In recent years, there has been a strong demand for power saving in image forming apparatuses from the viewpoint of environmental protection. Conventionally, in an image forming apparatus using an electrophotographic process, the power consumption of a fixing unit has been dominant, and the standby unit saves power by controlling the fixing unit at a temperature lower than that during operation and cutting off power supply. A method of realizing electric power is widely adopted. Recently, more advanced methods have been adopted in which not only the fixing unit but also all or almost all of the system power is shut off. In this case, the power consumption during standby is several W
It becomes possible to provide the following, and it becomes possible to provide an image forming apparatus which has an extremely large effect of power saving. On the other hand, in terms of convenience, the recovery time from the standby state is very important. That is, if the image forming apparatus cannot be used immediately because the image forming apparatus is being restored when it is desired to be used, the convenience is significantly reduced. When power saving in the standby state is mainly performed by controlling the fusing unit, efforts have been made to improve the efficiency of the heater, reduce the thickness of the fusing roller, and shorten the return time mainly for mechatronics products. It was As a result, the recovery time of the fixing unit has been improved from several minutes to several seconds. Generally, it often takes several seconds to initialize the control unit centered on the CPU. In the case of the system that shuts off the power of all or almost all of the system, the number of times required for this initialization with respect to the entire recovery time from the standby state when the recovery time of the fixing unit is in the range of several minutes and several tens of seconds Since the contribution rate per second was low, it was not necessary to consider it deeply. However, in a recent image forming apparatus in which the fixing unit has a reset time of several seconds, the reset time of the system greatly depends on the several seconds required for the initialization. This situation will be described below.

FIG. 10 is a block diagram of a digital copying machine as a conventional image forming apparatus. The image data of the document 2 read by the reading control unit 1 is subjected to image processing by an image processing unit (not shown) of the main control unit 3,
It is sent to the write control unit 4. The writing controller 4 controls the lighting of a laser diode (not shown) based on the image data sent from the image processor, and forms an electrostatic latent image on the electrophotographic process 5. On the other hand, the transfer paper conveyed from the paper feeding unit (not shown) has toner transferred by the known electrophotographic process 5, and the toner is transferred onto the transfer paper by the fixing unit (not shown) heated by the fixing heater 6. It is fixed and a copy 7 is formed. The fixing heater 6 is controlled by the main control unit 3, the IO control unit 8, and the fixing control unit 9 so that the fixing unit is always at a desired temperature during operation.
In addition, to reduce system power consumption during standby,
Control or cut off the power supply at a lower temperature than during operation. Further, in the case of a system of shutting off all or almost all of the power supply of the system during standby, not only the fixing heater but also the main controller 3, the IO controller 8, the fixing controller 9, and the like are shut off. In addition to the above, the digital copying machine of FIG. 10 has an operation unit 10, an ADF 11, a bank (paper feeding bank).
12, a sensor 13, a clutch solenoid 14, and a power supply 15.

FIG. 11 is a block diagram of a main controller and an IO controller of a conventional image forming apparatus. When the reset signal generated by the reset IC 22 is released after the power is turned on, the CP
U21 starts a series of operations according to the control program stored in ROM23. The RAM 24 is used as a work area for control programs. In addition, the nonvolatile memory 2
Reference numeral 5 stores adjustment data of the image forming apparatus, usage history, and the like, which is used for maintenance activities. Since the CPU 21 generally has a general-purpose specification, the control program is
First, the inside of the CPU 21 is initialized. Also, the RAM 24
In many cases, the contents are undefined immediately after the power is turned on, so after the CPU initialization, All “0” or ALL “1”
The RAM 24 is initialized by writing. Furthermore, CPU
Since the peripheral ASIC 26 and the peripheral control ASIC 31 are often made to have general-purpose specifications, the CPU peripheral ASIC 26 and the peripheral control ASIC 31 are initialized after the RAM 24 is initialized. The peripheral control ASIC 31 will be described in more detail. Peripheral control ASIC 31 is CPU 21, ROM
Since it is mounted on a board different from that of 23 or the like, it is connected to a dedicated control bus separated from the CPU bus by the CPU peripheral ASIC 26 for the purpose of reducing the bus load. This AS
IC mainly includes ADF11, bank 12, sensors 1
3, an input / output system I / F such as a clutch solenoid 14 and a fixing controller 9 are connected. In order to make general-purpose functions in the ASIC correspond to these I / Fs, it is necessary to perform input setting for input, output setting for output, and serial communication setting for serial communication.

FIG. 12 is a block diagram of the peripheral control ASIC. The peripheral control ASIC 31 is connected to a function block 41 that realizes each function such as PIO, UART, and timer, a register block 42 that sets various settings to the function block 41, operation control, and a control bus such as an address bus and a data bus. And a CPU I / F 43 for internally performing address decoding and controlling access to the register block 42. The description will be given below by taking PIO as an example.
In order to prevent the control signal to the load from becoming active due to an unexpected output at the time of reset and after the reset is released, normally, all terminals of the PIO are set to the input ports by the register block 42, and the input / output terminals are in the Hi-Z state.
In the case of a control signal to a load, such as a motor, which is to be made inactive at the time of reset and after reset is released, the control signal is made inactive by pulling up or pulling down the input / output terminal. After reset is released, CP
By setting the register block 42 from the CPU (not shown) via the U I / F 43, the terminal to which the input load is connected is the input, the terminal to which the output load is connected is the output, and the output is also the output. Initial values and the like are set, and desired input / output is performed. The same operation is sequentially performed for the UART, the timer, etc., and the initialization of the peripheral control ASIC 31 is completed. Further, in order to ensure safety of the load of the fixing heater 6 and the like, after a series of initialization is completed and it is confirmed that there is no problem in the operation of the system, the lighting control is started. Immediately after the start of lighting, control is performed so that the desired set temperature is reached quickly by full lighting, and after reaching the desired set temperature, control is performed so that the temperature is always kept constant by temperature monitoring.

[0006]

FIG. 13 shows how the power is turned on, the initialization is performed, and the fixing heater is turned on. In addition, an example of the time required for each operation is shown in FIG.
Shown in. Since the control program operates sequentially from the power-on to the start of the fixing heater in FIG. 13, the system recovery time is 54.1 s when the fixing heater recovery time is long, and 9.1 s when it is short. It can be seen from FIG. Now, let us consider the contribution ratio of the peripheral control ASIC initialization time to the system recovery time. When the recovery time of the fixing heater 6 is long, it is 1.8% from FIG. 13, and it can be considered that there is almost no effect. However, when the recovery time of the fixing heater is short, it is 11.0%, which is a contribution rate that cannot be ignored. When further shortening the system recovery time, this portion may become a bottleneck and become a barrier to improvement of user convenience. The present invention has been made in view of the above circumstances, and a non-volatile memory for storing an initial value of setting data to a functional block is built in the peripheral control unit integrated circuit separately from the register block. Accordingly, it is an object of the present invention to provide an image forming apparatus in which a time required for initialization of an integrated circuit for a peripheral control unit by a control program is deleted, a system recovery time is shortened, power consumption is reduced, and user convenience is improved. And

[0007]

In order to achieve the above object, the invention according to claim 1 is for a main control means for controlling the whole and for a peripheral control section for controlling each part according to a command of the main control means. In an image forming apparatus including an integrated circuit, the integrated circuit for peripheral control unit includes a functional block for implementing a predetermined function, a register block for storing setting data in the functional block, and a register block separately. An image forming apparatus having a built-in non-volatile memory for storing an initial value of setting data to a functional block is the most main feature. According to a second aspect of the present invention, in the image forming apparatus according to the first aspect, the initial setting data to the functional blocks stored in the non-volatile memory of the peripheral control unit integrated circuit is instructed by the command of the main control unit when the power is turned on. The main feature of the image forming apparatus is that it has a selector for selecting a register block in order to load a value into the register block. According to a third aspect of the present invention, in the image forming apparatus according to the first or second aspect, when the main control unit accesses the peripheral control unit integrated circuit, the register block and the non-volatile memory have the same address on the memory map. The main feature of the image forming apparatus is the selector control means for controlling the selector that switches between the register block and the non-volatile memory. A fourth aspect of the present invention is characterized in that, in the image forming apparatus according to any one of the first to third aspects, the non-volatile memory is a ferroelectric memory.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In the following drawings, the same parts as those in the conventional example are designated by the same reference numerals. FIG. 1 is a configuration diagram of a main controller and an IO controller in the image forming apparatus of the present invention. After the power is turned on, with the release of the reset signal generated by the reset IC 22, the CPU 21 starts a series of operations according to the control program stored in the ROM 23. RA
M24 is used as a work area for the control program. Further, the non-volatile memory 25 stores adjustment data of the image forming apparatus, usage history, etc., and is utilized for maintenance activities. C
Since the PU 21 generally has a general-purpose specification, the control program first initializes the inside of the CPU 21 after the operation starts. In addition, the contents of the RAM 24 are often undefined immediately after the power is turned on.
The RAM 24 is initialized by writing L "0" or ALL "1". Further, since the CPU peripheral ASIC 26 is also often used as a general-purpose specification, the CPU peripheral ASIC 26 is initialized after the RAM 24 is initialized. Conventionally, since the peripheral control ASIC 31 (FIG. 11) is initialized sequentially thereafter, it takes time to initialize, but the peripheral control ASIC 32 according to the present invention eliminates this. Initialization of the peripheral control ASIC 32 according to the present invention will be described with reference to FIG.

FIG. 2 is a block diagram of a peripheral control ASIC according to the first embodiment of the present invention. Peripheral control ASIC32
Is internally connected to a function block 41 that realizes each function such as PIO, UART, and timer, a register block 42 that sets various settings to the function block 41, operation control, etc., and a control bus such as an address bus and a data bus. CPU I / F 43 that performs address decoding of the device and controls access to the register block 42, and the functional block 4 in advance at a factory or the like.
The control data to the non-volatile memory 44 and the function block 41 for setting and storing the initial state of
The control data from the first selector 45 and the CPU I / F 43 that switch between the data from the CPU 2 and the data from the nonvolatile memory 44 are transferred to the register block 42 and the nonvolatile memory 4.
The second selector 46 and the like for switching to which of 4 and 4 is supplied. The first selector 4 when the power is turned on
5, the control data to the functional block 41 is supplied from the non-volatile memory 44. The nonvolatile memory 44 has a second
The initial state of the functional block 41 is set and stored in advance by the CPU I / F 43 in a factory or the like by operating the selector 46, so that the functional block 41 operates with a desired initial value. CPU 21 and RAM 24 of the main controller 3
The initialization of each part such as
When the peripheral control ASIC 32 is accessed from 1, the second selector 46 supplies the control data from the CPU I / F 43 to the register block 42. Then, the control data supplied to the functional block 41 is switched to that supplied from the register block 42 by the first selector 45, and normal control is performed.

FIG. 3 shows a state from power-on to a series of initialization and lighting control of the fixing heater according to the first embodiment. 4 shows an example of the time required for each operation. It can be seen from FIG. 4 that the system recovery time is shortened. FIG. 5 is a configuration diagram of a peripheral control ASIC according to the second embodiment of the present invention. In this embodiment, the first selector 45 is eliminated. CPU I /
A load signal from the non-volatile memory 44 to the register block 42 is generated in response to the input of the reset signal to the F43, and the control data of the functional block 41 initially set and stored in the non-volatile memory 44 at the factory is initialized. The value is stored in register block 42. After reset is released,
The normal control state is entered and the CPU 21 controls the peripheral control ASIC
When access to 32 is made, the second selector 4
6, the control data from the CPU I / F 43 is supplied to the register block 42 to control the functional block 41. FIG. 6 shows a state from power-on to a series of initialization and lighting control of the fixing heater according to the second embodiment.
An example of the time required for each operation is the same as in FIG.

FIG. 7 is a block diagram of a peripheral control ASIC according to the third embodiment of the present invention. In this embodiment, a selector switching control unit 47 is added to the configuration of the second embodiment shown in FIG. CPU by the second selector 46
The control data from the I / F 43 is transferred to the register block 42.
And which of the non-volatile memory 44 is supplied is switched. The selection of the switching path is performed by setting the selector switching control unit 47. When the register block 42 is selected by the selector switching control unit 47, the CPU
Access from the CPU 21 via the I / F 43 is made to the register block 42. When the non-volatile memory 44 is selected by the selector switching control unit 47, the access from the CPU 21 is made to the non-volatile memory 44. Each function of the function block 41 (P
If the memory spaces of the registers used for controlling IO, UART, and timer) are each 0x040000 addresses, the number of address lines required for controlling the register block 42 is 20 for A19: 0 (control is possible up to 0x0FFFFF). When the switching control according to the present invention is not performed,
Furthermore, an address line to the non-volatile memory 44 is required,
There is a possibility that the number of address lines required for the peripheral control ASIC 32 will increase. However, in the present invention, since access switching is performed by the selector switching control unit 47, unnecessary address lines are not increased. This state is shown in FIG. 8 as an example of the CPU memory map. Further, when it is desired to change the initial value when the power is turned on next time by the setting of the user or the like, the selector switching control unit 47 is switched to the nonvolatile memory 44 side to update the data in the nonvolatile memory 44. The next time the power is turned on, the nonvolatile memory 44
Since the data is loaded into the register block 42, the device can be operated with the new set value. On this occasion,
Since it is not necessary to change the address in the non-volatile memory 44 for initial value setting and the register block 42 for normal control in software, control in software becomes easy. FIG. 9 is a peripheral control AS according to the fourth embodiment of the present invention.
It is a block diagram of IC. In this embodiment, the nonvolatile memory is composed of the ferroelectric memory 48. For this reason, it is possible to update the initial value of the device operation and the like almost without limit.

[0012]

As described above, according to the first aspect of the invention, the nonvolatile circuit for storing the initial value of the setting data in the functional block separately from the register block in the peripheral control unit integrated circuit. Built-in memory
It is possible to provide an image forming apparatus that can shorten the system recovery time by eliminating the time required for initialization of the peripheral control unit integrated circuit by the control program, reduce power consumption, and improve user convenience. Becomes According to the second aspect of the present invention, the initial value of the setting data for the functional block stored in the non-volatile memory of the peripheral control unit integrated circuit is loaded into the register block by the instruction of the main control unit when the power is turned on. In addition, by selecting the register block, the same effect as the above can be obtained. According to the third aspect of the present invention, when the peripheral control unit integrated circuit is accessed from the main control unit, the register block and the non-volatile memory have the same address on the memory map, and either the register block or the non-volatile memory is used. By switching access, the memory map becomes smaller and there is no need to use an extra address line. Furthermore, it is not necessary to switch register addresses between initial value setting and normal control, so software control is easy. It is possible to provide a different image forming apparatus. According to the invention described in claim 4, since the non-volatile memory is a ferroelectric memory, the control information rewriting frequency limit is almost eliminated (-1012 or more), and the image formation does not impair the user's convenience. It becomes possible to provide a device.

[Brief description of drawings]

FIG. 1 is a main controller in an image forming apparatus of the present invention,
It is a block diagram of an IO control unit.

FIG. 2 is a peripheral control ASI according to the first embodiment of the present invention.
It is a block diagram of C.

FIG. 3 is a diagram showing how initialization is performed in the first embodiment of the present invention.

FIG. 4 is a diagram showing a time required for each operation in the first embodiment of the present invention.

FIG. 5 is a peripheral control ASI according to the second embodiment of the present invention.
It is a block diagram of C.

FIG. 6 is a diagram showing a state of initialization according to the second embodiment of the present invention.

FIG. 7 is a peripheral control ASI according to a third embodiment of the present invention.
It is a block diagram of C.

FIG. 8 is a diagram showing an example of a CPU memory map according to the third embodiment of the present invention.

FIG. 9 is a peripheral control ASI according to the fourth embodiment of the present invention.
It is a block diagram of C.

FIG. 10 is a block diagram of a digital copying machine as a conventional image forming apparatus.

FIG. 11 is a configuration diagram of a main control unit and an IO control unit of a conventional image forming apparatus.

FIG. 12 is a block diagram of a conventional peripheral control ASIC.

FIG. 13 is a diagram showing a state of initialization of a conventional image forming apparatus.

FIG. 14 is a diagram showing a time required for each operation of the conventional image forming apparatus.

[Explanation of symbols]

3 Main control unit (main control means) 8 IO controller 32 Peripheral control ASIC (integrated circuit for peripheral control unit) 41 Function Block 42 register block 44 non-volatile memory 46 Second selector (selector)

Claims (4)

[Claims] 1. An image forming apparatus comprising: a main control means for controlling the whole and a peripheral control section integrated circuit for controlling each section in accordance with a command from the main control section, wherein the peripheral control section integrated circuit comprises: A functional block for realizing a predetermined function, a register block for storing setting data in the functional block, and an initial value of the setting data for the functional block separately from the register block An image forming apparatus comprising: a non-volatile memory. 2. The image forming apparatus according to claim 1,
The register block is selected in order to load the initial value of the setting data for the functional block stored in the non-volatile memory of the peripheral control unit integrated circuit into the register block according to the instruction of the main control unit when the power is turned on. An image forming apparatus having a selector for controlling the image forming apparatus. 3. The image forming apparatus according to claim 1, wherein when the main control unit accesses the peripheral control unit integrated circuit, the register block and the nonvolatile memory have the same address on a memory map. ,And,
An image forming apparatus comprising: a selector control unit that controls a selector that switches between accessing a register block and a non-volatile memory. 4. The image forming apparatus according to claim 1, wherein the nonvolatile memory is a ferroelectric memory.