JP2003259209A - Device for converting image size - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a pixel size to 1/2 without changing frame periods or data rates. <P>SOLUTION: Digital data passing through a clock changing circuit 31A to change to double speed clock is caused to go through a horizontal filter 32, the number of effective pixels of video becoming 1/2 by horizontal filtering. In this case, the number of pixels of an input signal is prescribed, the number of pixels is between 352 and 176 pixels in a CIF (common intermediate format) standard and between 640 and 320 pixels in a VGA (video graphics array) standard. Next, the digital data passing through the horizontal filter 32 are written in a memory 34 when the number of effective lines is an odd number, while the data of the preceding line are read to be then subjected to filter operation with the data of the current line, being rewritten in the memory 34 when the number of the effective lines is an even number. This converts input data into 1/2 size. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to CCDs and CMOSs.
The present invention relates to an image size conversion device that handles a video output signal in a camera system that uses a sensor, a system that converts an analog video signal into a digital video signal, and the like.

[0002]

2. Description of the Related Art Conventionally, in a system for outputting a digital video signal, an image size conversion device used at the final stage of the system uses a frame memory to read the image signal with a vertical filter and at a different reading speed. , A method of performing image size conversion (see, for example, Japanese Patent Laid-Open No. 11-191852), a line memory having the same number of words as the number of horizontal pixels are prepared, vertical filtering is performed, and further horizontal filtering is performed. A method (see, for example, Japanese Patent Laid-Open No. 7-222117) has been proposed.

[0003]

By the way, in a camera or the like generally used for a portable terminal or the like, it is preferable that the size of the memory is smaller from the viewpoint of power consumption and circuit scale, and depending on the system. , 1/4 the number of pixels
However, there is a problem that the output data rate is halved even though (for example, CIF is converted to QCIF).

Therefore, an object of the present invention is to reduce the image size to 1 /
When reducing to N (N ≧ 2), by using a clock having the same frequency as the data clock used for output, the data rate and frame rate can be made constant, and the number of horizontal effective pixels for the memory is also fixed. An object of the present invention is to provide an image size conversion device that can be realized with 1 / N.

[0005]

In order to achieve the above object, the present invention is an image size conversion apparatus for inputting video data, converting the size of the video data and outputting the video data, the input clock of which is N (N
≧ 2) A clock transfer unit that transfers to a double speed clock, a horizontal filter unit that filters the horizontal direction of the video data, a memory of 1 / N word of the number of horizontal effective pixels, and a switching unit that switches the input to the memory. ,
By using a flip-flop with enable and using an N-times speed clock of the number of horizontal pixels, the pixel size can be reduced to 1 / without changing the frame period and the data rate.
It is characterized by reducing to N.

In the image size conversion apparatus of the present invention, the N-times speed clock of the number of horizontal pixels is used to reduce the pixel size to 1 / N without changing the frame period and the data rate, so that the image size conversion is performed. Regardless, the data rate and frame rate can be constant. Therefore, for example, the clock from the image size conversion device can be used in the subsequent stage, and the circuit configuration in the subsequent stage can be simplified. Further, since the clock has a fixed cycle, by inserting a code indicating the start and stop of the video area before and after the video area, it is possible to transfer the video data with a small number of signal lines. Furthermore, as for the memory, 1 / the number of horizontal effective pixels
This can be realized by N, and the circuit scale can be reduced.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of an image size conversion device according to the present invention will be described below. The embodiment described below is a preferred specific example of the present invention,
Although various technically preferable limitations are given, the scope of the present invention is not limited to these embodiments unless otherwise stated to limit the present invention.

FIG. 1 is a block diagram showing a schematic configuration of a camera system to which an image size conversion device according to an embodiment of the present invention is applied. The image size conversion device of this example is a system for converting a digital video signal or an analog video signal processed by a camera signal into a digital video signal, and the video signal is YUV422 (16 bits) or YUV422 (16 bits).
It is used as a device for outputting with UV (8 bits). In the camera system shown in FIG. 1, the CCD
Type image pickup device or an image pickup signal output from an image pickup device 10 using a CMOS sensor type image pickup device
The digital video signal is converted into an image size and output.

The camera signal processing unit 20 is originally shown in FIG.
As shown in (A), the luminance signal processing unit 21, the color signal processing unit 22, and the formatting unit 23 are provided, and the luminance signal processing unit 2
1 and the clock Φ1 of the color signal processing unit 22 is changed to the clock Φ2 of the format unit 23, and the format unit 2
3 is configured to be processed into YUV422 (8 bits) which is output at a clock rate twice as high as the internal signal. Then, the image size conversion device 24 of this example
As shown in FIG. 2B, is a system that is arranged in front of the format unit 23 and efficiently converts the image size.

FIG. 3 is an explanatory view showing an image reduced by using the system of this example, showing rates of the 1/2 scaler and the 1/4 scaler in comparison. In the 1/2 scaler, the total number of pixels and the number of effective pixels are 1/4 that in the normal state, the frame rate is constant, and the pixel data clock is 1/4 that in the normal state. Further, in the 1/4 scaler, the total number of pixels and the number of effective pixels are 1/16 in the normal state, the frame rate is constant, and the pixel data clock is 1/16 in the normal state. Among these, the image size conversion apparatus of this example realizes a 1/2 scaler.

FIG. 4 is a block diagram showing the arrangement of the image size conversion apparatus in this example. As shown in the figure, the image size conversion device includes clock transfer units 31A and 31A.
B, 31C, horizontal filter section 32, memory selector 33, memory 34, memory controller section 35,
It has an enable flip-flop 36 and a vertical synchronization signal generation block 37. FIG. 5 shows the clock transfer unit 31.
It is a block diagram which shows the structure of A, 31B, and 31C. The clock transfer unit 31 of the present example is composed of two flip-flops 41 and 42, and the first-stage flip-flop 41.
Is input to the second stage flip-flop 42 with the same clock as the output data rate. FIG. 6 is a block diagram showing the configuration of the horizontal filter unit 32. The horizontal filter unit 32 of this example includes a flip-flop 43, an adder 44, and a rounding (RND) circuit 4.
It is composed of 5.

FIG. 7 is a block diagram showing the structure of the memory selector 33. This memory selector 33
Has a vertical filter and size conversion output switching function, and is composed of a switch 46, an adder 47, and a rounding (RND) circuit 48, and switches the signal input to the memory 34. The memory 34 has a number of words that is ½ of the number of horizontal pixels (for example, 352/352 for CIF).
2 = 176). FIG. 8 is a block diagram showing the configuration of the memory controller unit 35. The memory controller unit 35 uses two counters 50 and 51 based on a selection signal of CIF / VEG to write a signal (XWR) 52, read signal (XRD) 53,
And read / write address switching signal (AD
D) Controls 54.

Next, the operation of the circuit having the above configuration will be described. First, in the description of the present example, the number of pixels and the number of lines of an input signal are specified in order to simplify the circuit. First, if the signal is the CIF standard, the number of vertical effective lines is 288, and the total number of lines including blanking is 288 + 2n (n ≧ 1).
0, 332, 334, and so on. Further, the number of horizontal effective pixels is 352, and the total number of pixels including blanking is 352 + 4n (n ≧ 1).
392, 396, 400, 404, 408, ... Pixels and the like. On the other hand, if the signal is VGA standard, the number of vertical effective lines is 480, and the total number of lines including blanking is 480 + 2n (n ≧ 0).
516, 518, ... Lines, etc. The number of horizontal effective pixels is 640, and the total number of pixels including blanking is 640 + 8n (n ≧ 0). For example, 79
2, 800, 808, ... Pixels and the like.

FIG. 9 is a simple timing chart showing the operation timing of such a circuit. The digital data that has passed through the clock transfer circuit 31A described above passes through the horizontal filter 32 and the number of effective image pixels is halved (from 352 pixels to 176 pixels for CIF, VGA
If so, it will be 640 pixels to 320 pixels). Next, when the number of effective lines is odd, the digital data that has passed through the horizontal filter 32 is written in the memory 34. When the number of effective lines is even, the data of the previous line is read out, and then the filter operation is performed with the data of the current line. , Memory 34 again
The operation is to write to.

Next, a circuit configuration of a level closer to practical use will be described. FIG. 10 is a block diagram showing the configuration of the image size conversion device when actually used. The same components as those shown in FIG. 4 are designated by the same reference numerals. As shown in the figure, the image size conversion device is configured such that the clock transfer units 31A-1, 31A-2, 31
B, 31C, horizontal filter sections 32-1, 32-2, memory selectors 33-1, 33-2, memory 34-
1, 34-2, a memory controller unit 35, flip-flops 36-1 and 36-2 with enable, and a vertical synchronization signal generation block 37. That is, in the circuit actually used, when handling the data of YUV422, the same circuit cannot be used for the horizontal filter due to the difference between Y and UV. Therefore, in this circuit, separate horizontal filter units 32-1 and 32-2 for Y data and UV data are prepared.
The two memories 34-1 and 34-2 are separately stored.

FIG. 11 shows a Y horizontal filter section 32-
1 shows the configuration and operation of No. 1, and FIG. 12 shows the configuration and operation of the horizontal filter unit 32-2 for UV. The illustrated example is a configuration example for sharing with the 1/4 scaler. Two flip-flops with enable 61, 62 are added to the horizontal filter for Y in order to have the same timing as the vertical filter. Further, in order to minimize the rounding error, this horizontal filter section does not perform rounding, but passes them to the vertical filter section as they are added (rounded by the vertical filter output). If you try to minimize the rounding error in this way, the memory size will increase by 1 bit, but if you want to minimize the circuit, if you give priority to it and round in the horizontal output, the memory size will be It can be reduced by 1 bit, and the entire memory can be reduced to 8 [bit] / 9 [bit].

Regarding the memories 34-1 and 34-2, taking into consideration the VGA size, 9 [bit] × 320.
Two [word] memories are used. Note that C
When using only IF, 9 [bit] x 176
A [word] memory size is sufficient. Further, the vertical filter sections (memory selectors 33-1 and 33-2) are configured as shown in FIG. 13, and the outputs of the horizontal filter sections 32-1 and 32-2 are set to 9 bits. To extend the bit. Also,
In FIG. 13, a changeover switch 71 for passing through the Y filter is provided. In addition, rounding (RN
D) Regarding the circuit 48, Y is a straight binary,
Since UV is a two's complement, the circuit configuration is different.

FIG. 14 is a block diagram showing a horizontal synchronizing signal generating circuit. This horizontal synchronizing signal generation circuit 80
It has counters 81 and 82 and a flip-flop 83,
By decoding the counter value for memory access, and by decoding the value corresponding to the effective pixel,
Effective area even if the blanking time changes (section of Hi)
Has a structure that does not change. FIG. 15 is a block diagram showing a vertical synchronizing signal generation circuit. This vertical synchronizing signal generation circuit is composed of a flip-flop 85,
By latching at the falling edge of the horizontal synchronizing signal, the constant effective area (Hi section) does not change even if the blanking time of the vertical synchronizing signal changes.

16 to 18 are detailed timing charts showing these operation timings. This timing chart illustrates the timing when the total number of horizontal pixels is 404. By using the image size conversion device as described above, it is possible to send data at a constant data rate while maintaining the frame rate, and the circuit configuration in the subsequent stage is simplified. For example, the clock from this circuit can be used later. In addition, since the clock has a fixed cycle, if you insert a code indicating the start and stop of the video area before and after the video data, enable is not required and the video data can be delivered with the minimum number of signal lines. .

FIG. 19 is a block diagram showing a modification of the image size conversion device according to this embodiment. This example
The two memories 34-1 and 34-2 shown in FIG.
One memory 3 of 8 [bit] x 320 [word]
This is changed to 4 '. With such a configuration, the memory size (address decoder part) can be reduced. FIG. 20 is a block diagram showing another modification of the image size conversion device according to the present embodiment. In this example, the order of the clock transfer unit 31 and the horizontal filter unit 32 shown in FIG. 4 is exchanged, and horizontal filtering is performed before the clock transfer.

[0021]

As described above, in the image size conversion device of the present invention, the pixel size is reduced to 1 / N without changing the frame period and the data rate by using the clock of N times the horizontal pixel number. can do. Therefore, for example, the clock from the image size conversion device can be used in the subsequent stage, and the circuit configuration in the subsequent stage can be simplified. Further, since the clock has a fixed cycle, by inserting a code indicating the start and stop of the video area before and after the video area, it is possible to transfer the video data with a small number of signal lines. further,
The memory can be realized by 1 / N of the horizontal effective pixel number, and the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a camera system to which an image size conversion device according to an embodiment of the present invention is applied.

FIG. 2 is a block diagram showing a camera signal processing unit of the camera system shown in FIG.

FIG. 3 is an explanatory diagram showing an image reduced by using the camera system shown in FIG.

4 is a block diagram showing a configuration of an image size conversion device provided in the camera system shown in FIG.

5 is a block diagram showing a configuration of a clock transfer unit of the image size conversion device shown in FIG.

6 is a block diagram showing a configuration of a horizontal filter unit of the image size conversion device shown in FIG.

7 is a block diagram showing a configuration of a memory selector of the image size conversion device shown in FIG.

8 is a block diagram showing a configuration of a memory controller unit of the image size conversion device shown in FIG.

9 is a simple timing chart showing the operation timing of the image size conversion device shown in FIG.

10 is a block diagram showing a configuration of the image size conversion device shown in FIG. 4 when it is actually used.

11 is a timing chart and a block diagram showing an operation and a configuration of a Y horizontal filter unit of the image size conversion apparatus shown in FIG.

12 is a timing chart and a block diagram showing an operation and a configuration of a UV horizontal filter unit of the image size conversion device shown in FIG.

13 is a block diagram showing a configuration of a vertical filter unit (memory selector) of the image size conversion device shown in FIG.

14 is a block diagram showing a horizontal synchronization signal generation circuit of the image size conversion device shown in FIG.

15 is a block diagram showing a vertical synchronization signal generation circuit of the image size conversion device shown in FIG.

16 is a detailed timing chart showing the operation timing of the image size conversion device shown in FIG.

17 is a detailed timing chart showing the operation timing of the image size conversion device shown in FIG.

18 is a detailed timing chart showing the operation timing of the image size conversion device shown in FIG.

FIG. 19 is a block diagram showing a modified example of the image size conversion device according to the embodiment of the present invention.

FIG. 20 is a block diagram showing another modification of the image size conversion device according to the embodiment of the present invention.

[Explanation of symbols]

10 ... Image sensor, 20 ... Camera signal processing unit, 21 ...
... Luminance signal processing unit, 22 ... Color signal processing unit, 23 ... Formatting unit, 24 ... Image size conversion device, 31A,
31A-1, 31A-2, 31B, 31C ... Clock transfer section, 32, 32-1, 32-2 ... Horizontal filter section, 33, 33-1, 33-2 ... Memory selector, 34, 34- 1, 34-2 ... Memory, 35 ...
Memory controller, 36 ... Flip-flop with enable, 37 ... Vertical sync signal generation block.

Claims (5)

[Claims] 1. An image size conversion apparatus for inputting video data, converting the size of the video data, and outputting the converted video data, wherein a clock transfer unit for transferring an input clock to an N (N ≧ 2) double speed clock, and a horizontal direction of the video data. A horizontal filter section for filtering the number of horizontal effective pixels, a memory of 1 / N words of the number of horizontal effective pixels, a switching section for switching the input to the memory, and a flip-flop with an enable. By doing so, the pixel size is reduced to 1 / N without changing the frame period and the data rate. 2. The number of pixels in an effective image area forming the total number of horizontal pixels of input image data + the number of pixels in a horizontal blanking period are 352 + 4n (n ≧ 1) in the CIF standard and 640 + 4n (n ≧ 1) in the VGA standard. ), The number of lines in the effective video area forming the total number of vertical lines + the number of lines in the vertical blanking period are 288 in the CIF standard.
+ 2m (m ≧ 1), VGA standard 480 + 2m (m ≧
The image size conversion apparatus according to claim 1, wherein the circuit configuration is minimized by defining 1). 3. An address counter of the memory is used to generate a horizontal synchronizing signal so that a horizontal synchronizing signal whose effective image area does not change even if the number of pixels in the horizontal blanking period of the total number of horizontal pixels is changed. The image size conversion device according to claim 1, further comprising a horizontal synchronization signal generation circuit to be created. 4. An effective image area even if the number of lines in the vertical blanking period of the total number of vertical lines is changed using the horizontal synchronization signal generated by the horizontal synchronization signal generation circuit and the input vertical synchronization signal. 4. The image size conversion device according to claim 3, further comprising a vertical synchronization signal generation circuit that generates a vertical synchronization signal that does not change. 5. The image size conversion apparatus according to claim 1, wherein the rounding error is minimized by increasing the bit size of the memory by 1 bit without rounding the output of the horizontal filter unit. .