JP2003258204A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, when a constitution of conventional function blocks is applied to a semiconductor memory of a cross point constitution, integration degree of a memory cell group having the cross point constitution of a word line and a bit line is lowered from a theoretical ideal integration degree, as a region for occupying a transistor is generally larger than an allowing interval between the bit line and the word line. <P>SOLUTION: The memory cell group block of the cross point constitution is controlled by divided right and left word line control blocks and divided upper and lower bit line control blocks and a switch group block. The word lines are alternatively sorted to right and left word line control blocks via the switch group, and the bit lines are alternatively sorted to bit line control blocks one by one via the switch group and connected. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called cross-point type memory semiconductor device in which a memory element is arranged in an overlapping portion of a word line and a bit line, and a word line and a bit line, and a word line control block and a bit line control. The present invention relates to a layout method of a block area efficient and a configuration of a method for improving the integration degree. Particularly, it relates to high integration of a nonvolatile memory using a ferroelectric material.

[0002]

2. Description of the Related Art A conventional semiconductor memory having a typical cross point, that is, a method of arranging a memory element at the intersection of a word line and a bit line in principle, has a DR shown in FIG.
Like AM (Dynamic Random Access Memory),
Insulated gate field effect transistor (hereinafter MOSFET)
Abbreviated) and a memory cell group composed of a memory element of a capacitor that stores electric charge of 1,0 information. In addition, as in a ROM (Read Only Memory) using the MOSFET transistor shown in FIG.
The information of 1,0 is used by using T, depending on whether the MOSFET is active or killed. In both cases, the memory element formed at the intersection of the cross points has a MOSFE
Was using T. FeRA this situation using a ferroelectric even ^E 2 PROM (electrically erasable programmable ROM)
The same applies to a non-volatile memory such as M (ferroelectric random access memory), and a MOSFET is used for a memory element configured at the intersection of cross points. In addition, as an example in which further improvements are made, Patent Publication 2001-273764
There is a method of controlling the word lines from above and below and the bit lines from the left and right as described above.

[0003]

In a semiconductor memory having a cross-point structure, which is a method of arranging a memory element at the intersection of a word line and a bit line in principle, from the viewpoint of increasing the degree of integration of the memory element, Ideally, the degree of integration of the memory cell group should be increased so that the word lines and bit lines are arranged as close as possible. However, MOSFETs are always used in the above-mentioned conventional semiconductor memories including the patent publication 2001-273764. MO
The basic structure of the SFET consists of a source and a drain made of diffusion layers, and a gate electrode made of polysilicon,
Since the signal line is connected to each by metal wiring such as aluminum, a space larger than the metal wiring of the word line and the bit line is required. Therefore, the aforementioned DRAM and RO
Since a conventional semiconductor memory such as M uses a MOSFET, there is a problem that the memory cell becomes larger than the ideal integration degree of the cross point configuration and the integration degree is reduced. Therefore, there is a problem that the cost increases when a large capacity memory is configured.

Further, even if an attempt is made to construct a memory with a high degree of integration without using MOSFETs in the memory cell area at the cross point, it is necessary to detect the stored signal from the memory element, and the signal detection circuit must detect it. Is MOSF
A large space is required for the circuit etc. by ET. The above situation will be described in a little more detail with reference to FIGS. 14, 17, and 18. FIG. 14 is a functional block layout diagram showing a configuration of a conventional semiconductor memory, which includes a memory cell block 140, a word line control block 141, and a bit line control block 142.
It shows the configuration of. Memory cell block 140
1 for each of the word line group and the bit line group of the memory cell group
It is controlled by the word line control block 141 and the bit line control block 142. In such a case, FIG. 17 is a circuit configuration diagram showing an outline of a part of the memory. In the figure, a portion surrounded by a broken line 170 is a cross-point memory cell group, in which each memory element is stored. The signal detection circuit 171 for detecting the 1 and 0 signals is shared by the bit lines 1771, 1772, 1773, 1774 and the like. In order to be shared, the changeover switches 1721, 1722, 1723, 1724 must be used.
Therefore, this switch is composed of MOSFETs. Therefore, as described above, the MOSF
The presence of ET makes the memory cell larger and the integration degree lower than the ideal integration degree of the cross point configuration.
There was a problem. That is, in FIG. 18, which is a pattern layout diagram in which the circuit of FIG. 17 is laid out, the switching MOSF is used when the sense amplifier for signal detection is shared.
Since the ETs 1721, 1722, 1723, 1724 are larger than the widths of the bit lines 1771, 1772, 1773, 1774, etc., the bit lines 1771, 1772, 1773,
The 1774s must be spaced apart. As a result, there is a problem that waste occurs in terms of area efficiency such that the memory cell is also expanded and configured.

Therefore, the present invention solves such a problem, and its purpose is to eliminate the decrease in the degree of integration due to the use of MOSFET and to effectively determine the layout of word lines and bit lines. It is an object of the present invention to provide a semiconductor memory in which the integration degree of memory cells is increased, the area efficiency is improved, and a large-capacity memory can be configured at low cost.

[0006]

A semiconductor memory device according to the present invention includes a memory cell block having a cross point structure and a first memory cell block.
And a second word line control block divided into two, a first and second two bit line control block divided into first, second, third and fourth switch group blocks, The first and second word line control blocks and the first and second switch group blocks sandwich the memory cell block having the Cron point configuration and sandwich the first word line control block and the first word line control block on the left side.
The switch group block is placed, the second word line control block and the second switch group block are placed on the right side, and every other word line is passed through the left and right first switch group blocks to the first word line control block and the second word line control block. Via the switch group block, the second word line control block is alternately connected and controlled. Further, the first and second bit line control blocks and the third and fourth switch group blocks sandwich the memory cell block having the Cron point configuration, and the first bit line control block and the third switch group block are provided on the upper side. The second word line control block and the fourth switch group block are placed on the lower side, and the first bit line control block and the fourth switch group block are passed through the upper and lower third switch group blocks with one bit line placed. And the second bit line control block is alternately divided and connected to control.

Further, when there are a plurality of memory cell blocks having a cross point structure, the word line control block located between the two memory cell blocks passes through the two switch group blocks and then the two first memory cell blocks. It is connected to both the memory cell block and the second memory cell block, and is switched by the two switch group blocks and used for signal control of the word lines of both the first memory cell block and the second memory cell block. It is characterized by the configuration.

Alternatively, when there are a plurality of memory cell blocks having a cross point structure, the bit line control block located between the two memory cell blocks passes through the two switch group blocks and then the two first memory cell blocks. Signal detection from both bit lines of the first memory cell block and the second memory cell block is performed by connecting to both one memory cell block and the second memory cell block and switching by the two switch group blocks. It is characterized by a configuration used for signal control including.

According to the above configuration of the present invention, every other word line group of the memory cell block is first divided into the first switch group block and the second switch group block and then connected. From the viewpoint of the switch group block and the second switch group block, only one is provided for every two word lines, so that there is a margin in layout, and a space for arranging switching MOSFETs can be created without waste. And
Since the signal that has passed through the first or second switch group block is input to the first or second word line control block, even if a relatively large number of circuit elements are required for complicated control regarding the word line, The switches can be shared by switching with the switches formed by MOSFETs in the first and second switch group blocks, and a relatively large number of circuit elements required for the complicated control of the word lines can be laid out without difficulty. .

Similarly, every other bit line group of the memory cell block is divided and connected to the third switch group block and the fourth switch group block, so that the third switch group block and the fourth switch group block are connected. From the perspective of the switch group block, only one bit line comes for every two bit lines, so there is room in the layout and there is no waste of switching MOS.
There is a space to put the FET. Since the signal that has passed through the third or fourth switch group block is input to the first or second bit line control block,
Even if a relatively large number of circuit elements are required for the signal detection sense amplifier and the read / write circuit, they can be shared by switching with the switch by the MOSFET in the first and second switch group blocks. A relatively large number of circuit elements required for detection sense amplifiers and read / write circuits can be laid out without difficulty.

With the above configuration, the degree of integration can be increased until the memory cell block at the cross point can be determined only by the layout of the word lines and the bit lines.

By dividing the memory cell block into a plurality of blocks and sharing the bit line control block or the word line control block located between them, the area efficiency of the integrated circuit chip as a whole can be improved.

As described above, when the memory cell block is formed by the cross points, the degree of integration is increased to the limit, and a large-capacity, low-cost semiconductor memory device is realized.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to Examples. FIG. 1 is a functional block layout diagram showing a first embodiment of the present invention. In FIG. 1, a region surrounded by a broken line 10 is a block of a memory cell group having a cross point structure in which a plurality of word lines and bit lines intersect. In the figure, a configuration example of 16 word lines and 16 bit lines is shown for simplification of description. 11 is a first word line control block,
Reference numeral 12 is a second word line control block. Reference numeral 13 is a first bit line control block, and 14 is a second bit line control block. 15 is a first switch group block,
16 is a second switch group block, 17 is a third switch group block, and 18 is a fourth switch group block. Both the first switch group block 15 and the second switch group block 16 input the word line of the memory cell block 10. However, the first word line of the memory cell block 10 is input to the first switch group block 15 on the left side from the top, the second line is input to the second switch group block 16 on the right side, and the third line is the first line on the left side. The word line of the memory cell block 10 is connected to the first switch group block 15 and the second switch group block 16 such that the fourth switch is input to the switch group block 15 and the fourth switch is input to the right side second switch group block 16.
The signals are alternately input to the switch group block 16. The signal that has passed through the first switch group block 15 is input to the first word line control block 11, and the signal that has passed through the second switch group block 16 is input to the second word line control block 12. Therefore, the first word line control block 1
The first and second word line control blocks 12 alternately control the word lines of the memory cell block 10 for each word line. The third switch group block 17 and the fourth switch group block 18 both input the bit line of the memory cell block 10. However, the bit lines of the memory cell block 10 are sequentially input from the left, the first to the lower third switch group block 17, the second to the upper fourth switch group block 18, and the third to the lower side. The bit lines of the memory cell block 10 are input to the third switch group block 17 and the fourth switch group block 18 on the upper side. Are being input alternately. The signal passed through the third switch group block 17 is input to the first bit line control block 13, and the signal passed through the fourth switch group block 18 is input to the second bit line control block 14. Therefore, the first bit line control block 1
3 and the second bit line control block 14 alternately control the bit lines of the memory cell block 10 for each bit line.

With the above configuration, the memory cell block 1
The control of each memory element of 0 is controlled by the first word line control block 1
The first, second word line control block 12, the first bit line control block 13, and the second bit line control block 14 share the control. That is, each memory element at the lattice points marked with black circles shown in FIG. 2 is performed by the first word line control block 11 and the first bit line control block 13. Further, each memory element of the lattice points marked with black circles shown in FIG. 3 is performed by the second word line control block 12 and the first bit line control block 13. Further, each memory element of the lattice points marked with black circles shown in FIG. 4 is performed by the first word line control block 11 and the second bit line control block 14. Further, each memory element at the lattice points marked with black circles shown in FIG. 5 is performed by the second word line control block 12 and the second bit line control block 14. Now, a more detailed situation of the block 10 of the memory cell group having the cross point configuration will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 6 is a circuit diagram showing a circuit configuration of a part of the memory cell group. Reference numeral 60 is a capacitor having ferroelectric characteristics, 61, 62, 63 and the like are word line groups, and 65, 66, 67 and the like are bit line groups. That is,
A nonvolatile memory having a capacitor structure is formed at the intersection of the word line and the bit line. 7 and 8 show the above with actual shape patterns. FIG. 7 is a plan view of the memory cell group having the cross point configuration as viewed from above. In FIG. 7, reference numerals 61, 62, and 63 are metal wirings made of aluminum that form word lines. Reference numerals 65, 66 and 67 are metal wirings made of aluminum which form bit lines. FIG. 8 is a cross-sectional view of the memory cell group having the cross point structure. In FIG. 8, reference numeral 61 is a metal wiring made of aluminum that forms a word line. Reference numerals 65, 66 and 67 are metal wirings made of aluminum which form bit lines. For example, PZT is provided at each intersection of the word line 61 and the bit lines 65, 66, 67.
A ferroelectric material 80 such as (lead zirconate titanate) is formed. The capacitor having the ferroelectric substance shown in FIG. 8 exhibits hysteresis characteristics such as 91 and 92 shown in FIG. 9 in the relationship between the voltage V applied to both ends and the polarization charge Q, which differs depending on the history of how the voltage is applied. It becomes an element. From the above, FIG. 1 has a nonvolatile ferroelectric memory element at each intersection of a word line and a bit line, and has two word line control blocks 11 and 12 divided into left and right and two bit lines divided into upper and lower. It is a semiconductor memory having a cross-point configuration with control blocks 13 and 14. Next, the features of this configuration will be further described. The above configuration is shown in FIG. 10 for the boundary portion between the memory cell group having the cross point configuration and the bit line control block. FIG. 10 is a schematic circuit diagram partially showing only the structure of the boundary between the memory cell group, the switch group block and the bit line control block. In FIG. 10, reference numeral 100 shown by a broken line box is a memory cell group having a cross point structure, and 1071, 1072, 1073, 1074, etc. are bit lines. 1021, 1022, 1023, 1024
Are switches belonging to the switch group block. Reference numeral 101 is a part of a bit line control block including a signal detection circuit that detects a signal that is information of each memory from a bit line, a writing circuit that writes data in the memory, and the like.
Since the signal detection circuit as an example included in the partial circuit 101 of the bit line control block requires a relatively large number of circuit elements, it cannot be individually arranged for each bit line, and the signal detection circuit for each bit line cannot be used. Multiple, 4 in Figure 10
Also serves as a shared circuit for books. Therefore, the changeover switches 1021, 1022 in the switch group block,
1023 and 1024 are required. In addition, 1081, 1082, 1083 on the opposite side of the memory cell group 100,
1084 and the like are bit lines. 1041, 1042, 1
Reference numerals 043 and 1044 denote switches belonging to the switch group block. Reference numeral 103 is a part of a bit line control block including a signal detection circuit that detects a signal that is information of each memory from a bit line, a writing circuit that writes data in the memory, and the like. Partial circuit 103 of bit line control block
The signal detection circuit as an example includes a circuit switch which requires a relatively large number of circuit elements and therefore is also used.
21, 1022, 1023, 1024 are required.

FIG. 11 is a layout pattern layout diagram showing the circuit diagram of FIG. 10 in an actual shape. In FIG. 11, there is a memory cell group in the area of the broken line 100, but details are omitted for simplification. 1071, 1072, 1
073, 1074, and 1081, 1082, 108
Bits 3 and 1084 respectively correspond to the bit lines having the same numbers in FIG. 1021, 1022,
1023, 1024 and 1041, 1042, 104
Reference numerals 3 and 1044 are changeover switches formed by MOSFETs and correspond to the respective switches having the same numbers in FIG. Although the bit line control block including the signal detection circuit is not shown in FIG. 11, the partial circuit 1 of the bit line control block including the signal detection circuit and the like is provided before the aluminum wiring 115.
01, and there is a partial circuit 103 of the bit line control block including a signal detection circuit and the like in front of the aluminum wiring 116. Now, the switch groups 1021, 1022, 1023, 102
4 incoming bit lines 1071, 1072, 107
3, 1074 have a relationship of every other one. Also, the bit lines 1081, 1082, 1083, 10 coming into the switch groups 1041, 1042, 1043, 1044.
84 are also in relation to each other. Therefore, each M that constitutes a switch has a width larger than the width of the bit lines arranged in a fine density.
Even if the OSFET requires a large space, only one bit line comes every other space, so that a space can be provided and the arrangement as shown in FIG. 11 can be taken. In the area of the memory cell group 100, the bit lines are 1074, 10
84, 1073, 1083, 1072, 1082, 10
71 and 108 are arranged side by side, and the bit line 107
They are arranged at a density twice as large as the intervals of 1, 1072, 1073, and 1074. Therefore, the cross-point memory cell group 100 shown in FIGS. 6, 7, and 8 can increase the degree of integration of the memory device up to the upper limit of the constraint allowed in the process shape of the bit line and the word line. It is possible to increase the integration degree to at least twice in the bit line direction by at least the conventional layout method shown in FIG.

Although the bit line side has been described above, the same technique can be applied to the word line side. By adopting the layout method of FIG. 1 in which the same method is applied to word lines, the integration density can be increased to four times in total.

As described above, the essence of the present invention is to arrange a word line control block and a bit line control block separately on the left and right sides and on the upper and lower sides to make a margin in the layout, and
By providing a switch group of MOSFETs that can be arranged in that region and sharing a control circuit including a signal detection circuit via the switch, it is possible to reasonably increase the degree of integration of the memory cell group. Therefore, it is not limited to the above-mentioned first embodiment.

For example, FIG. 1 shows an example of 16 word lines and 16 bit lines, but 64 or 128 lines are used.
It may be a book, or more or less. Also,
The factorial does not have to be two.

The number of word lines and the number of bit lines do not have to be the same.

The method of dividing the control block only on the bit line side may be applied, or it may be applied only on the word line side.

In the above, the material of the ferroelectric substance is P
Although described with respect to ZT, SBT (SrSi ₂ Ta ₂ O ₉ ) or other ferroelectric material may be used.

Further, not only an inorganic material but also an organic material may be used as long as it exhibits ferroelectric characteristics.

Further, since the essence of the present invention is a layout method that makes use of highly integrated memory elements, it may be used in a read-only ROM configuration even if it is not a RAM element using a ferroelectric memory as described above.

Further, even if it is not a memory element made of a ferroelectric material having a structure as shown in FIG. 8, it is also suitable and effective for a ROM having a diode matrix structure which is highly integrated with a cross point memory structure.

Further, although the case where the memory cell block is a single block has been described above, the same applies to the case where the memory cell block is a plurality of blocks.

FIG. 12 is a functional block layout diagram showing an embodiment when there are at least two memory cell blocks. In the figure, 1201 and 1202 are memory cell blocks. 1211, 1212, 1221, 1
222 is a word line control block. 1231, 12
32 and 1241 are bit line control blocks.

1213, 1214, 1223, 122
Reference numerals 4, 1233, 1234, 1243, and 1244 are switch group blocks. Here, the bit line control block 1
Reference numeral 231 controls both of the bit line groups of the memory cell block 1201 and the memory cell block 1202 by switching them by using the switch group blocks 1244 and 1233 and sharing them. In the case of sharing in this way, the space of two bit line control blocks can be almost the space of one bit line control block only by the increase of one switch group block that occupies a relatively small area. As a result, the occupied area can be made more efficient and the degree of integration can be improved.

FIG. 13 is a functional block layout diagram showing an embodiment in the case where at least two memory cell blocks exist and the word line control block is shared. In the figure, 1301 and 1302 are memory cell blocks. Reference numerals 1311, 1321, and 1322 are word line control blocks. 1341, 1342, 133
Reference numerals 1 and 1332 are bit line control blocks. 131
3, 1314, 1323, 1324, 1333, 133
4, 1343 and 1344 are switch group blocks.
The memory cell block 1301 is the word line control block 1
It is controlled by 311 and 1321. Memory cell group 1
302 is controlled by word line control blocks 1322 and 1321. Here, the switch group block 1314
The bit line control block 1321 is shared by the switching circuit of 1323 and 1323. With the above sharing, the occupied area can be made more efficient and the degree of integration can be improved.

[0029]

As described above, according to the present invention, there is an effect that the degree of integration of the memory cell group in the semiconductor memory device having the cross point structure can be increased to the degree of integration determined by the layout of the word lines and the bit lines.

Therefore, there is an effect that a large-capacity semiconductor memory device can be realized at low cost.

Further, since the word line control block and the bit line control block are separately arranged, the operating circuits are spatially dispersed, the noise intensity is lowered, and the malfunction does not easily occur. .

Even if the word line control block and the bit line control block are divided, the word line control block and the bit line control block can be shared when there are a plurality of memory cell blocks, so that the area occupied by these blocks is increased. Instead, there is an effect of increasing the integration degree of the memory cell group.

[Brief description of drawings]

FIG. 1 is a functional block layout diagram showing a first embodiment of the present invention.

FIG. 2 is a functional block layout diagram for explaining the configuration of the first exemplary embodiment of the present invention.

FIG. 3 is a functional block layout diagram for explaining the configuration of the first exemplary embodiment of the present invention.

FIG. 4 is a functional block layout diagram for explaining the configuration of the first exemplary embodiment of the present invention.

FIG. 5 is a functional block layout diagram for explaining the configuration of the first exemplary embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a cross-point memory cell group in an example of the present invention.

FIG. 7 is a plan view showing a configuration of a cross-point memory cell group in an example of the present invention.

FIG. 8 is a cross-sectional view showing the configuration of a cross-point memory cell group in an example of the present invention.

FIG. 9 is an electrical characteristic diagram of a nonvolatile memory element according to an example of the present invention.

FIG. 10 is a circuit diagram showing a relationship between a memory cell group and a bit line control block according to an embodiment of the present invention.

FIG. 11 is a layout pattern layout diagram showing the relationship between the memory cell group and the bit line control block in the embodiment of the present invention.

FIG. 12 is a functional block layout diagram showing sharing of bit line control blocks in the second embodiment of the present invention.

FIG. 13 is a functional block layout diagram showing sharing of word line control blocks in the third embodiment of the present invention.

FIG. 14 is a functional block layout diagram showing a configuration of a conventional semiconductor memory.

FIG. 15 is a functional block layout diagram showing a configuration of a DRAM which is an example of a conventional semiconductor memory.

FIG. 16 is a functional block layout diagram showing a configuration of a ROM that is an example of a conventional semiconductor memory.

FIG. 17 is a circuit configuration diagram showing a relationship between a memory cell group and a bit line control block of a conventional semiconductor memory having a cross point configuration.

FIG. 18 is a layout pattern layout diagram showing a relationship between a memory cell group and a bit line control block of a conventional semiconductor memory having a cross point structure.

[Explanation of symbols]

10, 1201, 1202, 1301, 1302, 14
0 ... Memory cell blocks 11, 12, 1211, 1212, 1221, 122
2, 1311, 1321, 1322, 141 ...
Word line control blocks 13, 14, 1231, 1232, 1241, 133
1, 1332, 1341, 1342, 142 ...
Bit line control blocks 15, 16, 17, 18, 1213, 1214, 122
3, 1224, 1233, 1234, 1243, 124
4, 1313, 1314, 1323, 1324, 133
3, 1334, 1343, 1344 ... Switch group block 60 ... Non-volatile memory elements 61, 62, 63, 152, 153, 154, 162,
163, 164 ... Word lines 65, 66, 67, 155, 156, 157, 165,
166, 167, 1071, 1072, 1073, 10
74, 1081, 1082, 1083, 1084, 17
71, 1772, 1773, 1774 ... Bit line 80 ... Ferroelectric material 91, 92 ... Dielectric charge characteristic against voltage 100, 170 ... Memory cell group 101, 103 ... Bit line control block Partial circuit 171 ... Signal detection circuits 115, 116 ... Signal wiring to partial circuits of the bit line control block 1021, 1022, 1023, 1024, 1041,
1042, 1043, 1044, 1721, 1722,
1723, 1724 ... Signal changeover switch 150, 160 ... MOSFET 151 ... Capacitor

Claims (5)

[Claims] 1. A semiconductor integrated circuit device having a memory having a cross-point structure, a memory cell block having a cross-point structure including a word line group and a bit line group, first and second word line control blocks, first, It is composed of a second bit line control block and first, second, third and fourth switch group blocks, and the word line group of the memory cell block is every other word line group of the first and second switch group blocks. To the first word line control block, and the signal line that passes through the second switch group is input to the second word line control block. The signal line is input to the block, and the bit line group of the memory cell block is alternately input to the third and fourth switch group blocks every other line, and the signal line that passes through the third switch group. Is input to the first bit line control block, the signal line passing through the fourth switch group is input to the second bit line control block, and the first and second word line control blocks are The first and second bit line control blocks are located on both sides of the memory cell block having the cross point configuration in the first direction, and the first and second bit line control blocks are provided in the second direction with the memory cell block having the cross point configuration interposed. A semiconductor memory device which is located on both sides, and wherein the first and second directions are directions orthogonal to each other. 2. A semiconductor memory device comprising a plurality of memory cell blocks according to claim 1. 3. A semiconductor memory device, wherein an insulated gate field effect transistor is used in the switch group block according to claim 1. 4. A semiconductor memory device according to claim 1, wherein the memory element of the memory cell block comprises a non-volatile memory. 5. The semiconductor memory device according to claim 4, wherein the nonvolatile memory uses a ferroelectric material.