JP2003256357A - Data processing apparatus and method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processing apparatus and method therefor capable of effectively transferring data. <P>SOLUTION: First of all, a CPU sends out a start address from an address bus to a memory during time t0 corresponding to 1 clock. In that case, an amount of transfer data indicating an amount of data to be sent out therefrom is sent out to a data bus. In the following time (T1), data (D0) are sent out to the data bus, and the data obtained by dividing the next data (D1) of the data (D0) into one-half are sent out to the address bus. In the following time (T2), the rest of the divided data is sent out to the address bus, and the next data (D2) of the data (D1) are sent out to the data bus. In this way, three words (data) are transferred by two clocks. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device and a data processing method for exchanging data between a central processing unit and a processed device such as a memory. In particular, the present invention relates to a data processing device and a data processing method capable of efficiently transferring data.

[0002]

2. Description of the Related Art Up to now, CPU (Central Processing)
Unit) or MPU (Micro Processing Unit) and a central processing unit, ROM (Read Only Memory) or RA
When data is transferred to or from a memory (device to be processed) such as M (Random Access Memory), the target address is sent to the address bus for each data, and the memory etc. receiving this stores it at the specified address. The data being sent was being sent.

FIG. 3 is a diagram showing a conventional data processing device between a CPU and a memory. FIG. 3 shows a CPU 101 that performs predetermined arithmetic processing and a memory 102 connected to the CPU 101. CPU 101 and memory 10
A 32-bit address bus, a 64-bit data bus, a CS (Chip Select) signal line, and an R / W (R
An ead / Write) signal line and a CNT (count) line are provided.

FIG. 4 is a diagram showing an example of a data processing method when data is transferred using the above-described data processing device. In FIG. 4, first, the CPU 101 sends the address (A0) from the address bus to the memory 102 during the time (T0) corresponding to one clock. At this time, the data (D0) designated by the address (A0) is sent to the data bus. After that, during the time (T1 to T5) corresponding to one clock, the address bus has addresses (A1 to A5) and the data bus has addresses (A1 to A5).
The data (D1 to D5) designated by is transmitted. In this way, one word (data) can be transferred in one clock, so in order to transfer 32 words of data,
Conventionally, 32 clocks are required.

[0005]

When a large amount of data is exchanged between the central processing unit and the memory, relatively continuous data such as cache update is exchanged in block units. Often. In that case, basically, by knowing the start address and the transfer amount, the central processing unit notifies the memory of the address for each data. It was hanging.

Various modes have been proposed for data transfer, but basically, the transfer data amount is limited by the width of the data bus for data transfer.

The present invention has been made in view of such a problem, and an object thereof is to provide a data processing device and a data processing method capable of efficiently transferring data.

[0008]

In order to solve the above-mentioned problems, a data processing apparatus of the present invention comprises a central processing unit which realizes a predetermined function, and an apparatus to be processed connected to the central processing unit. An address bus and a data bus provided between the central processing unit and the processed device, and a division provided in each of the central processing unit and the processed device for dividing / combining data into a predetermined amount And a coupling circuit, wherein both split coupling circuits are connected via the address bus.

A data processing method of the present invention is a data processing method for transferring data between a central processing unit and a processing target device connected to the central processing unit, wherein the central processing unit An address provided between the central processing unit and the processed device while transferring the data through a data bus provided between the device and the processed device and dividing the data into a predetermined amount. It is characterized by transferring data via a bus.

In the data processing method, when the data is transferred, it is preferable to first transfer the start address of the data and the transfer data amount of the data to the device to be processed.

As described above, according to the data processing device and the data processing method of the present invention, data can be transferred efficiently by exchanging data via the address bus.

[0012]

DETAILED DESCRIPTION OF THE INVENTION A description will be given below with reference to the drawings. FIG. 1 is a diagram showing a data processing device according to an embodiment of the present invention. Hereinafter, as an example, data processing between the CPU and the memory will be described. A central processing unit and a PCI (Peripheral Component Interconnect)
Data processing with peripheral devices (devices to be processed) such as slots, video cards, graphic accelerators, and network cards can be performed in the same manner.

FIG. 1 shows a CPU 1 which performs a predetermined arithmetic processing.
And the memory 2 connected to the CPU 1 is shown. C
A 32-bit address bus, a 64-bit data bus, a CS (Chip Select) signal line, an R / W (Read / Write) signal line, and a CNT (coun) are provided between the PU 1 and the memory 2.
t) line is provided. Inside the CPU 1 and the memory 2, there is provided a circuit for dividing 64-bit data into 32 bits, transferring them via an address bus, and then re-combining them to recognize 64-bit data. Note that here, 64-bit data is divided and combined into 32 bits, but the data amount and the division amount are not limited to this.

FIG. 2 is a diagram showing an example of a data processing method when data is transferred using the above-described data processing device. In FIG. 2, first, the CPU 1 sends the start address from the address bus to the memory 2 during the time (T0) corresponding to one clock. At that time, the transfer data amount indicating the amount of data to be transmitted is transmitted to the data bus. At the next time (T1), data (D0) is sent to the data bus and data (D0) is sent to the address bus.
The data (D1) next to 0) is transmitted in half. At the next time (T2), the remaining data of the data (D1) sent at the time (T1) divided in half is sent to the address bus. Also, at that time,
The data bus (D1) is followed by the next data (D2).
Is sent.

At the next time (T3), the data (D3) next to the data (D2) is sent to the data bus, and the data (D4) next to the data (D3) is divided in half into the address bus. Things are sent out. At the next time (T4), the data (D4) sent at the time (T3) is divided in half, and the remaining data is sent to the address bus. At that time, the data (D4) is written on the data bus.
The next data (D5) is transmitted.

The above times (T1, T2), (T3, T
As in 4), three data (words) are transmitted in two clocks. In this way, since 3 words (data) can be transferred in 2 clocks, in order to transfer and receive 32 words of data, 1 clock for setting the start address and transfer amount and 21 clocks for sending data are used. Total 2
It takes 2 clocks.

[0017]

As is apparent from the above description, according to the present invention, data can be transferred efficiently by exchanging data via the address bus.

[Brief description of drawings]

FIG. 1 is a diagram showing a data processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a data processing method when performing data transfer using the above-described data processing device.

FIG. 3 is a diagram showing a conventional data processing device between a CPU and a memory.

FIG. 4 is a diagram showing an example of a data processing method when performing data transfer using the above-described data processing device.

[Explanation of symbols]

1 CPU 2 memory

Claims (3)

[Claims] 1. A central processing unit that realizes a predetermined function, a processing target device connected to the central processing unit, an address bus provided between the central processing unit and the processing target device, and A data bus, and a split / coupling circuit provided in each of the central processing unit and the processing target device for splitting / combining data into a predetermined amount. A data processing device characterized by being connected. 2. A data processing method for transferring data between a central processing unit and a processing target device connected to the central processing unit, the central processing unit and the processing target device. The data is transferred via a data bus provided between the central processing unit and the processing target device, and the data is divided into a predetermined amount and the data is transferred via an address bus provided between the central processing unit and the processed device. A data processing method characterized by transferring. 3. The data processing method according to claim 2, wherein when the data is transferred, first, a start address of the data and a transfer data amount of the data are transferred to the device to be processed.