JP2003256355A - Dma control device, printing unit, and dma control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DMA control device, a printing unit, and a DMA control method capable of transmitting DMA at high speed and in proportion to an optional transmitting size on a bus in which an USB packet is capable of burst- transmitting when an optional size of the USB packet is fed from an exterior device. <P>SOLUTION: In the DMA controller 102 in which the USB packet data received from a host system 2 by an USB interface 103 performs DMA transmitting to a memory 101 on the data transmitting bus 105, a plurality of transmitting modes are provided as a DMA transmitting mode to the memory 101 on the data transmitting bus 105. Based on the values showing a size of the USB packet data and a data width of the data transmitting bus 105 obtained from the USB interface 103, the DMA transmitting mode of the USB packet data is controlled. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a DMA control device, a printing device, and a DMA control method for performing DMA transfer control for an interface, and more particularly to a US Pat.
DM suitable for performing DMA transfer control for USB bulk-out transfer endpoint provided in B interface
The present invention relates to an A control device, a printing device, and a DMA control method.

[0002]

2. Description of the Related Art Conventionally, DMA (Direct Memory Access)
The transfer control device controls data transfer from a data transfer source (source) to a data transfer destination (destination), and stores a data transfer source address, a data transfer destination address, and a data transfer amount in a predetermined storage area ( Generally, by setting the register in the setting register) and then controlling the start of data transfer from the processor or the like, the DMA transfer control device does not need individual data transfer control by the processor at the time of actual data transfer. Performs data transfer control. Then, when the data transfer of the set amount is completed, the DMA transfer completion interrupt is asserted. By asserting the DMA transfer completion interrupt, the processor reads / writes a memory area that reports the result of the data transfer amount that actually completes the data transfer and a memory area that reports the status (error, success, etc.) of the DMA transfer, and performs the DMA transfer. Monitor the performance of.

Further, in the case of DMA data transfer, a burst transfer function of data (a plurality of byte data are collectively transferred by continuous use of a bus cycle) in a data bus used by a DMA transfer controller for speeding up. Function) is often provided.

In a USB (Universal Serial Bus) interface, USB bulk transfer that guarantees accurate data transfer is normally used for printers. U
There are two types of SB bulk transfer depending on the transfer direction: bulk-out transfer (USB host (mainly PC) → USB device (printer)) and bulk-in transfer (USB host ← USB device). In the configuration of the bulk-out transfer endpoint of the USB device, the USB device is generally configured to read data for each USB packet.

[0005]

In a general USB device, the maximum packet size for one packet in bulk-out transfer is 64 in the USB1.1 specification.
Bytes, 512 bytes in the USB 2.0 specifications, and data can be read from the USB device for each packet. That is, the data that can be read from the USB device is 0 bytes to the maximum packet size (64 bytes in the USB1.1 specification,
In the 2.0 specification, it is 512 bytes).

The upper protocol layer of the USB of the printer is IEEE (Institute of Electrica).
l and Electronics Engineers) P1284.4 communication standards and standards established by each printer manufacturing company. In IEEE P1284.4, it is possible to determine the data transfer size even when performing the DMA transfer, by the header information that defines the data transfer size passed from the upper protocol layer. On the other hand, there are cases in which there is no method for the host side to determine the size of the data to be output to the printer in the standards and the like that are independently established by each printer manufacturing company. In this case, the USB packet is a so-called short packet that contains data that is less than the maximum packet size.

When the DMA transfer control device and the USB interface are combined to perform the DMA transfer control for the printer, the DMA transfer control device uses the burst transfer function provided by the data bus for the data transfer in order to speed up the data transfer. There is a case. However, even when the data bus provides the burst transfer function, there is a problem that the transfer size is limited due to the limited setting items, and it is not possible to transfer only data of an arbitrary size.

In view of the above problems, the present invention provides a high-speed and arbitrary transfer size of a USB packet on a bus capable of burst transfer even when a USB packet of an arbitrary size is transmitted from an external device. A DMA control device, a printing device, and a D device capable of performing DMA transfer according to
An object is to provide an MA control method.

[0009]

In order to achieve the above object, the present invention provides a DMA control device for performing DMA transfer of USB packet data received from the outside by a USB interface control device to a device on a bus. It has a plurality of transfer modes as a DMA transfer mode to a device on a bus, and based on a value indicating the size of the USB packet data and the data width of the bus acquired from the USB interface control device, It is characterized by having a control means for controlling the DMA transfer mode.

Further, according to the present invention, the printing apparatus uses the DMA.
A control device, the USB interface control device, the bus, a storage unit for DMA transfer of the USB packet data, and a printing unit for printing an image on a medium are characterized.

Further, the present invention is a DMA control method for performing DMA transfer of USB packet data received from the outside by a USB interface control device to a device on a bus, wherein a plurality of DMA transfer modes for the device on the bus are used. And the DMA transfer mode of the USB packet data is controlled based on the size of the USB packet data acquired from the USB interface controller and the value indicating the data width of the bus. .

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a system including a printer USB interface DMA transfer control device (DMA controller) according to an embodiment of the present invention. The system includes a printer device 1 including a printer controller device 10 and a printer engine device 11,
The host device 2 includes an application 20.

To explain the above-mentioned configuration in detail, the printer device 1
Is a device configured to include a printer engine device 11 and a printer controller device 10, and is a device that receives a print request from the host device 2 by an operation of a user 3 and prints an image on a paper medium. Printer engine device 11
Forms an image, and is configured as a laser beam printer engine that forms an image on a photosensitive drum by a laser beam and transfers toner. The printer controller device 10 is the printer device 1.
It is a controller that controls the printer engine device 11 incorporated in the main body. The host device 2 is, for example, Mi
It is configured as a PC (personal computer) equipped with Windows (registered trademark) XP, which is an OS of crosoft. Further, the printer device 1 and the host device 2 are connected via a USB cable 4.

FIG. 2 shows a printer device 1 according to this embodiment.
2 is a block diagram showing the configuration of the printer controller device 10 of FIG. The printer controller device 10 includes a CPU 1
00, memory 101, DMA controller 102, US
B interface 103, engine interface 10
4 and a data transfer bus 105.

The above-mentioned configuration will be described in detail. The USB interface 103 is connected to the host device 2 via the USB cable 4, and a USB transmitted from the host device 2 is transmitted.
It is composed of a USB bulk out endpoint 1030 for temporarily storing packets and a USB device controller 1031 for controlling communication with the host device 2. Further, the USB device controller 1031 detects the size of the USB packet received from the host device 2 and outputs the received packet size information signal 1034 to the DMA controller 102.

The memory 101 depends on how it is used.
USB buffer area 10 to which print data is DMA transferred
10, a page buffer area 1011 for holding the created drawing data, and an image processing area 1012 used for creating the drawing data. The engine interface 104 is an interface with the printer engine device 11. The CPU 100 is the DMA controller 10
2, the DMA transfer destination address is set, the DMA transfer amount is set, and the DMA transfer start instruction is controlled. The data transfer bus 105 includes a CPU 100, a memory 101, a DMA
It is a data transmission path that connects the controller 102 and the engine interface 104, and is configured to be capable of burst transfer.

FIG. 3 shows a printer device 1 according to this embodiment.
3 is a block diagram showing a configuration of a DMA controller 102 of the printer controller device 10 of FIG. The DMA controller 102 uses the DMA transfer destination address register 102.
0, DMA transfer amount setting register 1021, DMA control register 1022, bus transfer counter 1023, DMA control sequencer 1024, FIFO (First In First Ou)
t) The memory 1025.

To explain the above configuration in detail, the DMA controller 102 instructs the data transfer bus 105 to use the bus use request signal 1050, the bus use permission signal 1051, the bus use start signal 1052, and the data acknowledge signal 105.
3, transfer direction signal 1054, burst transfer request signal 10
55, byte enable signal 1056, address signal 1
057 and the data signal 1058 are used to control the DMA transfer. Further, the DMA controller 102 notifies the CPU 100 of the completion of the DMA transfer by using the DMA transfer completion interrupt signal 1026. USB interface 103
Requests the DMA controller 102 to start the DMA transfer by the DMA transfer request signal 1032, and sends the DMA transfer acknowledge signal 1033 and the USB packet data 1
According to 035, the USB packet is transferred to the DMA controller 102. The USB interface 103
The DMA controller 1 determines the size of the received USB packet by the received packet size information signal 1034.
02 is notified.

A DMA transfer destination address is set in the DMA transfer destination address register 1020. A DMA transfer amount is set in the DMA transfer amount setting register 1021. The DMA control register 1022 is operated by the CPU 100 at the start of DMA transfer. Bus transfer counter 1
The received packet size information signal 1034 is set in 023. The DMA control sequencer 1024 starts a DMA transfer operation by operating the DMA control register 1022. The packet data that has been received is read into the FIFO memory 1025.

Next, the printer controller device 10 of the printer device 1 according to the present embodiment configured as described above.
1 will be described in detail with reference to FIGS.

FIG. 4 is a flow chart showing an outline of a data flow from the printer device 1 receiving a print request from the host device 2 to the transfer of print data to the memory 101 in the printer controller device 10. 2 and 3
The flow of processing relating to data transfer control in the printer device 1 will be specifically described with reference to FIG.

Step S1: Now, it is assumed that the host device 2 is instructed by the user 3 to process the printing of the application data. Accordingly, the host device 2
Creates print data. Here, it is assumed that the print data is a display list prepared by host rendering, but LIPS (registered trademark) (LBP ImagePr) is used.
It may be data described in a page description language such as an Ocessing System), Post Script (registered trademark), PDF (registered trademark) (Portable Document Format file), or the like. After this processing, the process proceeds to step S2.

Step S2: The print data created by the host device 2 in step S1 is transferred to the printer device 1 via the USB interface 103. In the case of USB1.1 specifications, a USB packet of 64 bytes or less is sent from the host device 2 to the printer device 1.
In case of 0 specification, a USB packet of 512 bytes or less
It is assumed that the USB bulk transfer is performed during one USB bulk transfer. After this processing, the process proceeds to step S3.

Step S3: USB interface 1 of the printer controller device 10 of the printer device 1 to which the USB packet is transferred from the host device 2 in step S2
03 from the USB bulk out endpoint 1030 in the memory 03 according to an instruction from the DMA controller 102.
Print data in the USB buffer area 1010 in 01
MA is transferred. After this processing, the process proceeds to step S4.

Step S4: The CPU 100 of the printer controller device 10 of the printer device 1 uses the memory 101
Drawing data is created using the print data transferred to the internal USB buffer area 1010. The CPU 100 uses the image processing area 1012 in the memory 101 in the drawing data creation process. The created drawing data is held in the page buffer area 1011 in the memory 101.
After this processing, the process proceeds to step S5.

Step S5: The CPU 100 of the printer controller device 10 of the printer device 1 judges whether the drawing data for one page is completed. When the drawing data for one page is completed, the process proceeds to step S6. 1
If the drawing data for the page is not completed, the process returns to step S2.

Step S6: A page buffer area 1 in the memory 101 holding drawing data for one page
The drawing data is transferred from 011 to the engine interface 104. After this processing, the process proceeds to step S7.

Step S7: The drawing data is transferred from the engine interface 104 of the printer controller device 10 to the printer engine device 11, and an image is formed on a paper medium.

5 and 6 are flowcharts showing the DMA transfer control of the DMA controller 102 of the printer controller device 10 of the printer device 1 in step S3 of FIG. The DMA controller 1 will be described with reference to FIGS.
The mechanism of the 02 DMA transfer control will be specifically described.

In this embodiment, the USB 2.0 specification is taken as an example, but it may be compliant with the USB 1.1 specification. In the present embodiment, the bus of the data transfer bus 105 is 32 bits (4 bytes) wide, write control is performed by the byte enable signal 1056, and burst transfer control is performed by the burst transfer request signal 1055. In one burst transfer, it is assumed that eight consecutive 4-byte transfers are performed. That is,
The burst transfer size is 32 bytes. Therefore, in one bus transaction of the data transfer bus 105,
It is assumed that there are four transfer sizes of 1 byte, 2 bytes, 4 bytes, and 32 bytes. Further, it is assumed that a value from 0 to 4096 can be set in the DMA transfer amount setting register 1021. Further, in the present embodiment, it is based on the USB 2.0 specification, and it is assumed that the maximum packet size of the USB bulk-out endpoint 1030 is 512 bytes.

Step S301: In the printer controller device 10 of the printer device 1, the CPU 100 sets D
For the MA controller 102, the DMA transfer destination address is set in the DMA transfer destination address register 1020,
The DMA transfer amount is set in the DMA transfer amount setting register 1021, and the DMA control register 1022 is operated to set the DMA transfer amount.
Start the transfer. By operating the DMA control register 1022, the DMA control sequencer 1024 starts its operation. After this processing, the process proceeds to step S302.

Step S302: USB bulk-out endpoint 1030 of USB interface 103
Then, print data for one packet (up to 512 bytes) arrives from the host device 2. After the arrival of the packet, the process proceeds to step S303.

Step S303: The USB device controller 1031 of the USB interface 103 is DM
A DMA transfer request signal 103 from the USB bulk-out endpoint 1030 to the A controller 102.
Assert 2. At the same time, the USB device controller 1031 outputs a reception packet size information signal 1034 to the DMA controller 102. After this processing, the process proceeds to step S304.

Step S304: DMA controller 1
02 reads all the packet data, which has been completely received from the USB bulk-out endpoint 1030 of the USB interface 103, into the FIFO memory 1025.
The DMA controller 102 also sets the value of the received packet size information signal 1034 in the bus transfer counter 1023. When all the data in the FIFO memory 1025 is read, the DMA transfer request signal 1032 is negated. After this processing, the process proceeds to step S305.

Step S305: DMA controller 1
02 determines the value of the bus transfer counter 1023. If the value of the bus transfer counter 1023 is 3 or less, the process proceeds to step S306. When the value of the bus transfer counter 1023 is 4 or more and less than 32, the process proceeds to step S308. If the value of the bus transfer counter 1023 is 32 or more, the process proceeds to step S310.

Step S306: DMA controller 1
02 indicates the memory 101 with respect to the data transfer bus 105.
The non-burst data transfer (writing) of 3 bytes or less to the USB buffer area 1010 is performed. The transfer direction signal 1054 from the DMA controller 102 to the data transfer bus 105 indicates writing to the memory 101, and the address 1057 is the DMA transfer destination address register 10.
Using the value of 20, the data 1058 is the FIFO memory 1
The value held in 025 is used. The DMA controller 102 negates the burst transfer request signal 1055 to clearly indicate the non-burst data transfer. Further, the DMA controller 102 uses the bus transfer counter 1
Byte enable in accordance with the value of the lower 2 bits of 023, or when the value of the DMA transfer destination address register is not aligned by 4 bytes in the case of passing through step S310. Assert each bit of signal 1056.
After the non-burst data transfer of 3 bytes or less is completed by asserting the data acknowledge signal 1053, the process proceeds to step S307.

Step S307: DMA controller 1
02 decrements the value of the DMA transfer amount setting register 1021 by the lower 2 bits (3 or less) of the value currently set in the bus transfer counter 1023. Also, DMA
The controller 102 updates the DMA transfer destination address register 1020 (increments the lower 2 bits of the value currently set in the bus transfer counter 1023). Also, the DMA controller 102 sets the value of the bus transfer counter 1023 to the lower 2 of the currently set value.
Decrement by bit (3 or less). After this processing, the process proceeds to step S313.

Step S308: DMA controller 1
Reference numeral 02 denotes the memory 101 with respect to the data transfer bus 105.
Non-burst data transfer (writing) of 4 bytes to the USB buffer area 1010 is performed. The transfer direction signal 1054 from the DMA controller 102 to the data transfer bus 105 indicates writing to the memory 101, and the address 1057 is the DMA transfer destination address register 1020.
Of the FIFO memory 102.
The value held in 5 is used. DMA controller 1
02 negates the burst transfer request signal 1055,
Clearly indicate non-burst data transfer. Also, D
The MA controller 102 uses the byte enable signal 10
All 56 bits are asserted to clearly indicate a 4-byte non-burst data transfer. After the 4-byte non-burst data transfer is completed by asserting the data acknowledge signal 1053, the process proceeds to step S309.

Step S309: DMA controller 1
02 decrements the value of the bus transfer counter 1023 and the value of the DMA transfer amount setting register 1021 by four. Further, the DMA controller 102 updates the DMA transfer destination address register 1020 (increments by 4). After this processing, the process proceeds to step S313.

Step S310: DMA controller 1
02 determines whether or not the value of the DMA transfer destination address register 1020 is 4-byte aligned, and if it is 4-byte aligned (the lower 2 bits of the DMA transfer destination address register are 0b00), step S311.
Go to. If not aligned by 4 bytes, the process proceeds to step S306.

Step S311: DMA controller 1
02 indicates the memory 101 with respect to the data transfer bus 105.
32 bytes of burst data is transferred to the USB buffer area 1010. The transfer direction signal 1054 from the DMA controller 102 to the data transfer bus 105 is
Indicates writing to the memory 101, and the address 1057
Uses the value of the DMA transfer destination address register 1020, and the data 1058 uses the value held in the FIFO memory 1025. The DMA controller 102 is
The burst transfer request signal 1055 is asserted to clearly indicate the burst data transfer. After the 32-byte burst data transfer is completed, the process proceeds to step S312.

Step S312: DMA controller 1
02 decrements the value of the bus transfer counter 1023 and the value of the DMA transfer amount setting register 1021 by 32.
Further, the DMA controller 102 updates the DMA transfer destination address register 1020 (increments by 32). After this processing, the process proceeds to step S313.

Step S313: DMA controller 1
02 determines the value of the bus transfer counter 1023, and if the value of the bus transfer counter 1023 is 0, the step S3
Proceed to 14. If the value of the bus transfer counter 1023 is other than 0, the process returns to step S305.

Step S314: DMA controller 1
02 determines the value of the DMA transfer amount setting register 1021. If the value of the DMA transfer amount setting register 1021 is 0, the process proceeds to step S315. If the value of the DMA transfer amount setting register 1021 is not 0, the process returns to step S302 to wait until the next USB packet arrives and the DMA transfer request signal 1032 is asserted.

Step S315: DMA controller 1
02 has completed transfer of a predetermined DMA transfer amount, so D
The MA transfer interrupt signal 1026 is asserted, and the CPU 1
01 is notified of the completion of the DMA transfer.

FIG. 7 shows the DMA controller 102 of the printer controller device 10 of the printer device 1,
FIG. 9 is a timing chart showing an example of DMA transfer when a 4-byte DMA transfer size is designated. Hereinafter, FIG. 5, FIG.
An example of DMA transfer of a 38-byte USB bulk-out packet and a 6-byte USB bulk-out packet by designating a 44-byte DMA transfer size will be described with reference to FIG.

Time 1: The CPU 100 of the printer controller device 10 of the printer device 1 sets the DMA transfer destination address register 1020 of the DMA controller 102 to 0x.
00000002, the DMA transfer amount setting register 1021 to 44, and the DMA control register 1022.
To instruct the start of DMA transfer (step S
301). After this processing, the process proceeds to step S302.

Time 2: The first 38-byte USB bulk-out packet arrives from the host device 2 to the USB interface 103 of the printer device 1 (step S302). After the arrival of the packet, the process proceeds to step S303.

Time 3: The USB interface 103
The DMA transfer request signal 1032 is asserted, and the received packet size information signal 1 for the DMA controller 102
The value 38 is output to 034 (step S303). After this processing, the process proceeds to step S304.

Time 4: The DMA controller 102 is U
The SB packet data is read into the FIFO memory 1025 9 times with a 4-byte width and once with a 2-byte width. Also, DMA
The controller 102 sets the value 38 of the received packet size information signal 1034 from the USB interface 103 in the bus transfer counter 1023 (step S30).
4). After this processing, the process proceeds to step S305.

Time 5: In the DMA controller 102, the value of the bus transfer counter 1023 is 38, but since the DMA transfer destination address register 1020 is not 4-byte aligned, the address 0x00000002 is output and the DMA transfer destination address register is output. Starts non-burst transfer for the data amount (2 bytes) aligned by 4 bytes (step S305, step S310, step S306).

Time 6: DMA controller 102 is 2
The non-burst transfer of bytes is completed, and the DMA transfer destination address register 1020 is updated (incremented by 2).
DMA transfer destination address register 10 after increment
The value of 20 is 0x0000004. The DMA controller 102 also includes a bus transfer counter 1023 and D
The MA transfer amount setting register 1021 is decremented by 2 (step S307). The value of the DMA transfer amount setting register 1021 after decrement becomes 42. The value of the bus transfer counter 1023 after decrement becomes 36 (step S313). Since the value of the bus transfer counter 1023 is other than 0, the process returns to step S305.

Time 7: Since the value of the bus transfer counter 1023 is 36 and the DMA transfer destination address register is 4-byte aligned, the DMA controller 102 outputs the address 0x00000004 to transfer the 32-byte burst data. Start (step S30)
5, step S310, step S311).

Time 8: DMA controller 102 is 3
When the 2-byte burst transfer is completed, the DMA transfer destination address register 1020 is updated (32 increments). The value of the DMA transfer destination address register 1020 after the increment is 0x00000024. Also, D
The MA controller 102 uses the bus transfer counter 1023.
And the DMA transfer amount setting register 1021 is decremented by 32 (step S312). DM after decrement
The value of the A transfer amount setting register 1021 is 10. The value of the bus transfer counter 1023 after decrement becomes 4. After this processing, the process returns to step S305.

Time 9: Since the value of the bus transfer counter 1023 is 4, the DMA controller 102 starts the 4-byte non-burst data transfer (step S30).
5, step S308). Byte enable signal 105
6 clearly indicates that it is a 4-byte non-burst data transfer.

Time 10: The DMA controller 102
The 4-byte non-burst transfer is completed, and the DMA transfer destination address register 1020 is updated (incremented by 4). The value of the DMA transfer destination address register 1020 after the increment is 0x00000028. Also, D
The MA controller 102 uses the bus transfer counter 1023.
And the DMA transfer amount setting register 1021 is decremented by 4 (step S309). The bus transfer counter 1023 after decrementing is 0, and the first USB
Although the DMA transfer corresponding to the packet is completed, the value of the DMA transfer amount setting register 1021 after decrement is 6. Since the value of the bus transfer counter 1023 is 0 (step S313), the process proceeds to step S314.

Time 11: The DMA controller 102
The value of the DMA transfer amount setting register 1021 is 6 and the predetermined DMA transfer amount is not completed (step S31).
4) Therefore, it waits for the arrival of the next USB packet. After this processing, the process proceeds to step S302.

Time 12: A second 6-byte USB bulk-out packet arrives from the host device 2 to the USB interface 103 of the printer device 1 (step S302). After the arrival of the packet, the process proceeds to step S303.

Time 13: USB interface 103
Asserts the DMA transfer request signal 1032,
The value 6 is output as the received packet size information signal 1034 to the controller 102 (step S30).
3). After this processing, the process proceeds to step S304.

Time 14: The DMA controller 102
The USB packet data is read into the FIFO memory 1025 once with a 4-byte width and once with a 2-byte width. Also, DM
The A controller 102 is a USB interface 103.
The value 6 of the received packet size information signal 1034 from is set in the bus transfer counter 1023 (step S30).
4). After this processing, the process proceeds to step S305.

Time 15: The DMA controller 102
Since the value of the bus transfer counter 1023 is 6, the 4-byte non-burst data transfer is started (step S30).
5, step S308). Byte enable signal 105
6 clearly indicates that it is a 4-byte non-burst data transfer.

Time 16: The DMA controller 102
The 4-byte non-burst transfer is completed, and the DMA transfer destination address register 1020 is updated (incremented by 4). The value of the DMA transfer destination address register 1020 after the increment is 0x0000002C. Also, DM
The A controller 102 decrements the bus transfer counter 1023 and the DMA transfer amount setting register 1021 by 4 (step S309). The bus transfer counter 1023 after decrementing becomes 2. DMA after decrement
The value of the transfer amount setting register 1021 becomes 2. The value of the bus transfer counter 1023 is other than 0 (step S31)
3) Therefore, the process returns to step S305.

Time 17: The DMA controller 102
Since the value of the bus transfer counter 1023 is 2, the 2-byte non-burst data transfer is started (step S30).
5, step S306). Byte enable signal 105
6 clearly indicates that it is a 2-byte non-burst data transfer.

Time 18: The DMA controller 102
The 2-byte non-burst transfer is completed, and the DMA transfer destination address register 1020 is updated (incremented by 2). The value of the DMA transfer destination address register 1020 after the increment is 0x0000002E. Also, DM
The A controller 102 decrements the bus transfer counter 1023 and the DMA transfer amount setting register 1021 by 2 (step S309). The bus transfer counter 1023 after decrement is 0, and the DMA transfer corresponding to the second USB packet is completed. The value of the DMA transfer amount setting register 1021 after decrement is 0.
Is. Since the value of the bus transfer counter 1023 is 0 (step S313), the process proceeds to step S314.

Time 19: The DMA controller 102
Since the value of the DMA transfer amount setting register 1021 is 0, the DMA transfer is completed, and the DMA transfer interrupt signal 1026
Is asserted to notify the CPU 100 of the completion of the DMA transfer (step S315).

As described above, according to the embodiment of the present invention, even when a USB packet of an arbitrary size is sent from the host device 2 to the printer device 1, the printer controller device 10 of the printer device 1 is operated. The DMA controller 102 appropriately controls the transfer mode in the DMA transfer control by using the packet size information obtained from the USB interface 103, so that the USB packet can be transmitted at high speed and with high performance on the data transfer bus 105. It is possible to perform DMA transfer from the USB interface 103 to the memory 101 according to the transfer size.

[Other Embodiments] In the present embodiment, the FIFO memory 1 inside the DMA controller 102 is described.
Although the example in which the USB packet data from the USB bulk-out endpoint 1030 of the USB interface 103 is temporarily fetched is described in 025, the present invention is not limited to this, and the USB bulk-out endpoint 1030 directly transfers the data transfer bus. Data may be output to 105, so-called fly-by transfer.

Further, in the present embodiment, the data transfer bus 1
The protocol No. 05 has been described by taking a virtual bus protocol capable of burst transfer as an example, but the present invention is not limited to this and may be a bus protocol provided by a commercially available embedded processor or the like. Even if the bus protocol does not allow burst transfer, DM
When the A transfer amount setting and the size of the USB packet are different, by performing the transfer during the non-burst transfer of the present embodiment, it is possible to perform the DMA transfer according to the arbitrary USB packet size.

Further, in the present embodiment, the printing method of the printer device is the electrophotographic method, but the present invention is not limited to this, and other than the electrophotographic method, an ink jet method, a heat sensitive method, a thermal transfer method, etc. Other printing methods may be used.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. A medium such as a storage medium that stores a program code of software that realizes the functions of the above-described embodiments is supplied to a system or apparatus, and the computer (or CPU or MPU) of the system or apparatus stores the medium in the medium such as the storage medium. It goes without saying that the present invention can also be achieved by reading and executing the executed program code.

In this case, the program code itself read from the medium such as the storage medium realizes the functions of the above-described embodiments, and the medium such as the storage medium storing the program code constitutes the present invention. It will be. As a medium such as a storage medium for supplying the program code, for example, a floppy (registered trademark) disk, a hard disk, an optical disk, a magneto-optical disk, a CD-RO.
M, CD-R, magnetic tape, non-volatile memory card,
ROM or download via a network can be used.

Further, by executing the program code read by the computer, not only the functions of the above-described embodiment are realized, but also the OS or the like running on the computer is actually executed based on the instruction of the program code. Needless to say, the present invention includes a case where a part or all of the processing of (1) is performed and the functions of the above-described embodiments are realized by the processing.

Further, after the program code read from a medium such as a storage medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the instruction of the program code is given. Based on the above, a case where a CPU or the like included in the function expansion board or the function expansion unit performs a part or all of actual processing and the processing realizes the functions of the above-described embodiments is not included in the present invention. Needless to say.

[0075]

As described above, according to the present invention,
Even when a USB packet of an arbitrary size is sent from the external device to the printing device, the USB packet can be DMA-transferred at high speed on the bus capable of burst transfer and according to an arbitrary transfer size.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a system including a printer USB interface DMA transfer control device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a printer controller device of the printer device according to the present embodiment.

FIG. 3 is a block diagram showing a configuration of a DMA controller of the printer controller device of the printer device according to the present embodiment.

FIG. 4 is a flowchart showing a process in the printer apparatus according to the present embodiment until print data is transferred to a memory inside a printer controller based on a print request from a host apparatus.

5 is a flowchart showing DMA transfer control of the DMA controller in step S3 of FIG. 4 according to the present embodiment.

6 is a flowchart showing DMA transfer control of the DMA controller in step S3 of FIG. 4 according to the present embodiment.

FIG. 7 is a timing chart showing DMA transfer control of a 44-byte USB packet according to the present embodiment.

[Explanation of symbols]

1 Printer Device (Printing Device) 2 Host Device (External Device) 4 USB Cable 10 Printer Controller 11 Printer Engine (Printing Unit) 100 CPU 101 Memory (Storage Unit) 102 DMA Controller (DMA Control Device, Control Unit) 103 USB Interface ( USB interface control device) 104 Engine interface 105 Data transfer bus (bus) 1020 DMA transfer destination address register 1021 DMA transfer amount setting register 1022 DMA control register 1023 Bus transfer counter 1024 DMA control sequencer 1025 FIFO memory 1030 USB bulk out endpoint 1031 USB Device controller (detection means) 1034 Received packet size information signal 1035 USB packet data 105 Byte enable signal

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2C061 AP01 AQ06 HJ06 HJ08 HK11                 5B021 AA02 BB01 BB04 BB11 CC05                       DD03                 5B061 AA00 BA03 DD05 DD06 DD11                       RR03                 5B077 AA23 AA42 AA44 BB05 MM02                       NN02

Claims (10)

[Claims] 1. A DMA control device for performing a DMA transfer of USB packet data received from the outside by a USB interface control device to a device on a bus, wherein a plurality of transfer modes are set as a DMA transfer mode to the device on the bus. And a control means for controlling the DMA transfer mode of the USB packet data based on the size of the USB packet data acquired from the USB interface control device and a value indicating the data width of the bus. DMA controller. 2. The plurality of transfer modes are a 1-byte transfer mode, a 2-byte transfer mode, a 3-byte transfer mode,
2. The DMA controller according to claim 1, further comprising a 4-byte transfer mode. 3. The DMA controller according to claim 1, wherein the plurality of transfer modes include a burst transfer mode and a single transfer mode. 4. The D according to claim 1, wherein the control means controls the transfer mode by a byte enable signal sent to the bus in the DMA transfer.
MA controller. 5. The control means sets D in response to alignment of a DMA transfer destination address in the DMA transfer.
5. The DMA control device according to claim 1, which controls the MA transfer mode. 6. The DMA controller according to claim 1, the USB interface controller, the bus, and the USB packet data are DMA.
A printing apparatus comprising: a storage unit to be transferred and a printing unit for printing an image on a medium. 7. The USB interface control device comprises:
7. The printing apparatus according to claim 6, further comprising a detection unit that detects the size of USB packet data received from an external device, and a bulk-out endpoint that temporarily stores the USB packet data. 8. A DMA control method for performing DMA transfer of USB packet data received from the outside by a USB interface control device to a device on a bus, wherein a plurality of transfer modes are set as a DMA transfer mode to the device on the bus. A DMA control method comprising: controlling the DMA transfer mode of the USB packet data based on a value indicating the size of the USB packet data and the data width of the bus, which is obtained from the USB interface control device. 9. The plurality of transfer modes are a 1-byte transfer mode, a 2-byte transfer mode, a 3-byte transfer mode,
9. The DMA control method according to claim 8, further comprising a 4-byte transfer mode. 10. The DMA control method according to claim 8, wherein the plurality of transfer modes include a burst transfer mode and a single transfer mode.