JP2003255008A - Apparatus and method for verifying circuit wiring - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus for verifying circuit wirings, capable of surely and easily verifying the state of the circuit wiring using a simple configuration. <P>SOLUTION: A verifying system 20 comprises a sensor panel 200 having a thin film transistor (TFT) to constitute a sensor element, a computer 21, a probe 22 for supplying verification signal to the circuit wiring 101, and a selector 23 for switching the supply of the signal to the probe 22. The computer 21 receives the verification signal from the panel 200, generates image data, and displays the image of the wiring to be verified on a display 21a. Thus, faults such as disconnections, short circuiting, faults or the like of the wiring 101 can be detected, based on the generated image data and the image data showing the wirings of design. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit wiring inspection device and a circuit wiring inspection method capable of inspecting the quality of circuit wiring.

[0002]

2. Description of the Related Art In the manufacture of a circuit board, it is necessary to inspect whether or not there is a disconnection or a short circuit after arranging the circuit wiring on the circuit board. In recent years, due to the high density of circuit wiring, when inspecting each circuit wiring, it is not possible to arrange an inspection pin at both ends of each circuit wiring at the same time and to provide a sufficient distance for contacting the tips. Therefore, in order to inspect the state of the circuit wiring without using pins, a non-contact type inspection method capable of receiving an electric signal from the circuit wiring without touching both ends of the circuit wiring has been proposed. (JP-A-9-264919).

In this non-contact type inspection method, as shown in FIG. 19, an inspection pin is brought into contact with one end side of a circuit wiring to be inspected, and the other end side of the circuit wiring is non-contacted. This is a method in which a sensor conductor is arranged on the substrate, the potential of the circuit wiring is changed by supplying an inspection signal from an inspection pin, and the potential change is detected by the sensor conductor to inspect a pattern disconnection or the like.

[0004]

However, the above-mentioned conventional non-contact inspection method can only detect whether or not the circuit wiring exists at a certain position on the circuit board (whether the potential at the pattern at the certain position changes). However, it is impossible for the operator to intuitively judge the pattern state or to easily judge the state between both ends of the circuit wiring.

[0005]

The present invention has been made for the purpose of solving the above-mentioned problems, and solves the above-mentioned problems. For example, an operator can easily and intuitively determine the state of circuit wiring. An object is to provide a circuit wiring inspection device.

As one means for achieving the above object, for example, the following configuration is provided.

That is, an inspection signal supply means for supplying an inspection signal to the inspection target circuit wiring, a detection means for detecting a potential change of the inspection target circuit wiring according to the supply of the inspection signal by the inspection signal supply means, and Image data generation means for generating image data representing the shape of the circuit wiring from the potential change position information detected by the detection means, and the detection means detects a potential change of the inspection target circuit wiring using a thin film transistor. It is characterized by

Further, for example, the inspection signal supply means is
An inspection signal is supplied to different circuit wirings at different timings.

Further, for example, the thin film transistor is a TFT arranged in a matrix.

Further, for example, a selection means for supplying a selection signal for selectively driving the thin film transistor is further provided, and the inspection signal supply means supplies the inspection signal to different circuit wirings at different timings. Then, the selecting means is arranged to extend in the horizontal direction within the thin film transistor.
A selection signal is input to the thin film transistor lines forming the line at the same time, and the inspection signal detection means simultaneously detects a potential change of the circuit wiring facing the thin film transistor line.

Further, for example, the circuit wiring is a collective substrate of a plurality of integrated circuit wirings, and the thin film transistor has an area of at least the integrated circuit wiring forming region of the collective substrate, and is located at a position facing the collective substrate. It is characterized by being positioned.

Further, for example, the circuit wiring board is a board on which a plurality of integrated circuits are mounted, and the thin film transistor has an area of at least the circuit board and is positioned at a position facing the circuit board. Is characterized by. Alternatively, it is characterized by further comprising a determining means for comparing the shape of the circuit wiring having the potential change with the circuit wiring information to judge the quality of the inspection target circuit wiring.

A circuit inspection method in an inspection apparatus for inspecting circuit wiring, wherein the potential change of the inspection target circuit wiring in response to the supply of the inspection signal by the inspection signal supply means for supplying the inspection signal to the inspection target circuit wiring. Is detected using a thin film transistor, image data representing the shape of the circuit wiring is generated from the detected potential change position information, and the circuit wiring state can be confirmed.

Further, for example, the supply of the inspection signal by the inspection signal supply means is such that the inspection signal is supplied to different circuit wirings at different timings.

Further, for example, to the different circuit wirings, the inspection signals are supplied at different timings, and at the same time, selection signals are simultaneously input to thin film transistor lines forming one line in the horizontal direction of the thin film transistors,
It is characterized in that the potential change of the circuit wiring facing the thin film transistor line is simultaneously detected for each line.

Further, for example, it is further characterized in that the shape of the circuit wiring having the potential change and the circuit wiring information are compared to determine the quality of the circuit wiring to be inspected.

[0017]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings. The configurations, relative arrangements of components, numerical values, and the like in the following description are not intended to limit the scope of the present invention to the scope of the following description.

The following description will be made by taking a case of an inspection apparatus for inspecting a wiring pattern in an integrated circuit chip as an example of circuit wiring, and a case in which only one integrated circuit chip is inspected as an explanation of the principle. To do.

However, the present invention is not limited to the examples described below, and even a mounting board on which a plurality of integrated circuit chips are mounted can be inspected in the same manner, and the circuit is actually driven. Inspecting each wiring pattern is also included.

[First Embodiment] As a first embodiment, an inspection system 20 using a thin film transistor such as a TFT transistor as a sensor element will be described. FIG. 1 is a schematic diagram of a pattern inspection system according to an embodiment of the present invention.

As shown in FIG. 1, in this embodiment, the sensor elements are sequentially driven line by line to detect a potential change.

<Structure of Inspection System> FIG. 2 is a schematic block diagram of the inspection system 20 of the present embodiment.

The inspection system 20 includes a sensor panel 200 having a plurality of sensor elements, a computer 21, and a probe 22 for supplying an inspection signal to the circuit wiring 101.
And a selector 23 for switching the supply of the inspection signal to the probe 22. The selector 23 can be composed of, for example, a multiplexer, a deplexer, or the like.

The computer 21 informs the selector 23 of control signals and circuit wiring 10 for selecting the probe 22.
1 is supplied to the sensor panel 200 in synchronization with the control signal supplied to the selector 23 to the sensor panel 200 to operate the sensor element (vertical synchronization signal (Vs
sync), a horizontal synchronization signal (Hsync) and a reference signal (Dclk) are supplied.

The inspection signal to be applied may be either a voltage pulse or an AC signal. Since the polarity of the signal can be limited by using the voltage pulse, the circuit can be designed by limiting the current direction in the sensor element to one direction, which simplifies the circuit design.

Further, the computer 21 responds to the fact that the detection signal flows to the circuit wiring by the sensor panel 2
Image signal corresponding to the circuit wiring pattern in which the detection signal flows, and the generated image is displayed on the display 21a.

Thus, the shape of the specific circuit wiring is searched for, and defects such as disconnection, short circuit, and chipping of the circuit wiring 101 are detected based on the generated image data and the image data showing the designed circuit wiring. You can

The tips of the probes 22 are in contact with one ends of the circuit wirings 101 on the circuit board 100, respectively, and supply inspection signals to the circuit wirings 101.

The selector 23 switches the probe 22 which outputs the inspection signal. Switching is performed based on the control signal supplied from the computer 21 so that the inspection signal is supplied to each of the plurality of independent circuit wirings 101 on the circuit board 100.

Further, the selector 23 connects the circuit wiring to which the inspection signal is not applied to a low impedance line such as a ground level (GND) or a power supply. This is to prevent the test signal from riding on the non-test circuit wiring due to crosstalk and the sensor from receiving an erroneous signal.

The sensor panel 200 is arranged in a contactless manner at a position facing the circuit wiring 101 of the circuit board 100,
The inspection signal supplied from the probe 22 detects a potential change generated on the circuit wiring 101, and outputs it as a detection signal to the computer 21. The distance between the sensor panel 200 and the circuit wiring is preferably 0.05 mm or less, but
It is possible if it is 5 mm or less. Further, the circuit board and the sensor panel 200 may be brought into close contact with each other with a dielectric insulating material interposed therebetween.

The circuit board 100 of FIG. 2 shows an example in which the circuit wiring 101 is provided only on one side, but the present embodiment is limited to the above example. Instead, it is possible to inspect a circuit board having circuit wirings 101 on both sides. In that case,
The two sensor panels 200 are arranged one above the other so as to sandwich the circuit boards for inspection.

Next, the detailed configuration of the computer 21 will be described with reference to FIG. FIG. 3 is a block diagram showing the hardware configuration of the computer 21 of this embodiment.

In FIG. 3, reference numeral 211 denotes the computer 2.
A CPU that controls the entire unit 1 and is also used for calculation and control, 212 is a ROM that stores programs executed by the CPU 211, fixed values, and the like, and 213 is a display that generates image data by processing input digital data. 21a, an image processing unit for processing the image data to be output to 2a.
Reference numeral 14 is a RAM for temporary storage, and H is stored in the RAM 214.
A program load area for storing programs loaded from the D215 and the like, a storage area for digital signals detected by the sensor panel 200, and the like are included. Digital signals from the sensor panel 200 received by the computer 21 are stored for each group of sensor elements corresponding to the shape of each circuit wiring.

Reference numeral 215 is a hard disk as an external storage device, and 216 is a CD-ROM drive as a removable storage medium reading device. An input / output interface 217 controls the input / output interface with the keyboard 218, the mouse 219, the sensor panel 200, and the selector 23 as input devices via the input / output interface 217.

A sensor chip control program, a selector control program, and an image processing program are stored in the HD 215, and the RAM 21 is executed when the respective programs are executed.
4 is loaded into the program load area and executed.

The image data showing the shape of the circuit wiring inspected by the sensor panel 200 and the image data showing the shape of the designed circuit wiring are also stored in the HD 215. The image data input from the sensor panel 200 may store a sensor element group facing the shape of each circuit wiring as a determination unit, or may store one frame of all the sensor elements as a determination unit.

The sensor chip control program, the selector control program, the image processing program, and the image data showing the shape of the designed circuit wiring are recorded in a CD-ROM, and this CD-ROM recording information is read by a CD-ROM drive. FD and D even if installed by
It may be read after being recorded in another medium such as VD or downloaded via a network.

FIG. 4 shows the sensor panel 20 of this embodiment.
It is a block diagram which shows the electric constitution of 0.

The sensor panel 200 has an electrical configuration as shown in the drawing and is attached to a package (not shown).

The sensor panel 200 includes a control unit 11, a sensor element group 12 composed of sensor elements 12a composed of a plurality of thin film transistor arrays, and a sensor element line 12b composed of a plurality of horizontally arranged sensor elements. And a vertical selection unit 14 for selecting the sensor element 1
A horizontal selection unit 13 that extracts a signal from the horizontal selection unit 2a, a timing generation unit 15 that generates a selection signal for selecting each sensor element line 12b, and a signal processing unit 16 that processes the signal from the horizontal selection unit 13. An A / D converter 17 for A / D converting the signal from the signal processing unit 16 and a power supply circuit unit 18 for supplying electric power for driving the sensor panel 200.

The control unit 11 is for controlling the operation of the sensor panel 200 in accordance with a control signal from the computer 21. The control unit 11 has a control register and sets the operation timing, amplification, and reference voltage of the sensor.

The sensor elements 12a are arranged in a matrix and detect a potential change on the circuit wiring 101 in accordance with an inspection signal supplied from the probe 22 to the circuit wiring 101 in a non-contact manner.

The timing generation unit 15 is the computer 2
1 to vertical sync signal (Vsync), horizontal sync signal (H
sync) and a reference signal (Dclk) are supplied, and a timing signal for selecting the sensor element 12a is supplied to the vertical selection unit 14, the horizontal selection unit 13, the signal processing unit 16, and the A / D converter 17.

The vertical selection unit 14 sequentially selects at least one row of the sensor element group 12 according to the timing signal from the timing generation unit 15. Vertical selection unit 14
From each sensor element 12a of the sensor element line 12b selected by, the detection signal is output at one time and input to the horizontal selection unit 13. The horizontal selection unit 13 amplifies the analog detection signals output from the 640 terminals, temporarily holds the analog detection signals, and sequentially processes the detection signals according to the timing signal from the timing generation unit 15 by a selection circuit such as a multiplexer. Output to the unit 16.

The signal processing section 16 further amplifies the signal from the horizontal selection section 13 to a level necessary for the determination processing and performs analog signal processing such as passing through a filter for removing noise,
It is sent to the A / D converter 17. In addition, the signal processing unit 1
6 also has an auto gain control, which automatically sets the voltage amplification factor of the read signal of the sensor to an optimum value.

The A / D converter 17 includes a signal processing section 16
The inspection signal of each sensor element 12a sent in analog form from is converted into, for example, an 8-bit digital signal and output. The power supply circuit 18 generates a reference clamp voltage or the like for the signal processing unit.

Here, in the sensor panel 200, A
Although the / D converter 17 is built in, the analog signal analog-processed by the signal processing unit may be directly output to the computer 21.

Next, the operation of the sensor panel 200 used in this embodiment will be described. FIG. 5 is a diagram for explaining a sensor element composed of a thin film transistor (TFT) according to this embodiment.

In the sensor panel 200, for example, X electrodes and Y electrodes are arranged in a matrix on a glass substrate, and thin film transistors (TFTs) are formed at intersections of the matrix. The thin film transistor (TFT) can be made of any material such as cadmium sulfide (CdS), cadmium selenide (CdSe), tellurium (Te), polycrystalline silicon, and amorphous silicon. If possible, a high-level detection signal can be obtained by using polycrystalline silicon or amorphous silicon.

As shown in the sectional view of the lower part, the sensor element 12a has a structure in which a gate (X electrode) is formed on a glass substrate, an insulating film is formed on the gate (X electrode), and an insulating film is interposed. The semiconductor thin film having the above structure is formed on the gate, and the source (Y electrode) and the drain are formed thereon.

The gate is connected to the vertical selection section 14,
The drain is connected to the lateral selection unit 13. Further, a potential barrier for discharging unnecessary charges is provided in the diffusion layer of the passive element.

The timing generation unit 15 causes the vertical selection unit 14
When the sensor element 12a is selected via, a signal is sent from the vertical selection section 14 to the gate, and the sensor element 12a is turned on (detection signal output possible state).

At this time, when the voltage as the inspection signal is applied from the probe 22, the potential of the circuit wiring 101 changes, and accordingly, the current flows from the source to the drain.
This becomes a detection signal and is sent to the signal processing unit 16 via the lateral selection unit 13. If the circuit wiring 101 does not exist at the position facing the sensor element 12a, no current flows.

Therefore, if the position of the sensor element 12a that has output the current as the detection signal is analyzed, the circuit board 1
At which position of 00, the circuit wiring 101 continuous from the electrode in contact with the probe 22 exists.

Here, the principle of current flow from the source to the drain will be described in more detail. 6 and 7 are model diagrams for explaining this principle in an easy-to-understand manner. FIG. 6 is a diagram for explaining a state in which no voltage is applied to the circuit wiring, and FIG. 7 is a diagram in which voltage is applied to the circuit wiring. It is a figure for demonstrating the closed state. 6 and 7, the selection signal is input to the gate and the gate is turned on.

As shown in FIG. 6, if no voltage is applied to the circuit wiring, the excess charges of the diffusion layer overflow from the discharge potential barrier lower than the potential of the potential barrier under the gate which is turned off. In that case, the source potential is determined by the discharge potential.

Next, as shown in FIG. 7, when the voltage V is applied to the circuit wiring, the circuit wiring is positively charged (becomes the potential V). Here, since the circuit wiring and the source side diffusion layer are separated from each other by a minute distance, the opposing source side diffusion layer is affected by the change in the potential of the circuit wiring, and the potential becomes V so that the electric charge flows. That is, the circuit wiring and the source side diffusion layer operate as if they are capacitively coupled, the potential of the source side diffusion layer becomes low, electrons flow in, and a current flows from the source to the drain.

When the circuit wiring is connected to the ground again,
The potential of the source side diffusion layer returns to its original value, and the surplus electrons are gradually discharged and released from the potential barrier.

<Signal Input / Output Timing of Sensor Panel 200> Next, the voltage application timings for the three circuit wirings and the output signals in that case will be specifically described with reference to FIGS. 8 and 9. FIG. 8 shows circuit wiring
9 is a diagram for explaining an inspection by a 6 × 6 sensor element in FIG.
Is an operation timing chart, and data indicating the shape of the circuit wiring, data indicating the shape of the circuit wiring, and data indicating the shape of the circuit wiring are sequentially output.

The sensor elements corresponding to the circuit wiring include (X2, Y1), (X3, Y1), (X4, Y).
1), (X2, Y2), (X3, Y2), (X4, Y
2), (X5, Y2), (X6, Y2), (X5, Y
3), there are 10 sensor elements located at coordinates (X6, Y3).

The sensor elements corresponding to the circuit wiring are (X1, Y1), (X2, Y1), (X1, Y).
2), (X2, Y2), (X3, Y2), (X2, Y
3), (X3, Y3), (X4, Y3), (X5, Y
3), (X6, Y3), (X3, Y4), (X4, Y
4), (X5, Y4), there are 14 sensor elements located at coordinates (X6, Y4).

The sensor elements corresponding to the circuit wiring are (X1, Y4), (X2, Y4), (X1, Y).
5), (X2, Y5), (X3, Y5), (X1, Y
6), (X2, Y6), (X3, Y6), (X4, Y
There are 9 sensor elements located at the coordinates of 6).

Of these, black (X2,
Y1), (X2, Y2), (X3, Y2), (X5, Y
3), for the five sensor elements (X6, Y3),
Used for inspection of both circuit wiring and circuit wiring. Therefore, both of these circuit wirings cannot be inspected by driving the sensor element once. Further, since both the circuit wiring and the circuit wiring are inspected by using the sensor element on the Y4 sensor element line, when using the method of simultaneously driving one horizontal sensor element line as described above, It is not possible to test both of these circuit traces in a single drive of the sensor element. On the other hand, such a problem does not occur between the circuit wiring and the circuit wiring 3.

Therefore, both the circuit wiring and the circuit wiring are inspected once during the period (one frame) in which all the sensor elements are driven, and the circuit wiring is inspected in the subsequent frames.

Therefore, as shown in the timing chart of FIG. 9, data showing the shape of the circuit wiring, data showing the shape of the circuit wiring, and data showing the shape of the circuit wiring are
It is output in order.

<Method of applying voltage to a plurality of circuit wirings>
Next, with reference to FIG. 1 and FIG. 10, a method for efficiently applying voltage to a plurality of circuit wirings according to the present embodiment will be described.

FIG. 1 is a diagram for explaining the order of voltage application to the circuit wirings when there are a plurality of circuit wirings in one circuit board. In FIG. 1, in order to simplify the explanation,
The circuit wiring to be inspected is indicated by a circle. The circuit wiring is modeled as being arranged in a matrix of m rows and n columns. The sensor panel 200 has a size that covers all circuit wiring.

When a plurality of circuit wirings are present in the reception area of the sensor, it is basically necessary to keep all the other circuit wirings at the reference potential (GND) while applying a voltage to one circuit wiring. If voltage is applied to two circuit wirings at the same time, even if the circuit wiring to be inspected is cut in the middle, it short-circuits with other circuit wirings to which voltage is applied at the same time, and voltage is applied from there to the end of the circuit wiring to be inspected This is because the voltage is applied and is erroneously determined to be pass, and an open defect is missed.

Since one voltage is applied to the circuit wiring while driving one sensor element line, even if a plurality of circuit wirings correspond to the same sensor element line, only one of the circuit wirings has a voltage. Cannot be applied.

Therefore, as shown in the figure, in the first frame, 1
The circuit wiring lined up in the second row is arranged vertically from the top in the figure,
The voltage is applied to the first line, the second line, ... Mth line. Also in the second frame, voltage is sequentially applied to the circuit wirings arranged in the second column from the top in the vertical direction in the drawing. In this way, the voltage is applied to all the circuit wirings in the nth frame.

FIG. 10 is a timing chart showing an example of the voltage application timing for the circuit wiring of FIG. 1 described above.

As shown in the figure, the first frame (first Vs
corresponding to 1st Hsync to 7th Hsync (between ysync and 2nd Vsync),
A voltage is applied to the circuit wiring (1, 1) in the first row and the first column. Next, a voltage is applied to the second-row, first-column circuit wiring (2, 1) corresponding to the eighth Hsync to the fourteenth Hsync. Further, following the circuit wirings (3, 1) and (4, 1), a voltage is applied to the circuit wirings (m, 1), then the second frame is started, and the circuit wirings (1, 2) to (m, 2) Voltage is applied to. In this way, the sensor element is repeatedly driven until the inspection of all the circuit wirings is completed, that is, up to the nth frame.

<Modeling of Circuit Wiring> Next, with reference to FIGS. 11 and 12, a method of modeling the circuit wiring of the present embodiment in a matrix will be described.

First, from the design shape data (for example, CAD data) of the circuit wiring, the area of the circuit wiring to be inspected is
It is cut out into a rectangle and the table shown in FIG. 11 is created.
FIG. 11 shows a table in which each circuit wiring is numbered, and the upper left coordinates of the rectangular area including the circuit wiring and the coordinates of the lower right sensor element are associated with each other.
Also, all frames are first.

Next, the circuit wirings are rearranged in order from the one having the smallest Y coordinate value at the upper left. In FIG. 11, 1
The second is the circuit wiring having the Y coordinate of Y1 and the circuit wiring.
The second is the circuit wiring whose Y coordinate is Y4.

Next, the value of the upper left Y coordinate of each circuit wiring is compared with the value of the lower right Y coordinate of the immediately preceding circuit wiring, and the value of the upper left Y coordinate of the circuit wiring is determined. If the Y-coordinate at the lower right of the immediately preceding circuit wiring is smaller, it is determined that the sensor element lines for reading those circuit wirings overlap, and the circuit moves to a different frame.

In the case of FIG. 11, first, the circuit wiring is
First, it is fixed as circuit wiring for applying voltage. Then, the upper left Y coordinate of the circuit wiring is compared with the lower right Y coordinate of the circuit wiring. In this case, the circuit wiring is Y3 and the circuit wiring is Y1. Since Y3> Y1, the circuit wiring is moved to the frame 2. Since frame 2 is inspected after frame 1, it will be moved to the bottom column of the table.

At this point, the circuit wiring immediately before the circuit wiring becomes the circuit wiring. Therefore, next, the upper left Y coordinate Y4 of the circuit wiring is compared with the lower right Y coordinate Y3 of the circuit wiring. Since Y4> Y3, the circuit wiring is the frame 1
Remain in. In the same manner, the frame 1 or the frame 2 is determined for all the circuit wirings from the circuit wirings. As a result, frame 1 and frame 2 can be grouped.

Next, the same operation is performed in the group of frame 2. In this case, whether the value of the upper left Y coordinate is larger than the value of the lower right Y coordinate of the circuit wiring to which the previous voltage is applied, the smaller circuit wiring moves to the frame 3, and the larger circuit wiring moves to the frame 2. Leave on.

With this, a group of frames 1, 2 and 3 is completed. Execute until there is no increase in frames, and end when there is no increase in frames.

As a result of such processing, the table shown in FIG. 12 is generated. The frame number corresponds to the column number in FIG. 1, and the number indicating the voltage application order in the same frame corresponds to the row number.

By referring to the table of FIG. 12,
First, the first to third Hsy after the first Vsync
nc (see Y coordinate), a voltage pulse is applied to the circuit wiring, a voltage pulse is applied to the circuit wiring corresponding to the fourth to sixth Hsync, and a second Vsync is further applied. A voltage pulse is applied to the circuit wiring in correspondence with the subsequent 1st to 4th Hsync.

Here, since it is assumed that the design shape data of the circuit wiring and the coordinates of the sensor element completely correspond to each other, the outer shape coordinates of the circuit wiring are simply used as the coordinates of the sensor element. However, in reality, the sensor and the circuit wiring are mechanically aligned with each other, which causes a positional deviation. Therefore, the Y coordinate that determines the inspection area may be slightly wider by adding the deviation.

<Image Processing Method> Next, referring to FIG. 13 and FIG.
With reference to, the handling of image data in the inspection system of the present embodiment will be described. FIG. 13 is a flow chart showing a process of extracting target data from a gold sample in the present embodiment, and FIG. 15 is a flow chart explaining image processing in the inspection system of the present embodiment.

First, with reference to FIG. 13, an explanation will be given on the process of extracting the target data before the start of the inspection according to the present embodiment. First, in step S141, the circuit wiring for one frame of the gold sample circuit board is inspected. That is, all the sensor elements are driven once, and digital data indicating the shapes of a plurality of circuit wirings that can be modeled in one vertical column is taken out.

In step S142, horizontal noise is removed. This is done by averaging the 10 dots at the left end in the horizontal direction and subtracting that value from the values of all the original image data.

In step S143, it is determined whether or not 10 frames have been read. If not, the process returns to step S141 to inspect the same circuit wiring again. When the inspection for 10 frames is completed, step S1
Proceed to 44.

In step S144, the image data for 10 frames is averaged and passed through the median filter in step S145. This removes local noise.

Next, after the contrast is corrected in step S146, the contour data is used as the target data in the RAM 214 of the computer 21 in step S147.
Stored in.

In step S147, it is determined whether or not digital data has been extracted from all the circuit wirings on the gold sample. If there is another uninspected circuit wiring, the process proceeds to step S149, and the other circuit wirings are checked. For the next frame, the processing from step S141 to step S147 is performed. By repeating this, the image data is extracted for all the circuit wirings.

If the image data of all the circuit wirings have been taken out, the process proceeds to step S150 to create a table. This table associates circuit wirings with their ranges and gradations. When the table is created, the target data extraction process ends.

Next, with reference to FIG. 14, a flow of data processing when actually inspecting an object to be inspected in the present embodiment will be described.

First, in step S151 of FIG.
1 Drive the sensor element line. Next, step S15
In 2, the obtained digital data is transferred line by line to the image processing unit 213 of the computer 21.

In step S153, it is determined whether the line is the last line of the frame. If the line is not the final line of the frame, step S
Proceed to 154 to proceed to the next line.

On the other hand, if the line is the last line of the frame in step S153, step S15
In step 5, it is determined whether the frame is the final frame. If the frame is not the final frame, the process advances to step S156 to proceed to the next frame.

On the other hand, if the frame is the final frame in step S155, the operation of the sensor panel 200 ends.

In step S157, the digital data for one line is input to the computer 21, and step S1
At 56, horizontal noise is removed. This method is the same as the method used in step S142 of FIG. However, if one such as step S143 or step S144
The averaging process of 0 frame is not performed, and after noise removal, the signal is passed through the median filter in step S159, and then in step S1.
At 60, it is stored in the RAM 214 of the computer 21.

Then, in step S161, it is determined whether all the lines of all the frames are stored in the RAM 214. If the transfer of all the lines is not completed, the process returns to step S157 and the processes of S157 to S161 are repeated.

If the processing for all lines of all frames is completed in step S161, the image processing unit 2
The operation of 13 ends.

In step S162, the data processed by the image processing unit 213 is input and stored in the RAM 214. In step S163, it is determined whether one frame of data has been stored in the RAM 214. If the image data for one frame is stored, the entire image data is passed through a median filter in step S164, contrast correction is performed in step S165, and step S16 is performed.
In step 6, after the binarization processing, contour tracing is performed.

Further, in step S167, the comparison with the target data obtained by the processing shown in FIG. 13 is performed by the method of least squares. After that, the process proceeds to step S168, the correlation values are obtained, and pass or fail is determined. next,
In step S169, the pass / fail result is displayed on the display 21a. The target data of the target frame is read in step S171 as parallel processing.

These steps S162 to S1
Step 69 is repeated until the results are displayed for all the frames through step S170. When the comparison with the target data of all the frames and the display of the results are completed, the inspection for one circuit board is completed. .

Since the contour tracing requires time, the field emission image data may be simply compared with the target data without performing the contour tracing. In that case, the gray value (gradation value) of the image data may be determined to be within ± several gradations of the image data extracted from the gold sample.

In the present embodiment, as described above, the pass / fail of the circuit wiring is determined by the image data, so that the accurate pass / fail determination can be made. Further, by displaying the image, the shape of the circuit wiring can be intuitively grasped, and the defective portion can be easily detected. Furthermore, even when a plurality of circuit wirings are present on one circuit board, the inspection order can be controlled to perform accurate and efficient inspection.

In the sensor panel 200, the sensor elements 12a are arranged two-dimensionally according to the shape of the circuit board 100, but they may be arranged three-dimensionally.

It is desirable that all the sensor elements 12a have the same shape as shown in FIG. This is because each sensor element 12a uniformly supplies the inspection signal to the circuit wiring and receives the signal appearing on the circuit wiring.

As shown in FIG. 3, it is desirable that the sensor elements 12a are arranged in a matrix in which the sensor elements 12a are arranged at equal intervals in the row direction and the column direction. that way,
It is possible to reduce the unevenness of the number of sensor elements 12a per unit area facing the circuit wiring, clarify the relative positional relationship between the sensor elements 12a, and easily identify the shape of the circuit wiring by the detection signal. This is because it can be converted. However, only one column may be arranged depending on the shape of the circuit wiring to be inspected.

Since the sensor panel 200 uses the TFT, the sensor element 12 on the surface of the product can easily have a large capacity.
Although a is an array of m rows and n columns, this is defined for convenience in this embodiment, and is actually designed, for example, according to the size of the inspection target substrate.

When setting the size, spacing, etc. of the sensor elements 12a in this manner, it is desirable to set the size and spacing according to the line width of the circuit wiring in order to realize a more accurate inspection. .

That is, since the signal charges can be concentrated near the surface of the passive element and the signal charge density can be increased, the capacitive coupling can be further strengthened. In that case, the conductive plate may be a thin metal film or a polycrystalline semiconductor.

In the embodiment described above, the change in the potential of the circuit wiring is detected, but the amount and the radiation shape of the electromagnetic wave radiated from the circuit wiring may be detected. If the amount and shape of a predetermined electromagnetic wave can be detected, it is determined that the circuit wiring is normally continuous. If an amount smaller than a predetermined amount and a different shape are detected, it is determined that the circuit wiring is distant or missing.

Further, although the probe is brought into contact with the end of the circuit wiring in the present embodiment, the inspection signal may be input from the starting point of the circuit wiring using the non-contact terminal.

In the present embodiment, one sensor element line is driven at the same time, but the present invention is not limited to this, and a plurality of sensor element lines may be driven at the same time.
It is also possible to drive a plurality of sensor elements in a non-line area area at the same time. Even in that case, when a plurality of sensor element groups facing the shape of the circuit wiring to be inspected overlap with a part of the sensor element groups facing the shape of another circuit wiring, the timing of applying to the other circuit wiring is set. ,
Different frame selection periods.

As described above, according to the present embodiment, the thin film transistor (TFT) is used as a circuit wiring sensor for judging the quality of the circuit wiring. Therefore, the circuit wiring shape is thin, inexpensive, and has a large area. Can be detected,
The quality of the inspection pattern can be easily recognized.

(Second Embodiment) Next, an inspection system according to a second embodiment of the present invention will be described with reference to FIG. FIG. 15 is a flowchart showing a process of performing a preliminary inspection and measuring a positional deviation of the circuit board before starting the inspection of the second embodiment according to the present invention.

The inspection system of the second embodiment does not use the gold sample but the designed image data (CAD
The difference from the first embodiment is that the data wiring) and the circuit wiring to be inspected are compared. Since the other points are the same as those of the first embodiment, the description thereof is omitted here, and the same components are denoted by the same reference numerals in the drawings.

In step S181, two or three circuit wirings of the circuit board to be inspected are inspected in one frame as circuit wirings (marks) for pretreatment. That is, image data showing the shapes of two to three marks provided on the circuit board in the vertical direction with a space therebetween is generated.

In step S182, horizontal noise removal is performed. This is done by averaging the 10 dots at the left end in the horizontal direction and subtracting that value from the values of all the original image data.

In step S183, it is determined whether or not the reading of the mark has been repeated 10 times. If not completed, the process returns to step S181 and the reading of the mark is repeated. When the inspection for 10 frames is completed, the process proceeds to step S184.

In step S184, the image data for 10 frames is averaged and passed through the median filter in step S185. This removes local noise.

Next, after the contrast is corrected in step S186, the center of gravity of the mark image is obtained in step S187, and the center of gravity of the obtained mark image and design image data (CAD data) is obtained in step S188. The positional shift (coordinate shift and angular shift) from the center of gravity of the mark is calculated.

Then, in step S189, actual inspection and image processing are performed. Here, step S18
The position of the generated image data is corrected based on the shift amount obtained in 8. The data processing in the actual inspection here is almost the same as that shown in FIG.
159 and step S160 are different only in that the coordinate conversion processing of one line of data is inserted.

According to the present embodiment, at the time of actual inspection, the generated image data and the image data showing the designed circuit wiring can be compared accurately, and the circuit wiring 101 can be disconnected or short-circuited. It is possible to detect defects such as cracks and chips with high accuracy.

(Third Embodiment) Next, FIG. 16 and FIG.
An inspection system according to a third embodiment of the present invention will be described with reference to FIGS. The inspection system of the third embodiment differs from the first embodiment in that two adjacent columns of circuit wiring are simultaneously inspected during one frame. Since the other points are the same as those of the first embodiment, the description thereof is omitted here, and the same components are denoted by the same reference numerals in the drawings.

FIG. 16 shows a case where a plurality of circuit wirings are provided in one circuit board according to the third embodiment of the present invention.
FIG. 17 is a timing chart showing an example of voltage application timing for circuit wiring shown in FIG. 16, and FIG. 18 is an output image example when voltage is applied at the timing shown in FIG. FIG.

In FIG. 16, for simplification of description, as in FIG. 1, circuit wirings to be inspected are represented by ◯, and the circuit wirings are arranged in a matrix of m rows and n columns. .

In the third embodiment, as shown in FIG. 16, in the first frame, the circuit wirings arranged in the first and second columns are arranged in the vertical direction in the drawing from the top to the first row. The voltage is applied to the 2nd row, ... The mth row. Even in the second frame, 3
Voltage is sequentially applied to the circuit wirings arranged in the second and fourth columns from the top in the vertical direction in the drawing. In this way, the voltage is applied to all the circuit wirings in the n / 2th frame.

FIG. 17 is a timing chart showing an example of voltage application timing for the circuit wiring shown in FIG.

As shown in FIG. 17, in the first frame (between the first Vsync and the second Vsync),
Corresponding to the first, third, fifth, and seventh Hsyncs, a voltage is applied to the circuit wiring (1, 1) in the first row and first column, and the second, fourth, sixth, and eighth A voltage is applied to the circuit wirings (1, 2) in the first row and the second column corresponding to Hsync. Then, a voltage is applied to the circuit wirings in the first column corresponding to the 9th, 11th, ... Hsyncs, and the circuit wirings in the 2nd column (corresponding to the 10th, 12th, ... Voltage is applied to 1, 2).

The same applies to the second and subsequent frames,
A voltage is applied to the odd-numbered circuit wirings corresponding to the odd-numbered Hsyncs, and a voltage is applied to the even-numbered circuit wirings corresponding to the even-numbered Hsyncs.

That is, the odd-numbered sensor element line is set to 1
Input timing of selection signal and detection timing of potential change from sensor element line so as to drive for detection of circuit wiring of column and drive even number of sensor element lines for detection of circuit wiring of second column , And controlling the timing of supplying the inspection signal to the circuit wiring.

In other words, the timing of applying the voltage to one circuit wiring is executed every other sensor element line. Image data appears line by line.

As a result, the odd-numbered circuit wirings are image-displayed only by the odd-numbered lines (FIG. 18A), and the even-numbered circuit wirings are image-displayed only by the even-numbered lines (FIG. 1).
8 (b)).

As described above, if the voltage is alternately applied to the odd-numbered circuit wirings and the odd-numbered circuit wirings in the same frame, the inspection time can be halved. It is also possible to obtain the outer shape of the entire circuit wiring by processing the image data and interpolating the missing line.

The circuit wirings in a plurality of columns may be inspected in one frame period depending on the resolution of the sensor. For example, in the case of 5 columns, a voltage may be applied to the same circuit wiring every 5Hsync.

[0137]

According to the present invention, the thin film transistor (T
FT) is used as a circuit wiring sensor to judge whether the circuit wiring is good or bad. Therefore, the thin and inexpensive circuit wiring shape of a wide area can be detected, and the quality of the inspection pattern can be easily recognized. It is possible to provide an inspection device and an inspection method capable of intuitively inspecting the shape of wiring.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a sensor driving sequence for circuit wirings in an inspection system according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram of an inspection system according to the present embodiment.

FIG. 3 is a block diagram for explaining a hardware configuration of a computer of the inspection system according to the present embodiment.

FIG. 4 is a block diagram showing an electrical configuration of a sensor panel 200 of the present embodiment example.

FIG. 5 is a thin film transistor (TFT) of the present embodiment.
It is a figure for demonstrating the sensor element comprised by.

FIG. 6 is a model diagram for explaining a principle that a current is generated according to a potential change of a circuit wiring in the sensor element according to the present embodiment.

FIG. 7 is a model diagram for explaining a principle that a current is generated according to a potential change of circuit wiring in the sensor element according to the present embodiment.

FIG. 8 is a diagram for explaining the inspection of circuit wirings by 6 × 6 sensor elements by the inspection system of the present embodiment.

9 is a timing chart showing a voltage application timing and a data output timing with respect to the circuit wiring shown in FIG.

10 is a timing chart showing an example of voltage application timings for the circuit wiring of FIG. 1 in the present embodiment.

FIG. 11 is a diagram showing a table for obtaining a voltage application order for a plurality of circuit wirings in the inspection system according to the first embodiment.

FIG. 12 is a diagram showing a table for obtaining a voltage application order for a plurality of circuit wirings in the inspection system of the present embodiment.

FIG. 13 is a flowchart showing a process of extracting target data from a gold sample in the inspection system according to the present embodiment.

FIG. 14 is a flowchart illustrating image processing in the inspection system according to the present embodiment.

FIG. 15 is a flowchart showing a process of obtaining a positional deviation from CAD data in the inspection system according to the second embodiment of the present invention.

FIG. 16 is a diagram illustrating a voltage application sequence for circuit wirings when a plurality of circuit wirings are provided in one circuit board according to the third embodiment of the present invention.

17 is a timing chart showing an example of voltage application timing of the third embodiment with respect to the circuit wiring of FIG.

FIG. 18 is a diagram showing an example of an output image when voltage is applied at the timing of FIG.

FIG. 19 is a diagram illustrating a conventional circuit board inspection device.

Claims (13)

[Claims] 1. A test signal supply means for supplying a test signal to a test target circuit wiring; a detecting means for detecting a potential change of the test target circuit wiring according to the supply of the test signal by the test signal supplying means; Image data generation means for generating image data representing the shape of the circuit wiring from the potential change position information detected by the detection means, and the detection means detects a potential change of the inspection target circuit wiring using a thin film transistor. A circuit wiring inspection device characterized in that 2. The circuit wiring inspection apparatus according to claim 1, wherein the inspection signal supply means supplies inspection signals to different circuit wirings at different timings. 3. The circuit wiring inspection apparatus according to claim 1, wherein the thin film transistors are TFTs arranged in a matrix. 4. A selection means for supplying a selection signal for selectively driving the thin film transistor, wherein the inspection signal supply means supplies an inspection signal to different circuit wirings at different timings. The selection means inputs a selection signal simultaneously to the thin film transistor lines forming one line in the horizontal direction of the thin film transistor, and the inspection signal detection means simultaneously detects a potential change of a circuit wiring facing the thin film transistor line. The circuit wiring inspection device according to claim 3, wherein 5. The circuit wiring is a collective substrate of a plurality of integrated circuit wirings, and the thin film transistor has an area of at least the integrated circuit wiring formation region of the collective substrate and is positioned at a position facing the collective substrate. 5. The circuit wiring inspection device according to claim 3, wherein the circuit wiring inspection device is provided. 6. The circuit wiring board is a board on which a plurality of integrated circuits are mounted, the thin film transistor has at least an area for the circuit board, and is positioned at a position facing the circuit board. The circuit wiring inspection device according to any one of claims 3 to 5, which is characterized. 7. A determination means is further provided for comparing the shape of the circuit wiring having the potential change with the circuit wiring information to determine the quality of the inspection target circuit wiring.
7. The circuit inspection device according to claim 6. 8. A circuit inspection method in an inspection device for inspecting circuit wiring, comprising: a potential change of the inspection target circuit wiring in response to the supply of the inspection signal by an inspection signal supply means for supplying an inspection signal to the inspection target circuit wiring. Is detected by using a thin film transistor, and image data representing the shape of the circuit wiring is generated from the detected potential change position information so that the circuit wiring state can be confirmed. 9. The circuit wiring inspection according to claim 8, wherein the inspection signal is supplied by the inspection signal supply means to different circuit wirings at different timings. Method. 10. The different circuit wirings are supplied with the inspection signal at different timings, and at the same time, a selection signal is simultaneously input to a thin film transistor line forming one line in the horizontal direction of the thin film transistor, and the thin film transistor line is supplied with the selection signal. Change the potential of the opposing circuit wiring,
10. The lines are detected simultaneously for each line.
The circuit wiring inspection method described. 11. The quality of the circuit wiring to be inspected is determined by comparing the shape of the circuit wiring having the potential change with the circuit wiring information.
The circuit inspection method according to any one of 1. 12. A computer-readable recording medium storing a computer program for implementing the circuit wiring inspection method according to claim 8 by computer control. 13. A computer program string for implementing the circuit wiring inspection method according to claim 8 by computer control.