JP2003249626A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of being highly integrated. <P>SOLUTION: The semiconductor memory device 351 is provided with a silicon substrate 1; bipolar transistors 101a, 101b formed on the silicon substrate 1; and memory elements 31a-31c having contact holes 61, receiving a part of the bipolar transistors 101a, 101b, and arriving at a front surface of the silicon substrate 1, while electrically connected to an interlayer dielectric 60 formed on the silicon substrate 1 as well as the bipolar transistors 101a-101c. The memory elements 31a-31c are provided with a first state wherein an electric resistance is relatively high and a second state wherein the electric resistance is relatively low. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a phase change memory (OUM: Ovonic Unified M
emory) or MRAM (Magnetic Random Access Memo)
ry)).

[0002]

2. Description of the Related Art In recent years, CD-RW (Compact Disk Rewri)
table) or DVD-RAM (Digital Versatile Dis)
Research and development of new semiconductor memory devices using the materials used for memory elements such as k) are in progress.
In this semiconductor memory device, as a memory element (memory cell), a chalcogenide-based material (Ge-Sb-Te-based material:
Chalcogenide alloy) is used. A chalcogenide material is heated and moderately cooled, resulting in an amorphous state (high resistance state) and a polycrystalline state (low resistance state).
There are two states. Since the electric resistances are different in these two states, it is possible to discriminate between "0" and "1" by reading this state.

In order to bring the chalcogenide material into a crystalline state, the chalcogenide material is kept at a temperature of less than 600 ° C. for about 10 nanoseconds. Then, it becomes a crystalline state by cooling. To change the chalcogenide-based material to the amorphous state, the chalcogenide-based material is heated at a temperature of 600 ° C.
The amorphous state is obtained by heating above and then rapidly cooling.

In a CD-RW or the like, this heating is performed by using a laser. When a chalcogenide-based material is used as a semiconductor memory device, the chalcogenide-based material is heated by passing a current through a heating element. Make a change. Such a semiconductor memory device includes a chalcogenide film as a memory element, a resistor for heating the film,
It consists of transistors that select memory cells. Such a memory cell is called an OUM.

There are various types of OUMs, and one using a junction type transistor (bipolar transistor) is known as a selection transistor. It is known that a bipolar transistor can generally operate at high speed. Therefore, an electric current can be rapidly passed to heat the chalcogenide material described above, or an electric current can be suddenly cut off to cool the chalcogenide material.

A semiconductor memory device using a bipolar transistor as a selection transistor is disclosed in, for example, Japanese Patent Publication No.
No. 5,507,071. FIG. 26 is a sectional view of the conventional semiconductor memory device disclosed in the above publication. Referring to FIG. 26, the memory cell 420 includes a lower layer 4
Including 12. The lower layer 412 includes access device elements such as diodes or bipolar transistors.

An electrode material layer 434 is formed on the lower layer 412. A protective film 416 is formed over the electrode material layer 434. A cell opening 418 is formed in the protective film 416. The pillar 444 is formed inside the cell opening 418. The pillar 444 includes a side surface spacer 448 and a protrusion 4
46 is provided. Protective film 416 and side spacer 44
8 and the chalcogenide layer 426 is formed on the protrusion 446. An upper electrode material layer 428 is provided on the chalcogenide layer 426.

[0008]

In the conventional memory cell 420 as described above, the bipolar transistor is formed in the lower layer 412 extending in the lateral direction. Therefore, there is a problem that the area of the bipolar transistor as an access device becomes large and it is difficult to highly integrate the memory cell made of the chalcogenide material.

Therefore, the present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device capable of high integration.

[0010]

A semiconductor memory device according to the present invention includes a semiconductor substrate, a junction type transistor formed on the semiconductor substrate, at least a portion of the junction type transistor, and a surface of the semiconductor substrate. An insulating layer formed on the semiconductor substrate, and a memory element electrically connected to a part of the junction type transistor provided in the hole. The memory element has a first state in which the electric resistance is relatively high and a second state in which the electric resistance is relatively low.

The junction type transistor has a first conductivity type well region formed in a semiconductor substrate, a second conductivity type impurity region formed in the first conductivity type well region facing the hole, and a first conductivity type well region formed in the first conductivity type well region. A first-conductivity-type conductive region provided in the hole so as to contact the second-conductivity-type impurity region.

In the semiconductor memory device according to the present invention having the above structure, the junction transistor is connected to the memory element. Therefore, an electric signal can be sent to the storage element at higher speed than in the case where a field effect transistor or a diode is connected to the storage element.
Further, since at least a part of the junction type transistor is provided in the hole, the area occupied by the junction type transistor on the semiconductor substrate is reduced, and high integration is possible.

Also preferably, the first state comprises an amorphous state and the second state comprises a crystalline state.

Further preferably, the semiconductor memory device is provided in the hole so as to be interposed between the memory element and the conductive region of the first conductivity type and has a larger electric resistance than that of the conductive region of the first conductivity type. A first heating layer having electric resistance and heating the memory element is further provided.

In this case, since the first heating layer generates heat by passing an electric current through the first heating layer, the heat can appropriately heat the memory element.

Further preferably, the semiconductor memory device further includes a second heating layer provided so as to be separated from the memory element to preheat the memory element. In this case, since the storage element is preheated by the second heating layer, the storage element can be rapidly heated.

Preferably, the semiconductor memory device further includes a plurality of junction type transistors. The second conductivity type impurity region is formed to extend in a predetermined direction. Each of the plurality of junction type transistors shares a second conductivity type impurity region extending in a predetermined direction. In this case, since one second conductivity type impurity region is shared by a plurality of junction type transistors, compared to the case where each of the plurality of junction type transistors has a different second conductivity type impurity region, A plurality of junction transistors can be formed in a narrow area.

Preferably, the semiconductor memory device is the second memory device.
The semiconductor device further includes a wiring layer extending along the conductivity type impurity region and electrically connected to the second conductivity type impurity region. In this case, since the wiring layer is connected to the second conductivity type impurity region, the amount of current flowing in the second conductivity type impurity region can be reduced.

Preferably, the semiconductor memory device is the first memory device.
The semiconductor device further includes a second conductivity type well region formed on the semiconductor substrate so as to surround the conductivity type well region. In this case, since the second conductivity type well region surrounds the first conductivity type well region, the potential in the first conductivity type well region can be set to an appropriate value.

Further preferably, the semiconductor memory device further includes a storage region including a plurality of storage elements and a plurality of junction transistors electrically connected to each of the plurality of storage elements. Each of the plurality of junction type transistors includes a plurality of second conductivity type impurity regions extending substantially in parallel with each other. A predetermined second of the plurality of second conductivity type impurity regions;
An odd-numbered second conductivity type impurity region counted from the conductivity type impurity region is electrically connected to the first current driving unit provided on one end side of the storage region. The even-numbered second-conductivity-type impurity regions counting from the predetermined second-conductivity-type impurity region are electrically connected to the second current driving means provided on the other end side of the storage region.

In this case, since the odd-numbered second-conductivity-type impurity regions and the even-numbered second-conductivity-type impurity regions are connected to different current driving means, the peripheral portion of the storage region is miniaturized. be able to. As a result, a semiconductor memory device that can be highly integrated can be provided.

Further preferably, the memory element has a first ferromagnetic layer, an insulating layer formed on the first ferromagnetic layer, and a second ferromagnetic layer formed on the insulating layer. A ferromagnetic layer.

Further preferably, the first ferromagnetic material layer, the insulating layer and the second ferromagnetic material layer are provided in the hole.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a plan view of a semiconductor memory device according to a first embodiment of the present invention. Figure 1
Referring to, semiconductor memory device 351 according to the first embodiment of the present invention includes silicon substrate 1 as a semiconductor substrate.
And bipolar transistors 101a to 101c and 102a to 102c as junction type transistors formed on the silicon substrate 1, and the bipolar transistor 1
01a-101c and 102a-102c, and an interlayer insulating film having a contact hole 61 as a hole reaching the surface of the silicon substrate 1, and bipolar transistors 101a-101c and 102a-provided in the contact hole 61. Storage elements 31a to 31c and 32a to 32c provided on the insulating layer so as to be electrically connected to a part of 102c. The storage elements 31a to 31c and 32a to 32c are
A first state (amorphous state) having a relatively high electric resistance,
And a second state (crystalline state) having a relatively low electric resistance.

N-type impurity regions 41a to 41c and 42a to 42c are formed on silicon substrate 1 as base regions of bipolar transistors 101a to 101c and 102a to 102c. n-type impurity region 41
A bit line 10a is provided on a to 41c. The bit line 10b is provided on the n-type impurity regions 42a to 42c. Both the bit lines 10a and 10b are made of chalcogenide-based material (Ge-Sb-Te-based material). Bit lines 10a and 10b extend parallel to each other. A part of the bit line 10a is a storage element 31a-31.
c. A part of the bit line 10b is a storage element 32a-.
32c. Storage elements 31a to 31c and 32a to
32c is electrically connected to n-type impurity regions 41a to 41c and 42a to 42c by a contact hole 61.

On bit lines 10a and 10b, word lines 20a to 20c extend in a direction intersecting the extending direction of bit lines 10a and 10b. Word line 20a
.About.20c are electrically connected to n-type impurity regions 41a to 41c and 42a to 42c through contact holes 71. The word lines 20a to 20c are connected to the bit lines 10a to
It extends in a direction substantially orthogonal to the extending direction of 10b.

Bipolar transistors 101a-101
c and 102a to 102c include n-type impurity regions 41a to 41c and 42a to 42c as base regions.

FIG. 2 is a sectional view taken along the line II-II in FIG. Embodiment 1 of the present invention with reference to FIG.
According to the semiconductor memory device 351 of the above, a silicon substrate 1 as a semiconductor substrate and a bipolar transistor 101 as a junction type transistor formed on the silicon substrate 1 are formed.
a-101c and bipolar transistors 101a-1
01c, at least a part of which is provided, and an interlayer insulating film 60 as an insulating layer having a contact hole 61 as a hole reaching the surface of the silicon substrate 1, and a bipolar transistor 101 provided in the contact hole 61.
storage elements 31a to 31c provided on the interlayer insulating film 60 so as to be electrically connected to a part of a to 101c. The memory elements 31a to 31c have a first state (amorphous state) having a relatively high electric resistance and a second state (crystalline state) having a relatively low electric resistance.

Bipolar transistors 101a-101
c is a p-type well region 3 as a first conductivity type well region formed in the silicon substrate 1, and a contact hole 6
Second formed in the p-type well region 3 so as to face the first
N-type impurity regions 41a to 4 as conductivity type impurity regions
1c and p-type impurity-doped doped polysilicon layers 51a to 51c as first-conductivity-type conductive regions provided in the contact hole 61 so as to contact the n-type impurity regions 41a to 41c. including.

When the memory elements 31a to 31c are heated to a first temperature (a temperature of 600 ° C. or higher) and then cooled, they become in an amorphous state, and a second temperature (600) lower than the first temperature. When it is heated to a temperature of less than ° C) and then cooled, it becomes a crystalline state.

A trench 1t is formed on the surface of the silicon substrate 1. Isolation oxide film 5 is buried in trench 1t. Adjacent bipolar transistors 101a to 101c are separated by this trench 1t. The isolation region can be formed deeper than the conventional partial oxidation method (LOCOS method). This can prevent the occurrence of latch-up.

The p-type well region 3 acts as a collector region of the bipolar transistors 101a to 101c. N-type impurity regions 41a to 41c are formed between adjacent trenches 1t so as to directly contact p-type well region 3 as the collector region. The n-type impurity regions 41a to 41c are respectively the bipolar transistors 1
It becomes the base regions of 01a to 101c.

The interlayer insulating film 60 is formed so as to cover the surface of the silicon substrate 1. The interlayer insulating film 60 is provided with a plurality of contact holes 61. Doped polysilicon layers 51a-51 are formed in the contact holes 61.
c is filled. Doped polysilicon layer 51a-
51c is a bipolar transistor 101a to 101c
Is the emitter region of. Doped polysilicon layer 51a
.About.51c is doped with a p-type impurity (for example, boron). When a current flows through the doped polysilicon layers 51a to 51c, the doped polysilicon layers 51a to 51c
Heats up. This heat causes the doped polysilicon layers 51a ...
It is transmitted to the memory elements 31a to 31c formed on 51c. This heat causes the memory elements 31a to 31c to change to an amorphous state or a crystalline state.

Bit line 10a is provided in contact with the plurality of doped polysilicon layers. The bit line 10a is in direct contact with the storage elements 31a to 31c. The bit line 10a and the storage elements 31a to 31c are both made of chalcogenide-based material (Ge-Sb-Te-based material). The portions of the bit line 10a to which the heat from the doped polysilicon layers 51a to 51c is sufficiently transferred are the storage elements 31a to 31c. The metal wiring layer 13 is provided on the bit line 10a to improve the signal propagation speed. The metal wiring layer 13 may not be provided.

The interlayer insulating film 7 is formed so as to cover the bit line 10a.
0 is formed. A plurality of word lines 20a to 20c are formed on the interlayer insulating film 70 at intervals.

Next, a method of manufacturing the semiconductor memory device shown in FIG. 2 will be described. 3 and 4 are cross-sectional views showing a method of manufacturing the semiconductor memory device shown in FIG. Referring to FIG. 3, first, a silicon substrate 1 is implanted with a p-type impurity such as boron. As a result, the p-type well region 3 is formed. A resist pattern is formed on the surface of the silicon substrate 1. The silicon substrate 1 is etched using this resist pattern as a mask. Thereby, the trench 1t is formed. A silicon oxide film is formed by, for example, CVD (chemical vapor deposition) so as to fill the trench 1t. The isolation oxide film 5 is formed by etching back the entire surface of this silicon oxide film by CMP (Chemical Mechanical Polishing). N-type impurity regions 41a to 41c are formed by implanting an n-type impurity such as arsenic into the surface of silicon substrate 1.

Referring to FIG. 4, interlayer insulating film 60 is formed on silicon substrate 1. A resist pattern is formed on the interlayer insulating film 60, and the interlayer insulating film 60 is etched according to this resist pattern. As a result, the contact hole 61 reaching the n-type impurity regions 41a to 41c is formed. Polysilicon is formed so as to fill the contact hole 61, and p-type impurities such as boron are implanted into this polysilicon. As a result, the doped polysilicon layer 5
1a to 51c are formed. Not limited to this method, the doped polysilicon layers 51a to 51c doped with impurities such as boron may be formed by, for example, the CVD method.

Referring to FIG. 2, chalcogenide material is deposited on interlayer insulating film 60. A resist pattern is formed on this chalcogenide material, and the chalcogenide material is etched using the resist pattern as a mask. As a result, the bit line 10a is formed. An interlayer insulating film 70 is formed on the bit line 10a. Interlayer insulating film 70
Form a metal layer on top. A resist pattern is formed on this metal layer, and the metal layer is etched using the resist pattern as a mask. As a result, word lines 20a to 20c are formed. The storage elements 31a to 31c are the bit lines 1
It is formed in the process of forming 0a. That is, the bit line 10
The portions of a that are heated by the doped polysilicon layers 51a to 51c to be in an amorphous or crystalline state become the storage elements 31a to 31c.

The p-type well region 3 is set to the ground potential or a negative potential. Preferably, the p-type well region 3 has a potential. When the potential of the p-type well region 3 is set to a negative potential during standby, the n-type impurity region 41a as a word line is formed.
The potential difference between the potential of 41c (power supply potential: Vdd) and the p-type well region 3 becomes large. As a result, the p-type well region 3 is reverse biased more strongly than the ground potential. At the time of access, the n-type impurity regions 41a to 41c as word lines are set to 0V, and the potential difference between the bit line 10a and the p-type well region 3 becomes large. This has the effect of making it easier for current to flow. Further, also in the parasitic npn bipolar formed between the adjacent storage element 31b, the base becomes the p-type well region 3. Since the p-type well region 3 has a negative potential, the parasitic n
The pn bipolar transistor is less likely to turn on, with favorable results.

When the potential of the p-type well region 3 is set to a negative potential, the word lines 20a to 20c or the bit line 1
A negative potential is applied to the p-type well region 3 before applying a power supply potential (Vdd or Vpp) to 0a to 10e. Because
This is because latch-up may occur when the potential of the p-type well region 3 becomes positive. Generally, when the power is turned on, it is unknown what the potential is in the semiconductor device. Therefore, the negative voltage is first applied to prevent latchup. In the above example, the negative potential is applied from the outside.
Ndom-access memory) and flash memory can generate a negative potential internally. This can also be applied this time, which can reduce the number of external power supply pads.

In the semiconductor memory device 351 according to the first embodiment of the present invention thus configured, the memory element 3 is included.
Bipolar transistors 101a to 101c and 102a to 102c as access devices are connected to 1a to 31c and 32a to 32c. Therefore, an electric signal can be sent to the storage elements 31a to 31c and 32a to 32c in a short time, and rapid heating can be performed. As a result, the crystalline and amorphous states can be optimally controlled.

Further, the bipolar transistor 101a
Reference numerals 101 to 101c and 102a to 102c are so-called vertical bipolars that are vertically stacked. Therefore, many bipolar transistors 101a to 101a are provided in a small area.
01c can be formed. As a result, the integration degree of the semiconductor memory device 351 can be improved.

Although the pnp bipolar transistor is shown in this embodiment, the npn bipolar transistor may be used as the access device.

(Second Embodiment) FIG. 5 is a sectional view of a semiconductor memory device according to a second embodiment of the present invention. Figure 5
Referring to FIG. 5, in semiconductor memory device 352 according to the second embodiment of the present invention, doped polysilicon layers 51a-5 are included.
1c and the storage elements 31a to 31c, the lightly doped polysilicon layers 55a to 55c are formed, which is different from the semiconductor storage device 351 according to the first embodiment.

That is, the semiconductor memory device 352 is provided in the contact hole 61 so as to be interposed between the memory elements 31a to 31c and the doped polysilicon layers 51a to 51c as the conductive regions of the first conductivity type. Further, lightly doped polysilicon layers 55a to 55c as a first heating layer having a resistance larger than that of the doped polysilicon layers 51a to 51c are further provided.

Lightly doped polysilicon layers 55a-5
5c is made of polysilicon doped with p-type impurities (for example, boron). The impurity concentration in the low-concentration doped polysilicon layers 55a to 55c is lower than the impurity concentration in the doped polysilicon layers 51a to 51c. As a result, the lightly doped polysilicon layers 55a to 55 are formed.
c has a larger electric resistance than the doped polysilicon layers 51a to 51c.

A CVD method can be used as a method of manufacturing such lightly doped polysilicon layers 55a to 55c. That is, after the doped polysilicon layers 51a to 51c are manufactured by the CVD method, the doping amount of impurities is reduced by the CVD method to form the low-concentration doped polysilicon layers 55a to 55c.

The semiconductor memory device 352 according to the second embodiment of the present invention thus configured has the same effects as the semiconductor memory device 351 according to the first embodiment. Furthermore, the lightly doped polysilicon layers 55a-5
Since 5c has a higher electrical resistance than the doped polysilicon layers 51a to 51c as the emitter region, the amount of heat generated increases when a current is passed through this portion. The lightly doped polysilicon layers 55a to 55c are used to form the memory element 31a.
~ 31c can be heated reliably.

(Third Embodiment) FIG. 6 is a plan view of a semiconductor memory device according to a third embodiment of the present invention. Figure 6
Referring to, a semiconductor memory device 353 according to the third embodiment of the present invention includes an n type impurity region 41 extending in one direction.
a to 41c, and a plurality of bipolar transistors 10
1a to 105c are the n-type impurity regions 41a to 41c.
The semiconductor memory device 351 differs from the semiconductor memory device 351 according to the first embodiment.

That is, the semiconductor memory device 353 further includes bipolar transistors 101a to 105c as a plurality of junction type transistors. The n-type impurity regions 41a to 41c as the second conductivity type impurity regions are formed so as to extend in a predetermined direction. Each of the plurality of bipolar transistors 101a to 105c shares the n-type impurity regions 41a to 41c. Specifically, the bipolar transistors 101a, 102a ... 105a are n
The type impurity region 41a is shared. The bipolar transistors 101b to 105b share the n-type impurity region 41b. The bipolar transistors 101c to 105c share the n-type impurity region 41c.

Word lines 20a to 20c are connected to the n-type impurity regions 41a to 41c, respectively. The plurality of n-type impurity regions 41a to 41c extend in parallel with each other. The distance between adjacent bit lines is constant at PB1,
The distance between adjacent word lines is constant at PW1.

When accessing any one storage element 32b, the potential of the bit line 10b connected to the storage element 32b is set to Vb (voltage higher than 0V), and the other unselected bit lines 10a, The electric potentials of 10c and 10e are set to 0V. Further, the potential of the word line 20b connected to the selected storage element 32b is set to 0V, and the potentials of the word lines 20a and 20c connected to the non-selected storage elements are set to Vdd. The bipolar transistor 102b connected to the storage element 32b at the intersection of the selected bit line 10b and the selected word line 20b is turned on and a current flows.

The semiconductor memory device according to the third embodiment of the present invention thus configured has the same effect as the semiconductor memory device according to the first embodiment. Further, since the plurality of bipolar transistors 101a to 105c share the n-type impurity regions 41a to 41c, many bipolar transistors 101a to 105c can be arranged in a narrow portion. Furthermore, as compared with the first embodiment,
The isolation region is reduced, and the semiconductor memory device 353 can be downsized.

(Fourth Embodiment) FIG. 7 is a sectional view of a semiconductor memory device according to a fourth embodiment of the present invention. Figure 7
Referring to, semiconductor memory device 354 according to the fourth embodiment of the present invention is different from semiconductor memory device 351 according to the first embodiment in that it has auxiliary wiring 81. The auxiliary wiring 81 is formed on the interlayer insulating film 70 and electrically connected to the source / drain region 203 of the n-channel transistor 201. The n-channel transistor 201 is
It has a source / drain region 203 and a gate electrode 202 formed on the silicon substrate 1 with a gate insulating film 204 interposed. The auxiliary wiring 81 is electrically connected to the source / drain region 203 through the contact hole 70h. The interlayer insulating film 8 is formed so as to cover the auxiliary wiring 81.
0 is formed on the word lines 20a and 2
0b is formed. In FIG. 7, the word lines 20 a and 20 b may be provided on the interlayer insulating film 70 and the auxiliary wiring 81 may be provided on the interlayer insulating film 80.

FIG. 8 is a circuit diagram of the auxiliary wiring shown in FIG. Referring to FIG. 8, auxiliary wiring 81 is connected to n-channel type transistor 201 and p-channel type transistor 205. The p-channel transistor 205 is connected to the power supply 206.

In this embodiment, an auxiliary wiring 81 extending parallel to the bit line 10a is provided on the bit line 10a. One of the roles of the auxiliary wiring 81 is to preheat the target cell when it is heated with heat. This is performed by setting the gate electrode of the p-channel type transistor 205 in the circuit of FIG. 8 to the ground potential. In this way, current flows from the p-channel transistor 205 to the n-channel transistor 201. When a current flows, Joule heat is generated due to the resistance of the auxiliary wiring 81, and the heat is transmitted to the storage elements 31a to 31b through the interlayer insulating film 70.
This allows the memory elements 31a and 31b to be preheated.

As a method of discharging heat, the potential of the gate electrode of the p-channel type transistor 205 is set to Vdd. As a result, the potential of the auxiliary wiring 81 becomes the ground potential. In this heat discharging method, the heat of the heated storage elements 31a and 31b is transferred to the auxiliary wiring 81 through the interlayer insulating film 70. In a solid state, there are electrons and atoms as a medium that conducts heat, and electrons have a faster rate of conducting heat. This is because the electrons can move freely in the solid. Thus, the storage element 3
The heat of 1a and 31b is transmitted to the auxiliary wiring 81 through the interlayer insulating film 70, and gives kinetic energy to the electrons of the auxiliary wiring 81. Since the electric potential of the electrons in the auxiliary wiring 81 is the ground potential, it is possible for the electrons to freely move around in a portion that is also at the ground potential. In this way, it is possible to easily preheat and exhaust heat.

(Fifth Embodiment) FIG. 9 is a plan view of a semiconductor memory device according to a fifth embodiment of the present invention. Figure 9
Referring to, a semiconductor memory device 355 according to the fifth embodiment of the present invention is a semiconductor memory device according to the third embodiment in that it has word lines 20a-20c extending above n-type impurity regions 41a-41c. Different from the storage device 353.

The semiconductor memory device 355 extends along the n-type impurity regions 41a to 41c, and is of the n-type impurity region 4.
Further provided are word lines 20a to 20c as wiring layers electrically connected to 1a to 41c.

The semiconductor memory device according to the fifth embodiment of the present invention thus structured has the same effect as the semiconductor memory device according to the third embodiment. Furthermore, the electric resistance of the word lines 20a to 20c is lowered, and the access speed to the bipolar transistors 101a to 105c is increased.

(Sixth Embodiment) FIG. 10 is a sectional view of a semiconductor memory device according to a sixth embodiment of the present invention. Referring to FIG. 10, the semiconductor memory device 356 according to the sixth embodiment of the present invention has the n-type bottom well region 2 surrounding the p-type well region 3 in that the semiconductor according to the first embodiment. Different from the storage device 351. That is, the n-type bottom well region 2 as the second-conductivity-type well region formed in the silicon substrate 1 so as to surround the p-type well region 3 as the first-conductivity-type well region is replaced with the semiconductor memory device 35.
6 further comprises.

In the semiconductor memory device 356, a negative potential may be applied to the memory elements 31a to 31c to set the potential of the p-type well region of the peripheral region 16 to the ground potential. In the peripheral region 16, the n-type impurity region 111 and the gate oxide film 11 are formed.
2 and the gate electrode 113 are formed. When a negative potential is applied to the back gate of the n-channel transistor, the back gate effect is applied and the threshold values of the other transistors are increased to decrease the operation speed. Therefore, the storage elements 31a to 31c can be surrounded and separated by a so-called triple well. As shown in FIG. 10, by surrounding the triple well, the potentials of the memory elements 31a to 31c can be set arbitrarily.

(Seventh Embodiment) FIG. 11 is a circuit diagram of a semiconductor memory device according to a seventh embodiment of the present invention. Referring to FIG. 11, a semiconductor memory device 357 according to the seventh embodiment of the present invention has a memory area 15 and a peripheral area 16. The first current driving means 110 is provided on the side of the one end 15a of the storage area 15. The second current driving means 120 is provided on the other end 15b side of the storage area 15.

In the first current driving means 110, a plurality of decoders 110a to 110 composed of inverters are provided.
n is provided. In the second current driving means 120,
A plurality of decoders 120a composed of inverters
120n is provided.

The semiconductor memory device 357 includes a memory including a plurality of memory elements 31a to 31d and a plurality of bipolar transistors 101a to 101d as junction transistors electrically connected to each of the plurality of memory elements 31a to 31d. The area 15 is further provided. Each of the plurality of bipolar transistors 101a to 101c includes a plurality of n-type impurity regions 41a to 41d as second impurity regions of the second conductivity type extending substantially parallel to each other. Of the plurality of n-type impurity regions 41a to 41d serving as word lines, odd-numbered n-type impurity regions 41a and 41c counting from the predetermined n-type impurity region 41a are provided on the first end 15a side of the memory region 15. It is electrically connected to one current driving means 110. The even-numbered n-type impurity regions 41b and 41d counting from the n-type impurity region 41a are electrically connected to the second current driving unit 120 provided on the other end 15b side of the memory region 15.

FIG. 12 is a plan view of the first current driving means shown in FIG. With reference to FIG. 12, the first current driving unit has a decoder 110a and a decoder 110b. An n-type well region 4 is formed on the surface of the silicon substrate. The potential of the n-type well region 4 is Vdd (power supply potential)
It is said that A p-type impurity region 115 is formed in the n-type well region 4.
a to 115c are formed. p-type impurity region 115
Gate electrodes 113a and 113b are formed so as to cross a to 115c. P-type impurity regions 115a and 115b are formed on both sides of gate electrode 113a. The p-type impurity region 11 is formed on both sides of the gate electrode 113b.
5b and 115c are provided.

The wiring 11 is electrically connected to the p-type impurity region 115b through the contact hole 117c.
7a is formed. The potential of the wiring 117a is set to the power supply potential.

An n-type impurity region 11 is formed in the p-type well region.
1a to 111c are formed. Gate electrode 113a
N-type impurity regions 111a and 111b are formed on both sides of. N-type impurity regions 111b and 111c are formed on both sides of gate electrode 113b. A wiring 117b is formed in the n-type impurity region 111b through the contact hole 117c. The potential of the wiring 117b is set to the ground potential.

The wiring 118a electrically connects the n-type impurity region 111a and the p-type impurity region 115a. Wiring 11
8a is connected to n-type impurity region 111a and p-type impurity region 115a through contact hole 118c.
The wiring 118b electrically connects the n-type impurity region 111c and the p-type impurity region 115c. The wiring 118b is formed through the contact hole 118c into the n-type impurity region 111c.
And p-type impurity region 115c. N-type impurity regions 111a and 111c are electrically connected to n-type impurity regions 41a and 41c as word lines.
A predetermined potential is applied to the gate electrodes 113a and 113d.

In the semiconductor memory device 357 according to the seventh embodiment of the present invention configured as described above, the n-type impurity region 41a is the first, and the n-type impurity regions 41a are odd-numbered, that is, the first, third, ... 2n. The -1st (n is a natural number) n-type impurity region (word line) is one end 1 of the storage region 15.
It is connected to the first current driver 110 on the 5a side. On the other hand, the even-numbered, that is, the 2n-th, n-type impurity region is connected to the second current driving unit 120 on the other end 15b side of the storage region 15. Therefore, by separately providing the current driving means, the adjacent n-type impurity regions 41a to 4a are formed.
The distance between 1d can be reduced, and the semiconductor memory device 357 can be highly integrated. Further, the same effect as semiconductor memory device 351 according to the first embodiment is obtained.

(Embodiment 8) FIG. 13 is a plan view of a semiconductor memory device according to an embodiment 8 of the invention. Referring to FIG. 13, in semiconductor memory device 358 according to the eighth embodiment of the present invention, decoders 110a and 110 are provided.
b is formed of an n-channel transistor,
It is different from the semiconductor memory device 357 according to the seventh embodiment.
That is, the decoder 110a includes two n-channel type transistors 131 and 132. The n-channel transistor 131 includes a gate electrode 113a and an n-type impurity region 111d formed on both sides of the gate electrode 113.
And 111e. n-channel transistor 1
32 denotes a gate electrode 113d and n-type impurity regions 111a and 111 formed on both sides of the gate electrode 113d.
b. Gate electrodes 113b and 113e forming a decoder for n-type impurity region 41c as a word line are formed on the silicon substrate. N-type impurity regions 111b, 111c, 111e and 111f are provided on both sides of the gate electrodes 113b and 113e.

FIG. 14 is a circuit diagram of the decoder shown in FIG. 14, decoder 110a includes two n-channel type transistors 131 and 132. Here, one word line WL0 (n in FIG.
Two signals X0 and X0P for controlling the gate electrode are required to select the type impurity region 41a).

When selecting the n-type impurity region 41a as the word line, the potential of the n-type impurity region 41a is set to the ground potential. The potential applied to the gate electrode of the n-channel transistor 132 is Vdd (power supply potential), and the potential applied to the gate electrode 113a of the n-channel transistor 131 is 0V.

When the n-type impurity region 41a as the word line is not selected, the n-channel type transistor 131 is used.
The potential of the gate electrode 113a is set to Vpp. Potential Vp
p is a potential higher than Vdd + Vth. Vth is n
It is the threshold voltage of the channel transistor 131.
For example, when Vdd = 2.0V, Vpp = 3.4
V. The potential of the gate electrode 113d of the n-channel transistor 132 is 0V. As a result, the decoder 110a can be composed of only n-channel transistors.

In this case, first, the same effect as that of the first embodiment is obtained. Further, since the p-channel type transistor is not necessary, it is not necessary to form the n-type well for the p-channel type transistor. In this part, CMOS (compleme
ntary mental-oxide semiconductor device) circuit reduces the risk of latch-up. Further, since the separation space at the well boundary is unnecessary, the area of the peripheral region can be reduced as compared with the case where the driver is composed of CMOS.

FIG. 15 is a circuit diagram of another decoder.
With reference to FIG. 15, in the decoder 110a, the signal X
0P is deleted, and the gate electrode of the n-channel transistor 131 is set to the power supply potential. In this case, the potential of the n-type impurity region 41a as the bit line becomes Vcc and is precharged. Moreover, since the potential of the p-type well region is 0 V or a negative potential, the pnp bipolar transistor does not operate. By adopting the layout shown in FIG. 15, required wiring can be further reduced.

FIG. 16 is a graph showing the potential of the decoder of FIG. As shown in this figure, signal X0 and signal X0P
If the signals are generated so that they do not overlap,
The two n-channel transistors 131 and 132 do not turn on at the same time. As a result, the through current can be reduced.

(Ninth Embodiment) FIG. 17 is a circuit diagram of a semiconductor memory device according to a ninth embodiment of the present invention. FIG. 17 shows a data bus from the bit line to the input pad. Signals Y0, Y1 and Y for selecting an arbitrary bit line
2 ... Reads the potential of the bit line. It is compared with a certain reference voltage Vref. Here, the bit line 10a
When is selected, the signal Y0 has a high potential and the signal / Y0R has a ground potential. In this case, the bit line 10a
A current flows into the gate via the power supply, the p-channel type transistor, the n-channel type transistor, the pnp bipolar and the p-type well region. In this example, the signal / Y0R is set to the ground potential for simplification, but it is actually 0V.
Intermediate levels from V to Vdd are often used.
An electric current flows through the bit line, and the magnitude relationship between the voltage drop of the bit line due to the change of the resistance value and the voltage Vref is amplified by the amplifier. The data of the selected bit line 10a is buffered and sent to the data line 141. In this case, the data line 141 is shared by the bit lines 10a to 10g. The amplitude of the data line 141 is finally output to the external pad. When the layout is performed with this configuration, if the storage area becomes small as described above, it becomes difficult to arrange the amplifiers in the respective areas.

FIG. 18 is a circuit diagram of the improved semiconductor memory device. Referring to FIG. 18, in the improved semiconductor memory device 359, when any one of bit lines 10a to 10g is selected, the potential of EN signal (activation signal) becomes high (Vdd), and Pre The signal potential is low (Gnd). By doing so, the signal Y0
The common node 142 potential for ~ Y7 is the ground potential during standby. When the signals Y0 to Y7 are selected, the potential of the selected bit line can be transmitted to the amplifier. Semiconductor storage device 359
Has a read circuit 160.

FIG. 19 is a circuit diagram of the read circuit 160 shown in FIG. Referring to FIG. 19, read circuit 160 has a plurality of OR gates 161 to 163. OR gate 1
61 to 163 are connected to another OR gate 164. The OR gate 164 has three inverters 165-16.
7 and the NOR gate 168.

In such a semiconductor memory device 359, the amplifier is shared, and the circuit layout becomes easy. As a result, LSI (large-scale integrated ci
rcuit) can be implemented.

(Tenth Embodiment) FIG. 20 is a circuit diagram of a semiconductor memory device according to a tenth embodiment of the present invention. Referring to FIG. 20, a semiconductor memory device 360 according to the tenth embodiment of the present invention is an improvement of semiconductor memory device 359 according to the ninth embodiment. First, a non-volatile semiconductor device using a multi-value storage method is known. The semiconductor memory device according to the present invention can also store multi-valued data.

FIG. 21 is a graph showing the concept of multilevel storage. Three reference threshold values shown in FIG. 21 are prepared. In this embodiment, the three thresholds are Vre
f1, Vref2 and Vref3. The falling potential of each bit line and the reference threshold values Vref1 to Vref1.
Each of Vref3 is compared and the result is read. This is done by block 170 in FIG. The result is buffered and output. By doing so, it is possible to perform storage at a higher density.

(Embodiment 11) A word line and a bit line may be short-circuited when a semiconductor memory device is manufactured. This causes a current to flow during standby. FIG. 22
FIG. 6 is a circuit diagram of a semiconductor memory device shown for explaining a short circuit between a bit line and a word line. For example, a short circuit may occur at the intersection of the bit line 10b and the word line 20c. The word line 20c is set to the power supply potential (Vdd) during standby. The potential of the bit line 10b is the ground potential during standby. As a result, a current flows from the word line 20c to the bit line 10b. The current flows through an n-channel type transistor that sets the bit line 10b to the ground potential during standby. Even if a redundant circuit is used for bit lines or word lines,
Current flows through this path.

FIG. 23 is a circuit diagram of a semiconductor memory device according to the eleventh embodiment of the present invention. Here, the fuse 171 is provided on the source side of the n-channel transistor 172 (MN1). Word line 20c and bit line 1
When 0b is short-circuited, the fuse 171 is cut. As a result, the current path can be cut by insulating the bit line 10b. Similarly, the fuse 171 may be provided on the drain side of the n-channel transistor 172.

FIG. 24 is a circuit diagram of an improved semiconductor memory device according to the eleventh embodiment of the present invention. Figure 2
4, in the further improved semiconductor memory device 361 of the present invention, the source of the n-channel transistor on the driver side is shared by using the node 173 (Vx1). A fuse 171 is placed between the node 173 and ground. As a result, the fuse 171 can be efficiently laid out. The fuse 171 may be a laser fuse or an electric fuse.

(Twelfth Embodiment) FIG. 25 is a sectional view of a semiconductor memory device according to a twelfth embodiment of the present invention. Referring to FIG. 25, a semiconductor memory device 363 according to the twelfth embodiment of the present invention is a so-called MRAM. The semiconductor memory device 363 includes a silicon substrate 1 as a semiconductor substrate and a bipolar transistor 101a as a junction type transistor formed on the silicon substrate 1.
And 101b, an interlayer insulating film 60 as an insulating layer having a contact hole 61 as a hole that receives a part of the bipolar transistors 101a and 101b and reaches the surface of the silicon substrate 1, and the contact hole 6.
Storage element 3 electrically connected to a part of the bipolar transistors 101a and 101b provided in
00a and 300b. The memory elements 300a and 300b have a first state in which the electric resistance is relatively high and a second state in which the electric resistance is relatively low.

The memory elements 300a and 300b are so-called TMR (tunneling magneto resistive) elements, and include a first ferromagnetic layer 303 and an insulating layer 302 formed on the first ferromagnetic layer 303. , Its insulating layer 3
02, and a second ferromagnetic layer 301 formed on top of the No. 02. The magnetization direction of the first ferromagnetic layer 303 is indicated by the arrow 30.
It is fixed in either 1a or 301b. On the other hand, the direction of magnetization of the second ferromagnetic layer 301 is
It is possible to change the direction shown by the arrow 301a and the direction shown by the arrow 301b. To reverse this magnetic field, bit line 310a and digit lines 320a and 3
Apply current to 20b. The magnetic field is inverted by applying a synthetic magnetic field of the magnetic fields formed by the two currents to the storage element 300a or 300b. Thereby, writing of data is performed. The magnetization direction of the first ferromagnetic layer 303 and the second
When the magnetization directions of the ferromagnetic layers 301 are the same, the electric resistance of the memory element 300a becomes small. First ferromagnetic layer 3
When the magnetization direction of No. 03 and the magnetization direction of the second ferromagnetic layer 301 are opposite (non-parallel), the electric resistances of the memory elements 300a and 300b increase.

At the time of reading data, n-type impurity region 41 is used.
A current is passed through the word line formed by a and 41b. Further, a current flows from the bit line 310a. Direction of magnetization of the first ferromagnetic layer 303 and the second ferromagnetic layer 30
Since the resistance of the memory element 300a changes depending on whether the magnetization direction of 1 is the same or opposite, the presence or absence of information can be determined by reading this current. Subsequent determination is made in the above-described first to first embodiments.
The same as 11.

The thus configured semiconductor memory device according to the present invention has the same effects as the semiconductor memory device according to the first embodiment.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0093]

According to the present invention as described above, it is possible to provide a semiconductor memory device in which memory elements are arranged at a high density. The above-described embodiment can be applied not only to a semiconductor memory device but also to a device in which a memory and a logic are mixed, such as a mixed memory and an SOC (system on silicon).

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line II-II in FIG.

FIG. 3 is a cross-sectional view showing a first step of the method for manufacturing the semiconductor device shown in FIG.

4 is a cross-sectional view showing a second step of the method for manufacturing the semiconductor device shown in FIG.

FIG. 5 is a sectional view of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 6 is a plan view of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram of auxiliary wiring shown in FIG.

FIG. 9 is a plan view of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 10 is a sectional view of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 11 is a circuit diagram of a semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 12 is a plan view of a first current driving unit in FIG.

FIG. 13 is a plan view of a semiconductor memory device according to an eighth embodiment of the present invention.

FIG. 14 is a circuit diagram of the decoder shown in FIG.

FIG. 15 is a circuit diagram of another decoder.

16 is a graph showing the potential of the decoder of FIG.

FIG. 17 is a circuit diagram of a semiconductor memory device according to a ninth embodiment of the present invention.

FIG. 18 is a circuit diagram of an improved semiconductor memory device.

FIG. 19 is a circuit diagram of a read circuit 160 shown in FIG.

FIG. 20 is a circuit diagram of a semiconductor memory device according to a tenth embodiment of the present invention.

FIG. 21 is a graph showing the concept of multilevel storage.

FIG. 22 is a circuit diagram of a semiconductor memory device shown for explaining a short circuit between a word line and a bit line.

FIG. 23 is a circuit diagram of a semiconductor memory device according to an eleventh embodiment of the present invention.

FIG. 24 is a circuit diagram of an improved semiconductor memory device according to an eleventh embodiment of the present invention.

FIG. 25 is a sectional view of a semiconductor memory device according to a twelfth embodiment of the present invention.

FIG. 26 is a cross-sectional view of a conventional semiconductor memory device.

[Explanation of symbols]

1 silicon substrate, 2 n-type well region, 3 p-type well region, 10a to 10g bit line, 20a to 20c
Word line, 31a to 31c, 300a, 300b storage element, 41a to 41c n-type impurity region, 60 interlayer insulating film, 61 contact hole, 301 second ferromagnetic layer, 303 first ferromagnetic layer, 351 to 363 semiconductor memory device.

Claims (10)

[Claims] 1. A semiconductor substrate, a junction type transistor formed on the semiconductor substrate, and at least a part of the junction type transistor,
And an insulating layer formed on the semiconductor substrate and having a hole reaching the surface of the semiconductor substrate, and a memory element electrically connected to a part of the junction transistor provided in the hole. The storage element has a first state in which the electric resistance is relatively high and a second state in which the electric resistance is relatively low, and the junction transistor is formed on the semiconductor substrate. Contacting the first conductivity type well region, the second conductivity type impurity region formed in the first conductivity type well region so as to face the hole, and the second conductivity type impurity region. A semiconductor memory device, comprising: a conductive region of a first conductivity type provided in the hole. 2. The first state includes an amorphous state,
The semiconductor memory device according to claim 1, wherein the second state includes a crystalline state. 3. An electric resistance, which is provided in the hole so as to be interposed between the memory element and the conductive region of the first conductivity type and has an electric resistance larger than that of the conductive region of the first conductivity type. The semiconductor memory device according to claim 1, further comprising a first heating layer that has and that heats the memory element. 4. The semiconductor memory device according to claim 1, further comprising two heating layers provided so as to be separated from the memory element and preheat the memory element. 5. The semiconductor device further comprises a plurality of the junction type transistors, the second conductivity type impurity region is formed to extend in a predetermined direction, and each of the plurality of the junction type transistors is a predetermined type. 2. The semiconductor memory device according to claim 1, wherein the second conductivity type impurity region extending in the direction is shared. 6. The semiconductor according to claim 5, further comprising a wiring layer extending along the second-conductivity-type impurity region and electrically connected to the second-conductivity-type impurity region. Storage device. 7. The semiconductor memory device according to claim 1, further comprising a well region of a second conductivity type formed in the semiconductor substrate so as to surround the well region of the first conductivity type. 8. A storage region further comprising a plurality of said storage elements and a plurality of said junction transistors electrically connected to each of said plurality of storage elements, each of said plurality of junction transistors , A plurality of second conductivity type impurity regions extending substantially parallel to each other, of the plurality of second conductivity type impurity regions, an odd-numbered one counting from a predetermined second conductivity type impurity region. The second-conductivity-type impurity region is electrically connected to a first current driving unit provided on one end side of the storage region, and is an even-numbered region counting from a predetermined second-conductivity-type impurity region. 8. The semiconductor according to claim 1, wherein the impurity region of the second conductivity type is electrically connected to a second current driving unit provided on the other end side of the storage region. Storage device. 9. The memory element includes a first ferromagnetic layer,
The semiconductor memory device according to claim 1, comprising an insulating layer formed on the first ferromagnetic layer, and a second ferromagnetic layer formed on the insulating layer. 10. The semiconductor memory device according to claim 9, wherein the first ferromagnetic layer, the insulating layer, and the second ferromagnetic layer are provided in the hole.