JP2003249100A - Semiconductor integrated circuit and method for testing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve accuracy of measurement of a normal/defective state of the semiconductor integrated circuit and to improve a fault detection rate by measuring a standby current of a semiconductor integrated circuit including a memory cell array. <P>SOLUTION: A P channel MOS transistor G1 is a switch for supplying and cutting off a power source, and inserted in a path supplying a power source to a memory cell array. When defect detection is performed by measuring a standby current without limiting to an IDDQ test, and influence of the off-leak can be reduced even if a memory cell array having much off-leak coexists by turning off the switch for supplying and cutting off a power source by a test signal ITEST. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an ASIC (Applic
(Specific Specific Integrated Circuit) and other semiconductor integrated circuits having a memory cell array, in particular,
A semiconductor integrated circuit and a semiconductor integrated circuit capable of improving a determination accuracy by measuring a standby current of a semiconductor integrated circuit including a memory cell array and determining whether the semiconductor integrated circuit is good or defective, and thus improving a failure detection rate. It relates to a circuit test method.

[0002]

2. Description of the Related Art CMOS (Complementary Metal Oxid)
In a semiconductor integrated circuit based on e Semiconductor), when the logic state of the internal signal or the signal output to the outside becomes a steady state by making the signal input from the outside into a steady state, the power supply current (standby current) supplied from the outside Becomes extremely small. Further, in a semiconductor integrated circuit having manufacturing defects or the like inside, the standby current becomes larger than its standard value.

Based on such characteristics of the semiconductor integrated circuit, called the IDDQ test, the standby current is measured, and the failure of the semiconductor integrated circuit is detected based on the measurement result.

[0004]

However, if the standard standby current of a semiconductor integrated circuit having no failure or the like is large, the failure detection rate based on the measurement result of the standby current is lowered.

In some ASICs, in addition to a logic part having various functions built therein, a memory part having a large number of memory cell arrays is provided. In memory cells, the leakage current (off-leakage) when the transistor is off tends to increase even when the logic state is in a steady state. Therefore, the leakage current due to defects in internal elements is buried in such off-leakage and isolated It becomes difficult to recognize, and as a result, the IDDQ test cannot be performed.

However, the failure detection of the memory unit itself is easier to perform the operation test than the logic unit, and the failure detection rate by the operation test is high. Therefore, the necessity of the IDDQ test is low. Therefore, the need for the IDDQ test is low in a semiconductor integrated circuit of a normal memory having no logic part or a semiconductor integrated circuit having a small specific gravity of the logic part.

FIG. 2 is a circuit diagram showing a basic structure of a memory section having a conventional memory cell array.

In this figure, reference character MC is a memory cell, reference character PC is a precharge circuit, and the internal circuits thereof are as shown in FIG. In FIG. 3, the circuit of the portion of dashed-dotted line B1 of FIG. 2 is shown. FIG. 3 shows FIG.
The same applies to the other memory cells MC, and the precharge circuit PC similarly acts on the operation of each memory cell MC.

Further, in FIG. 2, m memory cell arrays of n-bit words are provided. As a result, a memory section in which the memory cells MC are organized with an n-bit width and m words is configured. The access to the desired memory cell MC is performed by one word line WOR corresponding to the memory cell MC.
D1 to WORDm are set to the H state, and the bit line pair BIT1- * BIT1 to BITn- corresponding to the memory cell MC.
* Use BITn.

Here, in FIG. 3, the memory cell MC
Has two inverters of CMOS logic gates, the input and output of one inverter being connected to the output and input of the other inverter, thereby forming a flip-flop for holding bit data. ing. The memory cell MC has a word line WORD (WOR
Bit line pair BIT- * BIT (BIT1-) via an N-channel MOS transistor of a transfer gate which is turned on / off by one of D1 to WORDm).
* BIT1 to BITn-a pair of * BITn).

In FIG. 3, the precharge circuit PC is
When the precharge signal PCHG is in the L state before the word line WORD to be accessed is in the H state, the two P-channel MOS transistors are turned on,
The bit line pair BIT- * BIT is precharged to the H-state potential. Further, the precharge circuit PC may precharge the bit line pair to an intermediate potential between the L-state potential and the H-state potential.

In FIG. 3, when the word line WORD is in the L state and the precharge signal PCHG is in the H state, in the memory cell MC, the inverter on the left side in the figure is in the L state.
It is assumed that bit data is held so that the state is output and the right inverter outputs the H state. Then, off leak occurs as shown by arrows A1 to A3. If such an off-leakage current is large, a leak due to a defective element to be built up is buried, and it becomes difficult to separate and recognize, and the failure detection rate of the IDDQ test decreases.

The present invention has been made to solve the above-mentioned conventional problems. The standby current of a semiconductor integrated circuit including a memory cell array is measured to determine whether the semiconductor integrated circuit is good or bad. It is an object of the present invention to provide a semiconductor integrated circuit and a semiconductor integrated circuit test method capable of improving accuracy and thus improving a failure detection rate.

[0014]

First, a semiconductor integrated circuit according to the first invention of the present application is a semiconductor integrated circuit having a memory cell array, the semiconductor integrated circuit being provided in a path for supplying power to the memory cell array. The above problem is solved by providing a power supply cutoff switch for cutting off the power supply that can be turned on and off from the outside.

Further, the semiconductor integrated circuit includes a circuit for setting a standby current measurement mode from outside the semiconductor integrated circuit, and each memory cell constituting the memory cell array has a CMOS logic gate. A flip-flop circuit configured to hold bit data using a pre-charge circuit for pre-charging a bit line, and supply power to the source of a P-channel MOS transistor of the flip-flop circuit. A power supply cutoff switch on the memory cell side that is turned off in the standby current measurement mode and a precharge stop circuit that deactivates the precharge circuit in the standby current measurement mode. By configuring the switch to cut off the supply, While suppressing the Riseru array other operation speed decreases, it is possible to apply the present invention.

Next, the semiconductor integrated circuit test method of the second invention of the present application turns off the power supply cutoff switch of the semiconductor integrated circuit of the first invention, measures the standby current of the semiconductor integrated circuit, The problem is solved by determining whether the semiconductor integrated circuit is good or bad according to the magnitude of the current as the measurement result.

The operation of the present invention will be briefly described below.

The present invention is not limited to an ASIC, but relates to a semiconductor integrated circuit in which a memory section having a memory cell array and a logic section coexist. According to the present invention, in such a semiconductor integrated circuit, a power supply cutoff switch for cutting off the power supply, which can be turned on and off from the outside of the semiconductor integrated circuit, is provided in a path for supplying power to the memory cell array. There is.

Therefore, not only in the IDDQ test, but when the standby current is measured to detect a defect, if the above-mentioned power supply cutoff switch is turned off, a memory cell array with a large amount of off-leakage is mixed. Also, the influence of the off-leakage can be reduced, and the failure detection rate of the logic section can be improved.

As described above, according to the present invention, the memory cell
By measuring the standby current of the semiconductor integrated circuit including the array and determining the pass / fail of the semiconductor integrated circuit, the accuracy of the determination can be improved, and thus the failure detection rate can be improved.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of a memory section built in with a logic section in a semiconductor integrated circuit of an embodiment to which the present invention is applied.

In the semiconductor integrated circuit of this embodiment,
It has a logic section and a memory section as shown in FIG.
The IDDQ test is performed mainly for the logic part to detect the failure of the internal element. In the IDDQ test and other modes for measuring the standby current (hereinafter referred to as the standby current measurement mode), the test signal ITEST of FIG. 1 is set to the H state from outside the semiconductor integrated circuit.

The setting may be performed directly from outside or indirectly. That is, the test signal ITES
T may be input from the outside of the semiconductor integrated circuit through a predetermined terminal and set directly. Alternatively, the test signal ITEST may be generated internally, and for example, the logic state of the test signal ITEST may be indirectly manipulated by a signal input from the outside of the semiconductor integrated circuit.

In the configuration of this embodiment, the present invention is applied to the above-mentioned memory section of FIG. 2 to provide a power supply cutoff switch. The power supply cutoff switch is
In the present embodiment, it is realized by the reference symbols G1 and G2.

First, the P-channel MOS transistor G1
Is a memory cell side power supply cutoff switch provided in a path for supplying power to the source of the P-channel MOS transistor of the flip-flop circuit and turned off in the standby current measurement mode in which the test signal ITEST is in the H state. . Further, the NAND gate G2 serves as a precharge stop circuit that makes the precharge circuit PC inoperative in the standby current measurement mode.

The operation of the switch for cutting off the power supply of this embodiment will be described. First, as the first operation, the P channel M
The OS transistor G1 turns off when the test signal ITEST goes into the H state. As a result, in all the memory cells MC of the memory section, the CMOS logic gate inverters that form the flip-flops are cut off from the power supply VDD. Therefore, in the P-channel MOS transistor and the N-channel MOS transistor of the inverter, off-leakage flowing from the power supply VDD side to the ground GND side is suppressed.

Next, as a second operation of the power supply cutoff switch of the present embodiment, when the test signal ITEST goes to the H state in the NAND gate G2, regardless of the logic state of the precharge signal PCHG, The NAN
The precharge signal PCHG2 output from the D gate G2 is in the H state. Therefore, the precharge circuit PC becomes inoperative and the precharge operation is stopped. Then, in the P-channel MOS transistor of the precharge circuit PC, the bit line pair BIT1- * B from the power supply VDD side.
The current flowing to the IT1 to BITn- * BITn sides is suppressed.

As described above, by shutting off the power supply VDD as the first action and stopping the operation of the precharge circuit PC as the second action, off-leakage as indicated by reference characters A1 to A3 in FIG. 3 is suppressed. This reduces the standby current. Therefore, the leakage current due to internal element failure is
It is not buried in the leak, and the failure detection rate based on the IDDQ test and other standby current measurement results is improved.

In this embodiment, if the P-channel MOS transistor G1 of the power supply cutoff switch is provided in the path to the power supply VDD on the P-channel MOS transistor side, the flip-flop inverter
The electrical resistance from the power supply VDD to the inverter output increases, and the logic state at the inverter output changes from the L state to the H state.
The speed of transition to the state decreases. However, the speed reduction is unlikely to cause the speed reduction of the flip-flop. The increase in the electrical resistance of the path of the CMOS logic gate inverter forming the flip-flop to the power supply VDD on the P channel MOS transistor side is caused by the N channel M
Compared to the increase in the electrical resistance of the path to the ground GND on the OS transistor side, it is difficult to reduce the flip-flop operation speed. In the present embodiment, based on this point of view, the P-channel MOS transistor G1 of the power supply cutoff switch is provided in the path to the power supply VDD on the P-channel MOS transistor side.

Further, in this embodiment, since the NAND gate G2 is provided in the path until the precharge signal PCHG is input to the precharge circuit PC, the NAN is
Precharge signal PCHG for the operation time of D gate G2
Is delayed until it is input to the precharge circuit PC, and as a result, the operating speed of the precharge circuit PC decreases. However, the decrease in the operation speed of the precharge circuit PC is relatively unlikely to affect the access time of the memory section. From this point of view, in the present embodiment, the NAND gate G2 of the power supply cutoff switch is provided at the input of the precharge circuit PC.

As described above, according to this embodiment, the present invention can be effectively applied. Therefore, it is possible to improve the accuracy of the determination of the standby current of the semiconductor integrated circuit including the memory cell array and determine the pass / fail of the semiconductor integrated circuit, and thus improve the failure detection rate.

[0033]

According to the present invention, the standby current of a semiconductor integrated circuit including a memory cell array is measured to improve the accuracy of determination of whether the semiconductor integrated circuit is good or defective, thereby improving the failure detection rate. Can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a memory unit built in a semiconductor integrated circuit of an embodiment to which the present invention is applied together with a logic unit.

FIG. 2 is a circuit diagram showing a basic configuration of a memory unit having a conventional memory cell array.

FIG. 3 is a circuit diagram around a memory cell and a precharge circuit in the memory section.

[Explanation of symbols]

MC ... Memory cell PC ... Precharge circuit WORD1 to WORDm ... Word line BIT1- * BIT1 to BITn- * BITn ... Bit line pair G1 ... P channel MOS transistor G2 ... NAND gate PCHG, PCHG2 ... Precharge signal ITEST ... Test signal

Claims (3)

[Claims] 1. In a semiconductor integrated circuit having a memory cell array, a power supply cutoff for cutting off the power supply, which can be turned on and off from the outside of the semiconductor integrated circuit, in a path for supplying power to the memory cell array. A semiconductor integrated circuit having a switch for use. 2. The semiconductor integrated circuit according to claim 1, further comprising a circuit for setting a standby current measurement mode from outside the semiconductor integrated circuit, wherein each memory cell constituting the memory cell array is , A flip-flop circuit configured to hold bit data by using a CMOS logic gate, and a precharge circuit for precharging a bit line is provided, and a P-channel MOS transistor of the flip-flop circuit is provided. A memory cell side power supply cutoff switch which is provided in a path for supplying power to a source and which is turned off in the standby current measurement mode; and a precharge stop circuit which deactivates the precharge circuit in the standby current measurement mode. The power supply cutoff switch is configured by The semiconductor integrated circuit according to claim. 3. The semiconductor integrated circuit according to claim 1, wherein the switch for cutting off the power supply is turned off, the standby current of the semiconductor integrated circuit is measured, and the semiconductor integrated circuit is measured according to the magnitude of the measured current. A semiconductor integrated circuit test method, characterized in that the circuit is judged as good or bad.