JP2003249081A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device in which erasure can be performed efficiently. <P>SOLUTION: The nonvolatile semiconductor memory device has a plurality of nonvolatile memory cells arranged in an array state, a plurality of word lines WL in which the same word line is connected commonly to gates of nonvolatile memory cells arranged in the same row, and two memory cell arrays 103, 103' having a plurality of bit lines BL in which the same bit line is connected commonly to drains of nonvolatile memory cells arranged in the same column and in which source nodes of the plurality of nonvolatile memory cells are divided. Also the device is provided with source line selecting circuits 105 provided respectively between divided source nodes of the memory cell arrays 103, 103' and a boosting circuit 106, and a timing adjusting circuit 104 for shifting apply start timing of high voltage for erasure to a plurality of source nodes among a plurality of source nodes by turning on a plurality of source line selecting circuit 105. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a flash memory having a structure in which erasing is performed in block units.

[0002]

2. Description of the Related Art FIG. 5 is a schematic diagram showing a general sectional structure of one memory cell in a nonvolatile semiconductor memory device (memory). In FIG. 5, 10 is a floating gate, 11 is a control gate,
Reference numeral 12 is a drain region, and 13 is a source region. V1 is a drain voltage, V2 is a control gate voltage, and V3 is a source voltage.

For erasing data, as shown in FIG. 5, a high voltage VPP is applied to the source region 13 of the memory cell, the drain region 12 is floated, and the control gate 11 is removed.
Is fixed to the voltage GND, and electrons are emitted from the floating gate 10 to the source region 13 by the FN (Fowler-Nordheim) phenomenon, thereby lowering the threshold value.

FIG. 6 is a block diagram showing a structure of a conventional flash EEPROM using the memory cell having the above structure. In FIG. 6, reference numeral 601 is a control circuit, and 602.
Is an X decoder, 603 is a memory cell array, 604 is a booster circuit, 605 is a Y decoder, 606 is a Y gate transistor, 607 is a sense amplifier circuit, and 608 is an input / output circuit.

The memory cell array 603 is shown in FIG.
Memory cells composed of the floating gate 10 and the control gate 11 having the above structure are arranged. Memory cell array 6
03 are arranged in a matrix of m rows and n columns.
The sources of these memory cell arrays 603 are commonly connected. Further, the control gates of the memory cell array 603 are commonly connected for each row. The drains of the memory cell array 603 are commonly connected for each column. Memory cell array 6
The common source of 03 is connected to the booster circuit 604, and the high voltage necessary for erasing is supplied.

The row line (word line) WL of the memory cell array 603 is connected to the X decoder 602. A column line (bit line) BL of the memory cell array 603 is connected to a sense amplifier circuit 607 including a load transistor for reading data via a Y gate transistor 606. The sense amplifier circuit 607 is connected to an input / output circuit 608 for inputting / outputting data to / from an external terminal and a control circuit 601 for controlling the operation of each unit. The control gate of the Y gate transistor 606 is connected to the Y decoder 605. The control circuit 601 includes an X decoder 602, a Y decoder
It is connected to the decoder 605 and the booster circuit 604.

Therefore, in the conventional nonvolatile semiconductor memory device, the control gate of the memory cell has 0 volt (voltage GND).
(Fixed), floating the drain region and applying a constant voltage to the common source region, it becomes possible to erase all the memory cells at once.

[0008]

In the conventional nonvolatile semiconductor memory device, the control gate of the memory cell is set to 0 volt (fixed to voltage GND), the drain region is floated, and a constant voltage is applied to the common source region. Although cells are erased collectively, there is a problem that the erase voltage drops due to the erase current during erase, which increases the erase time.

In view of the above problems, it is an object of the present invention to provide a non-volatile semiconductor memory device that can be erased efficiently.

[0010]

In order to solve this problem, a nonvolatile semiconductor memory device according to claim 1 of the present invention is arranged in the same row as a plurality of nonvolatile memory cells arranged in an array. A plurality of word lines in which the same word line is commonly connected to the gates of the nonvolatile memory cells,
A memory cell array configuration having a plurality of bit lines in which the same bit line is commonly connected to the drains of the non-volatile memory cells arranged in the same column, and a common source node of the plurality of non-volatile memory cells is divided into a plurality. have. Further, a plurality of source line switches respectively provided between the divided common source node and the erase high voltage generation circuit, and a plurality of divided common source nodes by turning on the plurality of source line switches And a timing adjustment circuit for shifting the application start timing of the high voltage for erasing between the common source nodes divided into a plurality of parts.

According to this structure, by providing the timing adjusting circuit, the application start timing of the erase high voltage to the plurality of divided common source nodes by turning on the plurality of source line switches is divided into a plurality of timings. It is possible to shift between common source nodes. As a result, at the time of data erasing, it is possible to prevent the peaks of the erase current values of the common source nodes of the memory cell array in which the common source node is divided into a plurality from overlapping, thus suppressing the peak of the erase current value at the time of data erasing. You can
As a result, the drop of the erase voltage due to the erase current during erase can be suppressed, data can be erased efficiently, and the erase time can be shortened.

According to a second aspect of the present invention, a non-volatile semiconductor memory device has a plurality of non-volatile memory cells arranged in an array and a gate of the non-volatile memory cells arranged in the same row has the same word line. A plurality of word lines connected in common and a plurality of bit lines in which the same bit line is connected in common to the drains of the nonvolatile memory cells arranged in the same column, and a common source of the nonvolatile memory cells It has a memory cell array configuration in which a node is divided into a plurality of parts. Further, a plurality of source line switches respectively provided between the common source node divided into a plurality of high voltage generation circuits for erasing, and a high voltage for erasing to a plurality of nodes by turning on the plurality of source line switches. A plurality of pulse generation circuits for intermittently applying the voltage are provided, and the pulse timings of the plurality of pulse generation circuits are shifted from each other.

According to this structure, by providing a plurality of pulse generation circuits whose pulse timings are shifted from each other,
Since a high voltage for erasing is intermittently applied to a plurality of common source nodes divided by turning on a plurality of source line switches, a memory cell array having a plurality of common source nodes divided at the time of data erasing. It is possible to prevent the peaks of the erasing current values of the common source nodes of the above from overlapping. Therefore, it is possible to suppress the peak of the erase current value during data erase. As a result, the drop of the erase voltage due to the erase current during erase can be suppressed, data can be erased efficiently, and the erase time can be shortened.

A nonvolatile semiconductor memory device according to a third aspect of the present invention is the nonvolatile semiconductor memory device according to the second aspect, wherein pulse outputs of the plurality of pulse generating circuits do not overlap each other.

According to this structure, the erase currents of the common source nodes divided into a plurality in the memory cell array can be prevented from overlapping, so that the erase voltage drop due to the erase current during erase can be minimized. The data can be erased efficiently, and the erase time can be shortened.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

FIG. 1 is a block circuit diagram showing the overall structure of a nonvolatile semiconductor memory device (flash EEPROM) according to the first embodiment of the present invention. In FIG. 1, 101
Is a control circuit, and 102 is an X decoder. 103,10
Reference numeral 3'denotes two memory cell arrays having independent common source nodes. When the two memory cell arrays are collectively viewed, it can be said that the common source node is divided into two. Reference numeral 104 is a timing adjustment circuit, 105 is a source line selection circuit composed of a plurality of source line switches, 106 is a booster circuit which is a high voltage generation circuit for erasing, 107 is a Y decoder, 108 is a Y gate transistor, 109 is a sense amplifier. A circuit, 110 is an input / output circuit.

In the flash EEPROM of FIG.
Each of the memory cell arrays 103 and 103 'is composed of memory cells each having a floating gate and a control gate having the structure shown in FIG. 5, and arranged as shown in FIG.

The memory cell array 103 is arranged in a matrix of m rows and n columns. Memory cell array 10
The three control gates are commonly connected row by row. The drains of the memory cell array 103 are commonly connected for each column. The common source node of these memory cell arrays 103 is connected to the common source line SL1.

The memory cell array 103 'is also arranged in a matrix of m rows and n columns, and the control gates of the memory cell array 103' are commonly connected for each row.
The drains of the memory cell array 103 'are commonly connected for each column. The common source node of these memory cell arrays 103 ′ is connected to a common source line SL 2 which is different from the memory cell array 103.

In FIG. 2, M11 to M44 are memory cells constituting the memory cell array 103, and M51 to M44.
M84 is a memory cell that constitutes the memory cell array 103 '. WL11 to WL14 and WL21 to WL24 are row lines (word lines). BL1 to BL4 are column lines (bit lines).

Each memory cell array 103, 10
The common source lines SL1 and SL2 of 3'are selected by the source line selection circuit 105 of FIG. 1 and connected to the booster circuit 106, and a high voltage required for erasing is supplied. Further, the common source line SL2 is connected with a timing adjustment circuit 104 capable of controlling the timing at which application of a high voltage to the source line is started.

In this flash EEPROM, a memory cell array is divided into a plurality of memory cell arrays, and each memory cell array 10 is divided.
Since the individual source lines SL1 and SL2 are connected to 3, 103 ', the memory cell arrays 103, 1
Not only 03 'can be erased collectively, but each memory cell array 103, 103' can be erased individually.

Each memory cell array 103, 103 '
When individually erasing, the source line selection circuit 105
It is necessary to select the source lines SL1 and SL2 connected to the memory cell array 103 or 103 'to be erased.

The present invention describes the case of collectively erasing a plurality of divided memory cell arrays 103 and 103 '. In this case, the source line selection circuit 105 selects all the source lines SL1 and SL2. .

The row lines WL (WL11 to WL14, WL21 to WL24) of the memory cell arrays 103 and 103 'are
It is connected to the X decoder 102. Memory cell array 10
The column lines BL (BL1 to BL4) of 3, 103 ′ are connected to the sense amplifier circuit 109 including a load transistor for reading data via the Y gate transistor 108. The sense amplifier circuit 109 is connected to an input / output circuit 110 for inputting / outputting data to / from an external terminal and a control circuit 101 for controlling the operation of each unit. The control gate of the Y gate transistor 108 is the Y decoder 107.
Connected to. The control circuit 101 includes an X decoder 102,
It is connected to the Y decoder 107 and the booster circuit 106.

The operation of the above arrangement will be described below. When erasing all memory cells at once, the voltage generated in the booster circuit 106 drops due to the erase current. The voltage drop is most pronounced when the erase current peaks. Therefore, in the first embodiment, the timing at which the high voltage is applied to the common source lines SL11 and SL2 of the divided memory cell arrays 103 and 103 ′ is set so that the peaks of the erase currents do not overlap.
After the selection is made by the source line selection circuit 105, the timing adjustment circuit 104 makes it possible to perform control so that the timing at which the high voltage is applied to the plurality of divided common source lines SL1, SL2 is shifted.

As described above, in the case where the memory cell array is divided and the individual source lines SL11 and SL2 are connected to the respective memory cell arrays 103 and 103 ', when all the memory cell arrays 103 and 103' are erased. In some cases, the source line selection circuit 105 is necessary because the memory cell arrays 103 and 103 'may be individually erased.

In the present invention, all memory cell arrays 1
03, 103 ′ is erased, or only a plurality (not all) of the memory cell arrays 103, 103 ′ is erased by controlling the timing adjustment circuit 105 and individually erasing each of the memory cell arrays 103, 103 ′. Need not adjust the timing with the timing adjustment circuit 105.

According to this embodiment, since the timing adjusting circuit 104 is provided, the source line selecting circuit 10 is provided.
A plurality of common source nodes (common source lines SL1, S
It is possible to shift the application start timing of the erase high voltage to L2) between the common source nodes divided into a plurality of parts. As a result, the common source node is divided into a plurality of memory cell arrays 103 and 10 when erasing data.
It is possible to prevent the peaks of the erase current values of the common source nodes 3 ′, that is, the memory cell arrays 103 and 103 ′ from overlapping, and thus suppress the peaks of the erase current value during data erase.

As a result, the drop of the erase voltage due to the erase current during erase can be suppressed, data can be erased efficiently, and the erase time can be shortened. That is, since the peak of the erase current value at the time of data erase can be suppressed, the drop of the erase high voltage generated in the booster circuit 106 can be suppressed, the data can be erased efficiently, and the erase time can be reduced. Can be shortened.

FIG. 3 is a block circuit diagram showing the overall structure of a nonvolatile semiconductor memory device (flash EEPROM) according to the second embodiment of the present invention. In FIG. 3, 30
4, 304 'are pulse generation circuits, which replace the timing adjustment circuit 104 of FIG.

301 is a control circuit, 302 is an X decoder,
Reference numerals 303 and 303 'denote memory cell arrays having common source nodes independent of each other, 305 a source line selection circuit including a plurality of source line switches, 306 a boosting circuit which is a high voltage generation circuit for erasing, 307 a Y decoder, and 308 a reference numeral 308. A Y-gate transistor, 309 is a sense amplifier circuit, and 310 is an input / output circuit, which are the same as the elements of the same name in FIG.

In the flash EEPROM of FIG.
A memory cell array 303 having an independent common source node,
The common source lines SL1 and SL2 connected to the respective common source nodes of 303 ′ have pulse generation circuits 304 and 304 ′.
Respectively connected to. Pulse generator circuits 304 and 3
04 ′ is intermittent at a constant pulse interval until each source line switch in the source line selection circuit 305 is turned on and the erase operation is started, and then the source line switch is turned off and the erase operation is completed. , The start of erase operation,
The stop can be controlled.

In this case, the pulse generating circuits 304, 30
The 4'pulse outputs are in opposite phase to each other so that they do not overlap each other. The pulse outputs are allowed to partially overlap. The pulse generation circuits 304 and 304 ′ are selected by the source line selection circuit 305 and further connected to the booster circuit 106,
The high voltage required for erasing is supplied to the common source lines SL1 and SL2.

FIG. 4 is a timing chart showing the time change of the applied voltage to the common source lines SL1 and SL2. In FIG. 4, the voltage applied to the common source lines SL1 and SL2 is repeatedly started and stopped with a constant pulse width so that the peaks of the erase current values do not overlap during the erase operation of the respective memory cell arrays. Therefore, the booster circuit 30
The voltage drop generated in 6 can be suppressed.

According to this embodiment, a plurality of pulse generation circuits 304 and 30 whose pulse timings are shifted from each other are provided.
By providing 4 ′, a plurality of common source nodes (common source lines SL 1 and SL 2) divided by turning on a plurality of source line switches in the source line selection circuit 105.
Since the high voltage for erasing is applied intermittently to the
During data erasing, the peaks of the erase current values of the memory cell arrays 303 and 303 ′ in which the common source node is divided into a plurality can be prevented from overlapping.

Therefore, at the time of erasing data, each common source node, that is, the memory cell arrays 303, 30
It is possible to suppress the peak of the erase current value every 3 '. As a result, the drop of the erase voltage due to the erase current during erase can be suppressed, data can be erased efficiently, and the erase time can be shortened.

In both the first and second embodiments, the case where the memory cell array is divided into two has been described, but the same applies when the memory cell is divided into an arbitrary plurality.

[0040]

As described above, according to the present invention, since it is possible to suppress the drop of the erase voltage due to the erase current during data erase, the data can be erased efficiently and the erase time can be shortened. Can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a memory cell array in the embodiment of FIG.

FIG. 3 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing a change over time of an applied voltage to a common source node in the second embodiment.

FIG. 5 is a schematic diagram showing a cross-sectional structure of a flash EERROM cell.

FIG. 6 is a block diagram showing a configuration of a conventional flash EEPROM.

[Explanation of symbols]

101, 301, 601 Control circuit 102, 302, 602 X decoder 103, 103 ', 303, 603 Memory cell array 104 Timing adjustment circuit 105, 305 Source line selection circuit 106, 306, 604 Booster circuit 107, 307, 605 Y decoder 108 , 308, 606 Y gate transistors 109, 309, 607 Sense amplifier circuits 110, 310, 608 Input / output circuits 304, 304 'Pulse generation circuits SL1, SL2 Source line 10 Floating gate 11 Control gate 12 Drain region 13 Source region

Claims (3)

[Claims] 1. A plurality of nonvolatile memory cells arranged in an array, a plurality of word lines in which the same word line is commonly connected to the gates of the nonvolatile memory cells arranged in the same row, and the same column. A plurality of bit lines in which the same bit line is commonly connected to the drains of the non-volatile memory cells disposed in the memory cell array configuration, and a common source node of the plurality of non-volatile memory cells is divided into a plurality of memory cell array configurations. A plurality of common source nodes and a plurality of source line switches respectively provided between the common source node and the high voltage generation circuit for erasing, and the plurality of common divided common lines when the plurality of source line switches are turned on. And a timing adjustment circuit for shifting the application start timing of the erase high voltage to the source node among the plurality of divided common source nodes. Nonvolatile semiconductor memory device. 2. A plurality of non-volatile memory cells arranged in an array, a plurality of word lines in which the same word line is commonly connected to the gates of the non-volatile memory cells arranged in the same row, and the same column. A plurality of bit lines in which the same bit line is commonly connected to the drains of the non-volatile memory cells disposed in the memory cell array configuration, and a common source node of the plurality of non-volatile memory cells is divided into a plurality of memory cell array configurations. And a plurality of source line switches respectively provided between the common source node and the high voltage generation circuit for erasing, and erasing to the plurality of nodes by turning on the plurality of source line switches. A plurality of pulse generating circuits for intermittently applying a high voltage for use, and the pulse timings of the plurality of pulse generating circuits are shifted from each other. Volatile semiconductor memory device. 3. The non-volatile semiconductor memory device according to claim 2, wherein the pulse outputs of the plurality of pulse generation circuits do not overlap each other.