JP2003242027A - Interface device, data processing system, and data processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To read arbitrary data stored in a memory at a high speed. <P>SOLUTION: Firstly, a CPU 4 gives an address write command to an interface 2 based on the address write information written on a program. Next, the address for a memory is written in an address buffer 10 based on the address write command given from the CPU 4. The data stored in the memory 3 are firstly read based on the address for memory written in the address buffer 10, and stored in the data buffer 12. When the data are read, the CPU 4 gives the first read command to the interface 2, and if the data designated by the first read command are stored in the data buffer 12, the data are read from the data buffer 12. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface device for reading data stored in a data storage means and a data processing system equipped with the interface device. The present invention also relates to a data processing method for reading the data stored in the data storage means.

[0002]

2. Description of the Related Art In a storage device that stores data in a computer system, a memory such as a ROM or a flash memory that operates at a relatively low speed is used in order to increase the capacity of the storable data and reduce the cost. It is used. However, if a memory that operates at a relatively low speed is used in a storage device, the speed of reading data stored in the memory or the speed of storing data in the memory slows down, so that the operation of the entire computer system is low. It will be speed.

Therefore, in a computer system, a disk cache function and a DMA (Direct Mem) are provided in order to realize a large capacity, a low cost and a high speed operation.
oryAccess) function etc. are adopted.

As shown in FIG. 18, a data storage device 200 having a disk cache function has a memory 20 capable of storing a large amount of data and operating at a low speed.
1, a cache memory 202 having a small amount of data that can be stored and a high-speed operation, and a CPU (Central Processing Unit; Central Processing Uni) that reads data stored in the memory 201 and the cache memory 202.
t) 203.

In the disk cache function, first, the data once read from the memory 201 is temporarily stored in the cache memory 202. And the CPU 203
Reads from the cache memory 202 when reading the data again. That is, in the disk cache function, the locality of the read data that once read data is likely to be read soon afterwards is used to reduce the number of times the CPU 203 reads the data directly from the memory 201. , The time to read data is shortened.

On the other hand, as shown in FIG. 19, a data storage device 210 having a DMA function has a memory 211 that has a large amount of data that can be stored and that operates at a low speed.
A DMA controller 212 that controls reading or writing of data to and from the memory 211, and data read by the DMA controller 212 from the host device 2
13 and the like, and an interface 214 for supplying the data supplied from the host device 213 to the DMA controller 212.

The DMA function is a function for reading and writing data to and from the memory 211 under the control of the DMA controller 212 without involving a CPU (not shown). That is, when the data storage device 210 adopting the DMA function is installed in a computer system, the CPU can perform operations other than reading or writing of data in the memory 211 in parallel, so that the operation efficiency of the entire computer system is improved. It becomes possible to improve.

[0008]

However, in the data storage device 200 which employs the disk cache function, when reading data other than the data that has been read once, the CPU 203 reads the data directly from the memory 201. That is, when reading data other than the data that has been read once, the data reading speed becomes slow, and the operation of the entire computer system becomes slow.

Further, since the DMA controller 212 has a complicated structure, it may be difficult to design or mount it in a data storage device. That is, it may be difficult to manufacture the data storage device 210 that employs the DMA function.

The present invention has been proposed in view of the conventional circumstances described above, and it is possible to read the data stored in the data storage means at a high speed regardless of the locality of the read data. It is an object of the present invention to provide an interface having a simple configuration and a data processing system equipped with the interface. Another object of the present invention is to provide a data processing method capable of reading the data stored in the data storage means at a high speed regardless of the locality of the data.

[0011]

An interface device according to the present invention is an interface device which is connected to a data storage means and reads out data stored in the data storage means, and an address to which an address of the data storage means is written. Storage means, control means for reading the data stored in the data storage means based on the address written in the address storage means, and temporary storage means for temporarily storing the data read by the control means And is provided.

In the data processing system according to the present invention, the data storage means, the address storage means in which the address of the data storage means is written, and the data storage means are stored in the data storage means based on the address written in the address storage means. Interface means including a pre-reading control means for pre-reading the stored data, and a temporary storage means for temporarily storing the pre-read data by the pre-reading control means, and an address of the data storage means for the address storage means. And a control unit for reading the data stored in the temporary storage unit.

Further, the data processing method according to the present invention is
In a data processing method for reading data stored in a data storage means, a step of writing an address of the data storage means into the address storage means, and the data storage based on the address written into the address storage means And a step of temporarily storing the pre-read data in the temporary storage means, and a step of reading the data stored in the temporary storage means. Characterize.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First Embodiment First, a first embodiment of the present invention will be described.

The present invention can be applied to the data processing system 1 and the interface 2 shown in FIG.

The data processing system 1 includes an interface 2 to which a memory 3 is connected and a central processing unit (Ce).
ntral Processing Unit; hereinafter referred to as CPU. ) 4
With. Further, the interface 2 and the CPU 4 are connected to the bus 5.

The memory 3 stores programs and data. The memory 3 is composed of a plurality of memory cells, and each memory cell is provided with an address such as "4000" or "8000" (hereinafter referred to as a memory address). Note that hexadecimal numbers are actually used as the addresses, but in the present embodiment, they are expressed in decimal numbers for convenience of explanation.

In this embodiment, a ROM (Read Only Memory) is used as the memory 3. Also,
In the present embodiment, the memory 3 has 6000 memory cells, and each memory cell has 1000 to 6 memory cells.
It is assumed that a memory address of 999 is given.

The interface 2 is the address buffer 1
0, a controller 11, and a data buffer 12. The interface 2 uses the data buffer 1 based on the first data read command supplied from the CPU 4.
The data stored in 2 or the data stored in the memory 3 is output to the bus 5. In the interface 2, the controller 11 supplies the second data read command to the memory 3 based on the address write command supplied from the CPU 4 and instructing to write the specific memory address in the address buffer. The data stored in the data buffer 12 is read in advance (hereinafter referred to as prefetch) and stored in the data buffer 12. Details of the interface 2 will be described later.

The CPU 4 controls the interface 2 and each part (not shown) provided in the computer system in which the data processing system 1 is mounted. Also, C
The PU 4 is described in the program, for example, and is a first data read command to the interface 2 based on the data read information that commands to read the data stored in the memory cell of the specific memory address in the memory 3. To supply the memory 3 or the data buffer 12
Read the data stored in.

More specifically, first, the interface 2 confirms the data buffer 12 in response to the supplied first data read command. Then, when the data designated to be read by the first data read command is stored in the data buffer 12, the data is read from the data buffer 12, and when the data is not stored in the data buffer 12, the data is read. Read from the memory 3. Further, the CPU 4 supplies an address write command to the interface 2 on the basis of the address write information written in the program and instructing to write a specific memory address in the address buffer 10 to the address buffer 11. Write the address to.

The interface 2 will be described in detail below.

The address buffer 10 is composed of one memory cell, and an address "0000" (hereinafter referred to as an address buffer address) is given to the memory cell. Then, a memory address is written in the memory cell of the address buffer 10 based on an address write command.

The controller 11 uses the address buffer 1
Recognizing that the memory address has been written to 0, the prefetch instruction is supplied to the memory 3, the data stored in the memory 3 is read based on the written memory address, and the data buffer 12 is read. Remember. Specifically, the controller 11 reads the data stored in the memory cell of the memory address written in the address buffer 10 and the predetermined number of memory cells in which the memory cell and the memory address are continuous. Also,
The controller 11 recognizes that the interface 2 is supplied with the first data read command, supplies the memory 3 with the second data read command, and reads the data designated by the first data read command.

In this embodiment, the controller 1
In No. 1, the memory cell of the memory address written in the address buffer 10 is set as the head, and the data stored in 100 consecutive memory cells is pre-read. For example, when “4000” is written in the address buffer 10, the controller 11 prefetches the data written in the memory cell whose memory address is 4000-4099.

The data buffer 12 is the controller 11
The data prefetched from the memory 3 is temporarily stored.

In the interface 2 described above, the memory address is written in the address buffer 10 to pre-read the data stored in the memory 3. The writing of the memory address to the address buffer 10 is performed based on the address writing information described in the program. That is, the interface 2 performs prefetching at arbitrary timing by writing address write information at an arbitrary position on the program, and by setting the address to be written in the address buffer 10 as an arbitrary memory address. It is possible to read ahead the data stored in any memory cell. Therefore, interface 2
Regardless of the locality of the data to be read, it is possible to perform flexible and efficient prefetching and read the necessary data at high speed.

A so-called write command is used as the address write information. That is, interface 2
Allows the data to be prefetched using a command that has been conventionally used on a program, and the data can be prefetched easily.

The operation of the data processing system 1 described above is as described below.

When prefetching data in the data processing system 1, as shown in FIG. 2, first, in step S1, the CPU 4 instructs the interface 2 based on the address write information written in the program. Supply an address write command.

Next, in step S2, a specific memory address is written in a specific memory cell in the address buffer 10 based on the address write command.

Next, in step S3, the controller 11 recognizes that the memory address has been written in the address buffer 10 and supplies a prefetch instruction to the memory 3.

Then, in step S4, the data stored in 100 consecutive memory cells starting from the memory cell of the memory address written in the address buffer 10 is preread, and the data buffer 1 is sequentially read.
2 is supplied.

Next, in step S5, the data buffer 12 sequentially stores the data supplied from the memory 3.

Further, in step S6, it is determined whether the first data read command is supplied from the CPU 4 during the prefetch. When the first data read command is not supplied, the process proceeds to step S7, and when the first data read command is supplied, the process proceeds to step S20. The operation of the data processing system 1 after step S20 will be described later.

Then, in step S7, it is determined whether or not the prefetching is completed. When the prefetching is not completed, the process returns to step S4 and the prefetching is continued.

As the address write information described in the program, a so-called write command which is normally used to instruct the writing of data to the memory can be used. For example, "WRIT" in the program can be used.
A write command described as “E (address for address buffer) (address for memory)” is used. That is, in the data processing system 1, it is possible to prefetch data using an existing command.

The operation of reading data in the data processing system 1 is as shown in FIG. First, in step S10, based on the data read information described in the program, for example, C
The PU 4 supplies the interface 2 with the first data read command.

Next, in step S11, it is determined whether or not the interface 2 is prefetching. When pre-reading is being performed, the process proceeds to step S20 described later, and when pre-reading is not being performed, the process proceeds to step S12.

In step S12, the data buffer 12 provided in the interface 2 is confirmed, and the first buffer
It is determined whether or not the data instructed to be read by the data read command is stored in the data buffer 12. If the data is stored in the data buffer 12, the process proceeds to step S13, and if it is not stored in the data buffer 12, the process proceeds to step S14.

In step S13, the data buffer 12
Data is read out and output to the bus 5.

On the other hand, in step S14, the controller 11 supplies a second data read command to the memory 3.

Then, in step S15, the data instructed to be read by the second data read command is read from the memory 3 and output to the bus 5.

Further, when the first data read command is supplied to the interface 2 during the prefetching of data in the data processing system 1, FIG.
As shown in, first, in step S20, it is determined whether or not the data designated to be read by the first data read command matches the data being read ahead. If they do not match, the process proceeds to step S21, and if they match, the process proceeds to step S30.

In step S21, first, the supply of data from the memory 3 to the data buffer 12 is interrupted.

Next, in step S22, the controller 11 supplies the second data read command to the memory 3 and reads the data designated to be read by the first data read command from the memory 3.

Next, in step S23, the data designated to be read by the first data read command is read from the memory 3 and output to the bus 5. Then, in step S24, the interface 2 restarts prefetching.

On the other hand, in step S30, first,
Data designated to be read by the first data read command is read from the data buffer 12 and output to the bus 5. That is, prefetching of data from the memory 3 and reading of data from the data buffer 12 are performed in parallel.

While the pre-reading of data from the memory 3 and the reading of data from the data buffer 12 are being performed in parallel, the reading of data from the data buffer 12 is performed from the memory 3 in step S31. It is determined whether or not the data read ahead has been caught up. When it cannot catch up, it progresses to step S32, and when it catches up, it progresses to step S41.

Then, in step S41, the supply of data from the memory 3 to the data buffer 12 is interrupted, and in step S42, the controller 11 supplies a second data read command to the memory 3, and the memory 3 outputs the first data read command. The data specified to be read by the data read command is read.

Next, in step S43, the data designated to be read by the first data read command is read from the memory 3 and output to the bus 5, and the data is stored in the data buffer 12. .

On the other hand, in step S32, it is determined whether or not the reading of the data from the data buffer 12 is completed. When the reading of the data from the data buffer 12 is not completed, the process returns to step S30.

Next, the operation of the data processing system 1 will be described with a specific example. In the following, after the data processing system 1 pre-reads the data stored in the memory cells whose memory addresses are 4000 to 4099 as shown in FIG.
An example will be given when executing a program in which it is described that the data stored in the memory cells 0 to 4049 is read.

First, "WRITE 0000 400
According to the address write information written in the program "0", the CPU 4 sets "400" to the memory cell whose address in the address buffer 10 is 0000.
An address write command for instructing to write "0" is supplied to the interface 2.

Next, by supplying the address write command to the interface 2, the address buffer 10
Then, "4000" is written in the memory cell whose address buffer address is 0000.

Next, the controller 11 recognizes that "4000" has been written in the address buffer 10,
A pre-reading instruction for pre-reading the data stored in each memory cell whose memory address is 4000 to 4099 is supplied to the memory 3.

Next, the data stored in each memory cell having a memory address of 4000 to 4099 is read from the memory 3 and supplied to the data buffer 12.

Next, the data buffer 12 stores the data supplied from the memory 3.

Then, it is judged whether or not the first data read command is supplied, and also it is judged whether or not the prefetch is completed, and the preread is completed without supplying the first data read command. It is decided.

Next, "READ 4000 to 40
The CPU 4 supplies the first data read command to the interface 2 in accordance with the data read information written on the program "49".

Then, it is confirmed that the controller 11 is not in the middle of prefetching the data.

Next, the data buffer 12 is confirmed by the controller 11, and it is recognized that the data stored in the memory cells whose memory addresses are 4000 to 4049 in the memory 3 are stored in the data buffer 12. To be done.

Then, the data is stored in the data buffer 12
Are read out from and output to the bus 5.

As described above, according to the data processing system 1 according to the first embodiment, necessary data can be read at high speed. Further, the computer system equipped with the data processing system 1 operates at high speed.

Further, when prefetching in the data processing system 1, the CPU 4 does not operate except when writing the memory address to the address buffer 10. Therefore, in the data processing system 1, the load on the CPU 4 for reading data is reduced, and the computer system equipped with the data processing system 1 operates at high speed.

Furthermore, since the data processing system 1 has a simple structure, it can be easily designed and mounted on a computer system.

Although the address buffer 10 according to the first embodiment is composed of one memory cell,
A plurality of addresses may be stored by having a plurality of memory cells.

Although the ROM 3 is used as the memory 3 in the above description, a semiconductor memory other than the ROM having a low speed may be used. Further, the memory 3 is a semiconductor memory such as a memory stick that can be removed from the data processing system 1, a CD (Compact Disc), or a DV.
It may be a randomly accessible recording medium such as D or MD (registered trademark).

Second Embodiment Next, a second embodiment of the present invention will be described.

The present invention can be applied to the data processing system 20 shown in FIG. 6 and the interface 21 mounted on the data processing system 20.

The data processing system 20 comprises an interface 21 to which the memory 3 is connected and a CPU 23. Further, the interface 21 and the CPU 23 are connected to the bus 24.

The interface 21 includes a first address buffer 31, a second address buffer 32, a controller 33, a first data buffer 34, and a second data buffer 35. The interface 21 is
Based on the first data read command supplied from the CPU 23, the data stored in the first data buffer 34, the second data buffer 35, or the memory 3 is output to the bus 24. In the interface 21, C
Based on the write command supplied from the PU 23, the controller 33 supplies the second data read command to the memory 3 to pre-read the data stored in the memory 3 to read the data stored in the first data buffer 34 or the second data buffer 34. The data is stored in the data buffer 35. Details of the interface 21 will be described later.

The CPU 23 controls the interface 21 and each part (not shown) provided in the computer system in which the data processing system 20 is mounted. Further, the CPU 23 uses the interface 21 based on, for example, the data read information written on the program.
The first data read command is supplied to the memory 3, the first data buffer 34, or the second data buffer 3
The data stored in 5 is read. More specifically, first, the interface 21 confirms the first data buffer 34 and the second data buffer 35. Then, when the data designated to be read by the first data read command is stored in the first data buffer 34, the data is stored in the first data buffer 34.
From the second data buffer 35.
When the data is stored in, the data is read from the second data buffer 35. On the other hand, when the data is not stored in either the first data buffer 34 or the second data buffer 35, the data is stored in the memory 3
Read from. Further, the CPU 23 supplies an address write command to the interface 21 based on the address write information written in the program, and writes the address to the first address buffer 31 or the second address buffer 32. .

The interface 21 will be described in detail below.

The first address buffer 31 is composed of one memory cell, and an address "0000" (hereinafter referred to as a first address buffer address) is given to the memory cell. Then, the memory address is written in the memory cell of the first address buffer 31 based on the address write command supplied from the CPU 23.

The second address buffer 32 is composed of one memory cell, and the memory cell has "0020".
(Hereinafter, referred to as a second address buffer address) is assigned. A memory address is written in the memory cell of the second address buffer 32 based on an address write command supplied from the CPU 23.

The controller 33 recognizes that the memory address has been written in the first address buffer 31 and supplies a pre-read command to the memory 3, and the memory 33 stores it in the memory 3 based on the written address. The stored data is pre-read and supplied to the first data buffer 34.
In addition, the controller 33 uses the second address buffer 3
It is recognized that the memory address has been written in 2, and the data stored in the memory 3 is pre-read based on the written memory address and supplied to the second data buffer 35. Further, the controller 33 recognizes that the first data read command is supplied to the interface 21, supplies the second data read command to the memory 3, and is designated by the first data read command to read. The data is read from the memory 3.

In the present embodiment, the data stored in 100 consecutive memory cells starting from the memory cell of the memory address written in the first address buffer 31 or the second address buffer 32. Will be read ahead. For example, when “4000” is written in the first address buffer 31, the data written in the memory cells whose memory addresses are 4000 to 4099 is pre-read and the first data buffer 3
4 is stored. When “5000” is written in the second address buffer 32, the data written in the memory cell whose memory address is 5000 to 5099 is preread and stored in the second data buffer 35.

The interface 21 described above is the first
Address buffer 31 and second address buffer 3
2, a first data buffer 34, and a second data buffer 35.

The operation of the data processing system 20 described above will be specifically described as follows. In the following, as shown in FIG. 7, the memory address is 4000
To 4099, the data stored in the memory cells are read ahead and the memory address is changed from 5000 to 5
The data stored in the memory cell 099 is pre-read, and the memory address is 4000 to 4049.
An example will be given when executing a program for reading the data stored in the memory cell.

First, "WRITE 0000 400
The CPU 23 supplies the address write command to the interface 21 in accordance with the address write information written in the program "0".

By supplying the address write command to the interface 21, the address buffer address in the first address buffer 31 becomes 00.
“4000” is written in the memory cell that is 00.

Next, the controller 33 recognizes that "4000" has been written in the first address buffer 31 and gives an instruction to preread the data stored in the memory cells having memory addresses 4000 to 4099. The pre-reading instruction to perform is supplied to the memory 3.

Next, the memory addresses are changed from 4000 to 4
The data stored in the memory cell 099 is read from the memory 3 and supplied to the first data buffer 34.

Then, the first data buffer 34 stores the data supplied from the memory 3.

Next, "WRITE 0020 500
The CPU 23 supplies the address write command to the interface 21 in accordance with the address write information written in the program "0".

The address write command is supplied to the interface 21 so that the address buffer address in the second address buffer 32 becomes 00.
“5000” is written in the memory cell of 20.

Next, the controller 33 recognizes that "5000" has been written in the second address buffer 32, and instructs to prefetch the data stored in the memory cells whose memory addresses are 5000 to 5099. The pre-reading instruction to perform is supplied to the memory 3.

Next, the data stored in the memory cells whose memory addresses are 5000 to 5099 in the memory 3 are read from the memory 3 and supplied to the second data buffer 35. Then, the second data buffer 35 stores the data supplied from the memory 3.

Next, "READ 4000 to 40
The CPU 23 supplies a first data read command to the interface 21 in accordance with the data read information written on the program "49".

Next, in the interface 21, the first
The data stored in the data buffer 34 and the second data buffer 35 of the first data buffer 3 are confirmed, and the data stored in the memory cells of the memory 3 whose memory addresses are 4000 to 4049 are
4 is confirmed to be stored.

Then, the controller 33 reads the data stored in the memory cells whose memory addresses are 4000 to 4049 in the memory 3 from the first data buffer 34 and outputs it to the bus 24.

As described above, according to the data processing system 20 of the second embodiment of the present invention, the interface 21 has two
Since one address buffer and two data buffers are provided and the data prefetched from the memory 3 can be divided and stored in two, they are stored in physically distributed areas although they are logically continuous. It is possible to prefetch the existing data and output it logically continuously at high speed.

Further, in the data processing system 20, when the program being executed has a branch, the data necessary for proceeding to one side is stored in the first data buffer 34, and necessary for proceeding to the other side. By storing such data in the second data buffer 35, it is possible to read ahead all the data used at each branch destination and read the data at high speed when either program is executed.

Further, in the data processing system 20, it is possible to preread important data or data that is frequently used.

The data processing system 20 according to the second embodiment has two address buffers and two data buffers as described above, but a data processing system having three or more address buffers and data buffers is also considered. . Third Embodiment Next, a third embodiment of the present invention will be described.

The present invention can be applied to the data processing system 40 and the interface 41 shown in FIG.

The data processing system 40 includes a CPU 42.
And an interface 41 to which the first memory 43 and the second memory 44 are connected. Further, the interface 41 and the CPU 42 are connected to the bus 45. The interface 41 is the address buffer 5
0, a controller 51, and a data buffer 52. Here, the address buffer 50 is supposed to be able to store a plurality of addresses.

First memory 43 and second memory 44
Can be the same as the memory 3 described in the first embodiment. Therefore, the detailed description of the first memory 43 and the second memory 44 is based on the description of the memory 3 in the first embodiment.

Different addresses are given to the respective memory cells forming the first memory 43 and the respective memory cells forming the second memory 44. In the present embodiment, addresses of 1000 to 6999 are assigned to the respective memory cells that make up the first memory 43, and 7,000 to 12999 are given to the respective memory cells that make up the second memory 44. Address is assigned.

The operation of the data processing system 40 described above is as described below.

When prefetching data in the data processing system 40, as shown in FIG. 9, first, in step S80, the CPU 42 instructs the interface 41 based on the address write information written in the program. Supply an address write command.

Next, in step S81, the memory address is written in the memory cell of the address buffer 50 based on the address write command.

Next, in step S82, the controller 51 recognizes that the memory address has been written in the address buffer 50, and the first memory 43 or the second memory 43 is detected.
The prefetch instruction is supplied to the memory 44 of

Then, in step S83, the data stored in, for example, 100 consecutive memory cells starting from the memory cell of the memory address written in the address buffer 50 is preread and supplied to the data buffer 52. .

Next, in step S84, the data buffer 52 stores the data supplied from the memory 3.

Further, in step S85, it is determined whether or not the first data read command is supplied from the CPU 42 during the prefetch. When the first data read command is not supplied, the procedure proceeds to step S86, and when the first data read command is supplied, the step S1.
Go to 00. The operation of the data processing system 40 after step S100 will be described later.

Then, in step S86, it is determined whether or not the prefetching is completed. When the prefetching is not completed, the process returns to step S83 to continue the prefetching.

The operation of reading data in the data processing system 40 is as shown in FIG. First, in step S90, the CPU 42 supplies the first data read command to the interface 41 based on the data read information described in the program, for example.

Next, in step S91, it is determined whether or not the interface 41 is prefetching. If pre-reading is in progress, the process proceeds to step S100 described later, and if pre-reading is not performed, the process proceeds to step S92.

In step S92, the data buffer 52 provided in the interface 41 is confirmed, and the controller 51 determines whether or not the data instructed to be read by the first data read command is stored in the data buffer 52. to decide.

When the data is stored in the data buffer 52, the process proceeds to step S93, the data is read from the data buffer 52 and output to the bus 45.

When the data is not stored in the data buffer 52, the process proceeds to step S94, and the controller 51 stores the data designated by the first data read command in the first memory 43. Determine whether or not If it is stored in the first memory 43, the process proceeds to step S95, and if it is not stored, the process proceeds to step S97.

In step S95, the controller 51 supplies the second data read command to the first memory 43. Next, in step S96, the data is read from the first memory 43 and output to the bus 45.

On the other hand, in step S97, the controller 51 supplies a second data read command to the second memory 44. Next, in step S98, the second
The data is read from the memory 44 and output to the bus 45.

Furthermore, while the data processing system 40 is prefetching data, the interface 4
When the first data read command is supplied to 1,
As shown in FIG. 11, first, in step S100, the controller 51 determines whether or not the data designated to be read by the first data read command matches the data being read ahead. If they do not match, the process proceeds to step S101, and if they match, S1
Go to 10.

In step S101, first, the first
The supply of data from the memory 43 or the second memory 44 to the data buffer 52 is interrupted.

Next, in step S102, the controller 51 determines whether or not the data designated to be read by the first data read command is stored in the first memory 43. If it is stored in the first memory 43, the process proceeds to step S103, and if it is not stored, the process proceeds to step S105.

In step S103, the controller 51 supplies the second data read command to the first memory 43, and in step S104, the data is read from the first memory 43 and supplied to the bus 45.

On the other hand, in step S105, the controller 51 supplies the second data read command to the second memory 44, and in step S106, the data is read from the second memory 44 and supplied to the bus 45. Then, in step S107, the interface 41 restarts prefetching.

On the other hand, in step S110, the data is read from the data buffer 52 and output to the bus 45. Then, in step S111, the controller 51 determines whether the read from the data buffer 52 has caught up with the prefetch, and when the read from the data buffer 52 has caught up with the prefetch, step S1
If not, the process proceeds to step S112.

In step S121, first,
The supply of data from the memory 43 or the second memory 44 to the data buffer 52 is interrupted. Next, step S
At 122, the controller 51 determines whether or not the data designated to be read by the first data read command is stored in the first memory 43. When it is stored in the first memory 43, step S1
23, and if not stored, step S12
Go to 5.

In step S123, the controller 51 supplies the second data read command to the first memory 43. Then, in step S124, the first memory 4
The data is read from 3 and supplied to the bus 45, and the data is stored in the data buffer 52.

Further, in step S125, the controller 51 supplies the second data read command to the second memory 44. Then, in step S126, the data is read from the second memory 44 and supplied to the bus 45, and the data is stored in the data buffer 52.

On the other hand, in step S112, it is determined whether the reading from the data buffer 52 is completed. When the reading from the data buffer 52 is not completed, the process returns to step S110 to continue the reading.

The operation of the data processing system 40 described above will be specifically described as follows. In the following, as shown in FIG. 12, after pre-reading the data stored in the memory cells whose memory addresses are 4000 to 4099 in the first memory 43, the memory addresses in the second memory 44 are 5
The data stored in the memory cell 099 is pre-read, the data stored in the memory cells whose memory addresses are 4000 to 4049 in the first memory 43 is read, and finally the second memory 44 is read. An example will be given when the program for reading the data stored in the memory cells whose memory addresses are 5000 to 5049 is executed.

First, "WRITE 0000 400
The CPU 42 supplies an address write command to the interface 41 in accordance with the address write information written on the program "0".

By supplying the address write command to the interface 41, the address buffer address in the address buffer 50 becomes 00.
"4000" is written in the memory cell which is 00.

Next, the controller 51 recognizes that "4000" has been written in the address buffer 50, and pre-reads an instruction to pre-read the data stored in the memory cells whose memory addresses are 4000 to 4099. The instruction is supplied to the first memory 43.

Next, the memory addresses are changed from 4000 to 4
The data stored in the memory cell 099 is the first
Read out from the memory 43 and supplied to the data buffer 52. Then, the data buffer 52 is
The data supplied from the memory 43 of FIG.

Next, "WRITE 0004 500
The CPU 42 supplies an address write command to the interface 41 in accordance with the address write information written on the program "0".

Then, by supplying the address write command to the interface 41, "5000" is written in the memory cell of the address buffer 50 whose address for the address buffer is 04.

Next, the controller 51 recognizes that "5000" has been written in the address buffer 50, and pre-reads an instruction to pre-read the data stored in the memory cells whose memory addresses are 5000 to 5099. The instructions are supplied to the second memory 44.

Next, the memory addresses are changed from 5000 to 5
The data stored in the memory cell 099 is the second
Is read from the memory 44 and is supplied to the data buffer 52. Then, the data buffer 52 is
The data supplied from the memory 44 of FIG.

Next, "READ 4000 to 40
The CPU 42 supplies the first data read command to the interface 41 in accordance with the data read information written on the program "49".

Next, in the interface 41, the data buffer 52 is confirmed, and the data stored in the memory cells whose memory addresses are 4000 to 4049 in the first memory 43 are stored in the data buffer 52. Make sure that.

Then, the controller 51 sends the memory addresses from the data buffer 52 to 4000 to 4049.
The data stored in the memory cell is read out and output to the bus 45.

Next, "READ 5000 to 50
The CPU 42 supplies the first data read command to the interface 41 in accordance with the data read information written on the program "49".

Next, in the interface 41, the data buffer 52 is confirmed, and the data stored in the memory cells whose memory addresses are 5000 to 5049 in the second memory 44 are stored in the data buffer 52. Make sure that.

Then, the controller 51 sends the memory addresses from 5000 to 5049 from the data buffer 52.
The data stored in the memory cell is read out and output to the bus 45.

As described above, the data processing system 40 according to the third embodiment of the present invention has a structure in which the interface 41 is connected to the two memories, that is, the first memory 43 and the second memory 44. By dividing and storing in both the first memory 43 and the second memory 44, pre-reading can be performed quickly and efficiently. That is, for example, it becomes possible to pre-read the data stored in the second memory 44 in parallel while pre-reading the data stored in the first memory 43.

Further, depending on the address to be written in the address buffer 50, it is possible to pre-read the continuous data across the first memory 43 and the second memory 44 and store it in the data buffer 52. That is, for example, when the address “6950” is written in the address buffer 50 in the above, the data having the addresses 6950 to 7049 from the first and second memories 43 and 44 is prefetched and stored in the data buffer 52. be able to.

Although the data processing system 40 according to the third embodiment has a configuration in which the first memory 43 and the second memory 44 are connected to one interface 41, three or more memories are common. Those connected to the interface of can be similarly considered.

Fourth Embodiment Next, a fourth embodiment of the present invention will be described.

The present invention can also be applied to the data processing system 60, the first interface 61 and the second interface 62 shown in FIG.

The data processing system 60 includes a CPU 63.
A first interface 61 to which the first memory 64 is connected and a second interface 61 to which the second memory 65 is connected.
Interface 62 of. In addition, the first interface 61, the second interface 62, and the CPU
63 is connected to the bus 66.

The first interface 61 has the same structure as the interface 2 according to the first embodiment, and
Address buffer 70 and the first controller 71
And a first data buffer 72. The first interface 61 uses the first data read command supplied from the CPU 63 to generate the first data buffer 7
The data stored in No. 2 or the data stored in the first memory 64 is output to the bus 66.

In the first interface 61, C
Based on the address write command supplied from the PU 63, the first controller 71 supplies a second data read command to the first memory 64, prefetches the data stored in the first memory 64, The data is stored in the first data buffer 72.

The second interface 62 also has the same structure as the interface 2 according to the first embodiment, and has a second address buffer 73, a second controller 74, and a second data buffer 75. Equipped with. Second
The interface 62 of the second memory 6 or the data stored in the second data buffer 75 is based on the first data read command supplied from the CPU 63.
The data stored in 5 is output to the bus 66. Further, in the second interface 62, the second controller 74 supplies the third data read command to the second memory 65 based on the address write command supplied from the CPU 63, and stores the third data read command in the second memory 65. The stored data is pre-read and stored in the second data buffer 75.

The CPU 63 uses the first interface 61.
Or the second interface 62, the data processing system 6
Each part (not shown) included in the computer system in which 0 is mounted is controlled. Further, the CPU 63
For example, it is described in the program, and the first memory 6
4 or the second data to the first interface 61 or the second interface 62 based on the data read information instructing to read the data stored in the memory cell of the specific memory address in the second memory 65. A read command is supplied to read the data stored in the first memory 64, the second memory 65, the first data buffer 72, or the second data buffer 75.

More specifically, first, the CPU 63 supplies an address to be accessed to the first interface 61 and the second interface 62 via the bus 66. Then, the data specified by the address is the first
Data is read from the first data buffer 72 when the data is stored in the second data buffer 75, and the data is read from the second data buffer 75 when the data is stored in the second data buffer 75. Be done.

On the other hand, when the data is not stored in either the first data buffer 72 or the second data buffer 75, the data is read from the first memory 64 or the second memory 65. Furthermore, CPU6
3 is an address write to the first interface 61 based on the address write information instructing to write a specific memory address to a specific memory cell of the first address buffer 70 described in the program. An instruction is supplied, and a memory address is written in the first address buffer 70.

Furthermore, the CPU 63 causes the second interface to be written based on the address write information instructing to write the specific memory address to the specific memory cell of the second address buffer 73 described in the program. The address write command is supplied to 62,
The memory address is written in the second address buffer 73.

The data processing system 60 described above is
First interface 61 and second interface 6
2, the first interface 64 is connected to the first memory 64, and the second interface 6
A second memory 65 is connected to 2. That is,
The data processing system 60 has two interfaces,
It has two memories connected to each interface. Therefore, the data is divided into the first memory 64
By storing them in both the second memory 65 and the second memory 65, prefetching can be performed quickly and efficiently.

Further, since the data processing system 60 is provided with the first interface 61 and the second interface 62, it becomes possible to read out quickly and efficiently. For example, it becomes possible to read the data stored in the second data buffer 75 in parallel while reading the data stored in the first data buffer 72.

Note that the data processing system 60 according to the fourth embodiment has two interfaces connected to the bus 66, but a system having three or more interfaces can be considered in the same way.

Fifth Embodiment Next, a fifth embodiment of the present invention will be described.

The present invention can also be applied to the data processing system 80 and interface 81 shown in FIG.

The data processing system 80 includes a CPU 82.
And an interface 81 to which the memory 3 is connected. Further, the interface 81 and the CPU 82 are connected to the bus 84.

The interface 81 comprises a pre-reading section 90 and a continuous reading section 91. The prefetching unit 90 includes an address buffer 92, a first controller 93, and a first data buffer 94. The prefetching unit 90
It has a function of prefetching the data stored in the memory 3. The continuous read unit 91 also includes a second controller 95 and a second data buffer 96. The continuous reading unit 91 sequentially reads the data stored in the memory cells having the memory addresses consecutive to the memory addresses of the memory cells storing the data read from the memory 3 (hereinafter, referred to as continuous reading). .) Has a function.

The CPU 82 controls the interface 81 and each part (not shown) provided in the computer system in which the data processing system 80 is mounted. In addition, the CPU 82 writes the first data to the interface 81 based on the data read information which is written in the program and commands to read the data stored in the memory cell of the specific memory address in the memory 3. A read command is supplied to read the data stored in the memory 3, the first data buffer 94, or the second data buffer 96.

More specifically, first, the CPU 82
Confirms the first data buffer 94 and the second data buffer 96. Then, when the data designated to be read by the first data read command is stored in the first data buffer 94, the data is read from the first data buffer 94, and the data is read as the second data buffer 96. When the data is stored in, the data is read from the second data buffer 96.

On the other hand, when the data is not stored in either the first data buffer 94 or the second data buffer 96, the data is read from the memory 3. Further, the CPU 82 supplies an address write command to the interface 81 and writes an address to the address buffer 92 based on the address write information written in the program.

The interface 81 will be described in detail below.

The address buffer 92, the first controller 93, and the first data buffer 94 can be the same as the address buffer 10, controller 11, and data buffer 12 described in the first embodiment, respectively.

The second controller 95 is a CPU
The data stored in the memory cells at consecutive addresses with the memory cells storing the data once read from the memory 3 by 82 are sequentially read. And
The second data buffer 96 is the second controller 95.
The data read by is temporarily stored.

The interface 81 described above includes the prefetching unit 90 and the continuous reading unit 91, and the prefetching unit 90 can perform the prefetching and the continuous reading unit 91 can perform the continuous reading. By the continuous reading, the data stored in the memory cells at the addresses consecutive to the memory cells storing the data once read from the memory 3 are sequentially read from the memory 3 by the second controller 95, No. 2 data buffer 96.

That is, since the interface 81 is provided with the continuous reading section 91, it is possible to read the data from the memory 3 in advance without the pre-reading by the pre-reading section 90. In addition, the data processing system 80 can read out in advance more data than the amount that can be stored in the first data buffer 94.

The operation of the data processing system 80 described above is as described below.

It should be noted that during the operation of prefetching data in the data processing system 80, and during the prefetching of data in the data processing system 80, the first
The operation when the first data read command is supplied to the interface 81 of the above is the operation when prefetching the data in the data processing system 1 described in the first embodiment, and the operation of the data processing system 80 when the data is read in advance. The operation is the same as when the first data read command is supplied to the first interface 81 during the pre-reading.

According to the first data read command,
After the data is output from the first data buffer 94 or the memory 3 to the bus 84, the second controller 95 stores the data output to the bus 84 in the memory cells at consecutive addresses with the memory cells storing the data. Stored data is read from the memory 3 and the second data buffer 9
Supply to 6.

Next, the second data buffer 96 stores the data supplied from the memory 3.

The operation of the data processing system 80 described above will be specifically described as follows. In the following, first, the memory address as shown in FIG.
After prefetching the data stored in the memory cells from 000 to 4099, the memory address becomes 4000
As an example, a case of executing a program for reading data stored in memory cells No. 40 to No. 4099 will be described.

First, "WRITE 0000 400
The CPU 82 supplies an address write command to the interface 81 according to the address write information written in the program "0".

By supplying the address write command to the interface 81, "4000" is written to the memory cell of the address buffer 92 whose address buffer address is 0000.

Next, the first controller 93 recognizes that "4000" has been written in the address buffer 92, and instructs to preread the data stored in the memory cells having memory addresses 4000 to 4099. The pre-reading instruction to perform is supplied to the memory 3.

Next, the memory 3 has a memory address of 4
The data stored in the memory cells 000 to 4099 is supplied to the first data buffer 94. Then, the first data buffer 94 stores the data supplied from the memory 3.

Next, "READ 4000 to 40
The CPU 82 supplies the first data read command to the interface 81 in accordance with the data read information described in the program "99".

Next, in the interface 81, the first
The data buffer 94 is checked, and it is recognized that the data stored in the memory cells whose memory addresses are 4000 to 4099 are stored in the first data buffer 94.

Next, the first controller 93 reads the data stored in the memory cells whose memory addresses are 4000 to 4099 from the first data buffer 94 and outputs it to the bus 84.

While the data stored in the memory cells whose memory addresses are 4000 to 4099 are being read from the first data buffer 94, the second controller 95 reads the memory addresses from the memory 3 Is 4
The data stored in the memory cells 100 to 4199 are sequentially read and stored in the second data buffer 96.

Then, from the CPU 82 to the interface 8
When the first data read command indicating that the data stored in the memory cell whose memory address is 4100 to 4199 is read is supplied to 1, the data stored in the second data buffer 96 is Read out.

In the data processing system 80 according to the fifth embodiment, the interface 81 includes one prefetching unit 90 and one continuous reading unit 91, but at least one of the prefetching unit 90 and the continuous reading unit 91 is incorporated. A plurality of built-in devices can be considered in the same manner.

Sixth Embodiment Hereinafter, a sixth embodiment of the present invention will be described.

The present invention can be applied to the data processing system 100 and the interface 101 shown in FIG.

The data processing system 100 includes the CPU 10
2 and the interface 101 to which the memory 3 is connected
With. Also, the interface 101 and the CPU 10
2 is connected to the bus 104.

The interface 101 includes the prefetch section 110.
And a normal reading unit 111. Look-ahead unit 110
Is the address buffer 112 and the first controller 1
13 and a data buffer 114. Look-ahead section 1
Reference numeral 10 has a read-ahead function of the data stored in the memory 3. The normal reading unit 111 also includes a second controller 115. The normal read unit 111 reads data in a normal operation without prefetching the data. The details of the interface 101 will be described later.

The CPU 102 is the interface 101.
In addition, each part (not shown) included in the computer system in which the data processing system 100 is installed is controlled. Further, the CPU 102 is described in, for example, a program, and based on the data read information that instructs to read the data stored in the memory cell of the specific memory address in the memory 3, the interface 1
01 by supplying the first data read command to the memory 3
Alternatively, the data stored in the data buffer 114 is read.

More specifically, first, the CPU 102
Supplies the access destination address to the data buffer 114. Then, when the data having the address specified to be read by the first data read command is stored in the data buffer 114, the data is read from the data buffer 114, and the data is not stored in the data buffer 114. Sometimes the data is read from the memory 3. Further, the CPU 102
Supplies an address write command to the interface 101 and writes an address to the address buffer 112 based on the address write information described in the program. Furthermore, the CPU 102
A prefetch stop instruction is supplied to the interface 101 to stop the prefetch function in the data processing system 100.

The interface 101 will be described in detail below.

The prefetching unit 110 has the address buffer 11
2, the first controller 113, and the data buffer 1
14 and.

The address buffer 112 is composed of a plurality of memory cells, and each memory cell has "0000", "000".
An address buffer address such as 4 ″ is given. Each memory cell of the address buffer 112 is written with a memory address based on an address write command. One of the memory cells is used as an ON / OFF switch, and the data processing system 100 is
By writing predetermined data to the memory cell,
The prefetch unit 110 is set to not operate.

The address buffer 1 of this embodiment
12 has 20 memory cells, and each memory cell has "0000", "0001", "0002" ...
-Address buffer addresses "0018" and "0019" are assigned. Further, in the address buffer 112 of the present embodiment, the memory cell whose address for the address buffer is 10 is used as an ON / OFF switch, and the prefetch unit 110 operates by writing “1” in the memory cell. Will not do.

The first controller 113 recognizes that the memory address has been written in the address buffer 112, and prefetches the data stored in a predetermined number of memory cells from the memory cell of the memory address.
Further, the first controller 113 recognizes that data is written in the memory cell whose address for the address buffer is 10, and stops the operation.

The normal reading section 111 includes a second controller 115. The second controller 115 reads the data from the memory 3 and outputs it directly to the bus 104.

The operation of the data processing system 100 described above is as described below.

The interface 1 is operated during the data prefetch in the data processing system 100, the data read operation, and the data prefetch in the data processing system 100.
The operation when the first data read command is supplied to 01 is the operation when the data is prefetched and the operation when the data is read in the data processing system 1 described in the first embodiment. , And the operation when the first data read command is supplied to the interface 101 during the prefetch of data in the data processing system 100.

The operation of normal reading in the data processing system 100 is as described below.

First, as shown in FIG. 17, step S2
At 00, the CPU 102 supplies the interface 101 with a prefetch stop instruction indicating that “1” is written in the memory cell whose address buffer address is 10.

Next, in step S201, "1" is written in the memory cell of the address buffer 112 whose address buffer address is 10.

Next, in step S202, the first controller 111 determines that the address for the address buffer is 1
Recognizing that "1" has been written in the memory cell that is 0, the read-ahead function is stopped.

Next, in step S203, the CPU
102 supplies the interface 101 with a first data read command indicating that data is to be read.

Then, in step S204, the second
The controller 115 of reads the data stored in the memory 3 based on the first data read command,
Output to the bus 104.

In the data processing system 100 according to the sixth embodiment, the interface 101 is provided with the prefetch unit 1.
10 and one normal reading unit 111 are built in each, but a device in which at least one of the pre-reading unit 110 and the normal reading unit 111 is built in plural is similarly considered.

[0206]

According to the interface device of the present invention,
By writing the address in the address storage means, the data stored in the data storage means can be read in advance. Therefore, the interface device according to the present invention, regardless of the locality of the read data,
It becomes possible to read out necessary data flexibly, efficiently and at high speed.

In the data processing system according to the present invention, the address stored in the address storage means makes it possible to read the data stored in the data storage means in advance. The writing of the address in the address storage means is performed based on the address writing information written in the program. That is, in the data processing system according to the present invention, it is not necessary for the control unit to directly read the data from the data storage unit when reading the preread data. Therefore, the data processing system to which the present invention is applied can flexibly and efficiently read necessary data at high speed regardless of the locality of the read data.

Further, since the interface device and the data processing system to which the present invention is applied have a simple structure,
It becomes possible to easily design and implement in a computer system.

According to the data processing method of the present invention, by writing the address in the address storage means, the data stored in the data storage means can be read in advance. Therefore, according to the data processing method to which the present invention is applied, regardless of the locality of the read data,
It becomes possible to read out necessary data flexibly, efficiently and at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram of a data processing system to which the present invention is applied.

FIG. 2 is a flowchart showing an operation when prefetching is performed in the data processing system.

FIG. 3 is a flowchart showing an operation when reading data in the data processing system.

FIG. 4 is a flowchart showing an operation when reading data during pre-reading in the data processing system.

FIG. 5 is a diagram showing an example of a program executed in the data processing system.

FIG. 6 is a block diagram of another data processing system to which the present invention is applied.

FIG. 7 is a diagram showing an example of a program executed in the data processing system.

FIG. 8 is a block diagram of still another data processing system to which the present invention is applied.

FIG. 9 is a flowchart showing an operation when prefetching is performed in the data processing system.

FIG. 10 is a flowchart showing an operation when reading data in the data processing system.

FIG. 11 is a flowchart showing an operation when reading data during prefetching in the data processing system.

FIG. 12 is a diagram showing an example of a program executed in the data processing system.

FIG. 13 is a block diagram of still another data processing system to which the present invention has been applied.

FIG. 14 is a block diagram of still another data processing system to which the present invention has been applied.

FIG. 15 is a diagram showing an example of a program executed in the data processing system.

FIG. 16 is a block diagram of still another data processing system to which the present invention has been applied.

FIG. 17 is a flowchart showing an operation when normal reading is performed in the data processing system.

FIG. 18 is a block diagram showing a data processing system having a disk cache function.

FIG. 19 is a block diagram showing a data processing system having a DMA function.

[Explanation of symbols]

1 data processing system, 2 interface, 3 memory, 4 CPU, 10 address buffer, 11 controller, 12 data buffer

Claims (4)

[Claims] 1. An interface device connected to data storage means for reading data stored in the data storage means, the address storage means having an address of the data storage means written therein, and the address storage means written in the address storage means. An interface device comprising: control means for reading data stored in the data storage means based on an address; and temporary storage means for temporarily storing the data read by the control means. 2. A data storage unit, an address storage unit in which an address of the data storage unit is written, and a prefetch control for preliminarily reading out data stored in the data storage unit based on the address written in the address storage unit. Means, and interface means having a temporary storage means for temporarily storing the data previously read by the prefetch control means, and the address of the data storage means is written in the address storage means and stored in the temporary storage means. And a control means for reading the stored data. 3. The address is described in an execution program of the control means.
The described data processing system. 4. A data processing method for reading data stored in a data storage means, comprising: writing an address of the data storage means into the address storage means; and writing the address into the address storage means. A step of preliminarily reading the data stored in the data storage means based on the above, a step of temporarily storing the preliminarily read data in the temporary storage means, and a step of reading the data stored in the temporary storage means. And a data processing method comprising: