JP2003242024A5 - - Google Patents
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- Publication number
- JP2003242024A5 JP2003242024A5 JP2002369547A JP2002369547A JP2003242024A5 JP 2003242024 A5 JP2003242024 A5 JP 2003242024A5 JP 2002369547 A JP2002369547 A JP 2002369547A JP 2002369547 A JP2002369547 A JP 2002369547A JP 2003242024 A5 JP2003242024 A5 JP 2003242024A5
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- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/037163 | 2001-12-21 | ||
| US10/037,163 US6801991B2 (en) | 2001-12-21 | 2001-12-21 | Method and apparatus for buffer partitioning without loss of data |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003242024A JP2003242024A (ja) | 2003-08-29 |
| JP2003242024A5 true JP2003242024A5 (ja) | 2006-02-02 |
| JP4504615B2 JP4504615B2 (ja) | 2010-07-14 |
Family
ID=21892781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002369547A Expired - Fee Related JP4504615B2 (ja) | 2001-12-21 | 2002-12-20 | データ損失のないバッファ分割方法および装置 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6801991B2 (ja) |
| JP (1) | JP4504615B2 (ja) |
| KR (1) | KR100939649B1 (ja) |
| GB (1) | GB2386717A (ja) |
| TW (1) | TW200301421A (ja) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003056707A1 (en) * | 2001-12-28 | 2003-07-10 | Koninklijke Philips Electronics N.V. | Method for decoding data using windows of data |
| US8386727B2 (en) * | 2001-12-31 | 2013-02-26 | Hewlett-Packard Development Company, L.P. | Supporting interleaved read/write operations from/to multiple target devices |
| US6782461B2 (en) * | 2002-02-25 | 2004-08-24 | Intel Corporation | Dynamically adjustable load-sharing circular queues |
| US6813658B2 (en) * | 2002-03-27 | 2004-11-02 | Intel Corporation | Dynamic data queuing mechanism for packet networks |
| DE10219359B4 (de) * | 2002-04-30 | 2007-05-03 | Advanced Micro Devices, Inc., Sunnyvale | Vorrichtung und Verfahren mit einem Queuemechanismus |
| US8635355B2 (en) * | 2002-05-01 | 2014-01-21 | Stmicroelectronics, Inc. | Method for pre-caching content to enable true VOD systems from NVOD or stream limited VOD systems |
| US7639263B2 (en) * | 2007-01-26 | 2009-12-29 | Microsoft Corporation | Fast filtered YUV to RGB conversion |
| US7783823B2 (en) * | 2007-07-31 | 2010-08-24 | Hewlett-Packard Development Company, L.P. | Hardware device data buffer |
| US9911470B2 (en) | 2011-12-15 | 2018-03-06 | Nvidia Corporation | Fast-bypass memory circuit |
| US8904067B2 (en) * | 2012-03-13 | 2014-12-02 | Microsoft Corporation | Adaptive multi-threaded buffer |
| US9424685B2 (en) | 2012-07-31 | 2016-08-23 | Imagination Technologies Limited | Unified rasterization and ray tracing rendering environments |
| CN103632712A (zh) | 2012-08-27 | 2014-03-12 | 辉达公司 | 存储单元和存储器 |
| GB2505884B (en) * | 2012-09-12 | 2015-06-03 | Imagination Tech Ltd | Dynamically resizable circular buffers |
| US9685207B2 (en) | 2012-12-04 | 2017-06-20 | Nvidia Corporation | Sequential access memory with master-slave latch pairs and method of operating |
| US9281817B2 (en) | 2012-12-31 | 2016-03-08 | Nvidia Corporation | Power conservation using gray-coded address sequencing |
| US20140244921A1 (en) * | 2013-02-26 | 2014-08-28 | Nvidia Corporation | Asymmetric multithreaded fifo memory |
| US10141930B2 (en) | 2013-06-04 | 2018-11-27 | Nvidia Corporation | Three state latch |
| WO2015156830A1 (en) * | 2014-04-10 | 2015-10-15 | Hewlett-Packard Development Company, L.P. | Relocating a virtual address in a persistent memory |
| DE102015209486A1 (de) * | 2015-05-22 | 2016-11-24 | Robert Bosch Gmbh | FIFO Speicher mit im Betrieb veränderbarem Speicherbereich |
| US10644844B1 (en) * | 2017-04-05 | 2020-05-05 | Xilinx, Inc. | Circuit for and method of determining error spacing in an input signal |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4169289A (en) | 1977-07-08 | 1979-09-25 | Bell Telephone Laboratories, Incorporated | Data processor with improved cyclic data buffer apparatus |
| GB9510932D0 (en) | 1995-05-31 | 1995-07-26 | 3Com Ireland | Adjustable fifo-based memory scheme |
| US5860149A (en) | 1995-06-07 | 1999-01-12 | Emulex Corporation | Memory buffer system using a single pointer to reference multiple associated data |
| JPH09128214A (ja) * | 1995-10-31 | 1997-05-16 | Toshiba Corp | データ処理装置及びデータ処理方法 |
| JP3486498B2 (ja) * | 1996-01-10 | 2004-01-13 | キヤノン株式会社 | バッファ管理方法及びそれを用いた印刷装置 |
| US5956492A (en) * | 1996-03-29 | 1999-09-21 | Lsi Logic Corporation | N-deep fixed latency fall-through FIFO architecture |
| JP3307325B2 (ja) * | 1998-04-03 | 2002-07-24 | 日本電気株式会社 | データバッファ回路 |
| US6381659B2 (en) * | 1999-01-19 | 2002-04-30 | Maxtor Corporation | Method and circuit for controlling a first-in-first-out (FIFO) buffer using a bank of FIFO address registers capturing and saving beginning and ending write-pointer addresses |
| JP2000330761A (ja) * | 1999-05-18 | 2000-11-30 | Canon Inc | リングバッファ制御装置およびリングバッファ制御方法 |
| GB2371641B (en) | 2001-01-27 | 2004-10-06 | Mitel Semiconductor Ltd | Direct memory access controller for circular buffers |
-
2001
- 2001-12-21 US US10/037,163 patent/US6801991B2/en not_active Expired - Fee Related
-
2002
- 2002-11-28 TW TW091134656A patent/TW200301421A/zh unknown
- 2002-11-29 GB GB0227954A patent/GB2386717A/en not_active Withdrawn
- 2002-12-20 KR KR1020020081848A patent/KR100939649B1/ko not_active IP Right Cessation
- 2002-12-20 JP JP2002369547A patent/JP4504615B2/ja not_active Expired - Fee Related