JP2003233396A - Decoding device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To decode a bit stream while preventing an unrecoverable error. <P>SOLUTION: A decoding device which packetizes and decodes a bit stream formed of successive blocks to a specified data length is equipped with: a detection part which receives the bit stream and detects a bit pattern for synchronism from the bit stream to detect the head of a block; and a display signal generation part which generates a display signal showing whether the successive packets packetized to the specified data length are continuous with the foregoing and following packets. When processing for skipping packets is carried out, the detection part is supplied with a synchronizing bit detection start signal being the display signal showing that packets are discontinuous from the display signal generation part and discards a block where a synchronizing bit is being detected with the synchronizing bit detection start signal and starts detecting a synchronizing bit of a new block. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding device for decoding a bit stream, and more particularly to a decoding device capable of fast-forwarding and reproducing an encoded audio signal.

[0002]

2. Description of the Related Art As an encoding method for highly efficiently compressing a digital audio signal, for example, an international standard ISO / IEC 11172-3 called MPEG audio is used.
(MPEG1 audio) and the like are known. This is done by collecting multiple audio signals into blocks, converting the time domain signals into frequency domain signals in block units, and then performing quantization using human auditory characteristics to delete the amount of information. It is carried out. As an example, an encoding device that encodes an audio signal into MPEG-1 Audio Layer 3 (hereinafter referred to as MP3) will be described below. The encoding device blocks the input audio signal for each 1152 samples, performs band division using a band division filter, and performs MD division for each block.
CT (Modified Discrete Cosine Transform) processing is performed, the transform coefficient (TCOEFF) output by MDCT processing is quantized, and the quantized transform coefficient is compressed by variable length coding. , MP3 by multiplexing the synchronization bit and header information
Encode to file format. The sync bit indicates the beginning of the block and is present at the beginning of each block. The audio signal encoded in the MP3 file format as described above is mainly used for transmission via a communication path such as the Internet or accumulated and used in various media such as a hard disk. Also, when multiplexing,
Bits are sequentially arranged based on a certain rule such as grammar. Audio data encoded by the encoding device is called a bitstream.

The audio signal encoded in MP3 as described above is decoded by the decoding device. Here, the decoding device will be described below with reference to FIG. Decoding device 2
Is an input terminal 30 to which a bit stream is input, a memory circuit unit 31, a synchronization bit detection circuit unit 32, a demultiplexing circuit unit 33, an inverse quantization circuit unit 34, an inverse conversion circuit unit 35, and a reproduction unit. And an output terminal 36 for outputting a signal.

The bit stream input from the input terminal 30 is input to the memory circuit section 31 and temporarily stored therein. The memory circuit unit 31 temporarily stores the bitstream, thereby eliminating the processing time difference between the communication path and the decoding device 2. Then, the memory circuit unit 31 outputs the stored bit stream to the synchronization bit detection circuit unit 32. The synchronization bit detection circuit unit 32 searches for a synchronization bit pattern in the input bit stream and detects the beginning of each block. Then, the synchronization bit detection circuit unit 32 outputs the bit stream to the demultiplexing circuit unit 33.

The demultiplexing circuit section 33 separates the input bit stream into transform coefficients and header information, and outputs the separated transform coefficients and header information to the dequantization circuit section 34. The header information includes information such as a sync signal, a bit rate, a sampling frequency and the like. Further, the demultiplexing circuit unit 33 monitors the grammar of the bit stream, and when a grammatical error occurs, the demultiplexing process is interrupted and an error detection signal is output. This error detection signal is input to the synchronization bit detection circuit unit 32 as a synchronization bit detection start signal. Sync bit detection circuit unit 32
Then, the sync bit of the next block is detected based on the sync bit detection start signal. In addition, the demultiplexing circuit unit 3
3 is a variable length code (hereinafter referred to as V
It is called LC. In the case of), decryption processing is also performed.

The encoding will be described here. Fixed length code (hereinafter, referred to as FLC) is used for encoding.
Say. ) And VLC. FLC is a code having the same code length regardless of the data pattern. On the other hand, V
The LC is a code whose code length differs depending on the data pattern. For example, if there are 5 data patterns,
The most frequent pattern is encoded with 1 bit and the fewest pattern is encoded with 5 bits. VLC encoding can compress data at a higher level than FLC encoding.

The dequantization circuit section 34 dequantizes the input transform coefficient and outputs it to the detransformation circuit section 35. The inverse transform circuit unit 35 inversely transforms the input transform coefficient after the inverse quantization process, reconstructs the audio signal, and outputs the reconstructed audio signal from the output terminal 36.

The decoding device 2 decodes the bit stream as described above and reconstructs the audio signal.

Next, the case of performing fast-forward reproduction by the decoding device 2 will be described below. Decoding device 2
Then, fast-forward playback is performed by repeating the playback / skip processing of playing back several consecutive blocks from the bit stream that has been encoded and stored in advance and skipping the next few consecutive blocks. There is. For example, the decoding device 2 performs double-speed fast-forward reproduction by reading 5 blocks from the bit stream as one packet and then skipping the next packet (5 blocks).

[0010]

In the fast-forward reproduction as described above, it is necessary to accurately read each block from the bit stream without interruption. However,
When the bit stream is encoded by VLC, when fast-forward reproduction is performed by the decoding device 2, a block interrupted on the way is read, which causes a problem that an irrecoverable error occurs.

In order to solve the above problem, it is necessary to check the contents of the bitstream and synchronize the packet boundary position with the block boundary position before decoding the bitstream.

[0012] Therefore, the present invention has been proposed in view of the above-mentioned circumstances, and a bit stream in which VLC is used is packetized and read to prevent the occurrence of an irrecoverable error and It is an object of the present invention to provide a decoding device capable of performing fast-forward reproduction without performing processing for synchronizing the boundary position of a block and the boundary position of a block.

[0013]

In order to solve the above-mentioned problems, a decoding device according to the present invention is a decoding device for packetizing a bit stream formed of continuous blocks with a predetermined data length and decoding. , A bitstream is input, a detecting means for detecting a bit pattern for synchronization from the bitstream and detecting the beginning of a block, and whether a packet packetized with a predetermined data length is continuous with a preceding or subsequent packet or not. And a display signal generating means for generating a display signal indicating whether the packet is continuous at packet intervals, and the detecting means, when performing the process of skipping the packet, detects the discontinuity of the packet which is discontinuous from the display signal generating means. A sync bit detection start signal, which is a display signal indicating continuity, is supplied, and the sync bit detection is started by the sync bit detection start signal. Discard Tsu have blocks, and wherein the initiating synchronization bit detection of a new block.

In such a decoding device, a display signal indicating continuity or discontinuity between packets is generated at packet intervals and input to the synchronization bit detection means as a synchronization bit detection start signal.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

The present invention is applied to a decoding device 1 as shown in FIG. 1, for example. The decoding device 1 includes an input terminal 10 to which a bit stream is input, and a first memory circuit unit 11
, Synchronization bit detection circuit unit 12, and demultiplexing circuit unit 13
A continuous / discontinuous display signal generation unit (hereinafter referred to as a display signal generation unit) 14, a second memory circuit unit 15, a header information generation unit 16, a header information comparison circuit unit 17, and an adder 18. , Inverse quantization circuit section 19, and inverse conversion circuit section 20
And an output terminal 21 for outputting a reproduction signal.

The bit stream input from the input terminal 10 is input to the first memory circuit section 11 and temporarily stored therein. The first memory circuit unit 11 temporarily stores the bitstream to eliminate the processing time difference between the communication path and the decoding device 1. Then, the first memory circuit unit 11 outputs the stored bit stream to the synchronization bit detection circuit unit 12. Sync bit detection circuit section 12
Finds the bit pattern for synchronization from the input bit stream and detects the beginning of each block. Then, the synchronization bit detection circuit unit 12 outputs the bit stream to the demultiplexing circuit unit 13.

The demultiplexing circuit unit 13 separates the input bit stream into transform coefficients and header information, and outputs the separated transform coefficients and header information to the dequantization circuit unit 19. The header information includes information such as a sync signal, a bit rate, a sampling frequency and the like. In addition, the demultiplexing circuit unit 13 monitors the grammar of the bitstream, and if a grammatical error occurs, demultiplexing processing is interrupted and an error detection signal is output. This error detection signal is output to the adder 18.

Here, an error in the grammar of the bitstream will be described. A syntax error (hereinafter referred to as a syntax error) occurs when an error is added to the bitstream in the transmission path or when an encoder that encodes the original bitstream uses an encoding parameter that does not comply with the MPEG system. ) May occur. When a syntax error occurs in the bit stream, the demultiplexing circuit unit 13 generates an error detection signal and uses the generated error detection signal as a synchronization bit detection start signal for starting the detection of the synchronization bit via the adder 18. Are supplied to the synchronization bit detection circuit section 12. The synchronization bit detection circuit unit 12 detects the next start code from the position where the error of the bit stream has occurred. The sync bit detection circuit unit 12 performs error recovery based on the detected start code. Note that the bitstream from the position where the error occurred in the bitstream to the position where the error recovery was performed cannot be decoded, so by using the information of the already decoded data, the data lost due to the syntax error Interpolate parts.

Further, the demultiplexing circuit section 13 performs a decoding process when the block forming the input bit stream is a variable length code (VLC).

Here, the encoding will be described. Fixed length code (hereinafter, referred to as FLC) is used for encoding.
Say. ) And VLC. FLC is a code having the same code length regardless of the data pattern. On the other hand, V
The LC is a code whose code length differs depending on the data pattern. For example, if there are 5 data patterns,
The most frequent pattern is encoded with 1 bit and the fewest pattern is encoded with 5 bits. VLC encoding can compress data at a higher level than FLC encoding.

The demultiplexing circuit section 13 outputs a part of the demultiplexed header information to the header information comparing circuit section 17.

The display signal generation unit 14 generates a display signal indicating whether a packet composed of a plurality of blocks is continuous or discontinuous with the preceding and succeeding packets, and the generated display signal is transmitted in packet units to the second memory circuit unit. Output to 15. The second memory circuit unit 15 stores the input display signal, and the adder 1
Output to 8.

The header information generation unit 16 generates header information of blocks forming a bitstream and outputs the generated header information to the header information comparison circuit unit 17. The header information comparison circuit unit 17 includes a demultiplexing circuit unit 13
The header information input from the header information is compared with the header information input from the header information generation unit 16. The header information comparison circuit unit 17 outputs the comparison result to the adder 18.

The adder 18 adds the display signal input from the display signal generating section 14, the error detection signal input from the demultiplexing circuit section 13, and the comparison result input from the header information generating section 16. Then, the addition-processed signal is output to the synchronization bit detection circuit unit 12.

The dequantization circuit section 19 dequantizes the input transform coefficient and outputs it to the detransformation circuit section 20. The inverse transform circuit unit 20 inversely transforms the input transform coefficient after the inverse quantization process, reconstructs the audio signal, and outputs the reconstructed audio signal from the output terminal 21.

The decoding device 1 has the input terminal 10 as described above.
A bit stream input via the same is detected by the agreement bit detection circuit unit 12 as a synchronization bit, and the demultiplexing circuit unit 13 is detected.
Demultiplexing process is performed, and the inverse quantizing circuit unit 19 and the inverse transforming circuit unit 20 perform decoding process to output an audio signal from the output terminal.

The operation of fast-forwarding reproduction by the decoding device 1 will be described below.

In the decoding device 1, the bit stream input to the input terminal 10 is fast-forwarded and reproduced in packet units. Further, the decoding device 1 may, for example, as shown in FIG.
Packet P0 to packet P2 are reproduced, and packet P3 to
The packet P5 is skipped, and the packets P6 to P
8 is reproduced and the packets P9 to P11 are skipped, and the reproduction / skipping operation is alternately performed every three packets, thereby performing the double-speed fast-forward reproduction. The above-described reproduction / skipping operation may be performed in addition to three packets, and fast-forward reproduction other than double speed may be performed by changing the number of reproduced packets and the number of skipped packets.

At this time, the fast-forward reproduction operation differs depending on whether the block forming the packet is FLC or VLC. A case in which the block forming the packet is FLC will be described below. As shown in FIG.
6 FLC blocks (block B0 to block B5)
In the case where one packet (packet P0) is configured by, the boundary position of the packet and the boundary position of the last block in the packet match. Similarly, it is assumed that the packet boundary position and the block boundary position of the packets after the packet P1 are the same. In this way, when the packet boundary position and the block boundary position match, fast-forward reproduction can be performed by the reproduction / read skip operation as described above.

Next, the case where the block forming the packet is VLC will be described below. If the packet is composed of VLC blocks, the boundary position of the packet does not match the boundary position of the last block in the packet, and as shown in FIG. 3B, the block is interrupted in the middle. Become. If the block is interrupted on the way, the block itself cannot be reproduced. Therefore, if the block is interrupted at the packet boundary position as shown in FIG.
There is a problem that an irrecoverable error occurs during the decoding process. Therefore, it is necessary to solve the above problem before the decoding process.

Therefore, in the present invention, when performing fast-forward reproduction, the display signal generating section 14 generates a display signal indicating continuity or discontinuity with preceding and following packets for each packet based on the reproduction / skipping operation. The displayed signal is output to the sync bit detection circuit unit 12 as a sync bit detection start signal. For example, as shown in FIG. 2, when the reproduction / skipping operation is performed every three packets, as shown in FIG. 4A, the beginning of the packet P0, between the packet P2 and the packet P3, and the packet P5. Between packet P6 and
A display signal "1" indicating discontinuity is generated between the packets P8 and P9, and a display signal "0" indicating continuity is generated between the other packets. The display signal of FIG. 4A is generated at the same packet interval as the packet size when the bitstream shown in FIG. 4B is packetized. Further, in FIG. 4A, the upper part shows continuity or discontinuity with the previous packet, and the lower part shows continuity or discontinuity with the latter packet. Further, when performing normal reproduction, the display signal indicating discontinuity is also set to "0", and when performing fast-forward reproduction, the display signal indicating discontinuity is set to "1".

Next, the comparison processing of the header information comparison circuit section 17 will be described below. Sync bit detection circuit section 12
Then, the bit pattern for synchronization is detected from the input bit stream as described above, and the head of each block is detected. At the time of this detection, a bit pattern similar to the synchronization bit pattern may be erroneously detected as the synchronization bit pattern from the bit stream. The erroneously detected synchronization bit pattern is called a pseudo bit pattern, but this pseudo bit pattern is not detected by the error detection processing of the demultiplexing circuit unit 13 and is decoded similarly to the correct bit pattern. There's a problem. Therefore, in the present invention, the demultiplexing circuit unit 1
The header information obtained by separating in 3 is the header information comparison circuit unit 1
7 and the header information (hereinafter referred to as header information A) input from the demultiplexing circuit unit 13 by the header information comparison circuit unit 17 and the header information (hereinafter referred to as header information B) input from the header information generation unit 16. It is determined whether the header information A has a correct bit pattern or a pseudo bit pattern. Note that the header information generation unit 16 is assumed to generate the bit pattern of the block header information forming all bitstreams. Further, the header information gives information about a known bit stream, and uses, for example, bits related to control of error detection by sampling frequency or CRC. Since the above bits are unique to the bitstream and do not change, it is possible to reliably verify the synchronization bits.

By this comparison processing, the header information comparison circuit section 17 judges that the bit pattern in which the header information A is detected is a correct bit pattern when the header information B contains the same information as the header information A. On the other hand, when the header information B does not include the same as the header information A, the bit pattern in which the header information A is detected is determined to be a pseudo bit pattern. Header information comparison circuit unit 1
7 outputs the comparison result to the adder 18 when it determines that the bit pattern in which the header information A is detected is a pseudo bit pattern. In the sync bit detection circuit unit 12, the comparison result is input as a sync bit detection start signal,
The detection of the sync bit of the currently executed block is stopped, and the sync bit of the next block is detected.

In this way, the decoding device 1 detects the synchronization bit pattern from the input bit stream and generates the display signal generation unit 14 in the synchronization bit detection circuit unit 12 that detects the beginning of each block. A display signal indicating continuity or discontinuity between the packets is supplied as a synchronization bit detection start signal, and when the display signal indicating discontinuity is detected during fast-forward reproduction, the demultiplexing circuit unit 13 decodes the bit stream. During processing, the next sync bit is detected, the incomplete block decoding process is interrupted, and a new block decoding process is performed, so the packet boundary position and the block boundary position do not match. Even if it is, fast-forward playback can be performed without causing an irrecoverable error.

Further, in the decoding device 1, the demultiplexing circuit section 1
An error detection signal generated when a grammatical error in the bit stream is detected in 3 is supplied to the synchronization bit detection circuit unit 12 as a synchronization bit detection start signal together with the above-mentioned display signal, so that there is a problematic data before decoding processing. When a display signal indicating discontinuity is detected during fast-forward reproduction, the next demultiplexing circuit unit 13 detects the next synchronization bit while decoding the bit stream. , Because the decoding process of the incomplete block is interrupted and the decoding process of the new block is performed, even if the packet boundary position and the block boundary position do not match, fast-forwarding does not occur without irrecoverable error. Playback can be performed.

Further, in the decoding device 1, the comparison result obtained by comparing the header information detected from the bit stream by the header information comparison circuit unit 17 with the correct header information generated by the header information generation unit 16 is the above-mentioned display signal and error detection. The signal is supplied to the synchronous bit detection circuit unit 12 together with the signal as a synchronous bit detection start signal, a pseudo bit pattern can be specified before the decoding process, and when a display signal indicating discontinuity is detected during fast-forward reproduction, , While the demultiplexing circuit unit 13 is decoding the bit stream, the next sync bit is detected, the decoding process of the incomplete block is interrupted, and the decoding process of the new block is performed. Even if the boundary position and the block boundary position do not match, fast-forward playback can be performed without generating an irrecoverable error. Kill.

Further, in the conventional decoding device, in order to prevent an unrecoverable error, processing such as checking a block break is performed in advance, and processing for matching the packet boundary position with the block boundary position is performed. However, in the decoding device 1 to which the present invention is applied, the packet boundary position and the block boundary position that cause such an abnormal sound are determined. It is possible to perform fast-forward reproduction without performing a matching process.

Further, in the decoding device 1 to which the present invention is applied,
The size of the packet can be freely determined, and fast-forward reproduction can be performed without generating an irrecoverable error regardless of whether the block is FLC or VLC.

[0040]

As described above in detail, in the decoding apparatus according to the present invention, the detection means for detecting the bit pattern for synchronization from the input bit stream is connected to the consecutive packets generated by the display signal generation means. Alternatively, when a display signal indicating discontinuity is input and a display signal indicating discontinuity is detected during fast forward playback, the next sync bit is detected during the decoding process of the bitstream, and Since the decoding process of a new block is interrupted and the decoding process of a new block is performed, fast-forward reproduction is performed without generating an irrecoverable error even if the packet boundary position and the block boundary position do not match. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram of a decoding device to which the present invention has been applied.

FIG. 2 is a schematic diagram showing a data structure of a bitstream when reproducing / skipping a bitstream in packet units when fast-forwarding reproduction of data is performed by a decoding device to which the present invention is applied.

FIG. 3 is a schematic diagram (a) showing a boundary of a packet when a block is encoded by FLC, and the block is VLC.
It is a schematic diagram (b) which shows the boundary of the packet in the case of being encoded by.

FIG. 4 is a schematic diagram showing how a display signal generation unit provided in a decoding device to which the present invention is applied generates a display signal indicating continuous or discontinuous between packets at packet intervals.

FIG. 5 is a block diagram of a conventional decoding device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 input terminal, 11 1st memory circuit part, 12 synchronous bit detection circuit part, 13 demultiplexing circuit part, 14 continuous / discontinuous display signal generation part, 15 2nd memory circuit part, 16 header information generation part, 17 Header information comparison circuit unit, 18 adder, 19 inverse quantization circuit unit, 20 inverse conversion circuit unit, 21 output terminal

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) H04J 3/06 G10L 9/18 M 3/02 AF Term (Reference) 5D044 AB05 DE03 DE12 DE24 FG09 FG24 GK02 GK08 GK12 5D045 DA20 5J064 AA01 BA09 BB09 BC01 BC16 BD02 BD03 5K028 AA06 EE02 KK03 KK32 MM05 MM16 NN47

Claims (4)

[Claims] 1. A decoding device for packetizing a bit stream formed of continuous blocks with a predetermined data length and decoding the packet, the bit stream being input, a bit pattern for synchronization being detected from the bit stream, and a block And a display signal generating means for generating, at a packet interval, a display signal indicating whether a packet packetized with a predetermined data length is continuous or discontinuous with the preceding and subsequent packets. When the packet is skipped, the detecting means is supplied with a sync bit detection start signal, which is a display signal indicating the discontinuity of the discontinuous packet, from the display signal generating means, and starts the sync bit detection. Discards the block that was detecting the sync bit by the signal and starts detecting the sync bit of a new block. A decoding device characterized by: 2. An error detection means for detecting a grammatical error in the bit stream output from the synchronization bit detection means and generating an error detection signal, further comprising the error detection signal as a synchronization bit detection start signal. The decoding device according to claim 1, wherein the decoding device inputs the bit detection means. 3. The decoding device according to claim 1, wherein the bit stream is audio data that is variable-length coded. 4. Header information detecting means for detecting header information from a bitstream that has been subjected to error detection by the error detecting means, and header information generating means for generating header information of blocks forming the bitstream. It further comprises header information comparing means for comparing the header information detected by the header information detecting means with the header information generated by the header information generating means, and the comparison result of the header information comparing means is used as a synchronization bit detection start signal. 3. The decoding device according to claim 2, wherein the decoding is input to the synchronization bit detecting means.