JP2003228970A - Optical disk device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that since a lot of time is required for confirming whether a write command is entered from a host computer to an optical disk device or not when the optical disk device is to be moved to a low power consumption state, the disk device is moved to the low power consumption state during the time and the disk device becomes unable to receive the command. <P>SOLUTION: This optical disk device is provided with a circuit which is specialized by hardware so that the confirming of the reception of the write command is not performed by an interruption but performed without a time lag. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk device for writing / reading on / from an optical disk such as a CD.

[0002]

2. Description of the Related Art This type of optical disk device is provided with means for switching to a low power consumption state when not in use. To realize the low power consumption state, it is most effective to reduce the clock frequency of the device. However, this optical disk device and the host computer to which it is connected
A data transfer with a personal computer or the like requires a transfer rate at a somewhat high speed, and thus a fast clock is usually required for the optical disk device. Therefore, when data is being transferred between the optical disk device and the host computer, it is not possible to lower the clock frequency and switch to low power consumption.

However, in order to reduce the power consumption, for example, in Japanese Unexamined Patent Application Publication No. 2001-135009, the portion directly interfacing with the host computer maintains the clock frequency at a regular clock frequency and directly communicates with the host computer. The clock frequency is lowered for the non-interfacing part, and after receiving the command from the host computer and analyzing it, the clock frequency is returned to the normal clock frequency only when necessary.

[0004]

When entering a low power consumption state, it is necessary to confirm that a command has not arrived, but since the conventional confirmation method takes time, it is confirmed after the command is received. In the meantime, if the optical disk device just enters the low power consumption state, there is a problem that the packet command cannot be received.

Further, in the above-mentioned publication, since the portion directly interfacing with the host computer occupies a relatively large portion of the circuit, the effect of low power consumption is small, and it is judged whether the clock frequency is returned to the normal frequency after command analysis. It took me a while to get back. The present invention aims to solve the above-mentioned problems.

[0006]

The present invention relates to an optical disk device used by connecting to a host computer,
The low power consumption circuit provided for shifting to any low power consumption state receives a write command from the host computer when shifting to the low power consumption state during reading, writing and non-data transfer. It is characterized by having a means for confirming that it has not been done.

As a result, it is possible to avoid the inconvenience that the packet command cannot be received after that due to switching to the low power consumption state. In order to solve the problem that the effect of low power consumption is small, the part that directly interfaces with the host computer is made asynchronous so that commands can be received from the host computer even if the clock frequency is lowered, The power consumption is reduced by lowering the clock of the entire interface.

Further, in order to solve the problem that it took a long time to recover from the low power consumption state, when the host computer makes an access, the clock frequency is increased to reduce the power consumption. The reaction to return from the state was accelerated. However, if you always return to a steady state by accessing from the host computer, it will return even if it is not necessary. Instead, the power saving state of the optical disk device is realized by keeping the power saving state.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a configuration example of a host computer and an optical disk device in the case of ATA / ATAPI connection.
As is well known for the same connection, ATA / on the host computer side
Two ATA / ATAPI devices (hereinafter,
1), a hard disk (HDD) is connected to one and an optical disk device is connected to the other in FIG. It is necessary to set the priority for the two connected devices, and normally the hard disk is set as the master and the other devices are set as the slaves.

This setting is based on the ATA / ATAPI Register described later.
This is done by setting the specified bit of the Device / Head (Drive Select) register in "1" or "0", and the host computer refers to that register and gives priority to the device of master setting. To operate.

FIG. 2 shows ATA / ATAP in an optical disk device.
The I block and the clock switching part are shown. ATA / A
TAPI register 1 is from the host computer to ATA / ATAPI
It is written or read via I / F2. Then, the register 1 is read or written from the CPU (not shown) of the optical disk device through the Syscon I / F 3.
Firmware, which is a control program for the apparatus, is written in the memory connected to the CPU.

The built-in FIFO 4 is an ATA / ATAPI I / F 2 and a Buffer RAM for data transfer with the host computer.
Intermediary with I / F5. The buffer RAM connected to the Buffer RAM I / F 5 is a memory such as a DRAM and stores data to be written to the optical disc and data read from the optical disc. The ATAPI controller 6 controls each device described above. The clock switching circuit 7 switches the clock of the ATAPI controller 6.

FIG. 3 shows a timing chart when the host computer accesses the ATA / ATAPI register 1 via the ATA / ATAPI I / F 2. The circuit that fetches the access signal is an asynchronous circuit and operates at the signal edge of the ATA / ATAPI I / F2, so the clock switching circuit 6
The output MCK can access the ATA / ATAPI register 1 normally even if the frequency is low.

The ATA / ATAPI register 1 is defined by expanding a register specific to a hard disk of the ATA specification to a CD-ROM of the ATAPI specification and then integrating and redefining it.

[0015]

[Table 1]

As described above, the device selection is performed by the host computer writing to the device / head (drive select) register whether the master or the slave is selected. The device knows whether it is the master or the slave and the written value and compares it.

Now, an ATA device such as a hard disk is controlled by the host computer by writing / reading to the ATA / ATAPI register 1. A data register is used for data transfer. To set parameters for data transfer, in the case of an ATA device, the host computer writes a command in the command register, reads the ATA / ATAPI register 1 at that time, and sets the parameters. Therefore, even if it is restored from the low power consumption state after confirming that the data has been written in the command register, it is sufficiently in time for the next access.

On the other hand, an ATAPI device such as an optical disk device controls using packet commands. The host computer writes command A0h to the command register. The optical disc device receives it, sets the BSY bit in the status register, and clears the BSY bit when ready. The host computer confirms this and transfers the packet command 12 bytes. The parameters required for data transfer are included in these 12 bytes.

Since the transfer of 12 bytes of the packet command is performed at a data transfer speed which is determined in advance between the host computer and the optical disk device, the transfer in the low power consumption state of the MCK cannot be performed. . In this way, the ATAIP device supports the packet command, but when the A0h command is received, if the optical disk device just enters the low power consumption state, the packet command cannot be received.

However, in order to reduce the power consumption of the optical disk device as much as possible, in the present invention, the frequency of the MCK is immediately lowered to shift to the low power consumption state when it is not operating. In order to avoid the occurrence of a 12-byte packet command transfer error, it is necessary to check that the A0h command has not arrived.

The means for confirming that the A0h command is not received is firmware (F / F
W) takes time. In other words, from when the A0h command is received until it can be confirmed by F / W, F /
Although W recognizes that the A0h command has not been received, in reality the host computer has already issued the A0h command, and there is a time gap before recognition. If you switch to the low power consumption state during this time, packet command 1
Transfer of 2 bytes results in an error.

Therefore, when the A0h command is received, by adding the specialized low power consumption circuit 10 which does not shift to the low power consumption state, after receiving the A0h command, the low power consumption state is not generated. Make sure that the MCK frequency is always high and packet commands
A 12-byte transfer error is prevented.
The details will be described below with reference to the flowchart.

Low power consumption state (power save) described above
The operation at the transition to is shown in the flowchart of FIG. Not during power saving (step S1), not reading optical disc (step S2), not writing optical disc
(Step S3) When data is not being transferred (Step S3)
4), it is determined whether the A0h command is received (step S5). If the A0h command has not been received or if the packet command has already been received (step S6), the MCK frequency is set to 1, 2, 4, 8M.
After dropping to either Hz (step S7), PLL
The PLL (phase lock loop) of the circuit is put into a sleep state (step S8). Since this PLL circuit consumes a large amount of power, the effect of lowering the power consumption is great when the sleep state is set.

The operation at the time of returning from the low power consumption state is shown in the flowchart of FIG. When there is a read request for the ATA / ATAPI register 1 (step S11), it is next determined whether or not the return mode is designated (step S13). When the return mode is specified and when there is a write request (step S12), the frequency of MCK is changed to the clock (XCK) of the external crystal oscillator (step S14),
At the same time, the sleep of the PLL circuit is released (step S1).
5). After that, it is judged whether the transfer of the packet command 12 bytes is completed (step S16), and after the transfer is completed, the frequency of MCK is switched to PLLCK (step S17).

As described above, when there is an access from the host computer, the clock frequency is increased to speed up the response from the low power consumption state. However, if it is always returned to the steady state by access from the host computer, it will be returned even if it is not necessary.Therefore, it is judged whether or not the mode is returned after a read request is made, and the steady state is set only when necessary. I am trying to restore it.

[0026]

As described above, according to the present invention, when the write command is not received from the host computer when shifting to the low power consumption state, it is confirmed that the write command is received. It is possible to avoid switching to the low power consumption state before being performed.

Further, since the portion directly interfacing with the host computer is made asynchronous so that the command from the host computer can be received even if the clock frequency is lowered, low power consumption can be achieved.

When there is an access from the host computer, the clock frequency is increased to speed up the response from the low power consumption state. However, if you always return to a steady state by accessing from the host computer, it will return even if it is not necessary. Instead, the power saving state of the optical disk device can be realized by keeping the power saving state.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a host computer and an optical disk device in the case of ATA / ATAPI connection.

FIG. 2 is a block diagram showing a main part of the optical disk device of the present invention.

[Figure 3] Timing chart when the host computer accesses the ATA / ATAPI register

FIG. 4 is a flowchart showing an operation when shifting to a low power consumption state according to the present invention.

FIG. 5 is a flowchart showing an operation when returning to a low power consumption state according to the present invention.

[Explanation of symbols]

1 ATAPI register 2 ATAPI interface 3 Syscon interface 4 built-in FIFO 5 buffer RAM 6 ATAPI controller 7 Clock switching circuit 10 Low power consumption circuit

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) // G06F 1/04 301 G06F 1/04 301C

Claims (3)

[Claims] 1. An optical disc apparatus used by connecting to a host computer, wherein a low power consumption circuit provided for shifting to an arbitrary low power consumption state is used during reading, writing and non-data transfer. An optical disk device comprising means for confirming that a write command has not been received from a host computer when shifting to a low power consumption state. 2. The optical disk device according to claim 1, wherein the power consumption reduction circuit is capable of instantaneously recovering from a low clock low power consumption state by asynchronously processing a signal from the host computer. 3. When a read or write request is generated in the low power consumption state, the packet command is transferred with the clock being switched to the crystal oscillator clock, and after the transfer, the clock is switched to the operating PLL clock.
Alternatively, the optical disk device described in 2.