JP2003219030A - Misconnection monitoring system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a misconnection monitoring system that a primary time switch of a main signal control signal inserts a test pattern, a monitor function is provided to each switch panel so as to monitor the test pattern between the switch panels, and each switch panel monitors the test pattern among them to particularize the position at which misconnection takes place. <P>SOLUTION: The system of multi-stage connection configuration where a transmission apparatus, a time switch 10 in a cross connect section of an exchange, and a spatial switch 11 are connected in series is configured such that a host apparatus designates a connection destination/source package to select a FTS (Free Time Slot) pattern from a fixed position of the connection source and the time switch is used to replace the pattern with that of a fixed position of the connection destination. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an erroneous connection monitoring system for connection between packages (hereinafter abbreviated as PKG) of a transmission device or exchange, and more specifically, a firmware for monitoring connection between PKGs of the transmission device or exchange. FTS by wear (here, FTS is Free Time
A pattern setting method (abbreviation of Slot).

In recent years, with the diversification of communication services and the increase in the number of line users, it is required to efficiently accommodate various interfaces in one device. The PKG type and the number of PKG implementations accommodated in the device are It tends to increase. For this reason, in the case of an undefined PKG-to-PKG connection in which the connection configuration is not unique, not only the normality of the transmission line but also P
It is necessary to monitor erroneous connections when connecting the KG.

[0003]

2. Description of the Related Art A conventional instantaneous interruption control system using this kind of FTS pattern is disclosed in, for example, Japanese Patent Application Laid-Open No. 11-355390. This system requires one set of FTS pattern insertion circuit and FTS pattern extraction circuit to monitor the cable connection in one section. FIG. 6 is a conceptual diagram of a conventional system. In the figure, 1 is PK
G and 2 are PKGs connected to the PKG 1 via a cable 3. In PKG1, 1a is an FTS pattern insertion circuit for inserting FTS as a test pattern. In the PKG 2, 2a is an FTS pattern extraction circuit that extracts the FTS pattern (test pattern) sent via the cable 3 and determines the normality thereof.

In the system thus constructed,
From the PKG 1, the FTS pattern inserted by the FTS pattern insertion circuit 1a is transferred to the next PK via the cable 3.
It is sent to G2. In PKG2, the FTS pattern sent from PKG1 is taken out and its normality is confirmed. If the extracted FTS pattern does not match the pre-stored reference pattern,
It is determined that there is an erroneous connection between PKG1 and PKG2.

FIG. 7 is an explanatory diagram of a data format. In the figure, 4 indicates a frame. In the frame 4, 5 indicates a section overhead and 6 indicates a data area. Reference numeral 7 is an FTS pattern (test pattern) placed at a predetermined position in the section overhead 5.

[0006]

DISCLOSURE OF THE INVENTION The conventional FTS described above
In the pattern-based diagnostic control system, when the connection configuration between PKGs has n stages (n is an integer of 2 or more), n sets of FTS pattern insertion circuits and n sets of pattern extraction circuits are required. FIG. 8 is an explanatory diagram of a conventional multistage connection configuration. In the figure, 1 is TSW (time switch) or SS
A PKG including W (space switch) is connected to n PKGs # 1 to #n. In the # 1 PKG1, 1a is an FTS pattern insertion circuit for inserting an FTS pattern. In PKGs # 2 to #n,
Reference numeral 1b is an extraction circuit for extracting the FTS pattern from the PKG1 in the previous stage and checking its normality, and 1a is an FTS pattern insertion circuit for inserting the FTS pattern toward the PKG1 in the next stage.

In the circuit thus constructed, # 1
The FTS pattern insertion circuit 1a inserts the FTS pattern. The frame signal in which this FTS pattern is inserted is sent to PKG1 of # 2. In the # 2 PKG1, the take-out circuit 1b refers to the FTS pattern sent from the # 1 PKG1 and checks whether or not it matches a predetermined reference pattern. By this checking operation, it is determined whether or not the # 1 PKG1 and the # 2 PKG1 are erroneously connected. Next, PK of # 2
The G1 pattern insertion circuit 1a inserts the FTS pattern toward the # 3 PKG1. And # 3 PKG1
Then, the take-out circuit 1b receives the FTS pattern from the # 2 PKG1 and determines whether or not there is an erroneous connection between the # 2 and # 3 PKGs. Thereafter, the same operation is repeated until PKG1 of #n.

As described above, in the conventional system, it is necessary to prepare (n-1) sets of PKG1 including the FTS pattern insertion circuit 1a and the extraction circuit 1b shown in the figure, which increases the circuit scale. / It will lead to complication. In addition, when a T-S-T part such as a cross-connect (changing patterns) is included in the relay section of the cable connection (where T is a time switch and S is a space switch).
However, there is a problem that the diagnostic control method in which the FTS pattern is inserted and extracted at a predetermined position of the section overhead cannot be realized.

The present invention has been made in view of the above problems, and a test pattern is inserted from the primary side time switch of the main signal control signal so that each switch board has a monitoring function. An object of the present invention is to provide an erroneous connection monitoring system that can confirm the normality of a series of connections and at the same time identify the location of the erroneous connection by monitoring the test pattern between the switch boards.

[0010]

(1) FIG. 1 is a block diagram showing the principle of the present invention. In the horizontal direction of the figure, 10 is TS
W and 11 are space switches (SS
W). In this embodiment, first-order TSW # 1 to (m + 2) -th order TSW # 1 are provided in the lateral direction. TSWs # 1 to #n are provided in the vertical direction. Each TSW is connected via a cable. And, each TSW is an arbitrary one-to-one cable connection.

In each TSW 10, 10a is a primary T
It is an FTS pattern insertion circuit for inserting an FTS (test) pattern used only for SW. Secondary and subsequent TSW
In FIG. 10, 10b is a take-out circuit for taking out and analyzing the FTS pattern. Reference numeral 11 is a space switch (SSW) provided between the TSWs, and 11b is an extraction circuit provided in the SSW 11. The SSW 11 switches time slots (TS) on the time axis. Reference numeral 11a is a take-out circuit provided in the SSW 11 for taking out the FTS.

An arbitrary one-to-one cable connection is provided between the primary TSW and the (m-1) th TSW. The (m-1) th order TSW and the mth order TSW are arbitrary one-to-one cable connections. Also, the (m + 1) th TS
W and (m + 2) TSW are one-to-one arbitrary cable connections.

According to this structure, the primary T of the connection source is
By replacing the FTS pattern inserted by the SW pattern insertion circuit 10a with the fixed position of the next secondary TSW 10, the FTS pattern inserted at the fixed position of the secondary TSW 10 is extracted by the extraction circuit 10b. Therefore, the normality of the connection from the primary TSW to the secondary TSW can be confirmed.

(2) The invention according to claim 2 specifies an erroneous connection location by continuously using the operation according to claim 1 when the connection configuration is n stages (n is an integer of 1 or more). It is characterized by doing.

According to this structure, the operation according to claim 1 is performed between the TSWs of the respective stages, and the FTS pattern inserted in the predetermined fixed position of the second and subsequent TSWs is taken out to make the first order. It is possible to specify the erroneous connection location from the TSW of the TSW to the nth-order TSW.

(3) When the connection configuration is n stages (n is an integer of 2 or more), one FTS pattern insertion circuit and (n-1) pattern extraction circuits are provided. The feature is that the location of the incorrect connection can be identified by installing it.

With this configuration, the F of the first stage TSW is
The test pattern inserted from the TS pattern insertion circuit is extracted by the pattern extraction circuit provided in the (n-1) TSWs in the subsequent stage, whereby the erroneous connection location can be specified.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 2 is a system configuration diagram showing an embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. In the figure, 20 is (m
-1) A PKG (package) including the following TSW 10. Here, m is an arbitrary positive integer. In the PKG 20, reference numeral 20a is a control unit that performs pattern insertion and main signal control. Here, the main signal refers to a frame structure including section overhead and data. Here, the main signal control is control in which time slots (TS) on a frame are placed on the same time axis. The control unit 20a includes the FTS pattern insertion circuit 10a shown in FIG.
In the m-th order PKG 20, 20b is a control unit for performing pattern check and main signal control. The control unit 20b includes the take-out circuit 10b shown in FIG. 21 is SSW
PKGs containing 11. In the SSW21, 21
Reference numeral a is a control unit for controlling the main signal, and confirms the FTS pattern. At the same time, input frame signals from a plurality of TSWs connected to SSW11,
Change time slots on the time axis.

In the (m + 1) th order PKG20, 20
Reference numeral c is a control unit that performs pattern replacement and main signal control. Here, the pattern replacement means ((m + 1) T
Since S) is connected after the SSW 21, the FTS pattern after the replacement is arranged so that the FTS pattern is always included in the frame when the pattern is checked. At the same time, the FTS pattern is transferred to the main signal that matches it. (M +
2) The configuration of the next PKG is the same as that of the mth PKG 20.

Reference numeral 30 is a main controller for setting the time slot position of each TSW or SSW. As shown in the figure, the main control device 30 comprises a CPU 31 and firmware 32 connected thereto. The firmware 32 sets a time slot for each TSW 10 or SSW 11. Each TSW1
Since the firmware 32 gives the setting signal of the time slot of 0 or SSW11, the FTS is provided between the facing TSWs like the conventional system described above.
Since it is not necessary to provide the pattern insertion circuit and the extraction circuit, the number of circuits can be greatly reduced. 33 is a CPU
31 is a processor bus to which the firmware 32 is connected. The operation of the system configured as described above will be described below.

First, in the (m-1) th order PKG 20, the control section 20a inserts an FTS pattern given from the outside into the (m-1) th order TSW. The insertion position of the FTS pattern at this time is a specific position of the section overhead predetermined by the setting signal from the firmware 32.

Next, the m-th order TSW 10 has (m-1)
The FTS pattern transmitted next is input. Control unit 2
0b compares the FTS pattern with a predetermined reference pattern to check if there is any misconnection. The operation of the control unit 20b is an operation of extracting and confirming the FTS pattern and returning the confirmed FTS pattern to a predetermined position of the frame. Then, the control unit 20
After the pattern check is completed, b shifts the FTS pattern to the time slot position designated by the firmware 32 on the time axis. m-order TSW10 is
The main signal is sent to the PKG 21 including the SSW 11.

As described above, according to the embodiment of the present invention, the F inserted by the pattern inserting circuit of the connection source TSW is used.
By replacing the TS pattern with the fixed position of the next TSW, the FTS pattern inserted in the fixed position of the secondary TSW can be taken out by the extraction circuit.
The normality of the connection from the primary TSW to the secondary TSW can be confirmed.

In the PKG 21, the control unit 21a performs cross-connect connection control based on the control signal given from the firmware 32, and transfers the input FTS pattern to the slot position designated by the firmware 32. Here, the PKG 21 confirms the frame in which the FTS pattern is written. And P
The main signal sent from SSW11 of KG21 is (m +
1) Enter the next TSW 10. Here, the control unit 20c
Is after the main signal has been replaced by the SSW 11, the pattern replacement and the main signal control are performed so that the FTS pattern can be reliably detected. In addition, the control unit 20
The fetch circuit of c checks the FTS pattern sent. After that, the control unit 20c performs main signal control and then sets the frame pattern to the (m + 2) th TSW10.
Send to. (M + 2) In the next TSW10, the control unit 2
The fetch circuit of 0b checks the FTS pattern, and the control unit 20b controls the main signal.

In such a series of flows, each TSW is
The take-out circuit 10b (see FIG. 1) checks the FTS pattern to see if there is any misconnection. (M
+2) The next TSW is (m-1) th TSW to (m
Since the FTS pattern check results up to +1) th order are included, it is possible to determine whether or not there is an erroneous connection by checking the (m + 2) th order FTS pattern. If an abnormality is found in the FTS pattern, T
By tracing the SW in the opposite direction, which TSW or S
It is possible to check whether a wrong connection has occurred in SW.

As described above, according to the embodiment of the present invention, the pattern insertion and the pattern extraction operation are performed between the TSWs of each stage, and the predetermined fixed positions of the TSWs of the second stage (secondary) and thereafter are fixed. By taking out the FTS pattern inserted in, the erroneous connection location from the primary TSW to the nth TSW can be specified.

Further, in the present invention, since the firmware 32 connected to the CPU 31 performs control for performing such a series of operations, the FSW for each TSW 10 is performed.
TS pattern insertion processing is not required, and the circuit scale can be significantly reduced.

FIG. 3 is a diagram for explaining the operation of the primary time switch (TSW). The same parts as those in FIG. 2 are designated by the same reference numerals. In the primary TSW10, the control unit 20a
TS pattern insertion and main signal control are performed. At this time, the control unit 20a allocates the secondary FTS patterns of TSW # 1 to TSW # 4 to respective areas obtained by dividing the TS (time slot) 2 into four, according to an instruction from the firmware 32.

From the TSW 10, for example, TS1 to TS3 are transmitted as shown in the figure. At this time, the control unit 20a
Defines the FTS pattern allocation area using TS2. In the example of the figure, the address of the FTS pattern monitored by the secondary TSW # 4 is located at the position a, and the address of the FTS pattern monitored by the secondary TSW # 3 is located at the position b, c
Address of the FTS pattern monitored by the secondary TSW # 2 at the position of, and FTS monitored by the secondary TSW # 1 at the position of d
Assign each pattern address.

The frame in which the address of the FTS pattern used in each TSW is written in this way is the secondary TS.
It is sent to W10. In the secondary TSW10, the primary T
Refer to TS2 sent from SW10. And
For example, the secondary TSW # 1 refers to the area d of TS2 to confirm the position in the section overhead in which the FTS pattern addressed to itself is inserted, and refers to the FTS pattern addressed to itself. Then, confirm the normality of the connection. This behavior is
The same applies to the remaining TSW # 2 to TSW # 4.

FIG. 4 is another operation explanatory view of the time switch, showing the operation of the (m + 2) -th time switch. In this example, the operation of the TSW after passing through the space switch (SSW) is shown. Since the frames are switched in the SSW, the patterns are switched in the TSW in the subsequent stage of the SSW so that the FTS pattern can be surely confirmed.

(M + 2) SSW of the preceding stage to the next TSW
When a frame is sent from, the control unit 20c performs pattern replacement processing and main signal control. And
In order that the FTS pattern can be confirmed by the next (m + 3) th TSW, the (m + 3) th TSW # 1 to TS
For example, the insertion address of the FTS pattern is stored in the fourth position of the TS commonly in W # 4. Therefore, in the (m + 3) th TSW, TSW # 1 to TSW # 4 are common FTSs.
You will refer to the pattern. In this case, the FTS pattern is a pattern common to all TSWs # 1 to # 4.

(M + 2) In the next TSW10, AC
In the M control (control for calculating the positions of the start point and the end point of the TS insertion destination), in the (m + 2) th TSW, by replacing the FTS pattern with the time slot uniquely assigned to the (m + 3) th TSW, (m + 3) ) The next TSW monitors the normality of the connection. (M + 4) Next TSW
Similarly thereafter, the normality of the connection is monitored by detecting the FTS pattern detected by the (m + 3) th TSW 10 again. The normality of a series of connections can be confirmed and the erroneous connection location can be identified from the determination results of the primary TSW 10 to the (m + 3) th TSW (including (m + 4) th and subsequent).

FIG. 5 is a block diagram showing a second embodiment of the present invention. The system shown is the primary TSW1
A five-stage connection from 0 to the fourth-order TSW10 via the SSW11 on the way is shown. The same parts as those in FIG. 1 are designated by the same reference numerals. The system shown in FIG. 5 shows the case where m = 2 in the system of FIG. TS in each order
W is # 1 to # 3 and has the configuration of the TSW 10. S
SW11 is connected between the secondary TSW10 and the tertiary TSW10.

An arbitrary one-to-one cable connection is made between the primary TSW 10 and the secondary TSW 10. Also, the third TS
An arbitrary one-to-one cable is also connected between W10 and the fourth-order TSW10. The operation of the system configured as described above will be described below.

In the primary TSW 10, the FTS pattern is inserted. In the secondary TSW10, the primary TSW1
FTS pattern inserted from 0 is taken out and FTS pattern is extracted.
The pattern is taken out. FT which judgment was completed
S is returned to the predetermined position of the frame again, and the secondary TSW1
The main signal including the FTS pattern output from 0 is SS
Cross-connection is performed by W11, and patterns are exchanged.

In the third-order TSW 10, since the pattern that has passed through the SSW 11 is input, the FTS pattern is taken out and replaced. That is, in order to determine whether there is an erroneous connection and detect the FTS pattern, the patterns are exchanged. The FTS pattern replaced by the third-order TSW enters the fourth-order TSW, and the FTS pattern is extracted.

According to the embodiment of the present invention described above, the test pattern inserted from the FTS pattern insertion circuit of the TSW in the first stage is used as the pattern extracting circuit provided in the (n-1) TSWs in the latter stage. By taking out the test pattern with, the erroneous connection location can be specified.

[0039]

As described above, according to the present invention, the following effects can be obtained. (1) According to the invention of claim 1, the primary T of the connection source is
By replacing the FTS pattern inserted by the SW insertion circuit with the fixed position of the next secondary TSW, 2
The FTS pattern inserted at the fixed position of the next TSW can be taken out by the pattern take-out circuit, and the first T
The normality of the connection from SW to the secondary TSW can be confirmed.

(2) According to the invention of claim 2, the operation of claim 1 is performed between the TSWs of the respective stages, and the Ts of the second and subsequent stages are performed.
FTS inserted in a predetermined fixed position of SW
By taking out the pattern, it is possible to identify the erroneous connection location from the primary TSW to the nth TSW.

(3) According to the third aspect of the invention, the test pattern inserted from the FTS pattern insertion circuit of the TSW in the first stage is extracted by the pattern extracting circuit provided in the (n-1) TSWs in the second stage. By taking out the test pattern, it is possible to identify the incorrect connection location.

As described above, according to the present invention, a test pattern is inserted from the primary side time switch of the main signal control signal, and each switch panel (PKG) is provided with a monitoring function, so that a series of connection can be achieved. It is possible to provide an erroneous connection monitoring system capable of identifying a location where an erroneous connection has occurred by simultaneously checking the normality and monitoring the test pattern between the switch boards.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing a first exemplary embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of a primary time switch.

FIG. 4 is a diagram illustrating another operation of the time switch.

FIG. 5 is a block diagram showing a second exemplary embodiment of the present invention.

FIG. 6 is a conceptual diagram of a conventional system.

FIG. 7 is a diagram showing a data format.

FIG. 8 is an explanatory diagram of a conventional multistage connection configuration.

[Explanation of symbols]

10 TSW (time switch) 10a pattern insertion circuit 10b Extraction circuit 11 SSW (Space switch) 11a Extraction circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Katsumi Yokochi             2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa             Issue Fujitsu Digital Technology Stock Association             In-house (72) Inventor Masamitsu Komi             2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa             Issue Fujitsu Digital Technology Stock Association             In-house F term (reference) 5K019 AA07 AB05 BA02 BA57 BB55                       CD11

Claims (3)

[Claims] 1. In a system having a multi-stage connection configuration in which a time switch and a space switch in a cross-connect section of a transmission device and a switching device are connected in series, a connection source / source package is designated by a host device, Select the FTS pattern from a fixed position,
An erroneous connection monitoring system that uses a time switch to switch to a fixed position at the connection destination. 2. An erroneous connection monitor characterized by specifying an erroneous connection point by continuously using the operation according to claim 1 when the connection configuration has n stages (n is an integer of 1 or more). system. 3. An FTS pattern insertion circuit and (n-1) when the connection configuration has n stages (n is an integer of 2 or more).
The incorrect connection monitoring system according to claim 1, wherein the incorrect connection location is specified by installing a pattern extraction circuit.