JP2003218963A - Feed-forward/feedback system and method for non-casual channel equalization - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for reducing the effects of pulse spreading on hard-decision error rate. <P>SOLUTION: The feed-forward/feedback method for non-casual channel equalization in a communications system comprises the steps of: receiving a non-return to zero (NRZ) data stream input; using a first plurality of thresholds, estimating a first bit in the data stream using a second plurality of thresholds, determining a third bit value received subsequent to the first bit; comparing the first bit estimate to the third bit value; comparing the first bit estimate to a second bit value received prior to the first bit, and determining the value of the first bit in response to the comparisons. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD OF THE INVENTION (Related Application)
“SYSTEM” invented by stagnozzi et al.
AND METHOD FOR NON-CAUSA
L CHANNEL EQUALIZATION ”, a pending application (serial number 10/020,
426, filed on Dec. 7, 2001, and is a partial continuation application of proxy reference number 114).

The present application is directed to "SYSTEM AND METHOD FOR NO" invented by Yuan et al.
N-CAUSAL CHANNEL EQUALIZA
TION IN AN ASYMMETRICAL N
A pending application entitled "OISE ENVIRONMENT" (serial number 10 / 066,966,20
The application was filed on February 4, 2002, and is a partial continuation application of agent reference number 115).

This application is based on "SYSTEM AND METHOD" invented by Castagnozzi et al.
FOR NON-CAUSAL CHANNEL EQ
UALIZATION USING ERROR ST
ATITIC DRIVEN THRESHOLD
Pending application called "S" (serial number 10 /
077,332, filed February 15, 2002, and is a continuation-in-part application of proxy reference number 118).

This application is based on the "SYSTEM AND METHOD FOR A" invention invented by Aikel et al.
DJING A NON-RETURN TO
ZERO DATA STREAM INPUT TH
This is a partial continuation application of a pending application called "RESHOLD" (serial number 10 / 077,274, filed February 15, 2002, agent reference number 117).

The present application is directed to the "SYSTEM AND METHOD FOR FI" invented by Yuan et al.
VE-LEVEL NON-CAUSAL CHAN
A pending application entitled "ELEQUALZATION" (serial number 10/150, 301, 2002
The application was filed on May 17, 2015, and is a partial continuation application of agent reference number 119).

This application is based on the "SYSTEM AND METHOD FORT" invented by Milton et al.
EMPORAL ANALYSIS OF SERIA
A pending application called "LDATA" (serial number 10 / 193,961, filed July 12, 2002,
This is a partial continuation application of proxy reference number 129).

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to digital communications,
More specifically, it relates to systems and methods for minimizing the effects of inter-symbol interference in non-return-to-zero (NRZ) data channels.

[0008]

2. Description of Related Art FIG. 1 is a diagram showing a signal recovered from a non-dispersive channel of binary symmetry in the presence of noise (prior art). Conventionally, signals are waveforms used for communication (in this case, one unit step)
Is filtered using a transfer function matched to and thresholded at the voltage level most likely to produce a transmitted bit. In order to recover the transmitted information, difficult decisions must be made regarding the value of the received bits.

Pulse spreading occurs as a function of the filtering process and sometimes as a result of the transmission process. That is, the energy associated with a bit spreads to adjacent bits. If the degree of diffusion is small, then these effects can be limited to the nearest value, slightly degrading performance.

There are three basic types of pulse spreading. The first possibility is that both adjacent bits are zero (1
There is no adjacent bit). Second
The possibility is that only one of the adjacent bits (either the previous or the next bit) is one. In other words, only one of the adjacent bits is zero. The third possibility is that both adjacent bits are ones. For each of these cases, the possibility of error in determining the value of a bit can be minimized if different thresholds are used for different bit combinations.

FIG. 2 is a diagram showing the received waveform,
This waveform is distorted (prior art) in response to intersymbol interference that results from the dispersal of energy. The value at the output of the filter is different for each bit, due to the non-deterministic nature of the information and the scrambling often used in transmitting NRZ data streams,
It is essentially a random process. However, the received bits may be characterized using a probability density function, as shown. Even if the adjacent bits are not known, a single probability density function representing the random behavior of the input in all conditions and in all sequences can be extracted. However, a conditional probability density function can be defined for the above three cases. That is, the probability density function may be defined for the case where both adjacent bits are zero, only one of the adjacent bits is 1, and the two adjacent bits are 1.

With the knowledge of the decision that the bit value decision process made on the previous decoded bit,
And a corresponding probability density function can be selected, and a more accurate decision can be made for the current bit decision. However, conventional analog-digital (A /
D) In the case of conversion circuits, cost and accuracy make such a solution impractical.

The degree of dispersion exhibited by the channel, and hence the degree of separation of the conditional probability density functions, varies with a number of fixed and variable factors. Therefore, effective dispersion mitigation technology (effective dispersers)
ion migration technique
s) should be easily optimized for the channel and some adaptation to changes in the channel due to aging, temperature changes, reconfigurations, and other possible effects.

It would be advantageous if intersymbol interference caused by energy distribution in the received NRZ data channel could be minimized.

It would be advantageous if the bit decision threshold could be modified to account for the dispersed energy in adjacent bits in the NRZ data stream.

It is advantageous if the bit decision value can be made on the basis of the previous and subsequent bit values.

When propagating over long distances or through non-linear media, many communication channels exhibit a temporary spread of the communication waveform, which phenomenon is due to the non-causal nature of the failure. In addition, it is not effectively dealt with by the conventional linear equalization technique.

[0018]

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the effect of pulse spreading on difficult decision error rates in a communication system which is subject to transient spreading of the communication waveform. Is to present.

[0019]

SUMMARY OF THE INVENTION A method according to the present invention is a method for equalizing non-causal channels of feedforward / feedback in a communication system, the method comprising receiving a non-return-to-zero (NRZ) data stream input. And estimating a first bit of the data stream using a first plurality of thresholds, and using a second plurality of thresholds to obtain a third bit received subsequent to the first bit.
Determining the bit value of the first bit estimate, comparing the first bit estimate with the third bit value, and comparing the first bit estimate with the second bit estimate received prior to the first bit.
And comparing the first bit value in response to the comparison, and thereby determining the first bit value in accordance with the comparison.

The step of estimating the first bit of the data stream using the first plurality of thresholds may include the step of using a third threshold.

[0021] Using the second plurality of thresholds, the first
The step of determining a third bit value received subsequent to the bits of may include using two thresholds.

The step of determining the third bit value may include the step of determining the third bit value in response to the determination of the previous third bit value.

A step of defining a first threshold value (V1) so as to identify a first bit estimation value which is a high probability "1", and a first bit estimation value which is a high probability "0". Defining a second threshold (V0) to identify, and defining a third threshold (Vopt) to identify a first bit estimate between the first and second thresholds. Defining the first bit of the data stream using the first plurality of thresholds comprising: defining the first threshold, the second threshold, the third threshold. May be further included.

Defining a fourth threshold (V1 ') so as to identify a third bit estimate that is "1" with a high probability, and a third bit estimate that is "0" with a high probability. Defining a fifth threshold value (V0 ′) to identify the third threshold value, and determining the third bit value includes using the fourth threshold value and the fifth threshold value. May be included.

The step of determining the first bit value according to the comparison is performed by setting the second bit value to "0" when the second bit value and the third bit value are both "1". And only one of the third bits has a value of "1", as "1", and the second bit and the third bit
Are both “0”, the value is “1”, and N is lower than the first threshold and higher than the third threshold.
Identifying the RZ data stream input, and if only one of the second bit and the third bit is "1" if the second bit and the third bit both have a value of "0". Below the second threshold and as a “0” when the value is “0” and as a “0” when the second bit and the third bit are both a value of “1”, and Identifying the NRZ data stream input above a threshold of three.

The step of determining the third bit value is "0" when the previous third bit value is "1".
And identifying an NRZ data stream input below the fourth threshold and above the fifth threshold; and "1" if the previous third bit value was "0".
As a NRZ data stream input below the fourth threshold and above the fifth threshold.

The step of receiving a non-return-to-zero data stream comprises the step of receiving a forward error correction (FEC) encoded non-return-to-zero data stream, the method comprising: FEC decoding the first bit value according to the determination of the value;
Adjusting the threshold using FEC correction of the first bit value.

The first threshold, the second threshold, and the third
The FE of the first bit value to adjust the threshold of
The step of using C correction is F to adjust the threshold.
The step of using the statistical value of the EC error may be included.

The step of using the FEC error statistics to adjust the threshold comprises the step of evaluating the number of errors associated with a combination of a plurality of 3-bit sequences, each sequence comprising the second bit value, The error may be in the first (central) bit value, which subsequently comprises the first (central) bit value and subsequently the third bit value.

Evaluating the number of errors associated with the combination of the plurality of 3-bit sequences may include comparing the number of errors between different groups of 3-bit sequences.

The step of using the FEC error statistics to adjust the threshold is such that the number of errors between the first group of 3-bit sequences and the second group of 3-bit sequences is balanced. The step of adjusting the threshold may be included.

The steps of evaluating the number of errors associated with the combination of the plurality of 3-bit sequences are different.
The first (middle) bit value may be FEC corrected, including the step of comparing groups of bit sequences.

The step of evaluating the number of errors associated with the combination of the plurality of 3-bit sequences may be different.
Comparing the groups of bit sequences, wherein the first (center) bit value and the second bit value are F
EC may be corrected.

The step of evaluating the number of errors associated with the combination of said plurality of 3-bit sequences is different.
Comparing the groups of bit sequences, wherein the first (middle) bit value and the third bit value are F
EC may be corrected.

Tracking the NRZ data stream input when the second bit value is equal to the third bit value, and the tracked NRZ data stream.
The method may further include maintaining the average value of the data stream input for a long period of time, and adjusting the first threshold value and the second threshold value according to the average value of the long period.

Tracking the NRZ data stream input when the second bit value is equal to the third bit value, the second bit value and the third bit value are both "1". When it has a value, the NR
Tracking the Z data stream input, and tracking the NRZ data stream input when the second bit value and the third bit value both have a value of "0". .

The step of maintaining the average value of the NRZ data stream input for a long period of time includes the step of maintaining the average value of the NRZ data stream input when the second bit value and the third bit value both have a value of "1". Generating an average value of 1 and generating a second average value of the NRZ data stream input when the second bit value and the third bit value both have a value of "0". May be included.

The step of adjusting the first threshold value and the second threshold value according to the average value of the long period adjusts the first threshold value (V1) according to the first average value. And adjusting the second threshold value (V0) according to the second average value.

The method may further include the step of adjusting the third threshold value (Vopt) in response to the step of adjusting the first threshold value (V1) and the second threshold value (V0).

The step of adjusting the third threshold value (Vopt) in response to the step of adjusting the first threshold value (V1) and the second threshold value (V0) includes the steps of adjusting the first threshold value and the second threshold value. The step of setting the third threshold value substantially in the middle of the threshold value may be included.

The method may further include the steps of measuring an overall average NRZ data stream input voltage and setting the third threshold in response to the measured overall average.

Adjusting the fourth threshold value so as to be approximately in the middle of the first threshold value and the third threshold value, and so as to be substantially in the middle of the third threshold value and the second threshold value. Adjusting the fifth threshold value may be further included.

The method of the present invention comprises the steps of:
A method for equalizing a non-causal channel of feedforward / feedback, the method comprising receiving a non-return-to-zero (NRZ) data stream input, the method using a first plurality of thresholds. Estimating a first bit of the data stream; determining a third bit value received subsequent to the first bit value in response to the previous third bit value determination; Comparing a bit estimate of 1 with the third bit value; comparing the first bit estimate with a second bit value received prior to the first bit value; Determining the first bit value in response to the comparison,
Thereby, the above object is achieved.

The step of determining the third bit value may include the step of determining the third bit value using a second plurality of threshold values.

The method of the present invention comprises the steps of:
A method for equalizing a non-causal channel of feedforward / feedback, the method comprising receiving a non-return-to-zero (NRZ) data stream input, the method using a first plurality of thresholds. Estimating a first bit of a data stream, analyzing the first bit estimate of a first bit sequence to determine the first bit value, and determining a third bit value So that in the second bit sequence the first
Of the third bit estimate received subsequent to the bit value of 1?

Estimating the first bit of the data stream using a first plurality of thresholds may include estimating the first bit value for three thresholds.

First to determine the first bit value
Analyzing the first bit estimate of the sequence of bits of, analyzing the first sequence of bits received after the second sequence of bits, followed by the third sequence of bits received subsequently. May be included.

The second so as to determine the third bit value
Analyzing the third bit estimate of the sequence of bits of s may include analyzing the third bit estimate following the previous sequence of third bit values.

The method may further include estimating the third bit value using the second plurality of thresholds.

The step of estimating a third bit value using the second plurality of thresholds comprises the third threshold for the two thresholds.
May include the step of estimating the bit value of

The step of defining the first threshold value (V1) so as to identify the first bit estimation value which is “1” with high probability, and the first bit estimation value which is “0” with high probability are Defining a second threshold (V0) to identify, and a third threshold (Vopt) to identify a first bit estimate between the first threshold and the second threshold. Further comprising: defining the first bit estimate of the first bit sequence to identify the first bit value, the second bit value and the third bit value. Are both "1", the value is "0", and only one of the second bit value and the third bit value is "1".
And ‘1’ if both the second bit value and the third bit value are values of “0”, below the first threshold value and above the third threshold value. Identifying a data stream input, the second bit value and the third bit value as "1" if the second bit value and the third bit value are both "0". If only one of the two has a value of "0", it is set to "0", and if both the second bit value and the third bit value are "1", it is set to "0". Identifying the NRZ data stream input above a threshold of 2 and below the third threshold.

Defining a fourth threshold (V1 ') to identify a third bit estimate that is "1" with a high probability, and a third bit estimate that is "0" with a high probability. Further defining a fifth threshold value (V0 ′) to identify the second bit sequence, and analyzing a third bit estimate of the second bit sequence to determine the third bit value. Indicates that the previous third bit value is “1”
If it is “0”, the step of identifying the NRZ data stream input below the fourth threshold and above the fifth threshold, and the previous third bit value was “0”. The case “1” may include identifying an NRZ data stream input below the fourth threshold and above the fifth threshold.

The system of the present invention is a feedforward / feedback non-causal channel equalization communication system, which accepts an input, a threshold, for accepting a non-return-to-zero (NRZ) data stream. And a multiple threshold circuit having an output for providing a first bit estimate in response to a first plurality of voltage threshold levels, and an input for receiving the bit estimate from the multiple threshold circuit. A non-causal circuit having a first bit estimate and a third bit value received after the first bit value and determined in response to a previously determined third bit value; And a second received before the first bit value
A non-causal circuit having an output for providing a first bit value in response to a comparison with the bit value of
Thereby, the above object is achieved.

The multi-threshold circuit provides a third bit estimate in response to a second plurality of voltage threshold levels, and the non-causal circuit receives the third bit estimate. A future decision circuit having an input connected to the output of the multi-threshold circuit and an output for supplying a third bit value in response to a previous third bit value decision; A current decision circuit having an input for receiving a bit estimate of 1, the third bit value from the future decision circuit, and a second bit value, the first bit value being:
A current decision circuit having an output for providing the first bit value determined in response to comparing the second bit value and the third bit value; It may also include a past decision circuit having an input for receiving and an output for providing the second bit value.

The multi-threshold circuit has an input for accepting the NRZ data stream, an input defining a first threshold (V1), and a bit estimate at which the NRZ data stream input has a high probability of "1". A first comparator having an output for providing a signal identifying when to have an input, and an input for receiving the NRZ data stream,
A second comparator having an input defining a second threshold (V0) and an output for providing a signal that identifies when the NRZ data stream input has a bit estimate that is "0" with high probability. And an input for accepting the NRZ data stream, an input defining a third threshold (Vopt), and the NRZ data stream input having bit estimates of "0" and "1" with approximately equal probability. A third comparator having an output for providing a signal of

The multi-threshold circuit provides a bit estimate for the NRZ data stream input below the third threshold and above the second threshold, and the current decision circuit accordingly. When the second bit value and the third bit value are both "0", one of the first bit value of "1" and the second bit value or the third bit value If only one has a value of "0",
When the first bit value of “0” and the second bit value and the third bit value are both “1”, the first bit value of “0”
And bit values of

The multi-threshold circuit provides a bit estimate for the NRZ data stream input above the third threshold and below the first threshold, and the current decision circuit accordingly. , When the second bit value and the third bit value are both “1”, the first bit value of “0” and the second bit value and the third bit value If only one of them has a value of "1",
Even if the first bit value of "1" and the second bit value and the third bit value are both "0", the first bit value of "1" is supplied. Good.

The multi-threshold circuit is an input for accepting the NRZ data stream, a fourth threshold (V1 ').
A fourth comparator having an input defining the NRZ data stream and an output for providing a signal that identifies when the NRZ data stream input has a bit value that is likely to be "1"; Input to
An input defining a fifth threshold (V0 ′), and the NRZ
A fifth comparator having an output for providing a signal that identifies when the data stream input has a bit value that is likely to be "0".

The multi-threshold circuit provides a third bit estimate for the NRZ data stream input above the fifth threshold and below the fourth threshold, and the future decision circuit comprises: The NRZ data stream input may be identified as "0" if the previous third bit value was "1" and "1" if the previous third bit value was "0". .

The multi-threshold circuit has a forward error correction (FE)
A system for accepting an NRZ data stream encrypted according to C), said forward error correction (FEC) circuit having an input for receiving said first bit value from said acausal circuit, Decode the incoming data stream to provide the corrected bit value at the output,
It may further include an acausal circuit and a statistical calculator having an input connected to an output of the FEC circuit for providing a threshold to the multi-threshold circuit in response to the FEC correction.

The statistical calculator may be arranged such that, when each sequence includes the second bit value, followed by the first (center) bit value, and then the third bit value.
Estimating the number of said errors associated with a combination of multiple 3-bit sequences, said errors may be in said first (middle) bit value.

The statistical calculator may adjust the threshold in response to comparing the number of errors between groups of different 3-bit sequences.

The statistical calculator may adjust the threshold to balance the number of errors between the first group of 3-bit sequences and the second group of 3-bit sequences.

The statistical calculator may compare different groups of 3-bit sequences when the first (center) bit value is FEC corrected.

The statistical calculator may compare different groups of 3-bit sequences when the first (center) bit value and the second bit value are FEC corrected.

The statistical calculator may compare different groups of 3-bit sequences when the first (center) bit value and the third bit value are FEC corrected.

The statistical calculator supplies the fourth threshold value approximately midway between the first threshold value and the third threshold value and the midway point between the third threshold value and the second threshold value. A fifth threshold may be provided.

An averaging circuit having an input connected to the output of the acausal circuit and an input for receiving the NRZ data stream, the averaging circuit comprising:
If the second bit value and the third bit value are both equal to "1", track the NRZ data stream input, and then track the tracked NR.
Maintaining a first long term average of the Z data stream input, the averaging circuit having an output for providing the first threshold (V1) in response to the first long term average. The digitalization circuit may be further included.

The averaging circuit tracks the NRZ data stream input when the second bit value and the third bit value are both equal to "0",
Maintaining the average of the second long period of the RZ data stream input, and depending on the second long period, the second threshold (V
0) may be supplied.

The averaging circuit responds to the first threshold value and the second threshold value by the third threshold value (Vopt).
May be supplied.

The averaging circuit may supply the third threshold approximately in the middle of the first threshold and the second threshold.

The averaging circuit measures an overall average voltage of the NRZ data stream and, in response to the measured overall average, the third threshold (Vop) at the output.
t) may be supplied.

The averaging circuit supplies the fourth threshold value approximately in the middle of the first threshold value and the third threshold value,
The fifth threshold value may be supplied approximately in the middle of the third threshold value and the second threshold value.

The future decision circuit outputs a signal input connected to the output of the fourth comparator, a signal input connected to the output of the fifth comparator, a control input, and the third bit value. It may include a multiplexer (MUX) having an output for providing and a flip-flop having an input connected to the MUX output and an output connected to the MUX control input.

The above method utilizes multiple decision thresholds for each data bit. Post-processing of multiple decision data is used to reduce the data to a single difficult decision bit by bit. The multiple data thresholds are adjusted to optimally mitigate the diffusion effect.

The proposed approach to the above problem is to make multiple decisions for each bit that has a threshold for each of the conditional probability density functions described above.
Multiple decision data are stored for each individual bit time,
It is possible to be calculated for the next bit. This calculation is used to select the most appropriate threshold given the estimated neighbor values. The exact decision is output from the device used in the processing of the next bit and fed forward.

Accordingly, a method is provided for feedforward / feedback acausal channel equalization in a communication system. This method uses a non-zero return (N
RZ) receiving a data stream input, and 3.
Using one threshold, estimating the first bit in the data stream, using two thresholds, and determining a third bit value received following the first bit, Comparing the first bit estimate with the third bit value; comparing the first bit estimate with the second bit value received before the first bit; Responsively, determining the first bit value. In some aspects of the method, the third bit value is determined in response to the previous third bit decision value.

The method further includes a first threshold (V) to identify the first bit estimate that is "1" with a high probability.
1) and a second threshold (V0) to identify the first bit estimate with a high probability of "0".
And establishing a third threshold (V) to identify a first bit estimate between the first and second thresholds.
opt) and a fourth threshold (V) to identify a third bit estimate that is likely to be “1”.
1 ′) and a fifth threshold (V) to identify the third bit estimate that is “0” with high probability.
0 ') is defined.

The step of identifying a first bit estimate between the first threshold and the second threshold includes inputting the NRZ data stream input below the first threshold and above the third threshold, "0" if both the 2nd bit and the 3rd bit have a value of "1", and if only one of the 2nd bit and the 3rd bit has a value of "0" Identifying as “1” and NRZ data stream input above a second threshold and below a third threshold, where both the second and third bits have a value of “0” Is "1", and when only one of the second bit and the third bit has a value of "0", it is "0", and both the second bit and the third bit are "1". If the value is 0, the step of identifying as “0” is included.

The step of determining the third bit value is performed if the NRZ data stream input is below the fourth threshold value and above the fifth threshold value and the previous third bit value is "1". Is identified as "0", and the NRZ data stream input below the fourth threshold and above the fifth threshold is "0" if the previous third bit value was "0". Identifying as "1".

In one aspect of the method, the step of receiving a non-zero-return data stream comprises forward error correction (F
EC) encoded non-return-to-zero data stream. Then, the method further comprises following the determination of the first bit value, FEC decoding the first bit value, and using FEC correction of the first bit value to adjust the threshold. Include. Alternatively, the method tracks the NRZ data stream input if the second bit value equals the third bit value, maintaining a long-term average of the tracked NRZ data stream input, and The method further includes adjusting the first threshold value and the second threshold value according to the average.

[0082]

Further details of the above method and non-causal channel equalization communication system are provided below.

FIG. 3 is a schematic block diagram of the feedforward / feedback non-causal channel equalization communication system of the present invention. System 100 uses line 10 to receive a non-return-to-zero (NRZ) data stream.
4 and the input receiving the threshold on line 106
A plurality of threshold determination circuits 102 having the above inputs are provided. The multi-threshold decision circuit 102 provides an output on line 10 that provides a bit estimate in response to multiple voltage threshold levels.
Have 8 on.

The acausal circuit 110 receives the estimate of the bits from the multi-threshold decision circuit 102 on line 1
Prepare on 08. The acausal circuit 110 compares the estimated value of the current bit (first bit) with the determined value of the bit made over multiple clock cycles. More specifically, the acausal circuit 110 includes a first bit estimate, a third bit value received following the first bit, and a second bit value received prior to the first bit. Providing a first bit value in response to comparing the bit value. Further, the third bit value is determined according to the already determined third bit value. The acausal circuit 110 has an output and provides a bit decision value to an estimate of the current bit determined in response to the comparison of the acausal bit values.

The multi-threshold circuit 102 provides a third bit estimate over line 108 in response to the second plurality of voltage threshold levels. The acausal circuit 110 has an input and line 116 connected to the multi-threshold circuit output 108.
A future decision circuit 114 having an output of, and supplies a third bit value in response to the determination of the previous third bit value. The current decision circuit 118 has an input on line 108 and receives a first bit estimate from the multi-threshold circuit 102, a third bit value from the future decision circuit 114 on line 116, and a second bit value on line 120. Accept. The current decision circuit 118 has an output on line 122 for determining a first bit value determined in response to comparing the first bit estimate with the second bit value and the third bit value. Supply. Past decision circuit 124 has an input on line 122 for receiving a first bit value and an output on line 120 for supplying a second bit value. The past decision circuit 124 functions as a one clock cycle delay.

FIG. 4 is a detailed diagram of the multiple threshold circuit 102 of FIG. The multi-threshold circuit 102 receives an input on line 104 that receives the NRZ data stream, a first threshold (V
The input of line 106a that defines 1) and the line 1 that provides a signal that identifies when the input of the NRZ data stream has a high probability of having a bit estimate of "1".
It includes a first comparator 126 having an output of 08a. Second
Comparator 130 for the input of line 104 that accepts the NRZ data stream, the input of line 106b that defines the second threshold (V0), and the bit estimate that the input of the NRZ data stream is "0" with high probability. The output of line 108b which provides a signal identifying when to have. The third comparator 132 receives the input of line 104 that receives the NRZ data stream, a third threshold (Vopt).
The input of the line 106c that defines the line and the input of the NRZ data stream are "0" and "1" with almost the same probability.
Has an output on line 108c that provides a signal when having a bit estimate that is

Considering FIGS. 3 and 4, the multi-threshold circuit 102 determines that the third threshold (Vopt) on line 106c.
When presenting the first bit estimate to the NRZ data stream input on line 104 below and above the second threshold (V0) on line 106b, the current decision circuit 118 accordingly responds to the second decision. When the bit value and the third bit value both have a value of "0", the first bit value of "1" is supplied to the line 122. If only one of the second bit value and the third bit value has a value of "0", or if both the second bit value and the third bit value have a value of "1", then "0" The first bit value of ". NRZ data above the first threshold is considered a definite “1” and data below the second threshold is considered a definite “0”.

A multi-threshold circuit 102 outputs a first bit estimate for the NRZ data stream input on line 104 above a third threshold on line 106c and below a first threshold (V1) on line 106a. The current decision circuit 118 accordingly supplies the first bit value of “0” on the line 122 if the second bit value and the third bit value both have a value of “1”. To do. If only one of the second bit value and the third bit value has a value of "1", or if both the second bit value and the third bit value have a value of "0", then "1" The first bit value of “” is provided on line 122.

The multi-threshold circuit further includes an input on line 104 that receives the NRZ data stream, an input on line 106d that defines a fourth threshold (V1 '), and N.
Line 1 that provides a signal that identifies when the input of the RZ data stream has a high probability of having a bit value of "1".
It includes a fourth comparator 134 having an output of 08d. This signal is the third bit estimate. Fifth comparator 13
6 is a line 104 for receiving the NRZ data stream
Input, line 106 defining the fifth threshold (V0 ′)
e and an output on line 108e that provides a signal that identifies when the input of the NRZ data stream has a high probability of having a bit value of "0". This signal is another third bit estimate.

A multiple threshold circuit 102 is provided for the NRZ data stream input on line 104 above the fifth threshold (V0 ') on line 106e and below the fourth threshold (V1') on line 106d. When supplying the bit estimation value of 3, the future decision circuit 114 determines that the previous third bit value is “0” when the previous third bit value is “1” and the previous third bit value is “0”. , "1" identifies the NRZ data stream input. NRZ data above the fourth threshold is considered a definite “1” and data below the fifth threshold is considered a definite “0”.

Returning to FIG. 3, in some aspects of system 100, multi-threshold circuit 102 accepts a forward error correction (FEC) encoded NRZ data stream. Next, the system 100 further includes line 12
A forward error correction (FEC) circuit 150 having two inputs is included and receives a first bit value from an acausal circuit 110. The FEC circuit 150 decodes the incoming data stream on line 122 and provides the corrected bit value at the output on line 152. Statistical calculator 154 has an input connected to the output of the FEC circuit on line 152 and provides a threshold on line 106 to multiple threshold circuit 102 in response to FEC correction.

Statistical calculator 154 includes a plurality of 3-bit sequences if each sequence contains a second bit value followed by a first (center) bit value followed by a third bit value. Evaluate the number of errors associated with the combination.
The combination of these sequences has the first error (middle)
Is analyzed when it is a bit value of. Statistical calculator 15
4 adjusts the threshold on line 106 in response to comparing the number of errors between different groups of 3-bit sequences.

For example, the statistical calculator adjusts the threshold value to balance the number of errors between the first group of three bit sequences and the second group of three bit sequences. An example of three bit sequences, and the type of error analysis that can be performed with such an analysis, is described in co-pending patent application “SYSTEM AND METH”.
OD FOR NON-CAUSAL CHANNEL
EQUALIZATION USING ERROR
STATISTIC DRIVEN THRESHO
LDS "is provided in more detail and the application is incorporated herein by reference. Similarly, using such an analysis, a first threshold (V1), a second threshold (V1)
0), and how the third threshold (Vopt) can be adjusted is provided in detail.

In some aspects, the statistical calculator 1
54 compares different groups of three bit sequences if the first (middle) bit value is FEC corrected. In another aspect, the statistical calculator 154 is the first (center)
If the bit value of and the second bit value are FEC corrected, compare different groups of three bit sequences. Alternatively, the statistical calculator 154 compares different groups of three bit sequences when the first (center) bit value and the third bit value are FEC corrected.

Statistical calculator 154 typically provides a fourth threshold (V1 ') on line 106d approximately midway between the first and third thresholds, and a fifth threshold on line 106e (V1'). V0 ') is provided approximately midway between the third and second thresholds. However, the fourth threshold value and the fifth threshold value are set according to a more complicated analysis of the first threshold value, the second threshold value, and the third threshold value, or a third bit value error analysis. Can be done.

FIG. 3 further illustrates an alternative aspect of the system of the present invention when an averaging circuit is used. The system 100 then further includes an averaging circuit 160 having an output connected to the acausal circuit 110 on line 122 and an input on line 104 to receive the NRZ data stream. In the averaging circuit 160, both the second bit value and the third bit value are equal to “1”,
First of tracked NRZ data stream input
NR of line 104 when maintaining the average over a long period of
Track Z data stream input. The averaging circuit 160 has an output on line 106a and provides a first threshold (V1) according to the average of the first long period.

Similarly, in the averaging circuit 160, both the second bit value and the third bit value are equal to "0", and N
Tracking the NRZ data stream input on line 104 while maintaining the second long term average of the RZ data stream input. The averaging circuit 160 sets a second threshold (V0) corresponding to the average of the second long period on the line 10
Supply at 6b. In some aspects, averaging circuit 160 provides a third threshold (Vopt) on line 106c in response to the first and second thresholds. For example, the averaging circuit 160 may provide the third threshold to be approximately midway between the first threshold and the second threshold. Alternatively, the averaging circuit 160 measures the overall average voltage of the NRZ data stream on line 128 and provides a third threshold (Vopt) at the output of line 106c in response to the measured overall average. A first threshold, a second threshold,
And an example of using the above-described averaging technique to adjust the third threshold is given in co-pending patent application “SYSTEM A
ND METHOD FORNON-CAUSAL C
HANEL EQUALIZATION INAN
ASYMMETRIC NOISE ENVIRO
NMENT ", which is incorporated herein by reference.

The averaging circuit operates so that the fourth threshold value (V1 ') of the line 106d is approximately in the middle of the first threshold value and the third threshold value.
And the fifth threshold value (V0 ′) of the line 106e is provided approximately midway between the third threshold value and the second threshold value.

FIG. 5 is a truth table associated with the non-causal circuit 110 of FIG.

FIG. 6 is a schematic diagram showing the acausal circuit 110 of FIG. 3 in more detail. FIG. 6 represents only one of many designs that can be used to implement the present invention.
The future decision circuit 114 includes a signal input connected to the output of the fourth comparator on line 108d, a signal input connected to the output of the fourth comparator on line 108e, a control input on line 172, and a third input. Multiplexer (MUX) 1 with an output on line 116 for supplying the bit value of
Including 70. Flip-flop 174, eg, a D flip-flop, has an input connected to the MUX output on line 116 and an output connected to the MUX control input on line 172.

The current decision circuit 118 uses the lines 108a,
It has inputs connected to the outputs of the first, second and third comparators of the multi-threshold circuit at 108b and 108c, respectively. These three lines are
Corresponds to the threshold shown in FIG. Current decision circuit 118
Passes a third comparator signal on line 108c. The current decision circuit 118 includes an AND circuit 180 and an AND circuit 18.
2 and the OR circuit 184 to perform AND operation and O
Perform R operation. The one clock cycle delay is added using flip-flops 186 and 188.

A slightly different variation of the decision circuit is currently found in co-pending patent application "SYSTEM AND
METHOD FOR NON-CAUSAL CH
"ANNEL EQUALIZATION",
The application is incorporated herein by reference. In this other version, AND gates 180 and 182,
The OR gate 184 and flip-flops 186 and 188 are shown to be in the circuit in the future. In this previous version, the future circuit provides the first bit estimate with the third bit value to the present decision circuit. Similar functionality can now be achieved in the present invention by introducing elements 180-188 in the decision circuit.

Further, AND gates 190, 192, 1
94 and 196, and OR gate 198 are shown. This circuit is based on co-pending patent application "SYSTE
MAND METHOD FOR TEMPORAL
ANALYSIS OFSERIAL DATA, "which is hereby incorporated by reference.

The past decision circuit 116 delays the first bit value on the line 122 by one clock cycle, and
At 8, the 22nd bit value is provided. Further, the D flip-flop 199 is used for delay.

When the first bit estimation value and the second bit determination value and the third bit determination value are both "1", the present determination circuit 112 determines the second bit determination value and the third bit determination value.
Of the first bit decision value and the third bit decision value of the second bit decision value and the third bit decision value of the third bit decision value are both "0"
Supply the bit value of. To achieve these above objectives, particular circuit implementations of AND and OR gates are shown. Alternative circuit designs may achieve similar functionality. More important is the relationship between signal input and signal output.

Functional Description Referring to FIG. 3, in some aspects of the system, the NRZ input signal is buffered (not shown). The NRZ data signal is provided to a plurality of threshold comparators. In some aspects of the system, the timing recovery circuit (recover)
ry circuit) is used at the output of the comparator. The timing recovery circuit generates a clock and sample signal from the received data. The sample signal is
Synchronized to the center of the data bit. Once synchronization is performed, a method of offsetting sample points is provided to compensate for device or channel specific anomalies.

7a, 7b and 7c are flow charts illustrating the method of the present invention for non-causal channel equalization of feedforward / feedback.
This method generally corresponds to FIG. The method (and the method of FIGS. 8 and 9 below) is shown as a sequence of steps numbered for clarity,
The sequence of steps is not inferred from its numbering unless explicitly stated. Some of these steps may be skipped, performed in parallel, or performed without having to maintain the exact order of the sequence.

The method begins at step 700. Step 702 is a non-return to zero data stream.
stream) receives input. In some aspects, the data is pseudo-random binary serial data. Step 704 estimates a first bit of the data stream using the first plurality of thresholds. Step 7
06 uses a second plurality of thresholds to determine a third bit value received consecutively with the first bit. Step 708 compares the estimate of the first bit with the third bit value. Step 710 sets a first bit estimate to a first
Of the second bit value received prior to the second bit.
Step 712 determines the first bit value in response to this comparison.

In some aspects of the method, step 70
Estimating the first bit of the data stream using the first plurality of thresholds at 4 includes using three thresholds. In another aspect, determining the third bit value consecutively received in the first bit using the second plurality of thresholds in step 706 is 2
The step of using one threshold is included. In some aspects, the third bit value is determined in response to the previous third bit decision value.

In some aspects, step 701a.
Defines a first threshold (V1) to identify a first bit estimate that is "1" with a high probability. Step 7
01b defines a second threshold (V0) to identify the first bit estimate that is "0" with high probability. Step 701c includes a first threshold between the first threshold and the second threshold.
Third threshold (Vopt) to identify the bit threshold of
Stipulate. Then, the step of estimating the first bit of the data stream with the first plurality of thresholds in step 704 includes using the first, second and third thresholds.

In some aspects, step 701.
d defines a fourth threshold (V1 ′) to identify the third bit estimate that is “1” with high probability. Step 701e defines a fifth threshold (V0 ′) to identify a third bit estimate that is “0” with high probability. Then, in step 706, the step of determining the third bit value includes using the fourth and fifth threshold values.

In some aspects, determining the first bit value in response to the comparison (step 712) includes substeps. Step 712a processes the NRZ data stream input with the second bit less than the first threshold and greater than the third threshold, if both the second and third bits have a value of "1". Identified as "0", and if only one of the second and third bits has a value of "1", identified as "1" and both the second and third bits are "0". If the value is, the value is identified as "1". Step 712b includes N if the second bit is above the first threshold and below the third threshold.
Identifies the RZ data stream input as a "1" if both the second and third bits have a value of "0" and only one of the second and third bits is a "0". Is identified as “0”, and the second and third values
If both of the bits are "1", they are identified as "0".

In some aspects, step 706.
The step of determining the third bit value of the includes substeps. Step 706a identifies the NRZ data stream input below the fourth threshold and above the fifth threshold as "0" if the previous third bit value was "1". Step 706b processes the NRZ data stream input below the fourth threshold and above the fifth threshold if the previous third bit value is "0",
Identify as "1".

In some aspects of the method, receiving the non-zero-return data stream in step 702 includes receiving non-return-zero data encoded by forward error correction (FEC). The method may then include further steps. Step 714 FEC decodes the first bit value following the first bit decision value. Step 716 uses FEC correction of the first bit value to adjust the threshold. In some aspects, the first, second and third thresholds are adjusted using FEC error statistics that adjust the thresholds.

In step 716, the step of using the FEC error statistics to adjust the threshold comprises estimating the number of errors associated with a combination of multiple 3-bit sequences, where each sequence is a third.
The second (2) bit value following the first (center) bit value subsequent to the first (center) bit value and the error is at the first (center) bit value. In some aspects, estimating the number of errors associated with a combination of multiple 3-bit sequences includes comparing the number of errors between different groups of 3-bit sequences. For example, the FEC error statistics may include a first group of 3-bit sequences and a second group of 3-bit sequences.
Adjust the thresholds to balance the number of errors with the group of. More particularly, the step of estimating the number of errors associated with a combination of a plurality of 3-bit sequences comprises comparing different groups of 3-bit sequences,
Here, the first (center) bit value is FEC corrected. In one aspect, different groups of 3-bit sequences are compared, where the first (center) bit value and the second
The bit value of is corrected by FEC. In another aspect, different groups of 3 bit sequences are compared and the first (center) bit value and the third bit value are FEC corrected.

Alternatively, instead of steps 714 and 716, step 718 tracks the NRZ data stream input if the second bit value is equal to the third bit value. Step 720 maintains a long term average of the tracked NRZ data stream inputs. Step 722 adjusts the first threshold value and the third threshold value according to the long-term average value.

In some aspects, tracking the NRZ data stream input if the second bit value is equal to the third bit value in step 718 includes substeps. Step 718a is
Tracking the NRZ data stream input if both the second and third bits have a value of "1", step 718b determines the second and third bits.
Track the NRZ data stream input if the bit of the has a value of "0".

In some aspects, step 720.
In, maintaining a long term average value of the NRZ data stream input includes substeps. Step 720a creates a first average value of the NRZ data stream input if both the second and third bits have a value of "1". Step 720b creates a second average value of the NRZ data stream input if both the second and third bits have a value of "0".

The step of adjusting the first and second thresholds in response to the long term average value of step 722 may also include substeps. Step 722a adjusts the first threshold value (V1) according to the first average value. Step 722b determines the second threshold value (V) according to the second average value.
Adjust 0).

Step 724 corresponds to the step of adjusting the first threshold value (V1) and the second threshold value (V0).
The third threshold value (Vopt) is adjusted. In some aspects, a first threshold (V1) and a second threshold (V0)
The step of adjusting the third threshold value (Vopt) in accordance with the step of adjusting the value includes the step of setting the third threshold value approximately in the middle between the first threshold value and the second threshold value.

Alternatively, although not shown, step 7
24a measures the overall average value of the NRZ data stream input voltage. Step 724b (not shown) sets a third threshold value according to the measured overall average value.

Step 726 adjusts the fourth threshold to be approximately midway between the first and third thresholds. Step 728 adjusts the fifth threshold to be approximately midway between the third threshold and the second threshold. In another aspect, the fourth threshold value and the fifth threshold value are adjusted according to a more complex analysis of the first, second and third threshold values. Other methods of adjusting the fourth and fifth thresholds may be used so that they include only one of the plurality of errors in the third bit value.

FIG. 8 is a flow chart showing another aspect of the method of the present invention for feedforward / feedback non-causal channel equalization of a communication system. The method begins at step 800. Step 802
Receives a non-return to zero (NRZ) data stream input. Step 804 uses the first plurality of thresholds to
Estimate the first bit of the data stream. Step 806 determines the third bit value received after the first bit in response to the previous third bit decision value. Step 808 compares the first bit estimate with the third bit value. Step 810 compares the first bit estimate with a second bit value received before the first bit. Step 812 determines the first bit value in response to the comparison. In some method aspects, determining the third bit value in Step 806 includes determining the third bit value using a second plurality of thresholds.

FIG. 9 is a flow chart showing another variation of the method of the present invention for feedforward / feedback non-causal channel equalization. The method begins at step 900. Step 902 is
Receive a non-return to zero (NRZ) data stream input. Step 904 estimates a first bit of the data stream using a first plurality of thresholds. Step 906 analyzes the first bit estimate of the sequence of first bits to determine the first bit value.
Step 908 determines the third bit value,
In the sequence of second bits, analyze a third bit estimate received consecutively to the first bit.

In some aspects of the method, in step 904, estimating the first bit of the data stream using the first plurality of thresholds,
Estimating the first bit value according to three thresholds. In some aspects, analyzing the first estimate of the sequence of first bits to determine the first bit value in step 906 is followed by a third bit received next, First received next
Analyzing the sequence of second bits followed by the bits of.

In another aspect, in step 908, analyzing the third bit estimate of the sequence of second bits to determine the third bit value,
Analyzing the sequence by the third bit value before the third bit estimate is followed.

In some aspects, step 907.
Estimates a third bit value using the second plurality of thresholds. The step of estimating the third bit value using the second plurality of threshold values may include the step of estimating the third bit value with respect to the two threshold values.

Some aspects of the method include additional steps. Step 901a includes a first step to identify a first bit estimate that is "1" with high probability.
Threshold value (V1) is defined. Step 901b defines a second threshold (V0) to identify the first bit estimate that is "0" with high probability. Step 901c
Defines a third threshold (Vopt) to identify a first bit estimate between the first threshold and the second threshold. Then, in step 906, analyzing the first bit estimate of the sequence of first bits to determine the first bit value includes substeps (not shown). Step 906a includes determining the first bit if both the second bit and the third bit have a value of "1".
Identifying the NRZ data stream input as a "0" below a threshold of and above a third threshold and only one of the second and third bits has a value of "1" N smaller than the first threshold and larger than the third threshold
Identifies the RZ data stream input as "1",
NRZ data stream inputs that are less than the first threshold and greater than the third threshold are identified as "1" if both the bits of and the third bit have the value "0".
Step 906b identifies an NRZ data stream input greater than a second threshold and less than a third threshold as a "1" if both the second and third bits have a value of "0". , NRZ data stream input greater than a second threshold and less than a third threshold if only one of the second and third bits has a value of “0” as “0” Then, if both the second bit and the third bit have a value of “0”, the NRZ data stream input that is greater than the second threshold and less than the third threshold is identified as “0”.

Step 901 uses a fourth threshold (V) to identify a third bit estimate that is "1" with a high probability.
1 ') is specified. Step 901 includes a fifth step to identify a third bit estimate that is "0" with a high probability.
Threshold value (V0 ′) is defined. Then, step 908
In, the step of analyzing the third bit estimate of the sequence of second bits to determine the third bit value comprises substeps (not shown). Step 90
8a identifies an NRZ data stream input that is less than the fourth threshold and greater than the fifth threshold as "0" if the previous third bit value was "1". Step 9
08b is when the previous third bit value is "0",
An NRZ data stream input that is less than the fourth threshold and greater than the fifth threshold is identified as a "1".

Systems and methods have been provided for adjusting a non-causal NRZ data stream channel. Since intra-symbol variance is a non-causal obstacle, the estimation algorithm becomes more efficient when it is based on iteratively collected data. The degree of iteration affects the performance of the circuit and is chosen based on the execution tradeoffs. It is expected that one of ordinary skill in the art will perform such data collection. An exemplary analysis algorithm using only the previous bit and the next bit is explicitly described,
The invention is obviously applied to the algorithm with one previous bit value or one next bit value. NR
Although only the Z data stream is explicitly discussed, it will be understood by those skilled in the art that the temporal analysis of serial data of the present invention applies to other modulation formats. Further, while the present invention is illustrated using three levels of comparison to make a current bit estimate and two levels of comparison to determine bits in the future, those skilled in the art will appreciate that serial data of the present invention may be used. The time series analysis of
It will be appreciated that other modulation formats can be applied. Further, while the present invention has been illustrated using a three level comparison to create a current bit estimate and a two level comparison to determine future bits, the present invention illustrates which process Is not limited to any particular number of comparison levels. Other embodiments and variations of the invention may be envisioned by one of ordinary skill in the art.

Provided are feedforward / feedback systems and methods for non-causal channel equalization in communication systems. The method includes receiving a non-return-to-zero data (NRZ) data stream input, using three thresholds to define a first bit of the data stream, and using two thresholds to generate a first bit.
Determining a third bit value received after the first bit estimate, comparing the first bit estimate with the third bit value, the first bit estimate and the first bit value Comparing the second bit value received before, and determining the first bit value in response to the comparison. In some aspects of the methods of the invention,
The third bit value is determined according to the previous third bit determination value. The step of determining the third bit value is performed by setting “0” when the previous third bit value is “1” and “1” when the previous third bit value is “0”. Identifying an NRZ data stream input between a fourth threshold and a fifth threshold.

[0132]

As described above, it is possible to present a method for reducing the influence of the pulse spreading on the difficult decision error rate in a communication system which is affected by the temporary spreading of the communication waveform.

[Brief description of drawings]

FIG. 1 shows binary symmetry in the presence of noise,
FIG. 3 shows a signal recovered from a non-dispersive channel (prior art).

FIG. 2 is a diagram illustrating a received waveform that is distorted in response to intersymbol interference resulting from energy dispersion (prior art).

FIG. 3 is a schematic block diagram of a feedforward / feedback acausal channel equalization communication system of the present invention.

FIG. 4 is a detailed diagram of the multi-threshold determination circuit of FIG.

FIG. 5 is a truth table for the non-causal circuit of FIG.

FIG. 6 is a schematic diagram showing the non-causal circuit of FIG. 3 in more detail.

FIG. 7a is a flow chart illustrating the inventive method for feedforward / feedback acausal channel equalization.

FIG. 7b is a flow chart illustrating the method of the present invention for feedforward / feedback acausal channel equalization.

FIG. 7c is a flow chart showing the method of the present invention for feedforward / feedback acausal channel equalization.

FIG. 8 is a flow chart illustrating another aspect of the inventive method for feedforward / feedback acausal channel equalization in a communication system.

FIG. 9 is a flow chart showing another variation of the inventive method for feedforward / feedback acausal channel equalization.

[Explanation of symbols]

100 system 102 decision circuit 110 Non-causal circuit 114 Future decision circuit 118 current decision circuit 124 Past decision circuit

   ─────────────────────────────────────────────────── ─── Continued front page    (31) Priority claim number 10 / 077,274 (32) Priority date February 15, 2002 (February 15, 2002) (33) Priority claiming countries United States (US) (31) Priority claim number 10/150, 301 (32) Priority date May 17, 2002 (May 17, 2002) (33) Priority claiming countries United States (US) (31) Priority claim number 10 / 193,961 (32) Priority date July 12, 2002 (July 12, 2002) (33) Priority claiming countries United States (US) (31) Priority claim number 10 / 262,334 (32) Priority date October 1, 2002 (October 2002) (33) Priority claiming countries United States (US) (72) Inventor Keith Michael Conroy             United States New Hampshire             03079, Salem, Coventry Leh             N 7 (72) Inventor Daniel M. Castag notch             United States Massachusetts             02420, Lexington, Demarlow             Do 26 F-term (reference) 5K014 AA01 BA05 EA08 FA11                 5K029 AA01 BB03 CC01 DD02 DD22                       FF01 HH08                 5K046 EE06 EE10 EE32 EE47 EE49                       EF55

Claims (56)

[Claims] 1. A method for equalizing a feedforward / feedback non-causal channel in a communication system, the method comprising: receiving a non-return to zero (NRZ) data stream input; and using a first plurality of thresholds. The first of the data stream
, Estimating a third bit value received subsequent to the first bit using a second plurality of thresholds, and determining the first bit estimate by the second plurality of threshold values. Comparing the first bit estimate with a second bit value received prior to the first bit; and, in response to the comparison, comparing the first bit estimate with the first bit estimate. Determining a bit value. 2. The step of estimating a first bit of the data stream using the first plurality of thresholds comprises:
The method of claim 1 including the step of using a third threshold. 3. The step of using the second plurality of threshold values to determine a third bit value received subsequent to the first bit includes using two threshold values. The method described in. 4. The method of claim 1, wherein determining the third bit value comprises determining the third bit value in response to determining the previous third bit value. 5. A step of defining a first threshold value (V1) so as to identify a first bit estimation value which is a high probability "1", and a first bit estimation which is a high probability "0". Defining a second threshold (V0) to identify a value, and a third threshold (Vopt) to identify a first bit estimate between the first and second thresholds. ) Is defined, the step of estimating the first bit of the data stream using the first plurality of thresholds comprises the first threshold, the second threshold, the third threshold. The method of claim 4, further comprising using a threshold of 6. A step of defining a fourth threshold value (V1 ′) to identify a third bit estimate that is “1” with high probability, and a third bit that is “0” with high probability. Further defining a fifth threshold value (V0 ') to identify the estimate, the step of determining the third bit value uses the fourth threshold value and the fifth threshold value. The method of claim 5 including the steps. 7. The step of determining the first bit value according to the comparison is performed by setting the second bit and the third bit to be “0” when the second bit and the third bit both have a value of “1”. If only one of the bit and the third bit has a value of "1", then as "1", and if both the second bit and the third bit have a value of "0", then as "1", Identifying an NRZ data stream input below the first threshold and above the third threshold; and if the second bit and the third bit both have a value of "0", "1". As "," if only one of the second bit and the third bit has a value of "0",
And the second bit and the third bit are both "1"
7. The method of claim 6, comprising identifying an NRZ data stream input below the second threshold and above the third threshold as "0" if the value of is 0. 8. The step of determining the third bit value is below the fourth threshold value when the previous third bit value is “1”, which is “0”, and which is below the fifth threshold value. Identifying the NRZ data stream input above a threshold of, and, if the previous third bit value was "0", "1", below the fourth threshold and above the fifth threshold. Further identifying the NRZ data stream input. 9. The method of receiving a non-return to zero data stream comprises receiving a forward error correction (FEC) encoded non-return to zero data stream, the method comprising: 9. The method according to claim 8, further comprising: FEC-compositing the first bit value according to the determination of the bit value of, and adjusting the threshold value using FEC correction of the first bit value. the method of. 10. The step of using the FEC correction of the first bit value to adjust the first threshold, the second threshold, and the third threshold comprises FEC error to adjust the threshold. 10. The method of claim 9 including the step of using the statistic of. 11. The step of using FEC error statistics to adjust said threshold comprises the step of evaluating the number of errors associated with a combination of a plurality of 3-bit sequences, each sequence comprising said second bit. 11. The method of claim 10, comprising a value followed by the first (center) bit value, followed by a third bit value, the error being in the first (center) bit value. 12. The method of claim 11, wherein assessing the number of errors associated with the combination of the plurality of 3-bit sequences comprises comparing the number of errors between different groups of 3-bit sequences. . 13. The step of using FEC error statistics to adjust the threshold value balances the number of errors between the first group of 3-bit sequences and the second group of 3-bit sequences. 13. The method of claim 12 including the step of adjusting the threshold. 14. The step of evaluating the number of errors associated with a combination of the plurality of 3-bit sequences includes comparing groups of different 3-bit sequences,
The first (center) bit value is FEC corrected,
The method according to claim 12. 15. The step of evaluating the number of errors associated with the combination of the plurality of 3-bit sequences includes comparing groups of different 3-bit sequences,
13. The method of claim 12, wherein the first (center) bit value and the second bit value are FEC corrected. 16. The step of evaluating the number of errors associated with the combination of the plurality of 3-bit sequences comprises comparing groups of different 3-bit sequences,
13. The method of claim 12, wherein the first (center) bit value and the third bit value are FEC corrected. 17. Tracking the NRZ data stream input when the second bit value is equal to the third bit value, and maintaining an average value of the tracked NRZ data stream inputs for a long period of time. 9. The method of claim 8, further comprising: adjusting the first threshold and the second threshold in response to the long-term average value. 18. The step of tracking the NRZ data stream input when the second bit value is equal to the third bit value, wherein the second bit value and the third bit value are both "1". Tracking the NRZ data stream input when the second bit value and the third bit value both have a value of "0". And a step comprising:
7. The method according to 7. 19. Maintaining the average value of said NRZ data stream input for a long period of time, said NRZ data stream input when said second bit value and said third bit value both have a value of "1". Generating a first average value of, and the second bit value and the third bit value are both "0".
Generating a second average value of the NRZ data stream input when having a value of 1.
The method according to 8. 20. The step of adjusting the first threshold value and the second threshold value according to the average value of the long period adjusts the first threshold value (V1) according to the first average value. 20. The method according to claim 19, comprising the steps of: and adjusting the second threshold value (V0) according to the second average value. 21. The third threshold value according to the step of adjusting the first threshold value (V1) and the second threshold value (V0).
Further comprising adjusting a threshold (Vopt) of
21. The method of claim 20. 22. The third threshold value according to the step of adjusting the first threshold value (V1) and the second threshold value (V0).
22. The method of claim 21, wherein adjusting the threshold value (Vopt) of comprises the step of setting the third threshold value approximately midway between the first threshold value and the second threshold value. 23. The method of claim 17, further comprising measuring an overall average NRZ data stream input voltage and setting the third threshold in response to the measured overall average. The method described. 24. Adjusting the fourth threshold so as to be substantially in the middle of the first threshold and the third threshold, and being substantially in the middle of the third threshold and the second threshold. Adjusting the fifth threshold so that the method further comprises: 25. A method for equalizing non-causal channels of feedforward / feedback in a communication system, the method comprising: receiving a non-return-to-zero (NRZ) data stream input; Of the first of the data streams using a plurality of thresholds of
Estimating the third bit value received subsequent to the first bit value in response to the previous third bit value determination, the first bit estimate value With the third bit value, comparing the first bit estimate with a second bit value received prior to the first bit value, and, in response to the comparison, Determining the first bit value. 26. The method of claim 25, wherein determining the third bit value includes determining the third bit value using a second plurality of thresholds. 27. A method for equalizing a feedforward / feedback non-causal channel in a communication system, the method receiving a non-return to zero (NRZ) data stream input. Of the first of the data streams using a plurality of thresholds of
Estimating the first bit value of the first bit sequence to determine the first bit value, and second determining the third bit value to determine the third bit value. Of the third bit received subsequent to the first bit value of
Analyzing the bit estimate of the. 28. Estimating a first bit of the data stream using a first plurality of thresholds comprises three steps.
28. The method of claim 27, comprising estimating the first bit value for one threshold value. 29. Analyzing the first bit estimate of the first sequence of bits to determine the first bit value is subsequently received subsequent to the second sequence of bits. 28. The method of claim 27, comprising analyzing the first bit followed by the third bit received subsequently. 30. Analyzing the third bit estimate of a second sequence of bits to determine the third bit value comprises the step of analyzing the third sequence of bit values prior to the third sequence of bit values. 28. The method of claim 27, comprising analyzing a 3 bit estimate. 31. The method of claim 27, further comprising estimating a third bit value with a second plurality of thresholds. 32. Estimating a third bit value using the second plurality of thresholds comprises estimating the third bit value for two thresholds.
The method described in. 33. Defining a first threshold value (V1) so as to identify a first bit estimate that is "1" with a high probability, and a first bit estimate that is "0" with a high probability. Defining a second threshold value (V0) to identify a value, and a third threshold value to identify a first bit estimate between the first threshold value and the second threshold value (V0). Vopt) is defined, and the step of analyzing the first bit estimate of the first bit sequence to identify the first bit value comprises: When both the third bit values are "1", the value is "0", and when only one of the second bit value and the third bit value is "1", the value is "1". , And the second bit value and the third bit value are both “ "1" for the value of ".", Identifying an NRZ data stream input below the first threshold and above the third threshold, the second bit value and the third bit value. Both bit values are "0"
Is “1”, the second bit value and the third bit value are “0”, and the second bit value is “0”. Identifying the NRZ data stream input as being "0" if the third bit values are both "1", above the second threshold and below the third threshold. 28. The method of claim 27, wherein 34. Defining a fourth threshold value (V1 ′) to identify a third bit estimate that is “1” with a high probability, and a third bit that is “0” with a high probability. Defining a fifth threshold value (V0 ′) to identify an estimate, and analyzing a third bit estimate of a second bit sequence to determine the third bit value. Identifying the NRZ data stream input below the fourth threshold and above the fifth threshold as "0" if the previous third bit value was "1". And identifying the NRZ data stream input below the fourth threshold and above the fifth threshold as "1" if the previous third bit value was "0". 34. The method of claim 33, including. 35. A feedforward / feedback non-causal channel equalization communication system, the system comprising: an input for receiving a non-return to zero (NRZ) data stream; an input for receiving a threshold; And a multi-threshold circuit having an output for providing a first bit estimate in response to a first plurality of voltage threshold levels, and a non-causal having an input for receiving the bit estimate from the multi-threshold circuit. A circuit for determining a first bit estimate, a third bit value received after the first bit value and determined in response to a previously determined third bit value, and the first bit value. An acausal circuit having an output for providing a first bit value in response to comparing the previously received second bit value with the second bit value. 36. The multi-threshold circuit provides a third bit estimate in response to a second plurality of voltage threshold levels and the acausal circuit receives the third bit estimate. A future decision circuit having an input connected to the output of the multi-threshold circuit and an output for providing a third bit value in response to a previous third bit value decision; A current decision circuit having inputs for receiving the first bit estimate, the third bit value from the future decision circuit, and a second bit value,
A current decision circuit having an output for providing the first bit value determined in response to comparing the first bit value with the second bit value and the third bit value. 36. The system of claim 35, including a past decision circuit having an input for receiving the first bit value and an output for providing the second bit value. 37. The multi-threshold circuit comprises an input for accepting the NRZ data stream, an input defining a first threshold (V1), and a bit with a high probability that the NRZ data stream input is "1". A first comparator having an output for providing a signal for identifying when to have an estimate, an input for receiving the NRZ data stream, a second
A second comparator having an input defining a threshold (V0) of NRZ and an output for providing a signal that identifies when the NRZ data stream input has a bit estimate that is "0" with a high probability. An input for receiving the NRZ data stream, third
Comparator having an input that defines a threshold value (Vopt) of and an output to provide a signal when the NRZ data stream input has bit estimates of "0" and "1" with approximately equal probability. 37. The system of claim 36, including and. 38. The multi-threshold circuit provides a bit estimate for an NRZ data stream input below the third threshold and above the second threshold, and the current decision circuit accordingly. , When the second bit value and the third bit value are both “0”, the first bit value of “1” and the second bit value and the third bit value When only one of them has a value of "0", the first bit value of "0" and the second bit value and the third bit value are both "1".
38. The system of claim 37, wherein the first bit value of "0" is provided. 39. The multi-threshold circuit provides a bit estimate for an NRZ data stream input above the third threshold and below the first threshold, the current decision circuit Accordingly, when the second bit value and the third bit value are both "1", the first bit value of "0", the second bit value and the third bit When only one of the values has a value of "1", the first bit value of "1" and the second bit value and the third bit value are both "0".
39. The system of claim 38, wherein the system supplies a first bit value of "1" if the value of the. 40. The multi-threshold circuit is "1" with a high probability that the input for accepting the NRZ data stream, the input defining a fourth threshold (V1 '), and the NRZ data stream input. A fourth comparator having an output for providing a signal identifying when to have a bit value, an input for receiving the NRZ data stream, a fifth
A fifth comparator having an input defining a threshold value (V0 ′) and an output for providing a signal that identifies when the NRZ data stream input has a bit value that is likely to be “0”. 40. The system of claim 39, including. 41. The multi-threshold circuit provides a third bit estimate to the NRZ data stream input above the fifth threshold and below the fourth threshold, said future decision circuit. Indicates that the previous third bit value is “1”
41. The system of claim 40, which identifies the NRZ data stream input as "0" if it was, and "1" if the previous third bit value was "0". 42. The multi-threshold circuit is a system for receiving a forward error correction (FEC) encrypted NRZ data stream for receiving the first bit value from the acausal circuit. A forward error correction (FEC) circuit having an input of, which decodes an incoming data stream to provide a corrected bit value at the output, and a circuit for decoding the incoming data stream in response to the FEC correction. 42. The system of claim 41, further comprising a statistical calculator having an input connected to an output of the FEC circuit for providing a threshold to a multi-threshold circuit. 43. The statistical calculator is a plurality if the respective sequences include the second bit value, followed by the first (center) bit value, and then the third bit value. 43. The system of claim 42, wherein estimating the number of errors associated with a combination of three 3-bit sequences, the error being at the first (center) bit value. 44. The system of claim 43, wherein the statistical calculator adjusts the threshold in response to comparing the number of errors between groups of different 3-bit sequences. 45. The statistical calculator adjusts the threshold to balance the number of errors between the first group of 3-bit sequences and the second group of 3-bit sequences. 44. The system according to 44. 46. The system of claim 43, wherein the statistical calculator compares different groups of 3-bit sequences when the first (middle) bit value is FEC corrected. 47. The method of claim 43, wherein the statistical calculator compares different groups of 3-bit sequences when the first (center) bit value and the second bit value are FEC corrected. System. 48. The statistical arithmetic unit compares different groups of 3-bit sequences when the first (central) bit value and the third bit value are FEC-corrected. System. 49. The statistical calculator supplies the fourth threshold value approximately at the middle of the first threshold value and the third threshold value, and substantially at the middle of the third threshold value and the second threshold value. 43. The system of claim 42, wherein the fifth threshold is supplied to the. 50. An averaging circuit having an input connected to an output of the acausal circuit and an input for receiving the NRZ data stream, the averaging circuit comprising the second bit value. And the third bit value are both equal to "1", track the NRZ data stream input, and track the tracked N
Maintaining a first long-term average of the RZ data stream input, the averaging circuit having an output for providing the first threshold (V1) in response to the first long-term average. 42. The system of claim 41, further comprising a digitization circuit. 51. The averaging circuit tracks the NRZ data stream input when the second bit value and the third bit value are both equal to "0" and outputs a second of the NRZ data stream inputs. 51. The system according to claim 50, which maintains an average over a long period of time and provides the second threshold value (V0) in response to the second long period of time. 52. The averaging circuit according to the first threshold value and the second threshold value, the third threshold value (Vop).
52. The system of claim 51, which supplies t). 53. The system of claim 52, wherein the averaging circuit provides the third threshold approximately midway between the first threshold and the second threshold. 54. The averaging circuit measures an overall average voltage of the NRZ data stream, and the third threshold (V) at the output in response to the measured overall average.
51. The system of claim 50, which supplies opt). 55. The averaging circuit supplies the fourth threshold value approximately in the middle of the first threshold value and the third threshold value, and in the substantially middle point of the third threshold value and the second threshold value. 51. The system of claim 50, which provides the fifth threshold. 56. The future decision circuit includes a signal input connected to an output of the fourth comparator, a signal input connected to an output of the fifth comparator, a control input, and the third bit. 42. The system of claim 41, comprising a multiplexer (MUX) having an output for providing a value, and a flip-flop having an input connected to the MUX output and an output connected to the MUX control input.