JP2003216683A - Function verification unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a function verification generation unit capable of preparing the function verification description to verify function verification items of a circuit to be verified even when a person in charge of verification does not learn HDL or a verification description language other than HDL, a designer who has learned HDL does not learn the verification description language other than HDL, or the function verification description itself described in HDL is not verified, and a description method in which a designer or a person in charge of verification clearly and uniformly describes the verification content of the circuit operation by using a timing diagram. <P>SOLUTION: The function verification description generation unit having a means to input the logical relationship between wave profiles and the generation information of the logical relationship in the timing diameter and a means to generate the verification description from the timing diagram based on the logical relationship between the wave profiles and the generation information of the logical relationship comprises a terminal information extracting unit 1, a timing diagram editing unit 2, a verified operation extracting unit 3, and a verification description generation unit 4. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function verification device, and more particularly to general digital circuits such as a CPU (central processing unit) and a DSP (digital signal processing device) described in a hardware function description language format. The present invention relates to a technique effective when applied to a function verification description generation device in function verification.

[0002]

2. Description of the Related Art According to a study made by the present inventor, regarding a function verification device, for example, Japanese Patent Laid-Open No. 6-33297 is disclosed.
The technique described in Japanese Patent Publication No. 1 is cited. The above-mentioned Japanese Patent Laid-Open No. 6-332971 discloses a functional model in HDL (Hardware Function Description Language) format from terminal information, an input / output signal waveform of this terminal, and a timing diagram with timing constraint information of this input / output signal waveform. There is disclosed a functional model generation device having HDL generation means for generating.

[0003]

By the way, the functional model generating apparatus disclosed in Japanese Patent Laid-Open No. 6-332971 does not provide means for clearly describing verification items on a timing diagram, which is further clarified. The functional verification description for verifying the functional verification items is not generated. In particular, description generation using a verification description language other than HDL is not performed.

Further, as a result of the examination by the present inventor of the above-mentioned function verification device, the following facts have become clear.

For example, regarding a circuit element composed of a logic circuit, in recent years, with the advent of a high-performance functional simulator for inputting HDL, a design style of performing functional design of hardware by HDL has been established. In addition, in recent years, with the increase in the scale of logic circuits to be verified, a model using a verification description language based on temporal logic or time interval logic for efficiently performing functional verification using a functional simulator has been developed. Comprehensive functional verification technology using inspection methods has also become established. Especially in functional verification of logic circuits, designers and verifiers use timing diagrams to clarify the verification contents of circuit operation, but to verify the verification target logic circuit directly from the created timing diagram. However, the function verification description in HDL or a verification description language other than HDL needs to be prepared manually.

However, in order to create a functional verification description, for example, a verifier must be able to describe HDL or a function description language other than HDL. Therefore, the verifier uses HDL or a verification description language other than HDL. There is a problem that the person in charge of verification has to learn and the burden is heavy on the person in charge of verification. Further, even when a designer who has learned HDL creates a function verification description in HDL, the function verification description itself described in HDL must be verified, and the function verification is performed in a larger-scale logic circuit. Since there are many items, there is also a problem that a designer who has already learned HDL has a heavy burden.

Therefore, the present invention has been made to solve such a problem, and a person in charge of verification newly adds HDL.
HDL without learning verification description languages other than
Even if a designer who has already learned the verification learning language other than HDL does not perform the verification of the functional verification description itself described in HDL, the functional verification description for verifying the functional verification items of the circuit to be verified is provided. It is an object to provide a functional verification description generation device that can be created.

In addition, when the designer and the person in charge of verification clarify the verification contents of the circuit operation using the timing diagram, there is no means for clearly describing the verification item on the timing diagram, and the verification item is not provided. There is a problem in that the means for expressing is unclear, accurate information cannot be exchanged between the designer and the person in charge of verification, and verification efficiency is reduced due to human error.

Therefore, the present invention has been made in order to solve such a problem, and the designer and the person in charge of verification clearly and uniformly describe the verification contents of the circuit operation using the timing diagram. It is also intended to provide law.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the functional verification device according to the present invention is
A timing diagram of a verification description based on the logical relationship between the waveforms and the means for inputting the occurrence information of the logical relationship to the timing diagram, the logical relationship between the waveforms, and the occurrence information of the logical relationship. Means to generate from
It is characterized by having. In particular, at the time of creating a timing diagram, it is possible to describe by inserting objects prepared in advance, and automatically generate the behavior specification checker HDL description used for functional verification from the created data and the property language description used in the model checking method, It is possible to check the internal operation and whether the external input signal is observing the signal transition that should be satisfied.

Specifically, the function verification device according to the present invention is
The design data in the HDL format to be verified is read, and at least the terminal name, the internal pin name, the type of input / output, and the input / output signal and the internal regarding the terminals and internal pins included in the read design data in the HDL format to be verified A terminal information extracting unit for acquiring each terminal and internal pin information having the number of bits of the pin name, and each terminal and internal pin information connected to the terminal information extracting unit and acquired by the terminal information extracting unit, and selecting the terminal. For signals input and output via the and internal pins, timing constraint information regarding timing including this signal and a waveform, a logical relationship between the waveforms, and whether the logical relationship is always established or is established at least once. By inputting the occurrence information, the timing diagram in the design data of the HDL to be verified is edited. Connected to the timing diagram editing means and from the timing diagram editing means, the terminals and internal pin information, the timing constraint information, the logical relationship information between the waveforms, and the occurrence of the logical relationship. Verification target motion extraction means for extracting verification target motion information consisting of information, and whether the verification target motion expressed in a verification description language based on the verification target motion information is satisfied. And a verification description generation means for generating a function verification description for the purpose of verifying and the function verification description for the purpose of verifying whether the verification target operation in the HDL format is satisfied.

With this configuration, the designer and the person in charge of verification select the terminal and internal pin information obtained from the description of the HDL on the timing diagram editing means that is relatively operable to be verified, and the timing diagram is displayed. On the editing means, the signal waveform of the terminal or internal pin after this selection,
The timing diagram is created and edited on the timing diagram editing means while inputting the logical relationship between the waveforms and the occurrence information indicating whether the logical relationship is always established or is established at least once. Therefore, the timing diagram editing means acts so that the verification items can be clearly described on the timing diagram, and thus acts to eliminate the ambiguity of the expression of the verification items. Therefore, it works so that accurate information can be exchanged between the designer and the person in charge of verification, and works to eliminate human error.

Further, the verification target operation extracting means uses the timing diagram editing means, and uses the timing diagram information sent from the timing diagram editing means edited by the designer or the person in charge of verification to determine the logical relationship between the waveforms. The terminal and internal pin information including the waveform in which this logical relationship is designated, and the occurrence information of whether this logical relationship is always established or at least once is extracted, and the verification description generation means is the verification target. Occurrence of the logical relationship of the waveforms supplied from the operation extracting means, the terminal and internal pin information including the waveform in which the logical relationship is designated, and whether the logical relationship is always established or is established at least once. A function verification description is automatically generated based on information. Therefore, even if the designer or the person in charge of verification does not know the HDL or the verification description language other than HDL, the verification description generation means edits the timing diagram using the timing diagram editing means to clarify the verification contents of the circuit operation. The functional verification description is generated by performing the operation that the designer and the person in charge of verification, which is to implement the function, has been performed conventionally. Therefore, the verification description generation means, etc. acts to reduce the function verification work load on the designer and the person in charge of verification, reduces the design cost by improving the function verification efficiency, and further reduces the product production cost. To work.

The technique of the present invention and the above-mentioned Japanese Patent Laid-Open No. 6-3
When compared with the technology of Japanese Patent No. 32971, there are the following differences. The technology disclosed in Japanese Patent Laid-Open No. 6-332971 is a functional block in which no design description exists due to HDL, but some HDL description is required for verification by simulation.
This is a technique for generating an L behavior model description, and the technique of the present invention is a technique for generating an HDL description for verifying the design data in which a design description in HDL exists. It can be said that the difference appears in the difference in the input data. That is, the technique disclosed in Japanese Patent Laid-Open No. 6-332971 starts with a means for editing a timing diagram, whereas the technique according to the present invention starts with a means for reading design data.

In the following, the difference between the two technologies is shown in FIG.
A brief description will be given with reference to FIG. For example, if you create an HDL description of a memory interface and try to verify it, you need to describe the memory in HDL.
According to the technology of the publication (FIG. 65), an HDL that describes an operation model of a memory can be generated from a timing diagram. However, to verify whether the memory access operation is correct, it is necessary to visually check the operation with a waveform viewer supported by the simulator, or to write an HDL checker for verifying whether the operation is correct.

On the other hand, when the technique of the present invention (FIG. 66) is applied, not only the operation model of the memory becomes unnecessary, but also H for verifying whether the operation is performed correctly.
Since the DL description can be automatically generated, confirmation of whether the operation is performed correctly is automated. Further, in the above example, although both the input and the output are viewed, it is also possible to generate a description that checks only the input and only the output.
For example, it can be used for the purpose of verifying whether the logic circuit HDL in the preceding stage is sending a correct output signal to the verification target HDL, and the latter is for verifying whether the verification target HDL outputs a correct output signal sequence. Can be used.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, the same members are designated by the same reference numerals, and the repeated description thereof will be omitted.

In the embodiment of the present invention, Configuration of functional verification description generation device, 2. Object description,
3. 3. Structure of the motion tree to be verified and its modification, 4. TDO2V
erilog Algorithm5. TDO2CT
The description will be made in the order of L Algorithm.

1. Configuration of Function Verification Description Generation Device An example of the configuration of the function verification description generation device according to the embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a functional verification description generation device according to the present embodiment.

The functional verification description generation device according to the present embodiment is
When roughly classified, the terminal information extracting device 1 which is the terminal information extracting device, the timing diagram editing device 2 which is the timing diagram editing device, the verification target operation extracting device 3 which is the verification target operation extracting device, and the verification description creating device. It is composed of a certain verification description generation device 4, etc., and the verification description generated by the verification description generation device 4 is stored in the verification description file 5.

The terminal information extracting device 1 includes an HDL reading device 11, an HDL storage device 12 connected to an output side of the HDL reading device 11, a terminal information extracting device 13 connected to an output side of the HDL storage device 12, A terminal information storage device 1 connected to the output side of the terminal information extraction device 13
It is composed of 4. This terminal information extraction device 1 reads design data in the HDL format to be verified, and at least the terminal name, internal pin name, and input / output of the terminals and internal pins included in the read design data in the HDL format to be verified. It is a terminal information extracting means for acquiring the input / output signal, each terminal of the number of bits of the internal pin name, and the internal pin information.

The timing diagram editing device 2 is connected to the terminal information extraction device 1, that is, the output side of the terminal information storage device 14. The timing diagram editing device 2 selects the terminal and internal pin information acquired by the terminal information extracting device 1 and, regarding a signal input / output via the terminal and the internal pin, includes a timing related to the timing including the signal and the waveform. The constraint diagram, the logical relationship between these waveforms, and the occurrence information as to whether this logical relationship is always satisfied or at least once is input to edit the timing diagram in the design data of the HDL to be verified. It is a timing diagram editing means.

The verification target operation extraction device 3 includes a timing diagram storage device 31 connected to the output side of the timing diagram editing device 2 and a verification target operation information extraction device 32 connected to the output side of the timing diagram storage device 31. The verification target motion information extraction device 32
Of the verification target operation information storage device 33 connected to the output side of. The verification target operation extraction device 3 receives information on each terminal and internal pin, timing constraint information, logical relationship information between waveforms from the timing diagram editing device 2,
And verification target motion extraction means for extracting verification target motion information consisting of occurrence information of a logical relationship.

The verification description generation device 4 includes the verification target action extraction device 3, that is, the verification target action information storage device 3.
3 is connected to the output side. This verification description generation device 4
Functional verification for the purpose of verifying whether the verification target operation expressed in the verification description language based on the verification target operation information is satisfied or functional verification for the purpose of verifying whether the verification target operation in HDL format is satisfied. It is a verification description generation means for generating a description.

2. Description of Object An example of an object in the function verification description generation device according to the present exemplary embodiment will be described with reference to FIGS. 2 to 5. FIG. 2 is an explanatory diagram of a circuit example for explaining a compare object,
3 is an explanatory diagram of an example of a timing diagram for explaining a compare object, FIG. 4 is an explanatory diagram of an example of a timing diagram for explaining a weight object, and FIG. 5 is an explanatory diagram of an example of a check box for explaining a weight object. Is.

Signal objects (signal obj) are used for the purpose of explicitly describing the operation contents and signal transitions to be verified in the timing diagram.
ect), compare object (compare o
object), a weight object (wait ob)
object), relation object (relati)
4 types of objects (on object) are introduced.

2-1. Signal object (sign
al object) rela of the signal waveform drawn on the timing diagram
The value at the start point or the end point of the action object and the number of cycles on the timing diagram are shown. In particular, the value can take a signal value and a signal change. In addition, a signal change is a change from a specific signal value to a specific signal value, a change from a specific signal value, a change to a specific signal value, and a change in a signal value although it is not a division given a specific signal value. , Either of them can be expressed. Further, by specifying exi, for example, "a signal changes in a specified cycle at least once" or "a signal value reaches a certain value in a specified cycle occurs at least once". Can be expressed.

2-2. Compare object (comp
are object) By setting on the signal waveform drawn in the timing diagram, it is possible to describe a comparison operation such as signal value comparison with respect to the set signal value. In particular, when performing comparison, arithmetic logic operations such as bit cutout, shift, increment, and decrement can be described on the left side that consist of only signals for which compare object is designated. Also, on the right side, an arbitrary signal drawn in the timing diagram, signal: c given in the form of n
It is possible to describe a signal representing a signal value n cycles before the cycle in which the ompare object is designated, and an arithmetic logic operation expression formed by cutting out those bits.
As the comparison operation, any one of <, ≤, ==, ≠, ≥,> can be described. Furthermore, by specifying exi,
“At least 1 means that the comparison operation set in compare object is satisfied in the specified cycle.
“Times occur” can be expressed.

For example, in the circuit example shown in FIG. 2, in a multi-cycle adder (latency = 3 cycles), CLK, Valid, A [7: 0], B [7: 0].
In this case, D [8: 0] is output in response to the input of. The function is input data A [7: 0] at the rising edge of Valid.
And B [7: 0] are fetched and the addition result is output after three cycles. Verify that the addition is done correctly.

In the multi-cycle adder of FIG. 2, an example of a timing diagram is, for example, as shown in FIG. 3, rel_H of a relation object.
Compare obj at start point α and end point β of 1
The ect compare (D == A: 3 + B: 3) is shown.

2-3. Weight object (wait
object) It can be specified for the rising edge of the clock signal drawn in the timing diagram, and the signal value of the previous cycle can be repeatedly executed until a certain condition (hereinafter, wait release condition) is satisfied. Represent
In particular, as the wait release condition, it is possible to specify an arbitrary signal on the timing diagram and an arithmetic logic operation expression formed by cutting out the bit. In addition, a signal name to be checked can be designated in repeated execution. In particular, unless a signal to be checked by repeated execution is designated, "sometime the wait cancellation condition is satisfied" is displayed. Furthermore, by specifying exi, "sometime the wait cancellation condition is met occurs at least once."
It can be expressed as "or at least one time the wait cancellation condition is met and the designated signal repeatedly takes the same value until then".

For example, a plurality of wait objects
In some cases, only the order between objects can be specified and the cycle difference cannot be specified. In order to deal with this, special specifications as shown in FIG. 4 are provided. In this timing diagram example, after waiting ((B == C) & B &! E) is established one cycle after the rising edge of A, at least 0 cycles have elapsed, and then wait ((B ==
C) &&! E) is established, and after at least 0 cycle, wa
It means that it (A == 1) holds. It is also shown that D changes from 0 to 1 one cycle after the establishment of wait (A == 1).

Further, in the example of the check box, as shown in FIG. 5, for the boxes of repeating the signal names A to E and the Wait release, the check is checked, the check is not checked, and the default is non-checked. Check. However, when the signal value is Don't care, it is checked by default and cannot be changed by the user.

2-4. Relation object (re
relation object) represents a logical relationship between signal waveforms depicted in a timing diagram. That is, it is for expressing that a certain signal takes a certain value in a certain cycle, and a certain signal takes a certain value in a certain cycle. It is the role of the relation object to express-> in the proposition A-> B, where-> is "if". In addition,
It is possible to take all objects as the start and end points of the relation object. If the end points match, the relation object
It is possible to specify a logical operation between cts, for example (A-
> B) Δ (C-> B), it is interpreted as AΔC-> B. In particular, Δ represents any one of logical AND, logical OR, and logical EOR. Furthermore, (A->B)-> C is A->
(B-> C) = A &B-> C, and in general, a propositional expression configured in series by n relation objects is A1->A2-> ... An->, regardless of how parentheses are attached. An + 1 is interpreted as equation (1) and its meaning is given below.

A1 & A2 & ... &An-> An + 1 Especially, A1-> A2, A2-> A3 and relation
When object is designated, it is interpreted as if the proposition A1-> A2 A2-> A3 is drawn individually. That is, in order to obtain the proposition shown in equation (1), it is necessary to
It is necessary to draw on object as the start point or the end point. For example, A1-> A2, (relation connecting A1 and A2
object)-> A3, it becomes (A1->A2)-> A3, which is interpreted as A1 &A2-> A3. Further, when it is drawn as A2-> A3, A1-> (relation object connecting A2 and A3), it is interpreted as A1->(A2-> A3) = A1 &A2-> A3.

Further, exi is specified by relatio.
It is valid only when it is specified in the part corresponding to-> of the proposition composed of no objects, and is ignored otherwise, and when the specification is valid, "the proposition holds true at least once". Is interpreted as

3. Configuration of verification target operation tree and its modification An example of the configuration of the verification target operation tree and its modification will be described with reference to FIGS. 6 to 27. 6 is a flow diagram showing the structure of the operation tree to be verified and its modification, FIG. 7 is an explanatory diagram showing a hierarchical tree in storing HDL terminal information, and FIG. 8 is an explanatory diagram showing terminal information associated with the hierarchical tree of FIG. FIGS. 9 to 19 are explanatory diagrams showing an example of a timing diagram in storing a timing diagram, FIG. 20 is an explanatory diagram showing an example of dividing a timing diagram, and FIGS. 21 and 22 are explanatory diagrams showing stored images of the timing diagram. 23 is a flow chart showing the operation of the timing diagram dividing means, FIG. 24 is a flow chart showing the operation of the verification target operation information acquiring means in the extraction of the verification target operation, and FIG. 25 is an explanatory view showing the storage image of the verification target operation information. 26 and 27 are explanatory diagrams showing a storage image of a tree structure created from the verification target operation.

As shown in FIG. 6, the structure of the operation tree to be verified and its modification are described by first describing the storage method of the terminal information of the input HDL (step S101), and then in what format the input timing diagram is input. It is described how to store in the storage device (step S102), and finally, how to identify and cut out the verification target operation from that, and what format is stored in the storage device (step S10).
3).

3-1. Storing terminal information of HDL (FIGS. 7 and 8) Since a means for reading and analyzing HDL is known, only a storage image of terminal information is shown below. HD
The terminal name and bit width are stored separately for input / output / input / output in association with the L hierarchical tree. The hierarchical tree itself holds the instance name of the lower hierarchy.

The terminal information extraction device 1 shown in FIG. 1 described above.
A digital circuit described in, for example, the HDL format, such as a CPU, is input to the HDL reading device 11. Also, the HD transmitted by the HDL reading device 11
As shown in FIG. 1, the information of the digital circuit of L format is H
It may be stored in the DL storage device 12 or HD.
The output side of the L reading device 11 may be connected to the terminal information extracting device 13. With this terminal information extraction device 13, H
Terminal information such as “name” and “direction” shown in FIGS. 7 and 8 is extracted from the digital circuit information in the HDL format sent from the DL reading device 11 or the HDL storage device 12, and the extracted terminal information is It is stored in the terminal information storage device 14. 7 and 8 are diagrams showing an image when the terminal information is stored in the terminal information storage device 14. The terminal information extraction device 1 as described above
Is easily created from a conventional symbol table generated by a so-called HDL parser, and is not particularly developed for the function verification description generation device of the present invention.

That is, in the hierarchical tree example shown in FIG.
Top hierarchy-sub hierarchy (name: pcpun, pmas
n, ...)-Sub hierarchy (name: DW01, YX01,
..., DW01, ...). In the terminal information example of FIG. 8, the highest hierarchy-input-output-
Input / Output, Input-Terminal 1-Terminal 2 ..., Terminal 1-Name:
CMD / bit width: 3, terminal 2-Name: READ_n /
Bit width: 1, output-terminal 1 ..., terminal 1-name: W
AIT / bit width: 1, input / output-terminal 1, ..., Terminal 1
-Name: DATA / bit width: 32 is shown. Further, the sub-tiers are also as shown in FIG.

3-2. Storage of Timing Diagram (FIGS. 9 to 23) The timing diagram editing device 2 shown in FIG. 1 described above is connected to the terminal information extracting device 1 and the terminal name and internal information acquired by the terminal information extracting device 1 by GUI or the like. Pin names are selected by designers and verifiers, and timing constraint information such as input / output waveforms, setup and hold times for each terminal and internal pin, logical relationships between these waveforms, and this logical relationship are always Occurrence information as to whether it is established or is established at least once is input by a designer or a person in charge of verification. In this way, the selected terminal information,
The timing diagram editing device 2 to which the timing constraint information, the input / output waveform, the logical relationship between the waveforms, and the occurrence information of this logical relationship are supplied is the selected terminal information, the timing constraint information, the input / output waveform, and the waveform. Based on the logical relationship between them and the occurrence information of this logical relationship, for example, a timing diagram as shown in FIGS. 9 to 19 is edited.

In FIGS. 9 to 19, for example, ""
CMD [0: 1] "indicates a terminal name or an internal pin name and the number of bits through which a signal is input / output, and" (in) "indicates that the terminal is an input terminal. In FIG. 19, an arrow “→” represents a logical relationship between a start point and an end point, and a signal or an arrow or a symbol “WAIT” can be taken as the start point and the end point.
T "can be added to the clock edge with which the signal is synchronized, and this symbol" WAIT "is a condition for monitoring a signal change, that is, the progress of the timing diagram until the condition is satisfied is the clock edge to which the above" WAIT "is added. The control condition of the timing diagram for stopping can be specified by the designer or the person in charge of verification using the signal value to which the symbol "WAIT" is added, and the symbol "exi" is added to the start point and end point and the arrow. This symbol "exi" represents occurrence information that the logical relationship represented by the start point or the end point or the arrow connecting the start point and the end point to which the sign "exi" is added occurs at least once, and the arrows You can define the logical operation of
The logical operation between the arrows represents the logical relationship between the logical relationships represented by the operated arrows. The above logical relationship will be clarified in the following description. Further, a plurality of the above logical relationships can be set on one timing diagram.

In FIG. 9, the signal "CMD [0: 1]".
With rel_A1 as the starting point and the signal "TAG" as the ending point
The arrow labeled "→" labeled "Signal" CMD [0:
1] ”and a signal“ TAG ”are expressed as a logical relationship,
If [0: 1] is equal to 2'b01, TAG rises after one cycle ".
Signals "D [0: 7]" starting from the arrow labeled rel_A1 above labeled el_A2
The arrow terminating at represents the logical relationship between the above-mentioned arrow "rel_A1" and the signal "D [0: 7]".
[0: 1] is equal to 2'b01 and TAG is 1
If it starts after two cycles, D after two cycles
[0: 7] represents the proposition A2 "equal to 8'bxx1101xx".

In FIG. 10, the signal "CMD [0: 1]" in clock cycle 1 to which the symbol "exi" is added.
Means "at least once CMD [0: 1] may be equal to 2'b01", and the signal "CMD [0:
1] ”as the starting point and the signal“ TAG ”as the ending point rel_
The arrow "→" labeled B1 is the signal "CMD"
"0: 1""and the signal" TAG "represent the logical relationship,
TAG stands up one cycle later if CMD [0: 1] can be equal to 2'b01 at least once. "And also labeled rel_B1 above labeled rel_B2. The arrow starting from the given arrow and ending at the signal "D [0: 7]" is the arrow "rel_B1" and the signal "D [0:
7] ”represents a logical relationship and“ at least once is CMD
[0: 1] may be equal to 2'b01, and T
If AG rises one cycle later, two cycles later D [0: 7] is equal to 8'bxx1101xx. "

In FIG. 11, the signal "TAG" in the clock cycle 2 to which the symbol "exi" is added represents "the TAG may rise at least once" and the signal "CMD [0: 1]". An arrow labeled "→" labeled rel_C1 with a starting point and a signal "TAG" as an end point
Represents a logical relationship between the signal "CMD [0: 1]" and the signal "TAG". If "CMD [0: 1] is equal to 2'b01, the TAG may rise at least once after one cycle. Represents the proposition C1. Also, re
The arrow starting from the arrow labeled rel_C1 labeled l_C2 is the arrow “r”
el_C1 "and the signal" D [0: 7] "are expressed in a logical relationship," CMD [0: 1] is equal to 2'b01, and TAG rises at least once after one cycle, if at least once. D [0: 7] is 8 after 2 cycles
It represents the proposition C2 "equal to bxx1101xx".

In FIG. 12, the signal "D" output in synchronization with the clock cycle 3 to which the symbol "exi" is added.
“[0: 7]” is “D [0: 7] is 8 at least once.
"It may be equal to bxx1101xx", and the signal "TA" with the signal "CMD [0: 1]" as the starting point
The arrow labeled “→” labeled rel_D1 ending in G ”is the signal“ CMD [0: 1] ”and the signal“ TAG ”.
"CMD [0: 1] is 2'b01."
TAG stands for the proposition D1 that "rises after one cycle. Also, the arrow labeled rel_D1 above labeled rel_D2 is the starting point and the signal" D [0: 7] "is the endpoint. The arrow represents the logical relationship between the arrow "rel_D1" and the signal "D [0: 7]", and if "CMD [0: 1] is equal to 2'b01 and TAG rises one cycle later, then 2 D [0: 7] is 8'b at least once after the cycle
It may be equal to xx1101xx ”.

In FIG. 13, a signal "TA" starts from a signal "CMD [0: 1]" to which a symbol "exi" is added.
The label rel_E1 whose end point is G "is" label rel
An arrow labeled "rel_E1", which represents "the proposition represented by _E1 may be satisfied at least once," starts with the signal "CMD [0: 1]" and ends with the signal "TAG""→" Represents a logical relationship between the signal "CMD [0: 1]" and the signal "TAG", and "CMD [0: 1]".
Is equal to 2′b01, the proposition that TAG rises after one cycle may be met at least once. ”And the arrow labeled rel_E1 above labeled rel_E2. The arrow starting from and ending at the signal "D [0: 7]" is the above-mentioned arrow "rel_E1" and the signal "D [0: 7]".
"CMD [0: 1] is 2'b01."
And if TAG rises one cycle later, D [0: 7] will be 8′bxx11 two cycles later.
It represents the proposition E2 "equal to 01xx."
Note that the "exi" is ignored.

In FIG. 14, a signal "TA" starts from a signal "CMD [0: 1]" to which a symbol "exi" is added.
The label rel_F2 starting from the arrow labeled rel_F1 ending in G ”and ending in the signal“ D [0: 7] ”is“ label rel_F2 at least once.
The proposition represented by may be satisfied at least once, and the signal "CMD [0: 1]" is the starting point and the signal "TA
The arrow "→" labeled rel_F1 with the G "as the end point is the signal" CMD [0: 1] "and the signal" TA ".
G "represents a logical relationship, and" CMD [0: 1] is 2'b.
If it equals 01, TAG will rise after one cycle "
Represents the proposition F1. Further, an arrow starting from the arrow labeled rel_F1 and labeled rel_F1 and ending with the signal "D [0: 7]" is
If the arrow "rel_F1" and the signal "D [0: 7]" represent a logical relationship, and "CMD [0: 1] is equal to 2'b01 and TAG rises after one cycle, D after two cycles. [0: 7] is 8'bxx1101
The proposition "equal to xx may be satisfied at least once" is represented as proposition F2.

In FIG. 15, the signal "CMD [0:
1] ”as the starting point and the signal“ TAG ”as the ending point rel_
The arrow "→" labeled G1 is the signal "CMD"
"0: 1""and the signal" TAG "represent the logical relationship,
If CMD [0: 1] is equal to 2'b01, TAG is 1.
It represents the proposition G1 of "rise after a cycle" and also the signal "D [0:
7] "as the starting point and the arrow labeled rel_G1 as the end point is the above-mentioned arrow" rel_G1 ".
And the signal "D [0: 7]",
[0: 7] is equal to 8'bxx1101xx and 3
If CMD [0: 1] equals 2'b01 before the cycle, then TAG rises two cycles before "
Represents 2.

In FIG. 16, clock cycle 2 which is the end of the arrow "→" labeled rel_H1.
The symbol "WAIT" added to the signal "TAG" of "repeates the waveform from clock cycle 1 to clock cycle 2 until the condition TAG = 1'b1 is satisfied",
That is, until the condition TAG = 1'b1 is satisfied, T
AG is equal to 0 and D [0: 7] is 8'bxx001
The signal "CMD [0: 1]" represents "equal to 01xx".
Rel_ starting from and ending at the above symbol "WAIT"
The arrow "→" labeled H1 is the signal "CMD"
Represents a logical relationship between [0: 1] "and the above-mentioned symbol" WAIT ". If" CMD [0: 1] is equal to 2'b01, TAG is equal to 0 until the condition TAG = 1'b1 is satisfied. " And D [0: 7] is equal to 8'bxx00101xx ", and the signal" D [0: 7] "starts from the arrow labeled rel_H1 labeled rel_H2. The arrow ending at is the above-mentioned arrow "rel_H1" and signal "D [0: 7]".
"CMD [0: 1] is 2'b01."
And TAG is equal to 0 and D [0: 7] is 8'bxx until the condition TAG == 1'b1 is satisfied.
If equal to 00101xx, D after 2 cycles
[0: 7] represents the proposition H2 "equal to 8'bxx1101xx".

In FIG. 17, clock cycle 2 which is the starting point of the arrow "→" labeled rel_I2.
The symbol "WAIT" added to the signal "TAG" of "repeates the waveform from clock cycle 1 to clock cycle 2 until the condition TAG = 1'b1 is satisfied",
That is, "someday TAG changes from 0 to 1 and D
8'bxx0010 while [0: 7] is equal to 0 for TAG
After repeatedly holding 1xx, it changes to other values ”
, And the signal "D" starting from the above-mentioned symbol "WAIT"
The arrow labeled "→" labeled rel_I2 ending in [0: 7] "is the above symbol" WAIT "and signal" D ".
[0: 7] ”, which represents a logical relationship with
Changes from 0 to 1 and D [0: 7] is 8'bxx00
If it changes from 101xx to any other value, then two cycles later [0: 7] represents the proposition I1 "equal to 8'bxx1101xx." Also, the signal "CMD [0: 1] labeled rel_I1." The arrow starting from the arrow labeled "rel_I2" is the signal "CMD [0: 1]" and the above arrow "rel".
_I2 ”represents a logical relationship, and“ CMD [0: 1] is 2
It represents a proposition I2 that "if it is equal to b01, the above proposition I1 is satisfied".

In FIG. 18, clock cycle 2 which is the starting point of the arrow "→" labeled rel_J2.
The symbol "WAIT" added to the signal "TAG" of "repeates the waveform from clock cycle 1 to clock cycle 2 until the condition TAG = 1'b1 is satisfied",
That is, it means "someday TAG changes from 0 to 1", and the signal "D [0:
7] ”labeled rel_J2 and ending with“ → ”is the above symbol“ WAIT ”and signal“ D [0:
7] ”, and“ someday, if TAG changes from 0 to 1 two days later, D [0: 7]
Represents the proposition J1 "equal to 8'bxx1101xx. Also, the signal labeled rel_J1"
The arrow starting from CMD [0: 1] "and starting from the arrow labeled rel_J2 is the signal" CMD ".
It represents a logical relationship between [0: 1] and the arrow "rel_J2", and represents a proposition J2 that "the above proposition J1 holds if CMD [0: 1] is equal to 2'b01".

In FIG. 19, the signal "CMD [0:
1] ”as a starting point and signals“ D [0: 7] ”as an ending point r
The arrow labeled "→" labeled el_K1 is the signal "C"
It represents the logical relationship between MD [0: 1] "and the signal" D [0: 7] ". If" CMD [0: 1] is equal to 2'b01, D [0: 7] will be 8'after 4 cycles. " bxx1101xx
Represents the proposition K1 "equal to". Also, rel_
The symbol "W" added to the signal "TAG" of clock cycle 2 which is the starting point of the arrow "→" labeled K2
AIT is “repeat the waveform from clock cycle 1 to clock cycle 2 until the condition TAG = 1′b1 is satisfied”, that is, “someday TAG changes from 0 to 1 and D [0: 7] is 8'bxx00101xx changes to other values "and represents the above symbol" WAI
Re starting from T "and ending with signal" D [0: 7] "
The arrow "→" labeled l_K2 is the above symbol "
It represents a logical relationship between the WAIT "and the signal" D [0: 7] "," someday the TAG changes from 0 to 1 and D [0:
7] is 8'bxx00101xx while TAG is equal to 0
If the value changes from 8'bxx00101xx to any other value after repeatedly holding, then D after two cycles
[0: 7] represents the proposition K2 "equal to 8'bxx1101xx." Also, this label rel_K1 and this label rel_K2 labeled rel_K3.
Represents a proposition K3 that "either proposition K1 or proposition K2 holds". Also, the label rel_
Rel_K with K2 as the starting point and the signal "TAG" as the ending point
The arrow labeled "→" labeled 4 is the label rel above
_K2 represents a logical relationship between the signal "TAG", "someday after TAG changes from 0 to 1 and D [0: 7] holds 8'bxx00101xx repeatedly while TAG is equal to 0, D [0: 7] is 8'after 2 cycles
If it is equal to bxx1101xx, TAG changes from 0 to 1 and D [0: 7] changes from 8'bxx00101xx to any other value.
It represents the proposition K4 that "AG falls."

The timing diagram storage device 31 shown in FIG. 1 is input and edited by the designer or the verification subject by the timing diagram editing device 2.
For example, the information of the timing diagrams as shown in FIGS. 9 to 19 is stored. 21 and 22 are views showing an image when the timing diagram information input and edited by the designer or the verification subject by the timing diagram editing device 2 is stored in the timing diagram storage device 31.

That is, in the storage image examples of the timing diagrams shown in FIGS. 21 and 22, terminal 1-terminal 2-terminal 3, terminal 1-name / direction / bit width / target clock-high period / low period / rising edge. / Falling edge-0-0 → 1 ..., 0-value / setup value / hold value / output delay / WAIT setting / exi setting / arrow-starting / ending point / exi setting / arrow. Further, 0 → 1 ..., Terminal 2 and terminal 3 are similarly as shown in FIGS. 21 and 22.

In acquiring the timing diagram information, first, the timing diagram dividing means shown in the operation flowchart of FIG. 23 divides the timing diagram such that the clock cycle changes from 0, 0 to 1, 1 or the like. That is, it is as follows.

(1) In step S201, one terminal of the diagram is selected, the scanning from the left of the waveform defined in the terminal is started in step S202, and the variable flg is set to 0 in step S203. Step S2
In 04, it is determined whether or not this waveform being scanned has reached a position indicating a signal change. If it has reached, the process proceeds to step S205; otherwise, the process proceeds to step S206. Move to.

(2) Next, in step S205, 1 is assigned to the variable flg, and the process proceeds to step S206.

(3) In step S206, step S
This waveform scanning at 204 is setup,
It is determined whether or not the point where the timing constraint such as hold or output delay is set is reached. If the point is reached, the process is moved to step S207, and if not reached, the process is moved to step S209.

(4) In step S207, the signal name and the signal edge associated with the timing constraint are acquired and identified as the clock with which this terminal is synchronized,
In step S208, the identified clock and the edge of the clock are used as division points to divide the waveform being scanned in step S204, and the process proceeds to step S209.

(5) Next, in step S209, it is determined whether or not the scan performed in step S204 is completed, and if it is completed, the process is completed in step S210.
If not completed, the process proceeds to step S204.

(6) In step S210, the symbol f
It is determined whether or not lg matches 0. If they match, the process proceeds to step S211, and if they do not match, the process proceeds to step S213.

(7) In step S211, the user is inquired about the clock signal and the clock edge to be synchronized with the terminal, the user information is acquired, and the waveform defined in this terminal based on the user information is acquired in step S212. Division is performed, and the process proceeds to step S216.

(8) In step S213, the waveform defined at the terminal is divided at the signal change point, and in step S214, the distance from the signal change point is given by the shortest synchronous clock edge. That is, the division points whose distance is less than a half cycle period are excluded, and in step S215, this waveform is scanned again from the left side, and the adjacent division sections whose section harmony is less than one cycle period. Are merged, and the process proceeds to step S216.

(9) In step S216, the number of cycles is assigned to each of the divided sections while scanning the waveform again from the left.

(10) Finally, in step S217, it is determined whether or not all the terminals have been processed. If all the terminals have been processed, the processing ends. If not processed, the processing proceeds to step S201.

FIG. 20 is a diagram showing an image of the timing diagram obtained by the timing diagram dividing means. That is, in the timing diagram division example shown in FIG. 20, CMD [0: 1] (in), TAG (in), D synchronized with CLK (in)
The change of [0: 7] (out) is divided into cycle 0, cycle 1, cycle 2, and cycle 3.

Next, the waveform information of the terminal or the internal pin within the divided section obtained by the timing diagram dividing means, for example, information indicating whether the symbol "WAIT" is set, the symbol "WAIT" is set. In the case, the waveform information of all terminals or internal pins in the division section immediately before this division, the information whether the symbol "exi" is set, the information indicating whether the arrow "→" is the start point or the end point , If the arrow is the start point or the end point of the arrow, the label name of the arrow, information whether the symbol "exi" is set for this arrow, and whether this arrow is the start point or the end point of another arrow Information, the signal value of this pin or internal pin, and timing constraint information such as setup, hold, and output delay for this clock. Carry out the acquisition of gram information.

In the case of the output terminal, the output delay constraint set for the signal change is also set for the waveform information in the next divided section, and for the input terminal, the setup timing constraint set for the signal change is 1. It is also set in the waveform information in the previous divided section. When there is no terminal or internal pin waveform information in the divided section, the above-described FIG. 21 and FIG.
It is assumed that the symbol “null” is acquired as shown in FIG.
When acquiring the timing diagram information,
Rising, falling, and changes other than 0, 1, and binary values as signal values are also identified as values.

3-3. Cut out verification target operation (Fig. 24)
27 to 27) The verification target operation information extraction device 32 shown in FIG. 1 described above.
24 operates as shown in the operation flowchart of FIG. 24, acquires verification target operation information from the timing diagram information stored in the timing diagram storage device 31, and stores the result in the verification target operation information storage device 33. That is, it is as follows.

(1) In step S301, the variable j
Is substituted with 0, and 1 is added to this variable j in step S302.

(2) Next, in step S303, the waveform information of the jth terminal or the internal pin is acquired from the timing diagram information stored in the timing diagram storage device 31, and in step S304, the jth terminal is acquired. Alternatively, the terminal name set in the waveform information of the internal pin, the name of the internal pin, the direction, and the information of the synchronization clock and the synchronization edge of this synchronization clock are acquired, and 1 is assigned to the variable i in step S305,
In step S306, waveform information in the divided section corresponding to the i-th terminal is acquired from the waveform information of the j-th terminal or internal pin. However, if the value in the waveform information in the divided section acquired in this step is a change, the waveform information in the divided section of the preceding and succeeding cycles is also acquired.

(3) In step S307, the above i
It is determined whether or not an arrow is set in the waveform information in the divided section corresponding to the second, and if it is set, the process proceeds to step S311; otherwise, the process proceeds to step S308.

(4) In step S308, it is determined whether or not the symbol "WAIT" is set in the waveform information in the divided section corresponding to the i-th above, and if it is set, the process proceeds to step S309. If not set, the process moves to step S316.

(5) In step S309, the condition of this symbol "WAIT" set and this symbol "W"
Information of the terminal name or internal pin name in the waveform information of the terminal or internal pin associated with AIT ”and the waveform information of the i−1, i + 1th divided section in the waveform information of this terminal or internal pin Then, in step S310, the symbol of the waveform information in the divided section corresponding to the i-th set in the waveform information of the j-th terminal or the internal pin
Referring to the WAIT "setting location, the process is performed in step S313.
Move to.

(6) In step S311, the setting information of the symbol "exi" and the arrow for the waveform in the waveform information within the divided section corresponding to the i-th terminal set in the waveform information of the j-th terminal or internal pin are set. For "ex"
The setting information of i ″ is acquired, and then, in step S312, the arrow set in the waveform information in the divided section corresponding to the i-th terminal set in the waveform information of the j-th terminal or the internal pin is the starting point. Information is acquired or the end point is acquired, and the process proceeds to step S313.

(7) Steps S313 to S3
In 15, the arrow is set in the list obtained by tracing from the symbol "WAIT" or "exi" in the waveform information in the divided section corresponding to the i-th, where the waveform information of the j-th terminal or the internal pin is set. If it is set, it acquires the information of the start point or end point of the arrow and the symbol "exi" setting information for the arrow, and this processing is continued until the list is exhausted, and it is not set. In the case or when there is no list, the process proceeds to step S316.

(8) In step S314, the setting information of this arrow symbol "exi" is acquired, and in step S315
Then, information indicating whether the arrow is the start point or the end point is acquired, and the list in which the information indicating the start point or the end point of the arrow is stored is set, and then the process is performed in step S31.
Move to 3.

(9) In step S316, 1 is added to the symbol i, and in step S317, the total number of pieces of waveform information in the divided section in which the symbol i is set in the waveform information of the j-th terminal or internal pin is calculated. Whether or not it is exceeded is determined. If it is exceeded, the process proceeds to step S318, and if not exceeded, the process proceeds to step S318.

(10) Further, in step S318,
It is determined whether or not the symbol j exceeds the total number of waveform information of terminals or internal pins in the timing diagram information. If it exceeds, the process ends, and if not, the process proceeds to step S302.

The verification target operation information storage device 33 shown in FIG. 1 described above is connected to the output of the verification target operation information extraction device 32, and the verification set by the designer or the person in charge of verification in the above timing diagram information. The target operation, that is, information on the logical relationship between the waveforms is stored. Note that FIG.
5 is a diagram showing an image when the verification target operation extracted from the timing diagram information is stored in the verification target operation information storage device 33. FIG.

That is, in the storage image example of the verification target operation information shown in FIG. 25, rel_K1-rel_K2-
rel_K3-rel_K4, rel_K1-start point / end point / exi setting / logical expression, start point-direction / value / setup value / hold value / output delay / clock / cycle / e
xi setting / WAIT setting is shown. Furthermore, the end point,
The same applies to rel_K2, rel_K3, and rel_K4 as shown in FIG. However, the WAIT setting is n
If not, the condition / terminal 1 waveform information / terminal 2 waveform information / terminal 3 waveform information is connected.

The verification target motion information stored in the verification target motion information storage device 33 is regarded as the adjacency list of the graph formed by the start point and end point associated with each arrow label, and only the parent of each adjacency list is considered. A set 1 of arrow labels and a set 2 of arrow labels consisting only of children of each adjacency list are created, and the set with the smaller number of elements of set 1 and set 2 is subtracted in the sense of the set operation. The result is set 3.

Then, one arrow label included in the set 3 is taken out, a tree is constructed by, for example, searching the adjacency list in breadth-first order, and this operation is repeated until the set 3 becomes empty. Target motion information storage device 3
A tree structure is constructed from the verification target operation information stored in 3. 26 and 27 are tree diagrams created from the stored image of the verification target operation shown in FIG. 25, hereinafter referred to as a verification target operation tree, and are views showing this image.

That is, in the example of the storage image of the tree structure created from the verification target operation of FIG. 25 shown in FIGS. 26 and 27, rel_K3 / exi setting-rel_K
1 | rel_K2-rel_K1 / start / end point / exi setting-CMD [0: 1] / start / end point / exi setting-direction / value /
It shows setup value / hold value / output delay / clock / cycle / exi setting / WAIT setting. Furthermore, D [0: 7] / start / end point / exi setting, rel_K2
/ Start / End / exi setting-TAG / Start / End / exi setting,
The setting of D [0: 7] / start / end point / exi and rel_K4 are substantially the same as in FIGS. 26 and 27.

4. TDO2 Verilog Algor
itm According to FIG. 28 to FIG. 62, TDO2Verilog Al
An example of gorithm will be described. Figure 28 shows TDO2V
29 is a flow chart showing allocation of storage variables, FIG. 30 is a flow chart showing calculation of the number of storage cycles, FIG. 31 is an explanatory diagram showing a table structure in the calculation of the number of storage cycles, and FIG.
2 is a flow chart showing the generation of the Wait control flag and determination of the initial value, FIG. 33 is an explanatory diagram showing the table structure in the generation of the Wait control flag and determination of the initial value, FIG. 34 is a flow chart showing the determination of the initial value, and FIG. FIG. 36 is a flow chart showing variable declaration HDL description generation, FIG. 36 is a flow chart showing variable value storing HDL description generation, FIG. 37 is a flow chart showing graph transformation, and FIG.
8 to 54 are explanatory diagrams showing graph transformation, and FIG. 55 is a verification H.
56 is a flow chart showing the generation of DL, FIG. 56 is Property
Flow chart showing _simple, FIG. 57 is Proper
ty_wait showing a flow chart, FIGS. 58 and 59 show WaitBlock showing a flow chart, FIG. 60 and FIG.
1 is a flow chart showing WaitORBlock, and FIG. 62 is a flow chart showing ConseqBlock.

As shown in FIG. 28, TDO2Veril
og Algorithm first describes a means for identifying the number of cycles before which a value is stored for each signal, assigning a storage variable, determining an initial value, and generating a description for storing a signal value. (Step S401),
Next, the modification method of the verification target operation tree is described (step S
402) Finally, the HDL verification description generation means from the finally obtained verification target operation tree will be described (step S40).
3).

4-1. Storage variable allocation (FIGS. 29 to 36: FIG. 29) (1) In step S501, the number of cycles of the signal of the node storing the signal name of the operation tree to be verified should be stored. Then, the signal value storage registers of the same number as the number of cycles are assigned to each signal, and the information is stored in the table.

(2) In step S502, it is determined whether the operation tree to be verified includes a wait object. If it does, the process moves to step S503, and if not, the process moves to step S504.

(3) In step S503, w is equal to the number of wait objects included in the operation tree to be verified.
A flag for ait control is generated.

(4) In step S504, the initial value at reset of the register assigned to each signal is determined. This is done so that the verification HDL does not malfunction at the initialization stage.

(5) In step S505, the HDL description of the variable declaration of the register assigned to each signal and the wait control flag is generated.

(6) In step S506, the registers assigned to the respective signals are initialized at reset,
And an HDL description of signal value substitution is generated.

4-1-1. Calculation of the number of storage cycles (Fig. 3
0 and FIG. 31) (1) In step S601, all the cycle numbers of the node storing the signal name of the verification target operation tree are acquired,
Determine the maximum value. This value is the maximum number of cycles in the table.

(2) In step S602, a table that allows the setting of wait, storage / unnecessity, and initial value information to be stored in a cycle from 1 to the maximum value obtained in step S601 for all signals To create.

(3) In step S603, the number of cycles of the node storing the signal name of the operation tree to be verified is acquired, and the number of storage cycles of the signal is calculated in step S601.
The maximum value obtained in step-the acquired number of cycles is obtained, and 1 is set from 1 in the column of storage required / not required to the value obtained by the above calculation (it is assumed that 0 is stored in the initial state).

(4) In step S604, if all the nodes storing the signal name on the operation tree to be verified have been searched, the process is terminated, and if not, the process proceeds to step S603.

The table structure for calculating the number of storage cycles is, for example, as shown in FIG. That is, in the table structure example of FIG. 31, a signal name, an area for storing a signal value, whether or not a register is required, Wait setting,
Each area is provided for storing the number of cycles with respect to the initial value.

4-1-2. Wait control flag generation
Initial value determination (FIGS. 32 and 33) (1) In step S701, w of the verification target operation tree
Identify the node for which the ait object is set.

(2) In step S702, if the node identified in step S701 represents a repeat check, the process proceeds to step S703, and if not, the process proceeds to step S704.

(3) In step S703, the character string itr [I] is stored in the wait setting section of the corresponding cycle of the corresponding signal in the table, and the corresponding register necessity / unnecessity flag is set to 1 (initial value is NULL. Suppose there is.
The array index I is a variable that increases in accordance with the number of flags).

(4) In step S704, if the node identified in step S701 is used for the end condition, the process proceeds to step S705, and if not, the process proceeds to step S706.

(5) In step S705, the character string cond [I] is stored in the wait setting section of the corresponding cycle of the corresponding signal in the table, and the corresponding register necessity / unnecessity flag is set to 1 (initial value is NULL. The array index I is a variable that increases according to the number of flags).

(6) In step S706, wai
The number of t control flags is incremented (the initial value is 0). The flag name is wait_flg.
[2: 0] is set, and wait_flg [0] is a repeat start flag, and 1 indicates start and 0 indicates not start. Also,
wait_flg [1] is the repeat continuation flag,
1 indicates continuation, and 0 indicates non-continuation. Finally, wait_fl
g [2] is a repetition end flag, and 1 indicates end and 0 indicates not end. The initial values are all 0. In particular, when there are a plurality of flags, a plurality of flags are assigned by declaring them as a two-dimensional array such as reg [2: 0] wait_flg [number of flags-1: 0]. For example, the I-th flag is wait_flg [I] [2: 0].

(7) In step S707, if all the nodes for which the wait object is set have been searched, the process is terminated, and if not, the process proceeds to step S701.

The table structure in the generation of the Wait control flag and the determination of the initial value is as shown in FIG. 33, for example. That is, in the table structure example of FIG. 33, there are provided areas for storing signal names and signal values, and areas for storing register necessity / unnecessity, Wait setting, and the number of cycles for initial values.

4-1-3. Initial value determination (FIG. 34) (1) In step S801, the node in which the signal name of the verification target operation tree is set is identified.

(2) In step S802, 0 of the corresponding bit width is assigned to all the signals identified in step S801.

4-1-4. Variable Declaration HDL Description Generation (FIG. 35) (1) In step S901, the number of register required / unnecessary flags for the signal name on the table is 1.

(2) In step S902, if the signal identified in step S901 is 1 bit, the process proceeds to step S903; otherwise, the process proceeds to step S904.

(3) In step S903, reg declaration of variable name_tmp having a bit width of the number acquired in step S901 is made as a one-dimensional array. That is, reg [the number obtained by (1) -1: 0] variable name_
tmp; is generated. The processing moves to step S905.

(4) In step S904, as a two-dimensional array, the number of arrays acquired in step S901 is declared as a variable name_tmp. That is, the following description is generated: reg [bit width-1: 0] variable name_tmp [number obtained by (1) -1: 0];

(5) In step S905, wai
Two-dimensional array reg of wait flags for t counts
Make a declaration. That is, the following description is generated: reg [2: 0] wait_flg [wait count number-1: 0];

(6) In step S906, if all the signals on the table have been acquired, the process proceeds to step S907, and if not, the process proceeds to step S901.

(7) In step S907, [Lo
g2 maximum number + 1] is calculated, and cnt_ of the bit width is calculated.
tmp is declared as reg, and flg_tmp is also declared as reg. That is, the following description is generated: reg [[log2 (maximum value of the number acquired in (1))] + 1: 0] cnt_tmp; regflg_tmp ;. Here, [log2 (the maximum value of the number acquired in (1))] represents the maximum integer that does not exceed log2 (the maximum value of the number acquired in (1)).

4-1-5. Variable Value Storage HDL Description Generation (FIG. 36) (1) In step S1001, as many integer variables as the number of reg-declared variables are declared. That is, the following description is generated: Integer [Number of variables-1: 0] I;

(2) In step S1002, the following alwayss @ (posedge clock signal name o
r negage reset signal name) begin if (! reset signal name) begin is generated.

(3) In step S1003, re
g Initialization description of all declared variables is signal name_tmp
While creating the correspondence between the array number of the above and the cycle number of the table, a description for assigning an initial value to the signal name_tmp is generated. For example, a description such as the following signal name_tmp [0] <= 1'b0; is generated.

(4) In step S1004, end else begin To generate the description.

(5) In step S1005, re
g For all declared variables, depending on whether it is 1-bit or multi-bit, the following signal name_tmp [0] <= signal name; // 1 bit signal name_tmp [0] [bit width-1: 0] < = Signal name [bit width-1: 0]; // Generate any of the descriptions in the case of multiple bits.

(6) In step S1006, re
g For any of the declared variables, one of the following descriptions is generated according to whether it is 1-bit or multi-bit. However, k is incremented by 1 each time the signal name changes.

For (I [k] = 0; I [k] <bit width; I [k] = I [k] +1) // in case of 1 bit Signal name_tmp [I [k] +1] <= signal First name_tmp
[I [k]]; for (I [k] = 0; I [i] <bit width; I [k]
= I [k] +1) / in the case of multiple bits Signal name_tmp [I [k] +1] [bit width-1: 0]
<= Signal name_tmp [I [k]] [bit width-1:
0]; (7) In step S1007, if (! Flg_tmp) begin cnt_tmp = cnt_tmp + 1; if (cnt_tmp == multi-bit signal name_tmp maximum value of bit width of variable) flg_tmp = 1; .

(8) In step S1008, end end To generate the description.

4-2. Deformation of motion tree to be verified (Fig. 37-
(FIG. 54: FIG. 37) (1) The vertex of the operation tree to be verified, which is signal o
All vertices for which only bject is set have a corresponding index with reference to the table, variable name_t
Replace with mp. In addition, even at the other vertices,
This conversion is performed when the signal name is included.

(2) In step S1101, the vertices representing the Boolean operation between the relation objects on the verification target operation tree are acquired.

(3) In step S1102, re
Boolean operation between the relation objects, topological sorting by depth-first search of the signal vertices of the tree to the left and below for the subtrees, and arranging the signal vertices in the reverse order to the obtained order, Let (A->B)-> C be A->(B-> C) and A & B
Transform the graph so that-> C. In general, all parentheses are removed and A1 & A2 & ... &An-> An + 1.
Transform the graph so that In particular, this process is re
Boolean operation between the relation objects is first performed under the condition that the lower subtree is not included, and then the relat
Boolean operation between ion objects The following subtrees are fixed and the processing is recursively performed.

(4) In step S1103, re
It is determined whether or not the Boolean operation between the relation objects includes &, and if it does, the process proceeds to step S1104.
Otherwise, the process proceeds to step S1105.

(5) In step S1104, it is determined whether or not the wait subobject is set in the lower subtree, and if so, the process proceeds to step S110.
If not, the process proceeds to step S1106.

(6) In step S1105, it is determined whether or not the wait object is set in the lower subtree, and if it is, the process proceeds to step S110.
8, otherwise, the process proceeds to step S1106.

(7) In step S1106, re
The graph transformation using the Boolean operation of the relation object is performed, and the process proceeds to step S1109.

(8) In step S1107, the user is notified that the wait object setting is incorrect, and the process ends.

(9) In step S1108, graph transformation is performed by merging signals other than the wait object of the tree, and the wait o located at the bottom of the tree is merged.
Mark bject.

(10) In step S1109, it is determined whether or not the Boolean operations of all relation objects have been acquired, and if so, the process proceeds to step S1.
110, otherwise, the process proceeds to step S1101.
Move to.

(11) In step S1110, r
Boolean operation between association objects Assuming that the subtree below is fixed, the process of step S1102 is performed on the verification target operation tree, and the process is terminated.

The graph transformation will be described through the example of FIG. R surrounded by a square is a relation objec
The vertices representing t, and the other vertices are signal vertices. In particular, the signal vertices of m and y indicate that the wait object is set. That is, in the example of FIG. 38, r
-R- (r1 | r2) & r3-r1, r2, r3 -...
-A, b, c, d, e, f, g, i, j, k, r-r
-A4, r-r-r4 | r5-r4 -...- h, l,
m, a1, r-r-r4 | r5-r5-a5, r-r-
r4 | r5-r5-r-r6 | r7 & r8-r6, r
7, r8 -...- o, p, q, r, s, t, u, v,
w, r-r-r4 | r5-r5-r-r -...- x,
It shows a hierarchical tree of y, z, a1, r-r-r-a2, a3.

The graph modification of FIG. 38 is similar to that of FIGS.
According to No. 4, it is performed as follows.

(1) In FIG. 39, the relation
Represents a Boolean identification. (R1 ‖ r2) & r3
-..., r6 | r7 & r8 -..., r4 | r5-
.. is identified.

(2) In FIG. 40, (A->B)->
The transformation of C into A->(B-> C) is shown. r1 -...
-The order of a, b, c, k is a, b as in (a).
, C, k, and transform as shown in (b).

(3) In FIG. 41, (A->B)->
The transformation (continuation) of C into A->(B-> C) is shown. Similarly, r2 -...- d, e, f, g, h in order, r3-
...- Determine the order of i, j, k as shown in (a),
It deforms as shown in (b).

(4) In FIG. 42, A->(B->
The transformation of C) into A &B-> C is shown. (A) to (b)
, (R1 | r2) & r3-r1-a & b & c,
k, (r1 | r2) & r3-r2-d & e & f & g,
k, (r1 | r2) & r3-r3-i & j, k.

(5) In FIG. 43, the relation
Represents a transformation using Boolean. As in (a) to (b), r- (a & b & c | d & e & f & g)
& I & j.

(6) In FIG. 44, the relation
Represents the transformation with Boolean (remaining). (A)
, R6 | r7 & r8-r6, r7, r8 -...
-Modify -o, p, q, r, s, t, u, v, w as shown in (b).

(7) In FIG. 45, the relation
Representation (continuation) using Boolean (remaining). Similarly, as in (a) to (b), r6‖r7 &
r8-r6-o & p & q, w, r6 | r7 & r8-r7
-R & s & t, w, r6 | r7 & r8-r8-u & v,
Transform into w. Furthermore, as in (c), r-o & p &
Transformed into q & r & s & t / u & v, w.

(8) In FIG. 46, an intermediate result of graph transformation is shown. The results of FIGS. 43 and 45 are summarized in FIG. 46.

(9) In FIG. 47, the relation
Represents a variant using Boolean again. Similarly, again, r4 | r5-r4 -...- h, l, m, a1, r
4 | r5-r5-a5, r4 | r5-r5-r -...
-O & p & q & r & s & t | u & v, w, x, y, z,
Transform a1.

(10) In FIG. 48, relatio
Represents a recursive execution of n Boolean processing. (A)
The order is determined as shown in FIG.

(11) In FIG. 49, wait ob
A->(B-> C) when Jject is included
The transformation from B to C is shown. From (a) to (b),
r4 || r5-r4 -...- h, l, m, a1, r4 |
r5 -...- a5 & (o & p & q & r & s & t / u &
v) & w & Transform to x, y, z, a1.

(12) In FIG. 50, the identification of the lowest wait object in the subtree is shown. wait o
bject is m and y.

(13) In FIG. 51, an intermediate result of graph transformation is shown. The results of FIG. 46 and FIG. 50 are summarized in FIG.

(14) In FIG. 52, graph transformation (order determination) in the entire verification target operation tree is shown. The order is determined as shown in FIG. 52 for the entire verification target operation tree.

(15) In FIG. 53, graph transformation ((A->B)-> C A-> (B in the entire verification target operation tree
-> C)). When the order is determined and transformed as shown in FIG. 52, the result is as shown in FIG.

(16) In FIG. 54, A &B-> of graph transformation (A->(B-> C) in the entire operation tree to be verified.
(Transformation into C). Finally, the graph transformation in the entire verification target operation tree is as shown in FIG. That is, r-
((A & b & c | d & e & f & g) & i & j) & k & a
4, r-r-r4 | r5-r4 -...- h, i, m,
a1, r-r-r4 | r5-r5-a5 & (o & p & q
& R & s & t | u & v) & w & x, r-r-r4 | r5
-R5-r -... y, z, a1, r-r-r-a2
It becomes a3.

4-3. Generation of verification HDL (FIGS. 55 to 6)
2: FIG. 55) (1) In step S1201, delayCnt
= 1 and the leftmost vertex of the motion tree to be verified is acquired, and m
ost_left.

(2) In step S1202, it is determined whether or not the tree does not include wait, and if so, the process proceeds to step S1203, and if not, the process proceeds to step S1204.

(3) In step S1203, Pr
execute operation_simple, and terminate the process.

(4) In step S1204, Pr
execute operation_wait and execute the process in step S1.
Move to 205.

(5) In step S1205, Co
nseqBlock is executed, and the process ends.

4-3-1. Property_simp
le (FIG. 56) (1) In step S1301, the next vertex is acquired rightward from the vertex of the verification target operation tree in the depth-first search procedure.

(2) In step S1302, the following alwayss @ (posseged clock name) begin
n #delayCnt if (flg_tmp & Boolean expression representing acquired vertex)
Generate a description called begin.

(3) In step S1303, it is determined whether the tree includes exi, and if so, the process proceeds to step S13.
05, otherwise, the process proceeds to step S1304.

(4) In step S1304, the following if (! (most_left represents the boolean expression)) To generate the description.

(5) In step S1305, the following if (! (Boolean expression represented by most_left)) $ display ("Error occurred!
!! )); Is generated.

(6) In step S1306, end end The following description is generated, and the processing ends.

4-3-2. Property_wait
(FIG. 57) (1) In step S1401, flow_flg
= 0.

(2) In step S1402, the next vertex is acquired rightward from the vertex of the operation tree to be verified in the depth-first search procedure.

(3) In step S1403, the vertex acquired in step S1402 is most_left.
It is determined whether or not, and if so, the process ends, and if not, the process proceeds to step S1404.

(4) In step S1404, it is determined whether the vertex acquired in step S1402 is relation, and if so, the process proceeds to step S1405, and if not, the process proceeds to step S1406.

(5) In step S1405, Pr
Executes operation_wait.

(6) In step S1406, the vertex acquired in step S1402 is the rel of the boolean expression.
determination is made, and if so, step S1407
Otherwise, the process proceeds to step S1408.

(7) In step S1407, Wa
Execute it_Block.

(8) In step S1408, it is determined whether the vertex obtained in step S1402 is a Boolean expression consisting of signals, and if so, the process proceeds to step S1409, and if not, the process proceeds to step S1413.

(9) In step S1409, fl
It is determined whether or not ow_flg == 0, and if so, step S
If not, the process proceeds to step S1412.

(10) In step S1410, f
Let low_flg = 1.

(11) In step S1411, I
Substitute the following flg_tmp & Boolean expression representing the acquired vertex into f_expression.

(12) In step S1412, I
Substitute the Boolean expression represented by the acquired vertex below into f_expression.

(13) In step S1413, it is determined whether the vertex acquired in step S1402 is a wait, and if so, the process proceeds to step S1414.

(14) In step S1414, W
Execute aitBlock.

4-3-3. WaitBlock (Fig. 58
And FIG. 59) (1) In step S1501, a description "always @ (posseged clock name) #delayCnt" is generated.

(2) In step S1502, Wa
It is determined whether it_expression is empty, and if so, to step S1503, and if not, to step S150.
The processing shifts to 6.

(3) In step S1503, If
It is determined whether _expression is empty, and if so, the process proceeds to step S1504, and if not, the process proceeds to step S1505.

(4) In step S1504, the following if (! Wait cancellation condition) wait_flg [k] is set.
[0] = 1'b1; else wait_flg [k]
[0] = 1′b0;

(5) In step S1505, the following if (If_expression) wait_flg is set.
[K] [0] = 1'b1; else wait_flg
[K] [0] = 1′b0;

(6) In step S1506, the following if (Wait_expression) begin wait (Wait_expression) begin
Generate a description n.

(7) In step S1507, la
Determine whether stWaitFlg is empty, and if so, step S
If not, the process proceeds to step S1509.

(8) In step S1508, wait_flg [k] [2] = 1'b0; To generate the description.

(9) In step S1509, la
Set all wait_flg in stWaitFlg to 1'b0.

(10) In step S1510, I
It is determined whether f_expression is empty, and if so, the process proceeds to step S1511, and if not, step S1512.
Process shifts to.

(11) In step S1511, the description wait_flg [k] [0] = 1'b1; end end is generated.

(12) In step S1512, the description if (If_expression) begin wait_flg [k] [0] = 1'b1; end else begin wait_flg [k] [0] = 1'b0; end end is generated. .

(13) In step S1513, d
Increment elayCnt.

(14) In step S1514, the following alwayss @ (posedge clock name) #delayCnt if (| wait_flg [k] [1: 0]) begi
n wait (| wait_flg [k] [1: 0]) be
gin wait_flg [k] [0] = 1′b0; if (! (wait cancellation condition)) begin if (repetition condition) wait_flg [k] [2: 1] = 2′b01; else begin wait_flg [k] [1 : 0] = 2′b00; $ display (“Error Occurred
at interpolation. )); End end else wait_flg [k] [2: 1] = 2'b10; end end is generated.

(15) In step S1515, W
The following wait_flg [k] [2] is assigned to ait_expression.

(16) In step S1516, d
elayCnt is incremented, k is incremented, and the process ends.

4-3-4. WaitORBlock (FIGS. 60 and 61) (1) In step S1601, relation
Highest-level relative that exists below the Boolean expression of
The number of n is acquired and set as RootRelCnt.

(2) In step S1602, re
The leftmost vertex existing in the lower part of the Boolean expression of the relation is acquired and set as sub_most_left.

(3) In step S1603, j =
Set to 1.

(4) In step S1604, the jth highest relation from the left is acquired.

(5) In step S1605, the following subdelayCnt = delayCnt subIF_expression = If_expre
session subWait_expression = Wait_e
Substitute xpression.

(6) In step S1606, Pr
Executes operation_wait.

(7) In step S1607, j is incremented.

(8) In step S1608, j>
It is determined whether it is RootRelCnt, and if so, step S1
If not, the process proceeds to step S1604.

(9) In step S1609, su
The maximum value of bdelayCnt is set as delayCnt.

(10) In step S1610, W
ait_expression is the subIF_expression && subWait obtained by the above process.
It is an OR expression of _expression. That is, the following formula Wait_expression = | IsubIF_e
xpression [I] && subWait_exp
Substitute region [I] into Wait_expression.

(11) In step S1611, l
subWait_expres to astWaitFlg
Stores all sions.

(12) In step S1612, I
Empty f_expression.

(13) In step S1613, s
ub_most_left! = Most_left is determined, and if so, the process proceeds to step S1614, and if not, the process ends.

(14) In step S1614, it is identified whether the vertex is a signal, and if so, step S1615.
Otherwise, the process proceeds to step S1616.

(15) In step S1615, I
Substitute a Boolean expression consisting of a signal for f_expression.

(16) In step S1616, it is identified whether the vertex is a wait and the process proceeds to step S1617.

(17) In step S1617, W
Execute aitBlock and end the process.

4-3-5. ConseqBlock (FIG. 62) (1) In step S1701, most_left
It is determined whether t is wait, and if so, step S1702
Otherwise, the process proceeds to step S1704.

(2) In step S1702, Wa
Execute itBlock.

(3) In step S1703, the following alwayss @ (posseged clock name) begin
n #delayCnt if (Wait_expression) wait (Wait_expression) end A description is generated, and the process ends.

(4) In step S1704, alwayss @ (posedge) #DelayCnt To generate the description.

(5) In step S1705, Wa
It is determined whether it_expression is empty, and if so, to step S1708, otherwise, to step S170.
Processing is transferred to 6.

(6) In step S1706, the following if (Wait_expression) begin wait (Wait_expression) begin
Generate a description n.

(7) In step S1707, la
Determine whether stWaitFlg is empty, and if so, step S
If not, the process proceeds to step S1709.

(8) In step S1708, wait_expression = 1'b0; To generate the description.

(9) In step S1709, La
flg for all flg included in stWaitFlg
= 1′b0;

(10) In step S1710, I
It is determined whether f_expression is empty, and if so, to step S1712, and if not, step S1711.
Process shifts to.

(11) In step S1711, the following description if (If_expression) begin is generated, and the process proceeds to step S1712.

(12) In step S1712, it is determined whether the verification target operation tree includes exi, and if so, the process proceeds to step S1713, and if not, the process proceeds to step S1714.

(13) In step S1713, the following if (! (Boolean expression of signal represented by most_left)) $ display ("Error occurre")
d. "); Is generated, and the process proceeds to step S1715.

(14) In step S1714, the following description if (! (Boolean expression of signal represented by most_left)) is generated, and the process proceeds to step S1715.

(15) In step S1715, W
It is determined whether ait_expression is empty, and if so, to step S1717, otherwise, to step S17.
The process is transferred to 16.

(16) In step S1716, the following description "end" is generated, and the process proceeds to step S1717.

(17) In step S1717, I
It is determined whether f_expression is empty, and if so, to step S1719, and if not, step S1718.
Move the processing to.

(18) In step S1718, the following description "end" is generated, and the process proceeds to step S1719.

(19) In step S1719, the description "end" is generated, and the process ends.

5. TDO2CTL Algolithm FIG. 63 and FIG. 64 show that TDO2CTL Algo
An example of ritm will be described. Figure 63 is TDO2CTL
Flow chart showing Algorithm, Figure 64 is CTL
It is a flowchart which shows a production possibility determination.

As shown in FIG. 63, TDO2CTL A
lgorithm first describes a method for checking whether a verification target operation tree can generate a CTL (step S
1801), then, the modification point of the modification algorithm of the verification target operation tree is described (step S1802), and the algorithm for generating the CTL from the finally obtained verification target operation tree is described (step S1803). However, since there are many parts similar to the Verilog-HDL generation described above,
I will not go into details.

5-1. CTL Generation Possibility Judgment (FIG. 64) (1) In step S1901, it is judged whether or not there is a vertex on the right side in which a cycle past from the left side is specified among the signal vertices of the operation tree to be verified. If not, the process proceeds to step S1904.

(2) In step S1902, AN
Wa below the Boolean vertices of the relation containing D
It is determined whether or not there is an it vertex, and if there is, the step S190.
4, if not, the process proceeds to step S1903.

(3) In step S1903, the rightmost vertex of the operation tree to be verified (called most_left)
If exi is specified for the relation vertex to which is connected, and if the time of the vertex on one side matches the time of the rightmost vertex, then step S1904
Otherwise, the process proceeds to step S1905.

(4) In step S1904, CT
The user is notified that L cannot be generated, and the process ends.

(5) In step S1905, Mo
The closest non-Boolean relat to st_left
All exi specifications other than the ion vertex are deleted, and the process ends.

5-2. Deformation of the verification target motion tree Only the changes and additions in the modification of the verification target motion tree are described. In the modification of the motion tree to be verified, first, the wait vertex information is set to AX: n {A (repetition condition &! Wait cancellation condition Uw for all wait vertices.
ait cancellation condition)}. In particular, n of AX: n is a wait obje.
Corresponds to the number of cycles on the waveform of ct.

Next, each signal vertex is replaced with AX: n (signal name) using the cycle number n. Then, a topological sort is performed to search for the youngest wait vertex or the signal vertex to which the exi is added in order, and the search vertex is divided into the case where it is subordinate to the Boolean operation vertex of relation and the case where it is not, and Do the operation. Basically, the processing is performed while tracing the tree in the depth-first search procedure in the left direction.

1) Boolean operation of relation when searched vertex is lower than vertex: A subtree including the vertex is acquired by the following method.

(1) Boolean operation of relation A relation vertex located immediately below the vertex is selected, and a vertex including the currently targeted wait vertex in the lower order is selected.

(2) Relation selected in (1)
Get a subtree consisting of all subordinate vertices.

Next, the cycle information of the signal vertex whose order obtained by topological sort is larger than that wait vertex is replaced with the relative cycle information according to the order.
Do this within a tree. The same is done for trees with relation vertices located immediately below the Boolean operation vertices of other relations, if a vertex with wait or exi is included.

Further, the replacement with the relative cycle information is similarly performed for the one having a larger order than the Boolean operation vertex of the relation, which uses the procedure of 2).

2) Otherwise, the cycle information of the signal vertex obtained by the topological sort having a higher order than that vertex is replaced with the relative cycle information according to the order. When the operation reaches the Boolean operation vertex of relation, each tree having a relation vertex lower than the Boolean operation vertex of relation as a vertex is independently replaced with relative cycle information. After this operation is completed, the tree is traced again and the relative cycle information is replaced until the Boolean operation vertex of the relation is reached.

In the replacement with the relative cycle information, A
X: n (signal name) is replaced with AY: m (signal name), and m is relative cycle information.

Next, A of the vertex information to which exi is added is replaced with E.

Next, (A->B)-> C is changed to A &B-> C.
In the operation of converting to, when AY, EX, and EY are not included, for example, AX (a) & AX (b) & AX: 2 (c) = AX (a &
b & AX (C)), and squeezing is performed by the number of cycles. If it is included, the following formula transformation rule is used as needed.

P & AY (Q) = P & AX (Q) P & EY (Q) = P & EX (Q) AX (P) & AY (Q) = AX (P & AX (Q)) AX (P) & EY (Q) = AX (P & EX (Q) Q)) AY (P) & AY (Q) = AY (P & AX (Q)) AY (P) & EY (Q) = AY (P & EX (Q)) EX (P) & AY (Q) = EX (P & AX (Q) ) EX (P) & EY (Q) = EX (P & EX (Q)) EY (P) & AY (Q) = EY (P & AX (Q)) EY (P) & EY (Q) = EY (P & EX (Q)) , The formula transformation is performed from the left. For example:

AY (P) & EY (Q) & AY: 2 (R) & EY: 3 (S) = AY (P) & EY (Q) & AY: 2 (R & EX: 3 (S)) = AY (P) & EY ( Q & AX: 2 (R & EX: 3 (S)) = AY (P & EX (Q & AX: 2 (R & EX: 3 (S))) Also, if ‖ is included, both sides of ‖ are regarded as a mass. For example:

AY (P) & EY (Q) & (AY: 2 (R) .parallel.EY: 3 (S)) = AY (P) & EY (Q & (AX: 2 (R) .parallel.EX: 3 (S)) ) = AY (P & EX (Q & (AX: 2 (R) ‖EX: 3 (S))) Note that the AND-OR expression is handled by applying the distributive law to the right side and then from & inside the OR. It can be modified and treated as described above, for example:

AY (P) & EY (Q) & (AY: 2 (R) & EY (R2) .parallel.EY: 3 (S) & AY (S2)) & AY (T) = AY (P) & EY (Q) & ( AY: 2 (R) & EY (R2) & AY (T) ‖EY: 3 (S) & AY (S2) & AY (T)) = AY (P) & EY (Q) & (AY: 2 (R) & EY (R2 & AX) (T) ‖EY: 3 (S) & AY (S2 & AX (T)) = AY (P) & EY (Q) & (AY: 2 (R & EX (R2 & AX (T)) ‖EY: 3 (S & AX (S2 & AX (T)) )) = AY (P) & EY (Q & (AX: 2 (R & EX (R2 & AX (T)) ‖EX: 3 (S & AX (S2 & AX (T)))) = AY (P & EX (Q & (AX: 2 (R & EX (R2 & AX (R2 & AX) (T)) ‖EX: 3 (S & AX (S2 & AX (T))))) AY (P) & EY (Q) & (AY: 2 (R) & ‖EY: 3 (S)) & (AY (T) ‖AY (T2)) & AY (T3) = AY (P) & EY (Q) & (AY: 2 (R) & ‖EY: 3 (S)) & (AY (T & AX (T3)) ‖AY (T2 & AX (T3))) = AY (P) & EY (Q) & (AY: 2 ( R) & AY (T & AX (T3)) ‖AY: 2 (R) & AY (T2 & AX (T3)) ‖EY: 3 (S) & (AY (T & AX (T3) ‖EY: 3 (S) & AY (T2 & AX (T3) ))) = AY (P) & EY (Q) & (AY: 2 (R & AX (T & AX (T3))) ‖AY: 2 (R & AX (T2 & AX (T3))) ‖EY: 3 (S & AX (T & AX (T3)) ) ‖EY: 3 (S & AX (T2 & AX (T3))) = AY (P) & EY (Q & (AX: 2 (R & AX ( T & AX (T3))) ‖AX: 2 (R & AX (T2 & AX (T3))) ‖EX: 3 (S & AX (T & AX (T3) ‖EX: 3 (S & AX (T2 & AX (T3)))) = AY (P & EX ( Q & (AX: 2 (R & AX (T & AX (T3))) ‖AX: 2 (R & AX (T2 & AX (T3))) ‖EX: 3 (S & AX (T & AX (T3) ‖EX: 3 (S & AX (T2 & AX (T3))) ))) Next, regarding the Boolean expression of relation, this is the same as the Verilog-HDL generation.

The above is the change / addition processing in the verification target operation tree.

5-3. Generation of CTL Basically, the processing is performed while following the modified verification target operation tree as in the case of the Verilog-HDL checker generation. Only the outline will be described here.

First, the leftmost vertex of the tree is acquired. The processing of the parts other than the vertex will be described below. While tracing the tree, simply combine the vertex information with &, and relatio
When it reaches the OR operation of n, the following processing is performed, and if it is terminated and there is a continuation, it is simply combined with & again. This is repeated until the leftmost vertex is reached, and the obtained & join formula-> the formula of the leftmost vertex is constructed, and the general formula transformation process is performed.

Processing by the OR operation of relation The subtrees at the lower level of this vertex are identified, and the leftmost end of each tree is acquired. If they do not match, the process is interrupted, and if they match, it is identified whether they match the leftmost vertex acquired earlier.

1) When it coincides with the leftmost end: The & of the vertices of the respective subtrees are joined by & in front of the leftmost end vertex in the order of depth-first search in the left direction. The resulting expression-> the form of the expression of the leftmost vertex is constructed for each subtree,
For example, if there are three sub-trees, (& join expression of sub-tree 1 ‖ sub-tree 2 & join expression ‖ sub-tree 3
&& Formula of-)-> Construct the formula of the leftmost vertex, and join it with && formula obtained up to now with & to proceed to the general formula transformation process.

2) If they do not match, the & of the vertices of each subtree are joined by & in the order of depth-first search in the left direction. For example, if there are three sub-trees, (& join expression of sub-tree 1 ‖ sub-tree 2 & join expression ‖ sub-tree 3
& Join expression of) and join this with the & join expression obtained so far.

In the general expression transformation process, Y is added to the expression of the leftmost vertex.
If there is, the obtained & join expression-> the expression of the leftmost vertex is
The obtained & combined expression-> (obtained & combined expression) & is transformed into the expression of the leftmost vertex, and the expression transformation processing is performed from the right side for the expressions before and after-> as in the expression transformation at the vertex. At this time, the transformation rule used in the equation transformation of the vertex and the following equation transformation rule are appropriately applied to remove Y. Substituting the obtained modified formula into the corresponding formulas at both ends of->, the CTL is obtained. If there is no Y, it may be output as it is.

A (P1UP2) & AY (Q) = A (P1
U (P2 & AX (Q)) A (P1UP2) & EY (Q) = A (P1U (P2 & E
X (Q)) E (P1UP2) & AY (Q) = E (P1U (P2 & A
X (Q)) E (P1UP2) & EY (Q) = E (P1U (P2 & E
X (Q)) For example,

[0263]       P & AY (Q) & AY: 2 (A (P1UP2)) & EY (S) & EY (A (P3UP4) & AY (T)-> AY: 2 (O) From       P & AY (Q) & AY: 2 (A (P1UP2)) & EY (S) & EY (A (P3UP4) & AY (T) and       P & AY (Q) & AY: 2 (A (P1UP2)) & EY (S) & EY (A (P3UP4) & AY (T) & AY: 2 (O) Make up. further,       P & AY (Q) & AY: 2 (A (P1UP2)) & EY (S) & EY (A (P3UP4) & AY (T)       = P & AY (Q) & AY: 2 (A (P1UP2)) & EY (S) & EY ( A (P3UP4 & AX (T)))       = P & AY (Q) & AY: 2 (A (P1UP2)) & EY (S & EX (A (P3UP4 & AX (T))))       = P & AY (Q) & AY: 2 (A (P1U (P2 & EX (S & EX (A ( P3UP4 & AX (T)))))))       = P & AY (Q & AX: 2 (A (P1U (P2 & EX (S & EX (A (P 3UP4 & AX (T))))))))       = P & AX (Q & AX: 2 (A (P1U (P2 & EX (S & EX (A (P 3UP4 & AX (T))))))))       P & AY (Q) & AY: 2 (A (P1UP2)) & EY (S) & EY (A (P3UP4) & AY (T) & AY: 2 (O)       = P & AY (Q) & AY: 2 (A (P1UP2)) & EY (S) & EY ( A (P3UP4) & AY (T & AX: 2 (O))       = P & AY (Q) & AY: 2 (A (P1UP2)) & EY (S) & EY ( A (P3U (P4 & AX (T & AX: 2 (O)))))       = P & AY (Q) & AY: 2 (A (P1UP2)) & EY (S & EX (A (P3U (P4 & AX (T & AX: 2 (O))))))       = P & AY (Q) & AY: 2 (A (P1U (P2 & EX (S & EX (A ( P3U (P4 & AX (T & AX: 2 (O)))))))))       = P & AY (Q & AX: 2 (A (P1U (P2 & EX (S & EX (A (P 3U (P4 & AX (T & AX: 2 (O))))))))))       = P & AX (Q & AX: 2 (A (P1U (P2 & EX (S & EX (A (P 3U (P4 & AX (T & AX: 2 (O)))))))))) Therefore,       P & AX (Q & AX: 2 (A (P1U (P2 & EX (S & EX (A (P3 UP4 & AX (T))))))))         -> P & AX (Q & AX: 2 (A (P1U (P2 & EX (S & EX (A (P3U (P4 & AX (T & AX: 2 (O))))))))))) CTL is obtained.

Therefore, according to the function verification description generation apparatus of the present embodiment, the designer or the person in charge of verification can perform HD processing on the timing diagram editing apparatus 2 which is relatively operable for verification.
The terminal and internal pin information obtained from the description of L is selected, and on the timing diagram editing device 2, the waveform of the signal of the selected terminal or internal pin, the logical relationship between these waveforms, and this logical relationship. It is possible to create and edit the timing diagram on the timing diagram editing device 2 while inputting the occurrence information indicating whether or not is always satisfied or is satisfied at least once.

Therefore, the timing diagram editing device 2 can clearly describe the verification item on the timing diagram, and thereby the ambiguity of the expression of the verification item can be eliminated. Therefore, accurate information can be exchanged between the designer and the person in charge of verification, and human error can be eliminated.

Further, the verification target operation extraction device 3 uses the timing diagram editing device 2 to logically analyze the waveforms from the timing diagram information sent from the timing diagram editing device 2 edited by the designer or the person in charge of verification. The verification description generation device 4 extracts the relationship, the terminal and internal pin information including the waveform in which this logical relationship is designated, and the occurrence information whether this logical relationship is always established or is established at least once. Logical relationship of waveforms supplied from the verification target operation extraction device 3, information on terminals and internal pins including waveforms in which this logical relationship is designated, and whether this logical relationship is always established or is established at least once. It is possible to automatically generate the functional verification description based on the occurrence information and the like.

Therefore, the verification description generation device 4 or the like edits the timing diagram using the timing diagram editing device 2 and edits the circuit operation even if the designer or the person in charge of verification does not know the HDL or the verification description language other than HDL. The functional verification description can be generated by performing the operation conventionally performed by the designer or the person in charge of verification for clarifying the verification content of. Therefore, the verification description generation device 4 reduces the function verification work load on the designer and the person in charge of verification,
It is possible to reduce the design cost by improving the function verification efficiency and further reduce the product production cost.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, the present invention is not limited to the technique described in the above embodiments, but can be applied to all digital circuits, and further, from the creation of design specifications and function inspection specifications to HDL and coding. It can be applied to a wide range of technologies including debugging work performed later.

[0270]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1) Since the timing diagram editing means can clearly describe the verification items on the timing diagram, and the ambiguity of the expression of the verification items can be eliminated by this, the designer and the person in charge of verification. Accurate information exchange between persons is possible, and human error can be eliminated.

(2) Even if the designer or the person in charge of verification does not know the HDL or the verification description language other than HDL, the verification description generating means, etc., edits the timing diagram using the timing diagram editing means to check the circuit operation. The function verification description can be generated by performing the operation that the designer and the person in charge of verification clarify the contents of verification, which reduces the burden of the function verification work on the designer and person in charge of verification. However, it is possible to reduce the design cost by improving the function verification efficiency and further reduce the production cost of the product.

(3) The verification person newly adds HDL or HDL
A designer who has already learned HDL can learn a verification description language other than HDL without learning a verification description language other than
It is possible to provide a functional verification description generation device capable of creating a functional verification description for verifying a functional verification item of a verification target circuit without performing verification of the functional verification description itself described in HDL.

(4) It becomes possible for the designer and the person in charge of verification to provide a description method that clearly and uniformly describes the verification contents of the circuit operation using the timing diagram.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a function verification description generation device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a circuit example for explaining a compare object in the functional verification description generation device according to the embodiment of the present invention.

FIG. 3 is an explanatory diagram of an example of a timing diagram for explaining a compare object in the functional verification description generation device according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram of an example of a timing diagram for explaining a weight object in the functional verification description generation device according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram of a check box example for explaining a weight object in the function verification description generation device according to the embodiment of the present invention.

FIG. 6 is a flowchart showing a configuration of a verification target operation tree and its modification in the function verification description generation device according to the exemplary embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a hierarchical tree in storing HDL terminal information in the functional verification description generation device according to the embodiment of the present invention.

8 is an explanatory diagram showing terminal information associated with the hierarchical tree of FIG. 7 in the functional verification description generation device according to the embodiment of the present invention. FIG.

FIG. 9 is an explanatory diagram showing a timing diagram example (1) in storing a timing diagram in the functional verification description generation device according to the embodiment of the present invention.

FIG. 10 is an explanatory diagram showing a timing diagram example (2) in storing a timing diagram in the functional verification description generation device according to the embodiment of the present invention.

FIG. 11 is an explanatory diagram showing a timing diagram example (3) in storing a timing diagram in the functional verification description generation device according to the embodiment of the present invention.

FIG. 12 is an explanatory diagram showing a timing diagram example (4) in storing a timing diagram in the functional verification description generation device according to the embodiment of the present invention.

FIG. 13 is an explanatory diagram showing a timing diagram example (5) in storing a timing diagram in the functional verification description generation device according to the embodiment of the present invention.

FIG. 14 is an explanatory diagram showing a timing diagram example (6) in storing a timing diagram in the functional verification description generation device according to the embodiment of the present invention.

FIG. 15 is an explanatory diagram showing a timing diagram example (7) in storing a timing diagram in the functional verification description generation device according to the embodiment of the present invention.

FIG. 16 is an explanatory diagram showing a timing diagram example (8) in storing a timing diagram in the functional verification description generation device according to the embodiment of the present invention.

FIG. 17 is an explanatory diagram showing a timing diagram example (9) in storing a timing diagram in the functional verification description generation device according to the embodiment of the present invention.

FIG. 18 is an explanatory diagram showing a timing diagram example (10) in storing a timing diagram in the functional verification description generation device according to the embodiment of the present invention.

FIG. 19 is an explanatory diagram showing a timing diagram example (11) in storing a timing diagram in the functional verification description generation device according to the embodiment of the present invention.

FIG. 20 is an explanatory diagram showing a timing diagram division example in the functional verification description generation device according to the embodiment of the present invention.

FIG. 21 is an explanatory diagram showing a storage image of a timing diagram in the functional verification description generation device according to the embodiment of the present invention.

22 is an explanatory diagram showing a storage image of a timing diagram following FIG. 21 in the functional verification description generation device according to the embodiment of the present invention. FIG.

FIG. 23 is a flowchart showing the operation of the timing diagram dividing means in the functional verification description generation device according to the embodiment of the present invention.

FIG. 24 is a flowchart showing the operation of the verification target operation information acquisition unit in the extraction of the verification target operation in the functional verification description generation device according to the embodiment of the present invention.

FIG. 25 is an explanatory diagram showing a storage image of verification target operation information in the function verification description generation device according to the embodiment of the present invention.

FIG. 26 is an explanatory diagram showing a storage image of a tree structure created from a verification target operation in the functional verification description generation device according to the exemplary embodiment of the present invention.

FIG. 27 is an explanatory diagram showing a storage image of a tree structure created from the verification target operation subsequent to FIG. 26 in the functional verification description generation device according to the exemplary embodiment of the present invention.

FIG. 28 is a diagram showing a functional verification description generation device according to an embodiment of the present invention, in which TDO2Verilog Algorithm
It is a flowchart which shows hm.

FIG. 29 is a flowchart showing allocation of storage variables in the functional verification description generation device according to the embodiment of the present invention.

FIG. 30 is a flowchart showing calculation of the number of storage cycles in the function verification description generation device according to the embodiment of the present invention.

FIG. 31 is an explanatory diagram showing a table structure for calculating the number of storage cycles in the function verification description generation device according to the embodiment of the present invention.

FIG. 32 is a flowchart showing Wait control flag generation / initial value determination in the function verification description generation device according to the embodiment of the present invention.

FIG. 33 is an explanatory diagram showing a table structure in the Wait control flag generation / initial value determination in the function verification description generation device according to the embodiment of the present invention.

FIG. 34 is a flowchart showing initial value determination in the function verification description generation device according to the embodiment of the present invention.

FIG. 35 is a flowchart showing variable declaration HDL description generation in the function verification description generation device according to the embodiment of the present invention.

FIG. 36 is a flowchart showing generation of a variable value storage HDL description in the functional verification description generation device according to the embodiment of the present invention.

FIG. 37 is a flowchart showing graph transformation in the function verification description generation device according to the embodiment of the present invention.

FIG. 38 is an explanatory diagram showing graph transformation in the function verification description generation device according to the embodiment of the present invention.

FIG. 39 is a graph showing a relation transformation (relation bool) in the function verification description generation device according to the embodiment of the present invention.
It is an explanatory view showing identification of ean).

40A and 40B are graph transformations ((A->) in the functional verification description generation device according to the exemplary embodiment of the present invention.
It is explanatory drawing which shows the transformation of B)-> C into A->(B-> C).

41 (a) and 41 (b) are graph transformations ((A->) in the functional verification description generation device according to the exemplary embodiment of the present invention.
It is explanatory drawing which shows the transformation (continuation) of B)-> C to A->(B-> C).

42A and 42B are graph transformations (A-> (B) in the functional verification description generation device according to the embodiment of the present invention.
It is an explanatory view showing a transformation of-> C) to A &B-> C).

43 (a) and (b) are graph transformations (relat) in the functional verification description generation device according to the embodiment of the present invention.
It is explanatory drawing which shows the deformation | transformation using ion Boolean.

44 (a) and 44 (b) are graph transformations (relat) in the functional verification description generation device according to the embodiment of the present invention.
It is explanatory drawing which shows the deformation | transformation using ion Boolean (remaining).

45 (a), (b) and (c) are graph transformations (r) in the function verification description generation device according to the embodiment of the present invention.
It is explanatory drawing which shows the modification (continuation) using the elimination Boolean (remaining).

FIG. 46 is an explanatory diagram showing graph transformation (interim result of graph transformation) in the function verification description generation device according to the embodiment of the present invention.

[Fig. 47] Fig. 47 is a graph showing a relationship transformation graph in the functional verification description generation device according to the embodiment of the present invention.
It is explanatory drawing which shows the deformation | transformation which used ean again.

48 (a) and 48 (b) are graph transformations (relat) in the function verification description generation device according to the embodiment of the present invention.
It is an explanatory view showing the recursive execution of the processing of ion Boolean).

49 (a) and (b) are graph transformations (wait) in the functional verification description generation device according to the embodiment of the present invention.
It is explanatory drawing which shows the transformation of A->(B-> C) into A &B-> C when an object is contained.

FIG. 50 is a graph transformation (lowermost wait of subtree) in the function verification description generation device according to the embodiment of the present invention.
It is an explanatory view showing identification of object).

FIG. 51 is an explanatory diagram showing graph transformation (interim result of graph transformation) in the function verification description generation device according to the embodiment of the present invention.

FIG. 52 is an explanatory diagram showing graph transformation (graph transformation (order determination) in the entire verification target operation tree) in the functional verification description generation device according to the embodiment of the present invention.

FIG. 53 is a graph transformation (graph transformation ((A->B)-> C in A->(B-> C) of the entire verification target operation tree) in the function verification description generation device according to the embodiment of the present invention; It is explanatory drawing which shows the transformation to))).

FIG. 54 is a graph transformation (graph transformation in the entire verification target operation tree (transformation of A->(B-> C) to A &B-> C) in the functional verification description generation device according to the embodiment of the present invention; FIG.

FIG. 55 is a flowchart showing generation of verification HDL in the functional verification description generation device according to the exemplary embodiment of the present invention.

FIG. 56 is a flowchart showing Property_sample in the function verification description generation device according to the embodiment of the present invention.

FIG. 57 is a flowchart showing Property_wait in the function verification description generation device according to the embodiment of the present invention.

FIG. 58 is a flowchart showing WaitBlock in the functional verification description generation device according to the embodiment of the present invention.

FIG. 59 is a flowchart showing WaitBlock following FIG. 58 in the function verification description generation device according to the embodiment of the present invention.

FIG. 60 is a flowchart showing WaitORBlock in the functional verification description generation device according to the embodiment of the present invention.

FIG. 61 is a flowchart showing WaitORBlock following FIG. 60 in the functional verification description generation device according to the exemplary embodiment of the present invention.

FIG. 62 is a flowchart showing ConseqBlock in the function verification description generation device according to the embodiment of the present invention.

FIG. 63 is a flowchart showing TDO2CTL Algorithm in the functional verification description generation device according to the exemplary embodiment of the present invention.

FIG. 64 is a flowchart showing CTL generation possibility determination in the function verification description generation device according to the embodiment of the present invention.

[Fig. 65] Fig. 65 is an explanatory diagram showing an outline of a technique of the publication for comparing the technique of the present invention and the technique of the publication.

FIG. 66 is an explanatory diagram showing an outline of the technique of the present invention for comparing the technique of the present invention with the technique of the publication.

[Explanation of symbols]

1-terminal information extraction device 2 Timing diagram editing device 3 Verification target motion extraction device 4 Verification description generator 5 Verification description file 11 HDL reader 12 HDL storage device 13-terminal information extraction device 14-terminal information storage device 31 Timing diagram storage 32 Verification target motion information extraction device 33 Verification target operation information storage device

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kei Suzuki             1-280, Higashikoigakubo, Kokubunji, Tokyo             Central Research Laboratory, Hitachi, Ltd. (72) Inventor Masaki Ito             1-280, Higashikoigakubo, Kokubunji, Tokyo             Central Research Laboratory, Hitachi, Ltd. (72) Inside the inventor             1-280, Higashikoigakubo, Kokubunji, Tokyo             Central Research Laboratory, Hitachi, Ltd. F-term (reference) 5B046 AA08 BA03

Claims (8)

[Claims] 1. A first inputting logical relationship between waveforms and occurrence information of the logical relationship to a timing diagram.
And a second means for generating a verification description from a timing diagram based on a logical relationship between the waveforms and the occurrence information of the logical relationship. 2. The function verification device according to claim 1, wherein the first means reads design data in HDL format to be verified, and a terminal and an internal part provided in the read design data in HDL format to be verified. Regarding the pin, at least a terminal name, an internal pin name, a distinction between input and output, and terminal information extraction means for obtaining each terminal and internal pin information of the number of bits of the input / output signal and the internal pin name, and connecting to the terminal information extraction means Then, the terminal and internal pin information acquired by the terminal information extracting means is selected, and regarding the signal input and output through the terminal and the internal pin, timing constraint information regarding the timing including the signal and the waveform, and between the waveforms. By inputting the logical relationship information of and the occurrence information of whether this logical relationship is always established or is established at least once, H to be verified
And a timing diagram editing means for editing a timing diagram in design data in DL format. 3. The function verification device according to claim 2, wherein the second means is connected to the timing diagram editing means, and the terminals and internal pin information, the timing constraint information, from the timing diagram editing means, Verification target operation extraction means for extracting verification target operation information consisting of logical relationship information between the waveforms and occurrence information of the logical relationship, and connected to the verification target operation extraction means, based on the verification target operation information A function verification description for verifying whether the verification target operation expressed in a verification description language is satisfied or a function verification description for verifying whether the verification target operation in HDL format is satisfied is generated. A verification description generation means, and a function verification device characterized by including. 4. The function verification device according to claim 1, wherein at the time of creating the timing diagram, it is possible to describe while inserting an object prepared in advance, and an operation specification checker HDL description used for function verification from created data, and A function verification device characterized by automatically generating a property language description used in model checking, checking internal operations, and checking whether a signal transition that an external input signal should satisfy is being observed. 5. The function verification device according to claim 4, wherein the object is a value at a start point or an end point of a relation object of a signal waveform drawn on the timing diagram, and the value on the timing diagram. A functional verification device characterized in that it includes a signal object capable of expressing the cycle number. 6. The function verifying device according to claim 4, wherein the object is set on a signal waveform drawn on the timing diagram so that a signal value comparison or the like is performed with respect to the set signal value. A functional verification device comprising a compare object capable of describing a comparison operation. 7. The functional verification device according to claim 4, wherein the object can be designated with respect to a rising edge of a clock signal drawn in the timing diagram, and a predetermined condition is satisfied until a predetermined condition is satisfied. A functional verification device comprising a weight object capable of representing that a signal value of a cycle is repeatedly executed. 8. The function verifying device according to claim 4, wherein the object includes a relation object capable of representing a logical relationship between signal waveforms drawn on a timing diagram. .