JP2003216673A - Apparatus and method for designing semiconductor integrated circuit, and medium recording semiconductor integrated circuit design program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that only simple timing adjustment can be performed because timing adjustment is performed considering a cross-talk noise after completing the block layout in a conventional technique. <P>SOLUTION: In a device to design a semiconductor integrated circuit by a computer programmed to optimize the timing of the lower hierarchy based on the timing information on the boundary between the lower hierarchy and the upper hierarchy by using the logical information of the semiconductor integrated circuit of a hierarchical structure, delayed fluctuation caused by the cross-talk noise of the upper hierarchy is included in the timing information on the boundary. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design technique for optimizing the timing of a semiconductor integrated circuit, and more particularly to the design of a semiconductor integrated circuit for performing an appropriate timing design against delay variation due to crosstalk noise inside the semiconductor integrated circuit. The present invention relates to an apparatus and method, and a medium in which a design program for a semiconductor integrated circuit is recorded.

In recent years, the degree of integration of semiconductor integrated circuits (LSIs) has been improved, and various functions have been mounted on one chip. In designing such a multi-functional LSI, since development is performed in parallel for each functional block in order to shorten the development period, an LS having a functional block hierarchy is provided.
It is necessary to design I. In this hierarchical design, timing adjustment between blocks is important and
It is desired to provide a design technology for a semiconductor integrated circuit that performs an appropriate timing design with respect to delay variation due to internal crosstalk noise.

[0003]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit having a hierarchical structure in which various functions are mounted on one chip has been provided. In a hierarchical design, timing must be coordinated between blocks so that the signals that cross the blocks will get their values into the next register at the correct clock edge.

By the way, in recent years, as the miniaturization of semiconductor circuits has progressed, the ratio of inter-wiring capacitance values has increased, and the variation in delay time of inter-block wiring has also increased due to crosstalk noise.

FIG. 1 is a flow chart showing an example of a conventional semiconductor integrated circuit design process.

As shown in FIG. 1, the conventional method for designing a semiconductor integrated circuit is such that the RTL is performed in step ST101.
(Register Transfer Logic) information is prepared (RTL design of the semiconductor integrated circuit is completed), block / pin arrangement is performed in step ST102, and further step S
Proceeding to T103, wiring between blocks is executed.

FIG. 2 is a block diagram schematically showing an example of a semiconductor integrated circuit having a hierarchical structure. In FIG. 2, reference numeral 200 indicates a semiconductor integrated circuit (chip), and 210,
Reference numerals 220, 230 and 240 denote blocks (circuit blocks, functional blocks). As shown in FIG. 2, the semiconductor integrated circuit 200 includes a block A (210) and a block B.
(220), block C (230), and block D (240), and each block 210-240 has pins (AP1, AP2; BP1, BP2; CP1, CP).
2; DP1, DP2) and inter-block wiring (L1, L
2, L3, L4) and is connected to another block.
Each block (for example, the block 220) is connected to the external pin (EX) via the pin (BP3) and the wiring (L5).
P1).

That is, in the above-mentioned step ST102, the blocks 210 to 240 and the pins (AP1, AP2; BP1, BP2; CP1, CP) of these blocks are included.
2; DP1, DP2) are arranged, and step S
At T103, inter-block wiring (L1, L2, L3, L
Execute 4).

Next, as shown in FIG. 1, step S
Proceeding to T105, the inter-block wiring delay value is calculated using the delay information (step ST104) that does not include crosstalk noise. Further, the process proceeds to step ST106, the block timing constraint is applied, and step ST1
At 07, logic synthesis is performed including RTL information (step ST101) to obtain a netlist (step S
T108). Then, the process proceeds to step ST109 to lay out the blocks.

Then, in step ST110, the crosstalk noise is calculated, and the process proceeds to step ST111 to correct the layout.

FIG. 3 is a diagram showing a part of the circuit in the semiconductor integrated circuit of FIG. 2. Part (flip-flops (latch) 211, 212 and logic circuit in the block A (210) of the semiconductor integrated circuit of FIG. 213) is an example of a logically synthesized netlist. In addition, in the example of FIG.
The logic circuit 213 is an exclusive OR (EXOR)
It is composed of a gate 2131, an AND gate 2132 and an OR gate 2133, and the output of the OR gate 2133 is connected to the pin AP1 of the block A.

[0012]

As described above, FIG.
In the conventional semiconductor integrated circuit design process shown in (1), after the block layout is completed in step ST109, the process proceeds to step ST110 to perform delay analysis in consideration of crosstalk noise. If the timing is violated, the process proceeds to step ST111 to correct the layout or replace the semiconductor element (cell).
The timing was adjusted by adding / deleting.

As described above, in the prior art, since the timing adjustment is performed in consideration of the crosstalk noise after the block layout is completed, only simple timing adjustment can be performed, and if there is a large delay variation. , There was a danger that the timing of signals between blocks could not be met.

An object of the present invention is to provide a semiconductor integrated circuit capable of performing an appropriate timing design with respect to delay variation due to crosstalk noise inside the semiconductor integrated circuit, in view of the problems of the conventional design processing of the semiconductor integrated circuit described above. To provide circuit design technology.

[0015]

According to a first aspect of the present invention, logical information of a semiconductor integrated circuit having a hierarchical structure is used,
An apparatus for designing a semiconductor integrated circuit by a programmed computer for optimizing timing of a lower layer based on timing information of a boundary between the lower layer and an upper layer, wherein the timing information of the boundary includes There is provided a semiconductor integrated circuit designing device including a delay variation due to crosstalk noise of an upper layer.

According to the second aspect of the present invention, the logic information of the semiconductor integrated circuit having the hierarchical structure is used, and the timing optimization of the lower layer is performed based on the timing information of the boundary between the lower layer and the upper layer. A method for designing a semiconductor integrated circuit, wherein the timing information at the boundary includes delay variation due to crosstalk noise in the upper layer is provided. .

According to a third aspect of the present invention, there is provided a medium for recording a program to be executed by a computer, wherein the program uses logical information of a semiconductor integrated circuit having a hierarchical structure, and optimizes timing of a lower hierarchy. A semiconductor integrated circuit is designed based on timing information at the boundary between the lower layer and the upper layer, and the timing information at the boundary includes delay variation due to crosstalk noise in the upper layer. There is provided a medium having a semiconductor integrated circuit design program recorded therein.

FIG. 4 is a flow chart for explaining the principle of the semiconductor integrated circuit according to the present invention.

As shown in FIG. 4, in the semiconductor integrated circuit design process according to the present invention, first, in step ST1, initial logic information (information such as RTL and netlist) is prepared, and in step ST2, blocks / pins are prepared. Arrangement is performed, and further, in step ST3, inter-block wiring information is extracted.

Next, in step ST5, the inter-block wiring delay value is calculated using the delay information (step ST4) including crosstalk noise. Further, in step ST6, the block timing is optimized, in step ST7, the logic synthesis is performed including the initial logic information (step ST1), and then in step S
Proceeding to T8, the logic information after optimization is obtained.

As is clear from the comparison between FIG. 4 and FIG.
In the present invention, the block layout (step ST in FIG.
109: Predict the delay variation amount due to crosstalk noise in the inter-block wiring (wiring in the upper layer (between blocks)) at the stage of logic design before the lower layer (layout in each block) (step ST4 : Using the delay information including crosstalk noise), timing optimization inside the block is performed.

That is, first, the initial logical information (step ST
Blocks and pins are arranged from 1) (step ST2), and wiring information between blocks is extracted from this (step ST3). Here, the wiring information between blocks refers to the wiring length, the degree of wiring congestion, the wiring interval, the wiring capacity, and the like.

Further, in the present invention, a delay information file for calculating the delay from the wiring information is prepared separately (step ST4), and this delay information contains the delay variation due to crosstalk noise. . Step ST
In 5, the delay value of the inter-block wiring is calculated from the delay information (step ST4) and the wiring information (step ST3). Then, in step ST6, a block timing constraint is generated based on the wiring delay value calculated in step ST5, and block timing optimization is executed in step ST7.

According to the present invention, the influence of the crosstalk noise of the inter-block wiring (delay information including the crosstalk noise) can be dealt with by optimizing the logic in step ST7. Therefore, as in the prior art shown in FIG. , Calculate crosstalk noise after layout (step ST110)
The degree of freedom in optimization can be increased, and as a result, for example, the timing of a path crossing a block can be easily satisfied.

That is, according to the present invention, since the logic information can be optimized by the timing constraint considering the delay variation due to the crosstalk noise, it is easy to design the semiconductor integrated circuit satisfying the timing specification between blocks. You can

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor integrated circuit designing apparatus and method according to the present invention, and a medium in which a semiconductor integrated circuit designing program is recorded will be described in detail with reference to the accompanying drawings.

FIG. 5 is a flow chart showing a first embodiment of the semiconductor integrated circuit design processing according to the present invention.

As shown in FIG. 5, in the method of designing a semiconductor integrated circuit according to the first embodiment, RTL information is prepared in step ST11 (the RTL design of the semiconductor integrated circuit is completed), and the block is stored in step ST12. / Pin arrangement, that is, the block arrangement and the pin position at the boundary with the upper hierarchy are determined. Here, the RTL information is written in a logical description language with a hierarchical structure. Further, in step ST13, the inter-block wiring length is calculated, that is, the inter-block wiring length is predicted (calculated) from the pin positions. This prediction method is performed, for example, by obtaining the Manhattan length from the coordinates of the two pins.

Information on the wiring length dependency of the wiring delay value including the inter-block wiring length thus obtained in step ST13 and the crosstalk noise delay variation calculated in advance (wiring length vs. crosstalk noise). Delay information: From step ST14) to step ST15, the delay value of the inter-block wiring is calculated. And this step ST
The delay value calculated in 15 is regarded as the delay value of the inter-block wiring, the timing constraint of the boundary of each block is determined in step ST16, and the process proceeds to step ST17 to perform the logical synthesis of the block, and the netlist. Is obtained (step ST18).

FIGS. 6, 7 and 8 are views for explaining the first embodiment shown in FIG. 5, and the first embodiment will be specifically described.

In the block arrangement shown in FIG. 6, the pin coordinates AP
If the Manhattan lengths of 10 and BP10 are calculated and the length of the inter-block wiring L10 is estimated to be 2 mm, for example, the wiring length dependence graph of the wiring delay value including the crosstalk noise delay variation shown in FIG. Therefore, the wiring delay value corresponding to the wiring length of 2 mm is 250 ps (minimum value) to
It is calculated to be 550 ps (maximum value). Here, reference numerals 110 and 120 denote blocks 11 and 1, respectively.
2 shows a latch (flip-flop) in 2.

Here, for example, the clock cycle (one cycle of the clock CLK) of the path passing through the wiring L10 is 200.
Assuming that the clock skew is 0 ps, the clock skew is 300 ps, and the number of logical stages inside the block A (11) and the block B (12) is the same, each block 1
The timing constraints of 1 and 12 are obtained as follows.

That is, as shown in FIG. 8, the maximum delay of the block A (11) is (2000 ps-300 p).
s-550ps) / 2 = 575ps, and the minimum delay of the block A is (300ps-250ps) / 2.
= 25 ps. The same calculation is performed for block B (12).

In the above, logic synthesis from RTL has been described as an example of timing optimization, but it can be applied to the case where the netlist after logic synthesis is further optimized. In addition, although the maximum delay that increases the delay and the minimum delay that decreases the delay are targeted, the LSI to be designed
Depending on the case, it may be applied only when the delay increases, or may be applied only when the delay decreases.

FIG. 9 is a flow chart showing a second embodiment of the semiconductor integrated circuit design processing according to the present invention.

As is clear from the comparison between FIG. 9 and FIG.
A method of designing a semiconductor integrated circuit according to the second embodiment is shown in FIG.
Step ST12 and step ST1 of the first embodiment shown in FIG.
Step ST20 is inserted between 3 and 3.

In the second embodiment, step ST1
After performing block / pin arrangement in step 2, step ST20
Proceed to step to perform inter-block wiring, and then step S
At T13, the wiring length between blocks is calculated. That is, in the second embodiment, the wiring length is calculated by actually performing the wiring (step ST20) instead of predicting the pin position as in the first embodiment described above. ing. As a result, the accuracy of the wiring length can be improved and a more accurate delay value can be used.

FIG. 10 is a flow chart showing a third embodiment of the semiconductor integrated circuit design processing according to the present invention.

As is clear from the comparison between FIG. 10 and FIG. 5, the semiconductor integrated circuit designing method according to the third embodiment is
A new step ST30 is provided as step ST13 of the first embodiment shown in FIG.

In the third embodiment, step ST1
After performing block / pin arrangement in step 2, step ST30
Then, the inter-block wiring length and the inter-block wiring congestion degree are calculated. That is, in the third embodiment, the wiring delay is calculated in consideration of not only the wiring length but also the congestion degree of the wiring as in the first embodiment described above. Here, the wiring congestion degree refers to a parameter that indicates a higher number as the distance between adjacent wirings is narrower.

11 and 12 are views for explaining the third embodiment shown in FIG. In FIG. 11, reference numerals L11 to L13 and L21 to L23 are blocks A.
The wiring between (11) and block B (12) is shown.

In the third embodiment, the wirings L11 to L13 having the wiring congestion degree α and the wiring L21 having the wiring congestion degree β in FIG.
To L23 are determined to determine the amount of crosstalk noise delay variation, and after the pin position of the block is determined in step ST12, a rough wiring path (wiring length) is obtained,
The density of the wiring is calculated, that is, the wiring congestion degree α (when the wiring is dense) and the wiring congestion degree β (when the wiring is sparse). Here, when the wiring congestion degree is high (α: wirings L11 to L13), the capacitance value between the wirings becomes high, and therefore the delay variation amount due to the crosstalk noise becomes large. Conversely, the degree of wiring congestion is low (β: wiring L
21 to L23), the capacitance value between the wirings becomes low, so that the delay variation amount due to the crosstalk noise becomes small.

That is, as shown in FIG. 12, in the wiring length dependency graph of the wiring delay value including the crosstalk noise delay variation, different curves are used according to the wiring congestion degrees α and β. Become. Therefore, the timing constraint of the block can be obtained with higher accuracy by considering the wiring congestion degree.

In the above description, the wiring congestion degree is obtained before execution of the block wiring. However, if the congestion degree is obtained after execution of the wiring, the timing constraint can be calculated with higher accuracy. Furthermore, the wiring congestion levels are α and β.
Needless to say, it is not limited to these two.

FIG. 13 is a flow chart showing a fourth embodiment of the semiconductor integrated circuit design processing according to the present invention.

As is apparent from the comparison between FIG. 13 and FIG. 9, the semiconductor integrated circuit designing method according to the fourth embodiment is
A new step ST40 is provided as step ST13 of the second embodiment shown in FIG.

In the fourth embodiment, step ST1
Block / pin arrangement is performed in step 2, and then step ST
After performing inter-block wiring in step 20, step ST40
Next, the adjacent wiring length of the inter-block wiring is calculated. That is, in the fourth embodiment, attention is paid to the adjacent wiring of the inter-block wiring in which delay variation due to crosstalk noise is a problem, the inter-block wiring adjacent wiring length in question is calculated, and the adjacent wiring length vs. crosstalk is calculated. The inter-block wiring delay value is calculated in step ST15 using the noise delay information (step ST41).

14 and 15 are views for explaining the fourth embodiment shown in FIG.

In the method of designing a semiconductor integrated circuit according to the fourth embodiment, after the inter-block wiring is executed in step ST20, the process proceeds to step ST40 to calculate the adjacent wiring length of the inter-block wiring. Here, the adjacent wiring length is
For example, it refers to the length of the wires that are separated by a specific distance (for example, the minimum wiring pitch). That is, FIG.
, Block A (11) and block B (1
When all the wirings have a specific interval (for example, the minimum wiring pitch) like the wirings L11 to L13 connecting 2), all the wiring lengths (distances between blocks) are the adjacent wiring lengths (2
mm). On the other hand, in FIG. 14, the block A (1
1) and the wirings L21 to L2 connecting the block B (12)
As shown in FIG. 3, even if the distance between blocks (all wiring lengths) is the same, a specific interval at which delay variation due to crosstalk noise poses a problem is a part of the wirings L21 to L23 (length Lb: 1 mm, for example). ), That is, the wiring L2
In the other portions (length La: 1 mm, for example) of 1 to L23, when the interval between adjacent wirings is wide and the delay variation due to crosstalk noise hardly poses a problem, the delay variation due to the crosstalk noise becomes a problem. The length (Lb) of the wirings L21 to L23 having a specific interval is the adjacent wiring length (1 mm).

That is, as shown in FIG. 14, even if the wiring length (distance between blocks) is the same, the delay variation due to the crosstalk noise differs depending on the adjacent wiring length. Therefore, as shown in FIG. 15, a graph of the wiring length dependency of the delay value without crosstalk noise and an adjacent wiring length dependency graph of the crosstalk noise delay value are prepared, and the crosstalk is calculated from these two graphs. Calculate noisy wiring delay.

Specifically, as shown in FIGS. 14 and 15A and 15B, the wirings L11 to L13 are provided.
When the wiring length is 2 mm and the adjacent wiring length is 2 mm, the maximum delay is 400 ps + 150 ps = 550 ps and the minimum delay is 400 ps−150 ps = 250 ps.
Becomes In addition, the wiring length such as the wirings L21 to L23 is 2
If the adjacent wiring length is 1 mm, the maximum delay is 400 p.
s + 50ps = 450ps, minimum delay is 400p
s−50 ps = 350 ps.

As described above, in the fourth embodiment, the delay value can be obtained with higher accuracy by obtaining the delay value from the adjacent wiring length. In the above explanation,
Although the distance between the wirings (adjacent wirings) when the wiring is performed at the minimum wiring pitch is used as a parameter, the wiring pitches of a plurality of pitches such as the second pitch and the third pitch are used in addition to the minimum pitch. The crosstalk noise delay can be calculated by using, as parameters, graphs as shown in FIGS. 15A and 15B for each. Further, the use of two pieces of delay information without crosstalk noise and crosstalk noise delay value information as in the fourth embodiment is directly applied to the first to third embodiments described above. be able to.

FIG. 16 is a flow chart showing a fifth embodiment of the semiconductor integrated circuit design processing according to the present invention.

As is clear from the comparison between FIG. 16 and FIG. 13, the method for designing a semiconductor integrated circuit according to the fifth embodiment is
New steps ST50 and ST51 are provided as steps ST40 and ST41 of the fourth embodiment shown in FIG.

In the fifth embodiment, step ST1
Block / pin arrangement is performed in step 2, and then step ST
After performing inter-block wiring in step 20, step ST50
Proceed to and extract the coupling capacitance of the inter-block wiring. That is, in the fifth embodiment, after the inter-block wiring is executed, the coupling capacitance between the wirings, which causes a delay variation due to crosstalk noise, is extracted. The larger the value of this coupling capacitance, the larger the delay variation due to crosstalk noise. Therefore, a more accurate crosstalk noise delay can be obtained by using a graph of the crosstalk noise delay value using the coupling capacitance value as a parameter.

17 and 18 are diagrams for explaining the fifth embodiment shown in FIG.

17 and 18 (a) and 18
As shown in (b), specifically, for example, the wiring L1
Focusing on 2, when the inter-block wiring is performed and the coupling capacitances to the wirings (L11 and L13) on both sides of the wiring L12 are 35 fF and 35 fF, respectively, the relationship between the coupling capacitance and the crosstalk noise delay is shown. The delay variation amount is +150 ps at the maximum and −15 at the minimum from the graph showing FIG.
It turns out that it becomes 0 ps.

FIG. 19 is a flow chart showing a sixth embodiment of the semiconductor integrated circuit design processing according to the present invention.

As is apparent from the comparison between FIG. 19 and FIG. 16, the semiconductor integrated circuit designing method according to the sixth embodiment is
Step ST60 and step ST61 are added to the fifth embodiment shown in FIG.

In the sixth embodiment, first, the block A is first synthesized by the designing method of the fifth embodiment shown in FIG. 16 (or any of the first to fourth embodiments described above). Go and generate a netlist. As a result, in step ST60, the semiconductor elements (= driving cells: buffers 111, 112, 11) that drive the inter-block wiring are
3) is required (extracted). On the other hand, a combination of a cell that drives the wiring L12 that is the target of timing analysis (target side: buffer 112) and a cell that drives the wirings L11 and L13 on the side that gives crosstalk noise (noise side: buffers 111 and 113) , A graph of the crosstalk noise delay value is created (step ST61), and the delay time of the target wiring is calculated using the graph of the drive cell combinations of the target side and the noise side obtained from the netlist (step ST15). By doing so, a more accurate crosstalk noise delay value can be obtained.

20 and 21 are views for explaining the sixth embodiment shown in FIG.

In the example shown in FIG. 20, the target side driving cell (buffer 112) is a buffer having a double driving force, and the noise side driving cells (buffers 111 and 113) are buffers having a four times driving force. As shown in FIG. 21 (a), for example, if the target side and the noise side are the same double buffer, the crosstalk noise delay value is ± 150 ps, but as shown in FIG. Delay value is +20 at maximum because the side drive cell is 4 times buffer
The change amount is 0 ps and the minimum is −200 ps, and the fluctuation amount is large. Using this value, the timing constraint is regenerated and block A is resynthesized.

In the above, the method of once synthesizing to obtain the driving cell has been described. However, even if the driving cell is determined before the first synthesis and the timing constraint is created and the driving cell is always used at the time of synthesizing. Good.

FIG. 22 is a flow chart showing a seventh embodiment of the semiconductor integrated circuit design processing according to the present invention.

As is clear from the comparison between FIG. 22 and FIG. 19, the semiconductor integrated circuit designing method according to the seventh embodiment is
Step ST70 is added to the sixth embodiment shown in FIG.

In the seventh embodiment, similar to the sixth embodiment described above, the design method of the fifth embodiment shown in FIG. 16 (or any of the first to fourth embodiments described above). Thus, the block A is once synthesized to generate a net list. This makes it possible to obtain (extract) the transition timing in addition to the drive cell extraction in the sixth embodiment. Here, since the transition timing has a normal width, it will be referred to as a timing window.

Timing window on target side (A2)
Then, when the timing windows (A1, A3) on the noise side overlap, there is a possibility that delay variation due to crosstalk noise will occur. On the contrary, when they do not overlap, delay variation due to crosstalk noise does not occur. As described above, if the crosstalk noise delay value is calculated in consideration of the overlapping of windows, it becomes unnecessary to consider a large change unnecessarily.

23, 24 and 25 are views for explaining the seventh embodiment shown in FIG.

As shown in FIG. 24, when the timing window A2 on the target side does not overlap with the timing window A1 on one noise side and the timing window A3 on the other noise side does not overlap, the timing is The delay variation of crosstalk noise is not received from the window A1. Therefore, the other timing window A
Since only 3 need be considered, the coupling capacity is 35f.
Assuming F, the crosstalk noise delay value will be calculated. That is, using the graph shown in FIG.
It is sufficient to allow for a variation in the crosstalk noise delay value that is +80 ps at the maximum and -80 ps at the minimum.

FIG. 26 is a flow chart showing an eighth embodiment of the semiconductor integrated circuit design processing according to the present invention.

As is clear from the comparison between FIGS. 26 and 22, the semiconductor integrated circuit designing method according to the eighth embodiment is
Step ST80 (step ST81) is added to the seventh embodiment shown in FIG.

In the eighth embodiment, similar to the sixth and seventh embodiments described above, the fifth embodiment shown in FIG. 16 (or any of the first to fourth embodiments described above). According to the design method (1), the block A is once synthesized to generate a netlist. This makes it possible to obtain (extract) the driving cell and the transition timing. Book 8
In the embodiment, the crosstalk noise delay value is calculated based on this information. At this time, step ST8.
At 0, it is determined whether inserting a repeater improves the delay. Here, the repeater refers to a buffer cell inserted in the middle of the wiring, and by making a blunt transition waveform, it has an effect of reducing the wiring delay value and crosstalk noise. If a repeater is inserted, the delay time of the repeater cell itself increases, so the above effect (reduction of wiring delay value and crosstalk noise)
It is decided whether or not to insert it by the trade-off with.

Then, in step ST80, if it is determined that the repeater should be inserted, the wiring is
The crosstalk noise delay value assuming that the repeater is inserted is obtained from the crosstalk noise delay information at the time of inserting the repeater 81, and the timing constraint is generated again to perform the resynthesis (steps ST15 to ST17). According to the eighth embodiment, since the delay value is predicted before the layout of repeater insertion is completed, the design period can be shortened.

In the above description, the repeater insertion is determined after the combination is made. However, before the combination, the repeater insertion is determined based on the congestion degree, the adjacent wiring length, the coupling capacitance value and the like. It is also possible to use a crosstalk noise delay value that assumes repeater insertion from the first synthesis.

In each of the above-mentioned embodiments, the explanation has been made by using the graph of the delay value of the crosstalk noise and the delay value when there is no noise, but the dynamic simulator using the capacitance value extracted without using the graph. The result of can also be used. Also, the graph for calculating the delay value is
For the sake of clarity, the explanation has been made with the function of only the wiring length and the coupling capacitance value, but a value depending on the wiring layer, the wiring width, the wiring interval, etc. may be used.

FIG. 27 is a diagram for explaining an example of a medium in which the design program of the semiconductor integrated circuit according to the present invention is recorded. In FIG. 27, reference numeral 310 is a processing device, 3
Reference numeral 20 denotes a program (data) provider, and 330 denotes a portable storage medium.

The semiconductor integrated circuit designing method according to each of the above-described embodiments is performed by, for example, a processing device 31 as shown in FIG.
It is given as a program (data) for 0 and executed by the processing device 310. The processing device 310 includes an arithmetic processing device main body 311 including a processor, and a processing device side memory (eg, RAM (Random Access) that stores a result of giving a program (data) to the arithmetic processing device main body 311 or processing the program. Memory) and hard disk) 312 and the like. The program (data) provided to the processing device 310 is loaded and executed on the main memory of the processing device 310.

The program (data) provider 320 is a means for storing the program (data) (destination memory: DASD (Direct Access Storage Device)) 3
21 to provide a program (data) to the processing device 310 via a line such as the Internet,
Alternatively, the processing device 31 is provided via a portable storage medium 330 such as a CD-ROM, an optical disk, or a floppy disk.
Provide to 0. The medium in which the design program of the semiconductor integrated circuit according to the present invention is recorded is the above-mentioned processing device side memory 31.
2, line destination memory 321, and portable storage medium 33
Needless to say, it includes various items such as 0.

(Supplementary Note 1) A semiconductor is programmed by a computer using logic information of a semiconductor integrated circuit having a hierarchical structure and performing optimization of timing of a lower layer based on timing information of a boundary between the lower layer and an upper layer. An apparatus for designing an integrated circuit, wherein the boundary timing information includes delay variation due to crosstalk noise of the upper layer.

(Supplementary Note 2) In the semiconductor integrated circuit design apparatus according to Supplementary Note 1, the logic information of the semiconductor integrated circuit is written in a logical description language in a hierarchical structure. apparatus.

(Supplementary Note 3) In the semiconductor integrated circuit designing apparatus according to Supplementary Note 1, the semiconductor integrated circuit is characterized in that the delay variation due to the crosstalk noise of the upper hierarchy includes an increase in delay. Design equipment.

(Supplementary Note 4) In the semiconductor integrated circuit designing apparatus according to Supplementary Note 1, the delay variation due to the crosstalk noise in the upper layer includes a decrease in delay. Design equipment.

(Supplementary Note 5) In the semiconductor integrated circuit design apparatus according to Supplementary Note 1, the delay variation due to the crosstalk noise in the upper layer is calculated based on the predicted wiring length before wiring in the upper layer. A semiconductor integrated circuit designing device.

(Supplementary Note 6) In the semiconductor integrated circuit design apparatus according to Supplementary Note 1, the delay variation due to the crosstalk noise in the upper layer is based on the predicted degree of wiring congestion before wiring in the upper layer. A device for designing a semiconductor integrated circuit, which is characterized by the following requirements.

(Supplementary Note 7) In the semiconductor integrated circuit design apparatus according to Supplementary Note 1, delay variation due to crosstalk noise in the upper layer causes wiring in the upper layer, and a long wiring is provided at a specific interval. A device for designing a semiconductor integrated circuit, characterized in that it is calculated based on the calculated length.

(Supplementary Note 8) In the semiconductor integrated circuit design apparatus according to Supplementary Note 1, delay variation due to crosstalk noise in the upper layer causes wiring in the upper layer, and the coupling capacitance between the wirings is obtained from the result of the wiring. And a semiconductor integrated circuit designing device, wherein the device is obtained based on the extracted value of the coupling capacitance.

(Supplementary Note 9) In the semiconductor integrated circuit designing apparatus according to any one of Supplementary Notes 1 to 8, the delay variation due to the crosstalk noise in the upper layer causes information of a semiconductor element which drives a wiring in the upper layer. A device for designing a semiconductor integrated circuit, which is required to include the above.

(Supplementary Note 10) In the semiconductor integrated circuit designing apparatus according to any one of Supplementary Notes 1 to 9, the delay variation due to the crosstalk noise in the upper layer crosses the target wiring of the upper layer and the target wiring. An apparatus for designing a semiconductor integrated circuit, characterized in that it is also required to include information on the timing of transition of wiring that affects talk noise.

(Supplementary Note 11) Any one of Supplementary Notes 1 to 10
In the semiconductor integrated circuit design apparatus according to the paragraph (3), a repeater insertion for suppressing crosstalk is performed on the upper layer, and delay variation due to crosstalk noise of the upper layer is An apparatus for designing a semiconductor integrated circuit, which is obtained by predicting a case of insertion before repeater insertion layout is performed.

(Supplementary Note 12) The logic information of the semiconductor integrated circuit having the hierarchical structure is used to optimize the timing of the lower layer and design the semiconductor integrated circuit based on the timing information of the boundary between the lower layer and the upper layer. A method of designing a semiconductor integrated circuit, wherein the timing information of the boundary includes delay variation due to crosstalk noise of the upper layer.

(Supplementary note 13) In the method for designing a semiconductor integrated circuit according to supplementary note 12, the logic information of the semiconductor integrated circuit is written with a hierarchical structure in a logic description language. Method.

(Supplementary Note 14) In the method for designing a semiconductor integrated circuit according to Supplementary Note 12, the delay variation due to the crosstalk noise of the upper hierarchy includes an increase in delay. Design method.

(Supplementary Note 15) In the method for designing a semiconductor integrated circuit according to Supplementary Note 12, the delay variation due to the crosstalk noise in the upper layer includes a decrease in delay. Design method.

(Supplementary Note 16) In the method for designing a semiconductor integrated circuit according to Supplementary Note 12, the delay variation due to the crosstalk noise of the upper layer is obtained based on the predicted wiring length before wiring the upper layer. A method for designing a semiconductor integrated circuit, comprising:

(Supplementary Note 17) In the semiconductor integrated circuit designing method according to Supplementary Note 12, the delay variation due to the crosstalk noise in the upper layer is based on the predicted degree of wiring congestion before wiring in the upper layer. A method of designing a semiconductor integrated circuit, characterized in that

(Supplementary Note 18) In the method for designing a semiconductor integrated circuit according to Supplementary Note 12, the delay variation due to the crosstalk noise of the upper layer is such that the wiring of the upper layer is performed and the delay variation is long. A method of designing a semiconductor integrated circuit, characterized in that the length is calculated and the length is calculated based on the calculated length.

(Supplementary Note 19) In the method for designing a semiconductor integrated circuit according to Supplementary Note 12, delay variation due to crosstalk noise in the upper layer causes wiring in the upper layer, and a coupling capacitance between the wirings is obtained from the result of the wiring. Extract
A method for designing a semiconductor integrated circuit, which is obtained based on the value of the extracted coupling capacitance.

(Supplementary Note 20) In the method for designing a semiconductor integrated circuit according to any one of Supplementary Notes 12 to 19, the delay variation due to the crosstalk noise in the upper layer is information on a semiconductor element which drives a wiring in the upper layer. A method for designing a semiconductor integrated circuit, which is characterized in that it is also required.

(Supplementary Note 21) In the semiconductor integrated circuit designing method according to any one of Supplementary Notes 12 to 20, the delay variation due to the crosstalk noise of the upper layer crosses the target wiring of the upper layer and the target wiring. A method for designing a semiconductor integrated circuit, which is characterized in that it is also required to include information on the timing of transition of wiring that affects talk noise.

(Supplementary Note 22) In the semiconductor integrated circuit designing method according to any one of Supplementary Notes 12 to 21, repeater insertion for suppressing crosstalk is performed in the upper layer. Further, the delay variation due to the crosstalk noise of the upper layer is obtained by predicting the case of insertion before the layout of the repeater insertion is performed.

(Supplementary Note 23) A medium on which a program to be executed by a computer is recorded, the program using logical information of a semiconductor integrated circuit having a hierarchical structure,
The timing of the lower layer is optimized by designing the semiconductor integrated circuit based on the timing information of the boundary between the lower layer and the upper layer, and the timing information of the boundary includes delay variation due to crosstalk noise of the upper layer. A medium in which a design program for a semiconductor integrated circuit is recorded, which is included.

(Supplementary Note 24) A semiconductor integrated circuit characterized in that, in the medium in which the design program for a semiconductor integrated circuit according to supplementary note 23 is recorded, logic information of the semiconductor integrated circuit is written in a logical description language in a hierarchical structure. A medium that records the design program of.

(Supplementary Note 25) In the medium in which the semiconductor integrated circuit design program according to Supplementary Note 23 is recorded, an increase in delay is included in delay variation due to crosstalk noise in the upper hierarchy. A medium that records an integrated circuit design program.

(Supplementary note 26) In the medium having the semiconductor integrated circuit design program according to supplementary note 23 recorded therein, the delay variation due to the crosstalk noise of the upper layer is included in the semiconductor. A medium that records an integrated circuit design program.

(Supplementary Note 27) In the medium in which the semiconductor integrated circuit design program according to Supplementary Note 23 is recorded, the delay variation due to the crosstalk noise of the upper layer is predicted before the wiring of the upper layer is performed. A medium in which a design program for a semiconductor integrated circuit is recorded, which is obtained based on the length.

(Supplementary Note 28) In the medium in which the semiconductor integrated circuit design program according to Supplementary Note 23 is recorded, the delay variation due to the crosstalk noise of the upper layer is predicted before the wiring of the upper layer is performed. A medium on which a design program for a semiconductor integrated circuit is recorded, which is obtained based on the congestion degree of the.

(Supplementary Note 29) In the medium in which the semiconductor integrated circuit design program according to Supplementary Note 23 is recorded, delay variation due to the crosstalk noise of the upper layer is caused to be wired in the upper layer and separated at a specific interval. A medium in which a design program for a semiconductor integrated circuit is recorded, in which the length of wiring is calculated and the length is calculated based on the calculated length.

(Supplementary Note 30) In the medium in which the semiconductor integrated circuit design program according to Supplementary Note 23 is recorded, delay variation due to crosstalk noise in the upper layer is caused to be wired in the upper layer, and wiring is performed based on the result of the wiring. A medium in which a design program for a semiconductor integrated circuit is recorded, in which mutual coupling capacitances are extracted and obtained based on the value of the extracted coupling capacitances.

(Supplementary Note 31) In the medium in which the semiconductor integrated circuit design program according to any one of Supplementary Notes 23 to 30 is recorded, the delay variation due to the crosstalk noise of the upper hierarchy drives the wiring of the upper hierarchy. A medium on which a design program for a semiconductor integrated circuit is recorded, which is characterized by including information on a semiconductor element.

(Supplementary Note 32) In the medium in which the semiconductor integrated circuit design program according to any one of Supplementary Notes 23 to 31 is recorded, the delay variation due to the crosstalk noise of the upper hierarchy is reduced to the target wiring of the upper hierarchy and the target wiring. A medium in which a design program for a semiconductor integrated circuit is recorded, which is characterized in that information about a timing at which a wiring that affects crosstalk noise is transferred to the wiring of interest is also obtained.

(Supplementary Note 33) In the medium in which the semiconductor integrated circuit design program according to any one of Supplementary Notes 23 to 32 is recorded, repeater insertion for suppressing crosstalk is performed on the upper layer. A medium storing a design program for a semiconductor integrated circuit, characterized in that the delay variation due to the crosstalk noise of the upper layer is predicted and obtained when the layout of the repeater insertion is performed. .

[0112]

As described above in detail, according to the present invention, since the logic information can be optimized with the timing constraint in consideration of the delay variation due to the crosstalk noise, the semiconductor integrated circuit which satisfies the timing specification between the blocks. The circuit can be easily designed.

[Brief description of drawings]

FIG. 1 is a flowchart showing an example of a conventional semiconductor integrated circuit design process.

FIG. 2 is a block diagram schematically showing an example of a semiconductor integrated circuit having a hierarchical structure.

FIG. 3 is a diagram showing a part of a circuit in the semiconductor integrated circuit of FIG.

FIG. 4 is a flowchart for explaining the principle of the semiconductor integrated circuit according to the present invention.

FIG. 5 is a first design process of a semiconductor integrated circuit according to the present invention.
It is a flow chart which shows an example.

FIG. 6 is a view (No. 1) for explaining the first embodiment shown in FIG.

FIG. 7 is a view (No. 2) for explaining the first embodiment shown in FIG. 5;

FIG. 8 is a view (No. 3) for explaining the first embodiment shown in FIG. 5;

FIG. 9 is a second design processing of the semiconductor integrated circuit according to the present invention.
It is a flow chart which shows an example.

FIG. 10 is a flowchart showing a third embodiment of the semiconductor integrated circuit design processing according to the present invention.

FIG. 11 is a view (No. 1) for explaining the third embodiment shown in FIG. 10;

FIG. 12 is a view (No. 2) for explaining the third embodiment shown in FIG. 10;

FIG. 13 is a flowchart showing a fourth embodiment of the design processing of the semiconductor integrated circuit according to the present invention.

FIG. 14 is a view (No. 1) for explaining the fourth embodiment shown in FIG. 13;

FIG. 15 is a view (No. 2) for explaining the fourth embodiment shown in FIG. 13;

FIG. 16 is a flowchart showing a fifth embodiment of the semiconductor integrated circuit design processing according to the present invention.

FIG. 17 is a view (No. 1) for explaining the fifth embodiment shown in FIG. 16;

FIG. 18 is a view (No. 2) for explaining the fifth embodiment shown in FIG. 16;

FIG. 19 is a flowchart showing a sixth embodiment of the semiconductor integrated circuit design processing according to the present invention.

FIG. 20 is a view (No. 1) for explaining the sixth embodiment shown in FIG. 19;

FIG. 21 is a view (No. 2) for explaining the sixth embodiment shown in FIG. 19;

FIG. 22 is a flowchart showing a seventh embodiment of the semiconductor integrated circuit design processing according to the present invention.

FIG. 23 is a view (No. 1) for explaining the seventh embodiment shown in FIG. 22;

FIG. 24 is a view (No. 2) for explaining the seventh embodiment shown in FIG. 22;

FIG. 25 is a view (No. 3) for explaining the seventh embodiment shown in FIG. 22;

FIG. 26 is a flowchart showing an eighth embodiment of the semiconductor integrated circuit design processing according to the present invention.

FIG. 27 is a diagram for explaining an example of a medium in which a design program for a semiconductor integrated circuit according to the present invention is recorded.

[Explanation of symbols]

1, 200 ... Semiconductor integrated circuit (chip) 11, 12; 210, 220, 230, 240 ... Block (circuit block, functional block) 110, 120; 211, 212 ... Flip-flop (latch) 111-113 ... Buffer 213 ... Logic circuit 310 ... Processing device 311 ... Arithmetic processing device main body 312 ... Processing device side memory 320 ... Program (data) provider 321 ... Line destination memory 330 ... Portable storage medium AP1, AP2, AP10; BP1, BP2, BP3
BP10; CP1, CP2; DP1, DP2 ... Block pins L1, L2, L3, L4, L5; L10; L11 to L1
3; L21 to L23 ... wiring α, β ... wiring congestion degree

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/82 H01L 21/82 W 21/822 C 27/04 27/04 DF term (reference) 5B046 AA08 BA03 BA04 5F038 CA17 CD08 CD09 CD13 DF11 EZ09 EZ10 EZ20 5F064 BB03 BB04 BB19 EE02 EE08 EE15 EE43 EE46 EE47 HH01 HH06 HH09 HH10 HH11

Claims (10)

[Claims] 1. A semiconductor integrated circuit by a programmed computer which uses logic information of a hierarchical semiconductor integrated circuit and optimizes timing of a lower layer based on timing information of a boundary between the lower layer and an upper layer. A device for designing a semiconductor integrated circuit according to claim 1, wherein the timing information of the boundary includes delay variation due to crosstalk noise of the upper layer. 2. The semiconductor integrated circuit design device according to claim 1, wherein the delay variation due to the crosstalk noise of the upper layer is obtained based on a predicted wiring length before wiring of the upper layer. A semiconductor integrated circuit designing device. 3. The semiconductor integrated circuit design apparatus according to claim 1, wherein the delay variation due to the crosstalk noise of the upper layer is based on a predicted wiring congestion degree before wiring of the upper layer. A device for designing a semiconductor integrated circuit, which is required. 4. The semiconductor integrated circuit designing apparatus according to claim 1, wherein the delay variation due to the crosstalk noise of the upper layer is the wiring of the upper layer, and the length of the wiring is arranged at a specific interval. Is calculated and calculated based on the calculated length. 5. The semiconductor integrated circuit design device according to claim 1, wherein delay variation due to crosstalk noise in the upper layer causes wiring in an upper layer, and a coupling capacitance between wirings is obtained from a result of the wiring. A device for designing a semiconductor integrated circuit, which is extracted and obtained based on the value of the extracted coupling capacitance. 6. The semiconductor integrated circuit design apparatus according to claim 1, wherein the delay variation due to the crosstalk noise in the upper layer also includes information on a semiconductor element that drives a wiring in the upper layer. A device for designing a semiconductor integrated circuit, which is required to be included. 7. The semiconductor integrated circuit designing device according to claim 1, wherein the delay variation due to the crosstalk noise of the upper layer causes a crosstalk between the target wiring of the upper layer and the target wiring. An apparatus for designing a semiconductor integrated circuit, characterized in that it is also required to include information on the timing of transition of wiring that affects noise. 8. The semiconductor integrated circuit designing device according to claim 1, wherein repeater insertion for suppressing crosstalk is performed on the upper layer, and The device for designing a semiconductor integrated circuit is characterized in that the delay variation due to the crosstalk noise of the upper hierarchy is obtained by predicting the case of insertion before the layout of the repeater insertion is performed. 9. A method of designing a semiconductor integrated circuit by using logic information of a semiconductor integrated circuit having a hierarchical structure and optimizing timing of a lower layer based on timing information of a boundary between the lower layer and an upper layer. In the semiconductor integrated circuit design method, the boundary timing information includes delay variation due to the crosstalk noise of the upper layer. 10. A medium in which a program to be executed by a computer is recorded, wherein the program uses logical information of a semiconductor integrated circuit having a hierarchical structure, and optimizes timing of a lower layer in the lower layer and the upper layer. The semiconductor integrated circuit is designed based on the timing information of the boundary of the semiconductor integrated circuit, and the timing information of the boundary includes a delay variation due to the crosstalk noise of the upper layer. Made medium.