JP2003204265A - Analog-digital converter using superconductor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analog/digital (A/D) converter in which a high level of accuracy can be achieved even when the indeterminate output state of a comparator exists like when the high-temperature superconductor of a high inductance value is used. <P>SOLUTION: The A/D converter using the superconductor is equipped with: distribution circuits R101 to R10N for distributing an input current to a plurality of routes; a plurality of comparators 101 to 10N for receiving the distributed input currents and making outputs of any one of first and second values while depending on the value of the input current in clock injection; and output circuits 201 to 20N respectively provided on the output side of these comparators 101 to 10N for outputting the first value each time a clock is injected during a period in which the output of the comparators alternately repeats the first and second values and for outputting the value of the comparators as it is during the other period. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an analog-digital converter using a superconductor.

[0002]

2. Description of the Related Art Superconducting electronics for realizing various circuits by using superconductors for wiring or the like can realize very high speed functional circuits. When implementing an analog / digital converter using a superconductor, for example, IEEE Transactions o
n A QOS type comparator as described in Applied Superconductivity, Volume 1, 1991, p3 is used.

In the QOS type comparator, the output signals are "1" and "0" depending on the value of the input current when the clock is injected.
, Which has a characteristic that one bit can express one bit of a binary code. In the case of configuring a parallel comparison type (flash type) analog-digital converter, an electronic circuit using a conventional semiconductor requires 2 ^N comparators with the number of bits of analog-digital conversion output being N. On the other hand, when the QOS comparator using the superconducting wiring is used, only N comparators are required. Therefore, when N is particularly large, there is an advantage that the circuit scale of the entire analog-digital converter is greatly reduced.

[0004]

In a comparator using a superconductor such as a QOS type comparator, there is a state in which the output value becomes uncertain when the inductance in the superconducting loop is larger than a certain value. It has been pointed out. If such an output uncertain state exists, the accuracy of the comparator is reduced, and the conversion accuracy of the flash type analog-digital converter configured using the QOS type comparator is reduced.

As the superconductor material, niobium which is a metallic material having a small inductance is generally used. On the other hand, YBa
Since an oxide-based high temperature superconducting material such as CuO can have a higher operating temperature than niobium, the cost for cooling can be reduced, but when used as wiring, the inductance value becomes large. In addition, the lamp-edge type junction, which has good junction characteristics with the high-temperature superconductor, has an extra inductance due to its unique structure.

In a high temperature superconductor, it is difficult to manufacture a QOS type comparator with a small inductance value such that the output indeterminate state disappears. For example, if a typical inductance value of YBaCuO is substituted, the region of the input current in which the output is indeterminate is compared with the state of the output “0” even when the sampling rate of the analog-digital converter is relatively low. 10-30% occur. When the sampling rate is increased, the area of the input current in which the output is indeterminate is expected to further increase, which makes it extremely difficult to realize a high-speed analog / digital converter.

Under these circumstances, conventionally, when an analog-digital converter using a superconductor is manufactured,
Research and development is proceeding in the direction of using a superconducting material having a small inductance value and high cooling cost to the extent that the output uncertain state of the comparator does not exist. Therefore, analog-
There is a problem that it is difficult to reduce the price of the digital converter.

An object of the present invention is to provide an analog-digital converter which can realize high accuracy even when the output uncertain state of the comparator exists, as in the case of using a high temperature superconductor having a large inductance value. To do.

[0009]

In order to solve the above-mentioned problems, an analog-digital converter constructed by using a superconductor according to the present invention includes a distribution circuit for distributing an input current into a plurality of paths, and a distribution circuit. And a plurality of comparators whose outputs each take a value of a first value or a second value depending on the value of the input current at the time of clock injection and which are respectively provided on the output side of these comparators. The comparator outputs the first value during the period in which the output of the comparator alternately repeats the first and second values each time the clock is injected, and outputs the value of the comparator during the other periods. Is output as it is to output an analog-digital conversion output.

According to the present invention, by compensating the output uncertain state of the comparator, a highly accurate analog-digital converter can be realized even when a superconductor having a large inductance such as a high temperature superconductor is used. To be done.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. First, the QOS type comparator used in the analog-digital converter of the present embodiment will be described. The QOS type comparator has a configuration as shown in FIG. 1, for example. The symbol L represents the inductance of the superconducting wiring, and the symbol J represents a junction such as Josephson junction. In such a QOS type comparator, the value L of the inductances L1 to L3 in the superconducting loop in the dotted line in FIG. 1 and the LIc product which is the product of the critical current Ic of the junction J2 have a certain value (approximately 0.5Φ). ₀ ) is designed to be sufficiently smaller. Here, Φ = 2.07 × 10 ⁻¹⁵ Wb.
Ic is usually 100 so that noise does not affect circuit operation.
Since the value is designed to be μA or more, the value of the inductance L is selected accordingly. QO shown in Figure 1
The operating principle of the S-type comparator is as follows. First, the behavior with respect to the input current will be described. As shown in FIG. 2A, when an input current is injected into the QOS type comparator,
The current flowing through the junctions J2 and J3 increases. When the input current is increased, the junction J2 is turned on, one magnetic flux quantum enters in the superconducting loop in the dotted line in FIG. 1, and a circulating current flows as shown in FIG. 2 (b). In this state, an upward current, which is in the opposite direction to the state shown in FIG. 2A, flows through the junction J3. When the input current is further increased, the current flowing through the junctions J2 and J3 also increases, and eventually the junction J2 is turned on again, so that one more flux quantum enters the superconducting loop. In this state, the current flowing through the junction J3 again goes upward. Thus, the magnetic flux quantum enters the superconducting loop, and the current flowing through the junction J2 is adjusted so as not to exceed the critical current Ic at the junction J2.

By such an operation, the current flowing through the junction J3 periodically responds to the input current as shown in FIG. That is, as the input current increases, the current flowing through the junction J3 alternates between a state in which it gradually increases as shown in FIG. 2A and a state in which the direction reverses due to the circulating current as shown in FIG. 2B. Repeat. By allocating the cycle of the input current, that is, one state transition of FIG. 2A and FIG. 2B accompanying the increase of the input current to one bit of the output, one QOS type comparator can perform analog-digital conversion. One bit of the binary code which is the output of the container can be expressed.

Next, the operation for clock injection will be described. When a clock is injected into the QOS type comparator as shown in FIG. 1, the junction J7 is turned on, and a current flows in the direction of junctions J7 → J6 → J3 as shown in FIG. 4A. At this time, one of the junction J3 and the junction J6 is turned on. If the junction J6 is turned on, nothing is output.
The state in which nothing is output is defined as output "0". Figure 5
In (a), the joints J7, J6, J in the state of the output "0"
3 shows how J2 is switched. In FIG. 5A, the horizontal axis represents time and the vertical axis represents voltage (mV).

On the other hand, when the junction J3 is turned on, immediately after that, the flux quantum is output as shown in FIG. 4 (b), and at the same time, the flux quantum is generated in the superconducting loop formed by the inductance L1 and the junctions J2 and J3. Enters, and a circulating current flows. After that, the joint J2 is turned on as shown in FIG. 4C, and the original state is restored. In this way, the state in which the junction J3 is turned on and the magnetic flux quantum is output is the output “1”. In FIG. 5B, the joints J7, J6 and J7 in the state of the output “1” are shown.
The state of switching of J3 and J2 is shown. In FIG. 5B, the horizontal axis represents time and the vertical axis represents voltage (mV), as in FIG. 5A.

Which one of the junction J3 and the junction J6 is turned on, that is, whether the output is "1" or "0",
Determined by the value of input current. Therefore, the operation of the comparator in which the output takes a value of "1" or "0" according to the value of the input current is realized.

Next, the bias current will be described. Figure 1
When the bias current is injected into the QOS type comparator as shown in FIG. 3, the junction J3 is easily turned on when the clock is input, so that the area of the input current in the state of the output “1” is increased. By adjusting the value of the bias current, it is possible to equalize the regions of the input current that are in the state of the output “0” and the state of the output “1” and improve the accuracy.

The QOS type comparator as described above has an inductance L (L1, L1) as described in the section of the prior art.
If the value of (2, L3) is large, an output uncertain state exists. The generation mechanism of the output uncertain state of the QOS type comparator will be described below. When the value of the inductance L is large, there is a state in which the junction J2 is not turned on in the state of FIG. 4B for a certain input current. Join J2
When is not turned on, one more magnetic flux quantum is held compared to the original state as shown in FIG. 2B. In this state, the direction of the current flowing through the junction J3 is upward in FIG. 2 (b). When the next clock is input in this state, the junction J3 is not turned on and the junction J6 is turned on, so that nothing is output from the comparator. That is, 1
The comparator generates an output when the second clock is input, but does not generate an output when the second clock is input because the magnetic flux quantum is held.

It is uncertain whether the output of the QOS comparator is "1" or "0" with respect to the input current in such a state. The state of switching of the junction in this output uncertain state will be described in more detail. In the state where one more magnetic flux quantum is held, the orbiting current flows in the direction of J3 → J2 → L1 as shown in FIG. 2B, and therefore the upward current flows in the junction J3.

When the clock is injected in this state, the junction J6 is turned on. The current based on the clock is shown in FIG.
It flows not only to the joint J3 as in (a) but also to the joint J2. The orbiting current and the current based on the clock overlap, the junction J2 is turned on, and the flux quantum in the superconducting loop is reduced by one. The magnetic flux quantum is not output, and the state returns to the original state as shown in FIG. Further, when a clock is input, magnetic flux quanta are output, and the state shown in FIG. Since a series of these operations are repeated, the output of the QOS type comparator becomes an uncertain state by repeating "1" and "0" every clock as shown in FIG. In FIG. 7, the horizontal axis represents time and the vertical axis represents voltage (mV). When the value of the input current is increased, such an output uncertain state occurs during the transition period from the state of the output "1" to the state of the output "0" as shown in FIG.

On the other hand, the input current cycle (see FIG. 3) in the QOS type comparator shown in FIG. 1 is inversely proportional to the value of the inductance L1. The inductance L1 will be particularly called an input inductance. If the value of the input inductance L1 is multiplied by 2 ^m-1 , the input current period becomes 1/2 ^m-1 for the same input current value, so the weight of the output of the comparator is 1/2 ^m-1 . Become. That is, assuming that the output of the comparator having a certain value of L1 is the most significant bit of the analog-digital conversion output, the output of the comparator obtained by multiplying the value of L1 by 2 ^m-1 is m from the higher order of the analog-digital conversion output. It will be a bit. However, when the value of L1 is increased, as described above, the output uncertain state exists. Even if a niobium material is used for the superconductor, it is difficult to make the value of L1 four times or more without the output indeterminate state of the QOS type comparator.

In order to solve such a problem, in the embodiment of the present invention, the output side of the QOS type comparator has a period of an output uncertain state, that is, the output of the comparator is "0" and "0" at every clock injection. An output circuit forcibly outputting "1" is added during a period in which "1" is alternately repeated. As described above, when a clock is input in the state where one more magnetic flux quantum is held in the QOS type comparator, the QOS type comparator returns to the original state without generating an output. Therefore, the output repeats "1" and "0" for each clock with respect to the input current in which the output of the QOS comparator becomes indeterminate. In this way, during the output uncertain state in which the output of the QOS type comparator repeats "1" and "0" at each clock injection, the output circuit in the subsequent stage of the QOS type comparator is forced to output "1". By outputting, the output is fixed at "1".

Therefore, even if the inductance is large as in the case of using the high temperature superconductor, it is possible to realize the flash type analog-digital converter using the QOS type comparator with high accuracy. It is also possible to easily realize a QOS type comparator with a short input current cycle by increasing the value of the inductance L1 in FIG. Specific embodiments of the peripheral circuit of the QOS type comparator including the output circuit will be described below.

(First Embodiment) According to the first embodiment of the present invention, a circuit for injecting a reset clock for resetting the QOS type comparator into the QOS type comparator in addition to the normal clock. Is added, and when one or more magnetic flux quanta are input from the QOS type comparator between the injection of the clock and the injection of the next clock in the subsequent stage of the QOS type comparator, An output circuit that outputs only one is added.

Specifically, as shown in FIG. 9, a doubler 2 is inserted on the clock injection side of a QOS type comparator 1, and a destructive read register 3 is added as an output circuit at the subsequent stage of the QOS type comparator 1. To be done. The QOS type comparator 1 is shown in FIG.
It is assumed that the configuration is as shown in.

The doubler 2 is a circuit that outputs one magnetic flux quantum and then outputs another magnetic flux quantum to the input of one magnetic flux quantum. That is, the doubler 2 injects a normal clock into the QOS type comparator 1 and then further injects a reset clock. The doubler 2 includes, for example, as shown in FIG. 10, a branching device 21 that bifurcates the input first clock, a delay device 22 that delays one of the bifurcated one clocks by a certain time, and a delay device 22. It is composed of a synthesizer 23 which synthesizes the other branched clock and the clock delayed by the delay device 22 and outputs the synthesized clock as a second clock.

It is called destructive read out that the retained data is read as it is and the retained data disappears (destroys). The destructive read register 3 used in the present embodiment handles a magnetic flux quantum as an input, and even if the magnetic flux quantum is continuously input once or more, when the read clock is injected, only one magnetic flux quantum is output. It is an element that returns to the initial state. A clock (first clock) for which the reset clock is not generated by the doubler 2 is injected into the destructive read register 3 as a read clock.

FIG. 12 shows the state of FIG. 9 in the output uncertain state.
The switching of the junctions J7, J6, J3, and J2 in FIG. 1 when the doubler 2 and the destructive read register 3 are added as described above, and the state of the clock injected into the destructive read register 3 and the output of the register 3 are shown. Show. In FIG. 12, the horizontal axis represents time and the vertical axis represents voltage (mV). Joined J7
Are switched by the clock from the doubler 2. As shown in the switching waveform of the junction J7 in FIG. 12, the point that the reset clock is further injected after the original clock shown in FIGS. 5 and 7 is different from the above description.

Junctions J3 and J6 are alternately turned on each time the clock is injected. For example, when the original clock is injected, the junction J3 turns on, and at this time, the QOS
The output state of the type comparator 1 becomes "1". When the reset clock is injected, the junction J6 is turned on, and the output state of the QOS type comparator 1 is "0" at this time. Thus, the output state of the QOS type comparator 1 repeats "1" and "0".

The destructive read register 3 includes a doubler 2
First clock before passing through (clock of D in FIG. 12)
Is injected as the read clock, and if "1" is input from the QOS comparator 1 more than once between the injection of the first clock and the injection of the next first clock, "1" is output from the destructive read register 3 (output of D in FIG. 12). The number of times the QOS type comparator 1 outputs "1" between the time when the clock is injected into the destructive read register 3 and the time when the next clock is injected corresponds to the "0" state of the input current in FIG. Value is 0, 2 in "1" state, 1 in output indeterminate state
Times. As a result, when viewed from the output of the destructive read register 3, the output indeterminate state of the QOS type comparator 1 is compensated.

(Second Embodiment) In the second embodiment of the present invention, a circuit that outputs a clock only once when a clock is input twice and a clock is input to the subsequent stage of the QOS type comparator. When a magnetic flux quantum is input more than once between the start and the next clock injection, an output circuit for outputting only one magnetic flux quantum is added.

Specifically, as shown in FIG. 13, when the magnetic flux quantum is injected twice into the clock injection side of the destructive read register 3 which constitutes the output circuit, the frequency divider 4 which outputs the magnetic flux quantum once. Is inserted. The divide-by-two frequency divider 4 sets the clock frequency of the input clock (first clock) to 1
A clock (third clock) multiplied by 2 is generated, and Q
A clock (first clock) before being divided by the frequency divider 4 is injected into the OS type comparator 1.

FIG. 14 shows the state of FIG.
Switching of the junctions J7, J6, J3 and J2 in FIG. 1 when the frequency divider 4 and the destructive read register 3 are added as in No. 3, and the state of the clock injected into the destructive read register 3 and the output of the register 3. Indicates. In FIG. 14, the horizontal axis represents time and the vertical axis represents voltage (mV). Join J
7 is switched by the first clock. Junctions J3 and J6 are alternately turned on each time the clock is injected. For example, when the original clock is injected, the junction J3 is turned on, and at this time, the output state of the QOS type comparator 1 becomes "1". The output state of the QOS type comparator 1 is
It is "1" when the junction J3 is on, and "0" when the junction J6 is on.

In the destructive read register 3, a third clock (clock D in FIG. 14) having a period twice that of the first clock injected into the QOS type comparator 1 is divided into two.
The output of the QOS type comparator 1 is read only when this third clock is injected (the output of D in FIG. 14). The QOS type comparator 1 outputs "0" and "1" once after the third clock is injected into the destructive read register 3 and before the next third clock is injected. Therefore, as in the first embodiment, only "1" is output from the destructive read register 3, and the output of the destructive read register 3 compensates the output indeterminate state of the QOS type comparator 1. become.

(Third Embodiment) According to a third embodiment of the present invention, an output for outputting a logical sum of the current output of the QOS type comparator and the output one clock before is output after the QOS type comparator. A circuit is added.

Specifically, as shown in FIG. 15, the output of the QOS type comparator 1 is branched into two by the branching device 5. One output of the branching device 5 is supplied to one input end of the OR gate 7 via the shift register 6, and the other output is directly input to the other input end of the OR gate 7. The shift register 6 is supplied with the same clock as the clock injected into the QOS type comparator 1 as a shift clock. The OR gate 7 outputs the OR when the same clock as the clock injected into the QOS type comparator 1 is supplied.

FIG. 16 shows switching of the junctions J7, J6, J3 and J2 in FIG. 1 and the input clock and output of the OR gate 7 (clock and output of OR in FIG. 16) in the output uncertain state. . QO from OR gate 7
The logical sum of the output of the S-type comparator 1 and the output delayed by one clock (clock cycle) by the shift register 6 is output. That is, when the output of the QOS type comparator 1 repeats "0" and "1", the OR gate 7 repeatedly outputs the same output ("1"). Therefore, the OR gate 7 outputs only the output state "1" of the QOS type comparator 1, so that the output uncertain state of the QOS type comparator 1 is compensated.

(Fourth Embodiment) FIG. 17 shows a generalized configuration of the first embodiment shown in FIG.
A circuit for injecting n-1 reset clocks in addition to the normal clock is added to the S-type comparator, and a clock is injected and then the next clock is injected to the subsequent stage of the QOS-type comparator. When n or more magnetic flux quanta are input from the QOS type comparator until the above, an output circuit for outputting only one magnetic flux quanta is added.

Specifically, the n multiplier 12 (n is an integer of 2 or more) is inserted on the clock injection side of the QOS type comparator 11, and the destructive read constituting the output circuit at the subsequent stage of the QOS type comparator 11. A register 13 is added. The QOS type comparator 11 is assumed to have the configuration shown in FIG.

(Fifth Embodiment) FIG. 18 shows a generalized configuration of the second embodiment shown in FIG.
1 when the clock is input n times after the OS comparator
A circuit that outputs the clock only once and an output circuit that outputs only one flux quantum when the magnetic flux quantum is input n times or more between the input of the clock and the injection of the next clock To be done.

Specifically, an n frequency divider for generating a clock that is 1 / n times the clock frequency of the input clock (first clock) on the clock injection side of the destructive read register 13 that constitutes the output circuit. 14 is inserted, QOS
The clock before being divided by the n divider 14 is injected into the type comparator 11.

(Sixth Embodiment) FIG. 19 shows a generalized configuration of the third embodiment shown in FIG. QOS
The current output of the QOS type comparator and n-1
An output circuit that outputs a logical sum of the outputs up to the clock before is added.

Specifically, the output of the QOS type comparator 11 is branched into n by the branching device 15. The n outputs of the branching device 15 are input to the OR gate 17 through a plurality of shift registers 16 each having a different number of stages one by one. The same clock as the clock injected into the QOS type comparator 11 is supplied to the shift register 16 as a shift clock. The OR gate 17 outputs the OR when the same clock as the clock injected into the QOS comparator 11 is supplied. It is clear that the output uncertain state of the QOS type comparator 11 is also compensated by the fourth to sixth embodiments described above based on the same principle as that of the first to third embodiments.

Next, an embodiment of the flash type analog-digital converter using the QOS type comparator which compensates the output uncertain state described in the first to sixth embodiments will be described.

(Seventh Embodiment) FIG. 20 shows a flash type analog-digital converter according to a seventh embodiment of the present invention. The analog input current is N resistors R101
.. R10N are equally distributed to N paths and input to N QOS type comparators 101 to 10N. The outputs of the QOS type comparators 101 to 10N are taken out as N-bit analog-digital conversion outputs via the output circuits 201 to 20N described in the first to sixth embodiments. The output of the output circuit 201 is the most significant bit (MS
B), and the output of the output circuit 20m (m = 2, 3, N) is the output of the m-th bit from the high-order (the output of the output circuit 20N is the least significant bit (LSB)).

Here, the value of the input inductance L1 shown in FIG. 1 in the QOS type comparators 201 to 20N corresponds to the most significant bit of the analog-digital conversion output as shown in FIG. 21 (a). Assuming that the value of L1 in the QOS type comparator 201 is L1 = L ₀ , as shown in FIG. 21B, the value of L1 in the QOS type comparator 20m corresponding to the m-th bit from the higher order of the analog-digital conversion output is Value is L
1 = 2 ^m-1 L ₀ . Then, the QOS type comparator 20 corresponding to the most significant bit of the analog-digital conversion output.
The QOS type comparator 20 corresponding to the m-th bit from the higher order of the analog-digital conversion output for one input current cycle.
The input current period of ^m becomes 2 ^m-1 times.

With such a configuration, the output circuits 201 to 201
An N-bit analog-digital conversion output can be obtained from the output of 20N.

(Eighth Embodiment) FIG. 22 shows a flash type analog-to-digital converter according to an eighth embodiment of the present invention, in which an inductor L1 having N analog input currents.
The seventh embodiment is different from the seventh embodiment in that it is equally distributed to N paths by a distribution circuit composed of 01 to L10N and is input to N QOS type comparators 101 to 10N. QOS type comparator 2
The input inductance L shown in FIG.
The value of 1 is set as in the seventh embodiment.

As described above, according to the embodiment of the present invention, the output uncertain state of the QOS type comparator in the case of using the high temperature superconductor having a large inductance is compensated to realize the highly accurate analog-digital conversion. Therefore, the cost of cooling can be significantly reduced as compared with the niobium material. Further, since the output uncertain state of the QOS type comparator can be compensated by a small-scale circuit, it is suitable for a high temperature superconductor whose process technology is immature. Furthermore, the accuracy of analog-to-digital conversion is improved, and it can be expected that the error will be very small especially in static characteristics (low-frequency input, low-speed sampling). Even if it is applied when a niobium material is used as a superconductor, Digital conversion accuracy may increase.

[0049]

As described above, according to the present invention, in the analog-digital converter using the superconductor, it is possible to compensate the output uncertain state of the comparator and realize the high-precision analog-digital conversion. You can

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an example of a QOS type comparator.

FIG. 2 is a diagram explaining a basic operation of a QOS type comparator.

FIG. 3 is a diagram showing a periodic response of a QOS comparator to an input current.

FIG. 4 is a diagram for explaining a transition of operation with respect to a clock of a QOS comparator.

FIG. 5 is a diagram showing a switching state of each junction in a state where outputs of the QOS type comparator are “1” and “0”.

FIG. 6 is a diagram for explaining the operation principle of an output indeterminate state of a QOS type comparator.

FIG. 7 is a diagram showing a switching state of each junction when an output indeterminate state of a QOS type comparator occurs.

FIG. 8 is a diagram showing how an output indeterminate state of a QOS type comparator occurs.

FIG. 9 is a configuration diagram of a circuit for compensating for an output uncertain state of the QOS type comparator according to the first embodiment of the present invention.

FIG. 10 is a diagram showing a specific configuration example of a doubler.

FIG. 11 is a diagram showing a specific configuration of a destructive read register.

FIG. 12 is a diagram showing a switching state of each junction and an operation of a destructive read register when an output indeterminate state of the QOS type comparator occurs in the same embodiment;

FIG. 13 is a configuration diagram of a circuit for compensating for an output uncertain state of a QOS type comparator according to a second embodiment of the present invention.

FIG. 14 is a view showing a switching state of each junction and an operation of a destructive read register when an output indeterminate state of the QOS type comparator occurs in the same embodiment.

FIG. 15 is a configuration diagram of a circuit for compensating for an output uncertain state of a QOS type comparator according to a third embodiment of the present invention.

FIG. 16 is a diagram showing a switching state of each junction and an operation of an OR circuit when an output uncertain state of the QOS type comparator occurs in the same embodiment.

FIG. 17 is a configuration diagram of a circuit for compensating for an output uncertain state of a QOS type comparator according to a fourth embodiment of the present invention, which is a generalization of the first embodiment.

FIG. 18 is a configuration diagram of a circuit for compensating for an output uncertain state of a QOS type comparator according to a fifth embodiment of the present invention, which is a generalization of the second embodiment.

FIG. 19 is a configuration diagram of a circuit for compensating for an output uncertain state of a QOS type comparator according to a sixth embodiment of the present invention, which is a generalization of the third embodiment.

FIG. 20 is a diagram showing a configuration of an analog-digital converter according to a seventh embodiment of the present invention.

FIG. 21 is a view for explaining the input inductance of the most significant bit and the m-th bit QOS type comparator in the same embodiment.

FIG. 22 is a diagram showing a configuration of an analog-digital converter according to an eighth embodiment of the present invention.

[Explanation of symbols]

1 ... QOS type comparator 2 ... Doubler 3 ... Destruction read register 4 ... Divider 5 ... switch 6 ... Shift register 7 ... OR gate 11 ... QOS type comparator 12 ... n multiplier 13 ... Destruction read register 14 ... n divider 15 ... turnout 16 ... Shift register 17 ... OR gate 101-10N ... QOS type comparator 201-20N ... Output circuit R101 to R10N ... Distribution resistors L101 to L10N ... Distribution inductor

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hideyuki Sugiyama             Foundation law, 1-14-3 Shinonome, Koto-ku, Tokyo             International Superconductivity Industrial Technology Research Center Superconductivity             Engineering Research Center (72) Inventor Yoshinobu Tarutani             Foundation law, 1-14-3 Shinonome, Koto-ku, Tokyo             International Superconductivity Industrial Technology Research Center Superconductivity             Engineering Research Center (72) Inventor Keiichi Tanabe             Foundation law, 1-14-3 Shinonome, Koto-ku, Tokyo             International Superconductivity Industrial Technology Research Center Superconductivity             Engineering Research Center F-term (reference) 4M113 AC02 AD21 CA34                 5J022 AA06 BA01 CE01 CE08 CF01

Claims (5)

[Claims] 1. An analog-to-digital converter configured by using a superconductor, wherein a distribution circuit that distributes an input current to a plurality of paths and a distributed input current are received, and a value of the input current at the time of clock injection is set. A plurality of comparators each of which has an output that is one of the first and second values, and an output of the comparator that is provided on the output side of the comparator and that outputs each time the clock is injected. During the period in which the first and second values are alternately repeated, the first value is output, and during the other periods, the output value of the comparator is output as it is and used as each bit of the analog-digital conversion output. An analog-digital converter using a superconductor having an output circuit. 2. A multiplier for injecting n second clocks (n is an integer of 2 or more) for each first clock input and injecting the second clocks into the comparator, wherein the output circuit is The first output from the comparator each time the first clock is injected
An analog-digital converter using a superconductor according to claim 1, wherein the analog-digital converter is a destructive read register for reading the value of. 3. The frequency of the first clock input is 1 /
It has a frequency divider that generates a third clock multiplied by n times (n is an integer of 2 or more), the comparator is injected with the first clock, and the output circuit is injected with the third clock. The analog-to-digital converter using a superconductor according to claim 1, wherein the analog-to-digital converter is a destructive read register for reading the first value output from the comparator every time the reset is performed. 4. The output circuit outputs a logical sum of outputs of the comparators corresponding to consecutive n clocks (n is an integer of 2 or more) injected into the comparators. An analog-digital converter that uses a superconductor. 5. The plurality of comparators are provided corresponding to each bit of the analog-digital conversion output,
With respect to the input current cycle of the comparator corresponding to the most significant bit of the analog-digital conversion output, the input current cycle of the comparator corresponding to the m-th bit (m is an arbitrary integer) from the high order of the analog-digital conversion output is An analog-digital converter using a superconductor according to claim 1, which is set to 2 ^m-1 times.