JP2003203500A - Semiconductor memory device, test board, and test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which shortening and optimization of a write time are realized, and area can be reduced, and to provide a test board, and a test method. <P>SOLUTION: In operation of write-verify in which it is determined whether programming is performed appropriately for a memory cell or not during write operation, the number by which a page latch circuit 175 is not reset by a page latch data read-out circuit 178, that is, the number of memory cells by which write is not yet finished is counted by a counter 179. When write is progressed and the number of write fail bits is decreased, the number of pages written in parallel by a control circuit 1710 is increased so that sum of the counter 179 does not exceed 256 bits. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a semiconductor memory device capable of realizing optimization of rewriting time and improvement of reliability while realizing reduction of chip size, and simplification of inspection program and inspection. An inspection board and an inspection method capable of shortening the time are provided.

[0002]

2. Description of the Related Art A conventional semiconductor memory device will be described below.

The structure of a conventional semiconductor memory device is shown in FIG. In FIG. 24, 242 is a bit line, 243 is a memory cell, 244 is a word line, 245 is a source line, 246 is a data latch (page latch) circuit for latching write data, 247 is a sense amplifier, 24
Reference numeral 8 is an address decoder, 249 is a booster circuit that supplies a high voltage and current at the time of writing and erasing, and 2410 is a trimming information and redundant address information storage register.

Now, the operation of writing to the memory cell 243 will be described. In the above structure, write data is latched in the data latch circuit 246. Next, the data is written in units (one page unit) connected to the common word line 242. During writing Check if writing is normally performed. If there is a memory cell 243 for which writing has been completed, the page latch circuit 246 provided in the bit line 242 is reset. When all the page latch circuits 246 are reset, the writing of the page is completed and the process moves to the next page. This operation is repeated to write all page blocks. Here, in the case of a single power supply, the drain of the memory cell 243 (bit line 2
42) and control gate (word line 244)
Circuit 249 for generating high voltage and current applied to
Is equipped with.

The outline of the inspection will be described. In the conventional inspection, after all the inspections have been completed, it is determined whether the redundancy is possible or not possible. And make it work.

[0006]

A power supply circuit for realizing a single power supply, which corresponds to 2048-bit (one page) parallel writing in a conventional semiconductor memory device, occupies a very large proportion in the chip area. Also, the 2048 bits include memory cells that are not really written. However, although the user's program does not actually write all the memory cells, the conventional configuration takes time to write all the memory cells.

Further, the circuit scale of the register storing the trimming information and the redundant information at the time of operation is large, the control of the rewrite prohibited area is complicated, and the circuit scale is increased, and the chip size is increased.

Further, in the conventional inspection board and inspection, since it is judged whether the inspection is redundant or not possible due to non-redundancy after all inspections are completed, the inspection program of the tester used for inspection becomes complicated. The inspection time has also increased.

Therefore, it is an object of the present invention to increase the parallelism of memory cells for writing while preventing an increase in chip size, to realize a semiconductor memory device for shortening the writing time, shortening the inspection time, and simplifying the inspection program. It is to provide an inspection board and an inspection method.

[0010]

A semiconductor memory device according to claim 1, wherein a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, and a bit connecting the drains of the memory cells in the memory cell array. Line, a page latch circuit provided for each bit line, a transfer gate that electrically separates the page latch circuit from the bit line, a page latch read circuit that reads the contents of the page latch circuit, and data of the page latch read circuit Is compared with the write data, and if there is a mismatch, a comparison circuit is provided to make a fail decision.

According to the semiconductor memory device of the first aspect,
By latching the write data in the page latch circuit, reading the content, and comparing it with the write data, it is possible to detect a short circuit in the page latch circuit, and it is possible to make it defective because it is impossible to perform redundancy before a long write test.

According to another aspect of the semiconductor memory device of the present invention, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, and a bit line connecting the drains of the memory cells in the memory cell array are provided.
A page latch circuit provided for each bit line, a transfer gate that electrically separates the page latch circuit from the bit line, a transfer gate batch selection circuit that collectively selects transfer gates, and the contents of the page latch circuit are read. It is provided with a page latch read circuit and a comparison circuit that compares the data of the page latch read circuit with the write data and determines a failure if they do not match.

According to another aspect of the semiconductor memory device of the present invention,
The write data is latched in the page latch circuit, and the contents of the page latch circuit are read while the transfer gate is also selected all at once, and the short circuit between the page latch circuit and the bit line with a high defect rate is detected by comparing with the write data. Therefore, it is possible to make a defect as a non-redundant before a long write test.

According to another aspect of the inspection board of the present invention, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and each bit line. Inspection used for inspection of semiconductor memory device provided with page latch circuit, transfer gate electrically separating page latch circuit and bit line, and transfer gate batch selection circuit collectively selecting transfer gate In the case of a board, a connection unit for connecting a semiconductor memory device, a means connected to this connection unit for reading the contents of the page latch circuit, and the contents of the read page latch circuit are compared with the write data Inspection with write data comparison circuit equipped with comparison circuit for fail judgment It is over de.

According to the inspection board of the third aspect, the circuit for realizing the means for inspecting the data of the page latch circuit of the second aspect is used only for the inspection, but when incorporated in the semiconductor memory device, only this circuit is provided. Even if it is defective, this chip will be defective. Therefore, by mounting this circuit on the inspection board, it is possible to prevent defects of only the inspection circuit, and also to improve the temperature characteristics of this inspection circuit by high temperature inspection, etc. Deterioration can be prevented.

According to another aspect of the semiconductor memory device of the present invention, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, and a bit line connecting drains of the memory cells in the memory cell array.
A page latch circuit provided for each bit line, a transfer gate that electrically separates the page latch circuit from the bit line, and an inverted data batch latch circuit that collectively latches the inverted data in adjacent page latch circuits It is a thing.

According to another aspect of the semiconductor memory device of the present invention,
By measuring the power supply current while the inverted data is latched in the adjacent page latch circuits, it is possible to detect a short circuit in the adjacent page latch circuits, and it is possible to make it defective as a non-redundant before a long write test. .

According to a fifth aspect of the present invention, there is provided an inspection method, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and each bit line. Semiconductor memory including a provided page latch circuit, a transfer gate electrically separating the page latch circuit and a bit line, and an inverted data batch latch circuit for collectively latching inverted data in adjacent page latch circuits A method for inspecting a device is characterized in that a power supply current is measured in a state where inverted data is latched in a page latch circuit.

According to the inspection method of the fifth aspect, there is the same effect as the fourth aspect.

According to another aspect of the semiconductor memory device of the present invention, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, and a bit line connecting the drains of the memory cells in the memory cell array.
A page latch circuit provided for each bit line, a transfer gate for electrically separating the page latch circuit and the bit line, a batch latch circuit for collectively latching inverted data in adjacent page latch circuits, and a transfer gate It is provided with a transfer gate collective selection circuit for collectively selecting.

According to the semiconductor memory device of the sixth aspect,
By latching inverted data in adjacent page latch circuits and measuring the power supply current with the column gate also selected at a time, it is possible to detect short circuits between adjacent page latch circuits and bit lines with a high defect rate. It is possible to make a defect as non-redundant before a long write test.

According to a seventh aspect of the present invention, there is provided an inspection method, wherein a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and each bit line. A page latch circuit provided, a transfer gate that electrically separates the page latch circuit from the bit line, a batch latch circuit that collectively latches inverted data in adjacent page latch circuits, and a transfer gate collectively. A method for inspecting a semiconductor memory device comprising a transfer gate batch selection circuit for selecting, characterized in that the power supply current is measured in a state where the page latch circuit latches inverted data and the transfer gates are collectively selected. It is a thing.

According to the inspection method of claim 7, the same effect as that of claim 6 can be obtained.

According to another aspect of the semiconductor device of the present invention, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and each bit line. The page latch circuit provided, the transfer gate that electrically separates the bit line from the page latch circuit, the bit line voltage detection circuit that detects the voltage of the bit line, and the output of the bit line voltage detection circuit outputs the latch data. A latch reset circuit for inverting, a means for resetting the page latch circuit when the write is properly performed at the time of write verify for determining whether the write is properly performed, and a page latch read for reading the content of the page latch circuit Circuits and unreset A counter for counting the Jiratchi circuit for each page latch circuit, but with a failure determination circuit when the counter is more than the number count is.

According to the semiconductor memory device of the eighth aspect,
During the write test, the number of page latch circuits provided for each bit line that is not reset, that is, the number of memory cells in which write failures occur in the same bit line is counted, and the number of page latch circuits that are the same or more When the number of defects is counted, it can be determined to be non-redundant and can be determined to be defective in the middle of a long write test, and can also be determined to be defective before performing complicated redundancy processing.

According to another aspect of the inspection board of the present invention, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and each bit line. An inspection board used when inspecting a semiconductor memory device, comprising: a page latch circuit provided; a transfer gate electrically separating the page latch circuit from a bit line; and means for reading the contents of the page latch circuit. There is a connection unit that connects the storage device, a page latch read circuit that is connected to the connection unit and reads the contents of the page latch circuit, a counter that counts the page latch circuits that are not reset for each page latch circuit, and a number of counters. If it is counted more than Those were example.

According to the inspection board of the ninth aspect, the circuit realizing the means for inspecting the semiconductor device of the eighth aspect is used only for the inspection, but when incorporated, only this circuit is defective. Since this chip also becomes defective, mounting this circuit on a test board can prevent only the test circuit from failing, and also prevent temperature characteristic deterioration due to high-temperature testing of this test circuit. it can.

According to another aspect of the semiconductor device of the present invention, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, and if there is a defective memory cell in the memory array, redundancy is made in erase block units. A redundant circuit, a redundant block for replacing an erase block having a defective memory cell, a block selection address decoder for switching the erase block, a bit line connecting the drains of the memory cells in the memory cell array, and each bit line are provided. A page latch circuit,
A transfer gate that electrically separates the page latch circuit and the bit line, a bit line voltage detection circuit that detects the voltage of the bit line, a latch reset circuit that inverts the latch data by the output of the bit line voltage detection circuit, and a write During write-verify to determine whether data has been written properly, means for resetting the page-latch circuit when writing is properly written, a page-latch reading circuit for reading the contents of the page-latch circuit, and a page that has not been reset A first counter that counts the latch circuit for each page latch circuit, a first judgment circuit that makes a fail judgment when the first counter counts more than a certain number, a block selection address decoder, and a first counter And a second counter that counts bad blocks If the second counter has counted more than the number that is obtained with a fail determining second judging circuit.

According to the semiconductor memory device of the tenth aspect, in addition to the means of the eighth aspect, the number of page latch circuits which are not reset during the write test is counted in erase block units. Redundancy is performed in units of this erase block, so that defects exceeding the number of provided redundant blocks cannot be made redundant. That is, in the middle of a long write test, it is possible to make a defect as non-redundant and to make it defective before performing complicated redundant processing.

According to the eleventh aspect of the present invention, in the inspection board, memory cells having floating gates, a memory cell array in which the memory cells are arranged in an array, and if there is a defective memory cell in the memory array, redundancy is performed in erase block units. A redundant circuit, a redundant block for replacing an erase block having a defective memory cell, a block selection address decoder for switching the erase block, a bit line connecting the drains of the memory cells in the memory cell array, and each bit line are provided. A page latch circuit,
A transfer gate that electrically separates a page latch circuit and a bit line, an inspection board used when inspecting a semiconductor memory device equipped with a means for reading the contents of the page latch circuit, and a connection unit that connects the semiconductor memory device. ,
A page latch read circuit that is connected to the connection unit to read the contents of the page latch circuit, a first counter that counts the page latch circuits that have not been reset for each page latch circuit, and a first counter that counts more than a certain number. Failure determination circuit, a block selection address decoder, a second counter that counts defective blocks in conjunction with the first counter, and a second counter fails determination if a certain number or more is counted. The second determination circuit is provided.

According to the inspection board of the eleventh aspect, the circuit that realizes the means for the inspection of the tenth aspect is used only for the inspection, but when it is built in, even if only this circuit is defective, this chip is used. Therefore, by mounting this circuit on the inspection board, it is possible to prevent only the inspection circuit from being defective, and further to prevent the temperature characteristics from being deteriorated due to the high temperature inspection of the inspection circuit.

According to a twelfth aspect of the present invention, a semiconductor device has a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, and when there is a defective memory cell in the memory array, redundancy is made in erase block units. A redundant circuit, a redundant block for replacing an erase block having a defective memory cell, a bit line connecting the drains of the memory cells in the memory cell array, a page latch circuit provided for each bit line, a page latch circuit and a bit A transfer gate that electrically separates lines, a trimming circuit that suppresses process variations, a register that stores redundant addresses and trimming information, and a unit that transfers the information of the register to a page latch circuit and collectively writes the information to memory cells. It is equipped with.

According to the semiconductor memory device of the twelfth aspect, complicated processing of writing address information redundant to the trimming information subjected to the trimming processing for suppressing the process variation to the memory cell is performed, for example, the trimming information and the redundant address information. This can be simplified by connecting the register for storing the data and the page latch circuit so that the contents of the register can be collectively transferred to the page latch circuit.

According to another aspect of the semiconductor memory device of the present invention, a memory cell having a floating gate, a memory cell array in which memory cells are arranged in an array, and a defective memory cell in the memory array are redundant in erase block units. A redundant circuit, a redundant block for replacing an erase block having a defective memory cell, and a bit line connecting the drains of the memory cells in the memory cell array,
A sense amplifier that reads information from a memory cell, a latch circuit that holds data read by the sense amplifier, a page latch circuit that is provided for each bit line, and a transfer gate that electrically separates the page latch circuit and the bit line. A trimming circuit that suppresses process variations is provided, and a register that stores redundant addresses and trimming information during operation is shared by using a latch circuit and a page latch circuit.

According to the semiconductor memory device of the thirteenth aspect, by using the page latch circuit and the latch portion of the sense amplifier data for the register for storing the trimming information and the redundant address information, the register circuit becomes unnecessary and the chip area is reduced. Reduction can be realized.

According to another aspect of the semiconductor memory device of the present invention, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and each bit line. A page latch circuit provided in
A transfer gate that electrically separates the page latch circuit and the bit line, a bit line voltage detection circuit that detects the voltage of the bit line, a latch reset circuit that inverts the latch data by the output of the bit line voltage detection circuit, and a page A page latch read circuit that reads the contents of the latch circuit, a write bit number counter that counts the number of bits that are actually written in the write data at the start of writing, and a write bit number counter that increases the number of bits that are written in parallel. It is equipped with a control circuit.

According to the semiconductor memory device of the fourteenth aspect, the number of bits to be actually written in the write data at the start of writing is counted in the write page unit by reading the page latch circuit, and the bits are written in parallel according to the number. The writing time can be shortened and optimized by increasing the number of bits. Further, it is possible to provide a semiconductor memory device capable of reducing the size of a power supply circuit occupying a large chip area.

According to another aspect of the semiconductor memory device of the present invention, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and each bit line. A page latch circuit provided in
A transfer gate that electrically separates the page latch circuit and the bit line, a bit line voltage detection circuit that detects the voltage of the bit line, a latch reset circuit that inverts the latch data by the output of the bit line voltage detection circuit, and a page A page latch read circuit that reads the contents of the latch circuit, a write bit number counter that counts the number of bits that are actually written in the write data at the start of writing, and a write bit number counter that increases the number of bits that are written in parallel. It is provided with a control circuit and a power supply voltage detection circuit that detects the power supply voltage and, in the case of a high power supply voltage, further increases the number of bits to be written in parallel.

According to the semiconductor memory device of the fifteenth aspect, the semiconductor memory device of the fourteenth aspect is provided with a power supply voltage detection circuit, and in the case of a high power supply voltage, by increasing the number of bits to be written in parallel, a high speed operation can be achieved. Write time can be realized.

According to another aspect of the semiconductor memory device of the present invention, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and each bit line. A page latch circuit provided in
A transfer gate that electrically separates the page latch circuit and the bit line, a bit line voltage detection circuit that detects the voltage of the bit line, a latch reset circuit that inverts the latch data by the output of the bit line voltage detection circuit, and a write During write-verify to determine whether data has been written properly, means for resetting the page-latch circuit when writing is properly written, a page-latch reading circuit for reading the contents of the page-latch circuit, and a page that has not been reset It is provided with a counter that counts the latch circuit in write page units, and a control circuit that increases the number of bits to be written in parallel when the counter is within a certain number during the write operation.

According to the semiconductor memory device of the sixteenth aspect, the page latch circuit of the bit normally written by the write verify during writing is reset.
The contents of this page latch circuit are read in write page units, and the number of page latch circuits that have not been reset, that is, the number of memory cells that have not been written, is counted, and the number of memory cells that have not been written is less than or equal to a certain number. At this point, the write time can be shortened and optimized by increasing the number of memory cells to be written. Further, it is possible to provide a semiconductor memory device capable of reducing the size of a power supply circuit occupying a large chip area.

According to a seventeenth aspect of the present invention, in a semiconductor memory device, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and each bit line. A page latch circuit provided in
A transfer gate that electrically separates the page latch circuit and the bit line, a bit line voltage detection circuit that detects the voltage of the bit line, a latch reset circuit that inverts the latch data by the output of the bit line voltage detection circuit, and a write During write-verify to determine whether data has been written properly, means for resetting the page-latch circuit when writing is properly written, a page-latch reading circuit for reading the contents of the page-latch circuit, and a page that has not been reset A counter that counts the latch circuit in write page units, a control circuit that increases the number of bits to be written in parallel when the counter is within a certain number during the write operation, and a high power supply voltage when the power supply voltage is detected, Equipped with a power supply voltage detection circuit that further increases the number of bits written in parallel Those were.

According to the semiconductor memory device of the seventeenth aspect, the semiconductor memory device of the sixteenth aspect is provided with a power supply voltage detection circuit, and in the case of a high power supply voltage, by increasing the number of bits to be written in parallel, high speed operation can be achieved. Write time can be realized.

According to a eighteenth aspect of the present invention, in a semiconductor memory device, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and each bit line. A page latch circuit provided in
A transfer gate that electrically separates the page latch circuit and the bit line, a bit line voltage detection circuit that detects the voltage of the bit line, a latch reset circuit that inverts the latch data by the output of the bit line voltage detection circuit, and a page A page latch read circuit that reads the contents of the latch circuit, a write bit number counter that counts the number of bits actually written in the write data in write page units at the start of writing, and a drain current of a memory cell when writing in write page units Write current detection circuit and write in page progresses, monitor the write current detection circuit,
It is provided with a control circuit that increases the number of pages to be written based on the contents of the write bit number counter when the write current decreases to some extent.

According to another aspect of the semiconductor memory device of the present invention, the content of the page latch circuit is read in write page units, the number of data to be actually written is recorded in write page units, and the write memory in write page units is set. The cell drain current is monitored by the detection circuit, and when the writing progresses and the writing current decreases to some extent, the writing time can be shortened and optimized by a means for increasing the number of pages to be written based on the recording of. Further, it is possible to provide a semiconductor memory device capable of reducing the size of a power supply circuit occupying a large chip area.

According to a nineteenth aspect of the present invention, in a semiconductor memory device, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and each bit line. A page latch circuit provided in
A transfer gate that electrically separates the page latch circuit and the bit line, a bit line voltage detection circuit that detects the voltage of the bit line, a latch reset circuit that inverts the latch data by the output of the bit line voltage detection circuit, and a page A page latch read circuit that reads the contents of the latch circuit, a write bit number counter that counts the number of bits actually written in the write data in write page units at the start of writing, and a drain current of a memory cell when writing in write page units Write current detection circuit and write in page progresses, monitor the write current detection circuit,
A control circuit that increases the number of written pages based on the content of the write bit number counter when the write current decreases to some extent, and further increases the number of written bits or the number of written pages in parallel when the power supply voltage is detected and the power supply voltage is high. It is provided with a power supply voltage detection circuit.

According to the semiconductor memory device of the nineteenth aspect, the semiconductor memory device of the eighteenth aspect is provided with a power supply voltage detection circuit, and in the case of a high power supply voltage, the number of bits to be written in parallel is further increased to achieve high speed operation. Write time can be realized.

According to another aspect of the semiconductor memory device of the present invention, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and each bit line. A page latch circuit provided in
A transfer gate that electrically separates the page latch circuit and the bit line, a bit line voltage detection circuit that detects the voltage of the bit line, a latch reset circuit that inverts the latch data by the output of the bit line voltage detection circuit, and a page A page latch read circuit that reads the contents of the latch circuit, a write bit number counter that counts the number of bits actually written in the write data in write page units at the start of writing, and a write voltage detection that detects the boosted voltage level in write page units. Equipped with a circuit and a control circuit that monitors the write voltage detection circuit as writing progresses in page units and increases the number of written pages based on the contents of the write bit number counter when the write voltage reaches a certain voltage level. Is something

According to the semiconductor memory device of the twentieth aspect, the content of the page latch circuit is read in write page units, the number of data to be actually written is recorded in write page units, and the write memory in write page units is stored. The cell drain voltage is monitored by the detection circuit, and when the write voltage reaches a predetermined voltage level, the write time can be shortened and optimized by increasing the number of pages to be written based on the recording of . Further, it is possible to provide a semiconductor memory device capable of reducing the size of a power supply circuit occupying a large chip area.

According to another aspect of the semiconductor memory device of the present invention, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting drains of the memory cells in the memory cell array, and each bit line. A page latch circuit provided in
A transfer gate that electrically separates the page latch circuit and the bit line, a bit line voltage detection circuit that detects the voltage of the bit line, a latch reset circuit that inverts the latch data by the output of the bit line voltage detection circuit, and a page A page latch read circuit that reads the contents of the latch circuit, a write bit number counter that counts the number of bits actually written in the write data in write page units at the start of writing, and a write voltage detection circuit that detects a boosted voltage level in write page units. And a control circuit that monitors the write voltage detection circuit as the writing progresses in page units and increases the number of written pages based on the content of the write bit number counter when the write voltage reaches a certain predetermined voltage level,
When the power supply voltage is detected and the power supply voltage is high, a power supply voltage detection circuit for further increasing the number of bits to be written or the number of pages to be written is provided.

According to the semiconductor memory device of the twenty-first aspect, the semiconductor memory device of the twentieth aspect is provided with a power supply voltage detection circuit, and in the case of a high power supply voltage, by increasing the number of bits to be written in parallel, high speed operation can be achieved. Write time can be realized.

According to another aspect of the semiconductor memory device of the present invention, a memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and each bit line. A page latch circuit provided in
It is provided with a transfer gate for electrically separating the page latch circuit and the bit line, a decoder for recognizing the write-inhibited area, and means for forcibly resetting the page latch circuit in cooperation with the decoder.

According to the semiconductor memory device of the twenty-second aspect, by recognizing the rewrite prohibited area and forcibly resetting the page latch circuit, writing can be easily prevented and deterioration of reliability such as program drain disturb is prevented. be able to.

[0054]

[First Embodiment] FIG. 1 shows a configuration of a semiconductor memory device according to a first embodiment of the present invention.
The semiconductor memory device according to the first embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, 11 is a bit line connecting the drains of the memory cells, 12 is a memory cell having a floating gate, a plurality of which are arranged in an array to form a memory cell array, and 13 is a control gate of the memory cell 12. Is connected to the word line, 14 is a source line that connects the sources of the memory cells 12, 15 is a page latch circuit that latches write data, and 16 is a transfer gate that electrically separates the memory cell 12 and the page latch circuit 15. A column gate, 17 is a latch circuit for latching a sense amplifier and sense amplifier data,
Reference numeral 18 is a row decoder for selecting the word line 13, 19 is a column decoder for selecting the column gate 16, 110 is a power supply circuit for generating a boosted voltage and current when rewriting the memory cell, 1101 is redundant information and trimming. Register for storing information during operation 1102
Is a page latch data read circuit for reading the data of the page latch circuit 15, and 1103 is a comparison circuit for comparing the write data with the contents of the page latch circuit 15.

Before performing the write inspection, the page latch circuit 15 is made to latch the write data. This latch data is read by the read circuit 1102, compared with the write data by the comparison circuit 1103, and if they do not match, a fail judgment is made and the adjacent page latch circuits 15
Can be judged to be short-circuited. Since redundancy only replaces defective memory cells, short-circuiting the page latch circuit 15 makes it impossible to relieve redundancy. In the current inspection,
Even if the page latch circuit 15 is short-circuited, a long write test is performed to the end, and it is determined that a multi-block write failure is impossible for redundancy through complicated processing of the inspection device.

With the configuration of the present invention, it is possible to provide a semiconductor memory device in which a short circuit between adjacent page latch circuits 15 can be determined as non-redundant before a long write test, and a defect can be determined.

[Second Embodiment] FIG. 2 shows a configuration of a semiconductor memory device according to a second embodiment of the present invention. A semiconductor memory device according to the second embodiment of the present invention will be described below with reference to FIG.

In FIG. 2, reference numeral 21 is a bit line connecting the drains of the memory cells 22, reference numeral 22 is a memory cell having a floating gate, and a plurality of memory cells are arranged in an array to form a memory cell array. Reference numeral 23 is a control of the memory cell 22. A word line connecting the gates, 24 a source line connecting the sources of the memory cells 22, 25 a page latch circuit for latching write data, and 26 a transfer gate for electrically separating the memory cells 22 and the page latch circuit 25. A certain column gate, 27 is a latch circuit for latching a sense amplifier and sense amplifier data, 28 is a row decoder for selecting the word line 13, 29 is a column decoder for selecting the column gate 26, and 210 is a memory cell rewrite. When boosted voltage and current are generated That the power supply circuit, 2101 a register for storing redundancy information and trimming information during operation, 210
Reference numeral 2 is a page latch data read circuit for reading the data of the page latch circuit 15, 2103 is a comparison circuit for comparing the write data with the contents of the page latch circuit 25, 21
Reference numeral 04 collectively opens the column gate 26 and bit line 2
This is a column gate batch selection circuit that connects 1 and the page latch circuit 25.

Before performing the write test, the page latch circuit 25 is made to latch the write data. The page latch circuit 25 is provided for each bit line 21.
The column gate batch selection circuit 2104 turns on all the column gates 26 to connect the bit line 21 and the page latch circuit 25. In this state, the latch data is read by the read circuit 2102, and the write data and the comparison circuit 21 are read.
It is possible to judge that the page latch circuits 25 adjacent to each other are short-circuited or the bit line 21 is short-circuited. Since redundancy only replaces defective memory cells, short-circuiting the page latch circuit 25 makes redundancy repair impossible. Further, the short circuit of the bit line 21 also extends over many blocks, so that redundant repair is impossible.
Redundancy can be achieved by using the replacement redundancy of the bit line 21, but it is difficult to realize in the case of a flash memory because there is an erase unit. Therefore, the semiconductor memory device according to the second embodiment of the present invention employs a redundancy replacement method in erase block units. In the current inspection, even for the short circuit of the page latch circuit 25 and the short circuit of the bit line 21 having a high defect rate, a long write inspection is performed to the end, and it is determined by the inspection apparatus that it is impossible to be redundant as a write failure of many blocks. Are going through.

According to the configuration of the present invention, it is possible to provide a semiconductor memory device in which a short circuit between adjacent page latch circuits 25 and a bit line short circuit having a high failure rate can be judged as non-redundant before a long write test and can be judged as non-redundant.

[Third Embodiment] FIG. 3 shows a configuration of a semiconductor memory device according to a third embodiment of the present invention. FIG. 4 shows the configuration of an inspection board according to the third embodiment of the present invention. A semiconductor memory device and an inspection board according to the third embodiment of the present invention will be described below with the configuration of FIG. 3 and the inspection board of FIG.

In FIG. 3, reference numeral 31 is a bit line connecting the drains of the memory cells, 32 is a memory cell having a floating gate, and a plurality of memory cells are arranged in an array to form a memory cell array, and 33 is a control gate of the memory cell. A word line to be connected, 34 is a source line for connecting sources of memory cells, 35 is a page latch circuit for latching write data, and 36 is a memory cell 32.
And a page latch circuit 35 are column gates which are transfer gates for electrically separating them, 37 is a latch circuit for latching sense amplifiers and sense amplifier data, 38 is a row decoder for selecting the word line 13, 39 is a column gate 36. Column decoder for selecting 3
Reference numeral 10 is a power supply circuit for generating boosted voltage and current when rewriting a memory cell, 311 is a register for storing redundancy information and trimming information at the time of operation, 314 is a column gate 36 at a time, and a bit line 31 and a page latch circuit 35. This is a column gate batch selection circuit that connects the two.

In FIG. 4, reference numeral 41 is an inspection board, 42 is a DUT socket in which the semiconductor memory device of FIG. 3 is fitted, 43 is a page latch data read circuit for reading the data of the page latch circuit 35 of FIG. It is a comparison circuit for comparing the contents of the latch circuit 35.

The DUT socket 42 of the inspection board 41 is shown in FIG.
The semiconductor memory device having the above configuration is inserted, and the write data is latched by the page latch circuit 35 before the write test is performed. The page latch circuit 35 is provided for each bit line 31. All the column gates 36 are turned on by the column gate batch selection circuit 314, and the bit line 31
To the page latch circuit 35. In this state, the latch data is read by the page latch data read circuit 43 mounted on the inspection board 41, compared with the write data by the comparison circuit 44, and if they do not match, Fail is determined, and the adjacent page latch circuits are detected. It can be determined that 35 is short-circuited or the bit line 31 is short-circuited. Since redundancy only replaces a defective memory cell, a short circuit in the page latch circuit cannot provide redundancy relief. In addition, the short circuit of the bit line also extends over many blocks, so that redundant repair is impossible. Redundancy can be achieved by using bit line replacement redundancy, but in the case of flash memory, it is difficult to implement because there is an erase unit. Therefore, the semiconductor memory device according to the third embodiment of the present invention employs a redundancy replacement method in erase block units. In the present inspection, the bit line 31 having a high short circuit rate and a high defect rate of the page latch circuit 35.
In the case of the short circuit, a long write inspection is performed to the end, and it is determined that it is impossible to be redundant as a write failure in many blocks through complicated processing of the inspection device.

According to the configuration of the present invention, it is possible to make a short circuit between adjacent page latch circuits 35 and a bit line short circuit having a high defect rate as a non-redundant defect before a long write test, and use it only for a test. It is possible to provide a semiconductor memory device and an inspection board that can prevent defects of only the inspection circuit by externally attaching the circuit to the inspection board, and can further prevent temperature characteristic deterioration due to high-temperature inspection of the inspection circuit.

[Fourth Embodiment] FIG. 5 shows the structure of a semiconductor memory device according to a fourth embodiment of the present invention. A semiconductor memory device inspection method according to the fourth embodiment of the present invention will be described below with reference to FIG.

In FIG. 5, reference numeral 51 is a bit line connecting the drains of the memory cells, 52 is a memory cell having a floating gate, and a plurality of memory cells are arranged in an array to form a memory cell array, and 53 is a control gate of the memory cell. A word line to be connected, 54 is a source line for connecting the source of the memory cell, 55 is a page latch circuit for latching write data, and 56 is a memory cell 52.
The column gate 56 is a transfer gate that electrically separates the page latch circuit 55 from the page latch circuit 55.
A column decoder 58 for selecting is a reverse data batch latch circuit for collectively latching reverse data in page latch circuits 55 adjacent in layout.

Before the write check, the adjacent page latch circuits 55 are made to collectively latch "1", "0", "1", "0" ... In this state, the power supply current of the semiconductor memory device of the present invention is measured. If the adjacent page latch circuits 55 are short-circuited, an abnormal power supply current can be observed, and at this point, redundancy is determined to be a failure. Redundancy is only replacement of defective memory cells, so
A short circuit in the page latch circuit cannot prevent redundancy. In the current inspection, a write inspection in which the short circuit of the page latch circuit 55 is long is performed up to the end, and it is determined through a complicated process of the inspection device that it is impossible to be redundant as a write failure in many blocks.

According to the configuration of the present invention, it is possible to provide a semiconductor memory device and an inspection method capable of determining a short circuit between adjacent page latch circuits as non-redundant before a long write inspection and making a defect determination.

[Fifth Embodiment] FIG. 6 shows a structure of a semiconductor memory device according to a fifth embodiment of the present invention. A method of inspecting a semiconductor memory device according to the fifth embodiment of the present invention will be described below with reference to FIG.

In FIG. 6, reference numeral 61 is a bit line connecting the drains of the memory cells, 62 is a memory cell having a floating gate, and a plurality of memory cells are arranged in an array to form a memory cell array, and 63 is a control gate of the memory cell. A word line to be connected, 64 is a source line for connecting sources of memory cells, 65 is a page latch circuit for latching write data, and 66 is a memory cell 62.
And a column gate 66 which is a transfer gate for electrically separating the page latch circuit 65 from each other.
Is a column decoder for selecting the column, 68 is an inversion data batch latch circuit that collectively latches the inversion data in the page latch circuits 65 adjacent in layout, and 69 is a column gate batch selection circuit that collectively selects the column gates 66. is there.

Before the write inspection, the adjacent data latch circuits 65 are set to "1" by the inverted data batch latch circuit.
Inverted data such as “0”, “1”, “0” ... Further, the column gate collective selection circuit 69 selects the column gates 66 collectively. In this state, the power supply current of the semiconductor memory device of the present invention is measured. If the page latch circuit 65 and the bit line 61 adjacent to each other are short-circuited, an abnormal power supply current can be observed, and at this point, redundancy is determined to be defective. Since redundancy only replaces a defective memory cell, a short circuit in the page latch circuit cannot provide redundancy relief. In addition, the short circuit of the bit line also extends over many blocks, so that redundant repair is impossible. Redundancy can be achieved by using bit line replacement redundancy, but in the case of flash memory, it is difficult to implement because there is an erase unit. Therefore, the semiconductor memory device according to the fifth embodiment of the present invention employs a redundancy replacement system in erase block units. In the current inspection, even for the short circuit of the page latch circuit 65 and the short circuit of the bit line 61 having a high defect rate, a long write inspection is performed to the end, and it is determined by a complicated inspection device that it is impossible to be redundant as a write failure of many blocks. Are going through.

According to the configuration of the present invention, it is possible to provide a semiconductor memory device and an inspection method capable of determining a short circuit between adjacent page latch circuits and a bit line short circuit having a high defect rate as non-redundant before a long write inspection. .

[Sixth Embodiment] FIG. 7 shows a structure of a semiconductor memory device according to a sixth embodiment of the present invention. A semiconductor memory device according to the sixth embodiment of the present invention will be described below with reference to FIG.

In FIG. 7, reference numeral 71 is a bit line for connecting the drains of the memory cells, 72 is a memory cell having a floating gate, and a plurality of memory cells are arranged in an array to form a memory cell array, and 73 is a control of the memory cell 72. A word line connecting the gates, 74 a source line connecting the sources of the memory cells 72, 75 a page latch circuit for latching write data, and 76 a transfer gate for electrically separating the memory cells 72 and the page latch circuit 75. A column gate, 77 is a column decoder for selecting the column gate 76, 78 is a bit line voltage detection circuit for detecting the voltage of the bit line 71, 7
Reference numeral 9 is a latch reset circuit that inverts the data of the page latch circuit 75 by the output of the bit line voltage detection circuit 77, 710 is a page latch data read circuit that reads the contents of the page latch circuit 75, and 711 is a page latch circuit 75 that has not been reset. A counter that counts each time, 712 is a determination circuit that determines a fail when the counter 711 has counted more than a certain number, 713 is an erase block, 714 is a user memory block used by the user, and 715 is redundant in erase units. Is a memory block for redundant replacement of.

During the write inspection, write verify is performed to determine whether the writing was properly performed. At this time, the voltage of the bit line 71 is detected by the bit line voltage detection circuit 78, and when the writing to the memory cell 72 is normally performed, the page latch circuit 75 is reset by the latch reset circuit 79. If it is not reset, the memory cell becomes a defective write memory cell. With respect to the defective write memory cell, the page latch circuit 75 provided for each bit line 71 is connected to the page data read circuit 710.
The counter 711 counts each page latch circuit 75 that has not been read and reset.

In the semiconductor memory device according to the sixth embodiment of the present invention, since the redundant replacement is executed up to two blocks (two redundant replacement memory blocks 715 are installed) in the erase block 713 unit, the erase block is executed. 713, word line 64 on the same bit line 71
Redundancy can be saved up to the book. Redundancy can be achieved by using bit line replacement redundancy, but in the case of flash memory, it is difficult to implement because there is an erase unit.

Therefore, the semiconductor memory device according to the sixth embodiment of the present invention employs a redundancy replacement system in erase block units. Therefore, the judgment circuit 712 judges that the counter 711 has reached 65 or more, and it can be judged that the redundancy is impossible. In the current inspection, a long write inspection is performed to the end, and it is determined that a multi-block write failure is impossible for redundancy through complicated processing of the inspection device.

According to the configuration of the present invention, it is possible to provide a semiconductor memory device capable of making a defect determination as non-redundant before a long write test.

[Seventh Embodiment] FIG. 8 shows a configuration of a semiconductor memory device according to a seventh embodiment of the present invention. FIG. 9 shows the configuration of an inspection board according to the seventh embodiment of the present invention. The semiconductor memory device and the inspection board according to the seventh embodiment of the present invention will be described below with the configuration of FIG. 8 and the inspection board of FIG.

In FIG. 8, 81 is a bit line connecting the drains of the memory cells, 82 is a memory cell having a floating gate, and a plurality of memory cells are arranged in an array to form a memory cell array. 83 is a control gate of the memory cell 82. Is a source line connecting the source of the memory cell 82, 85 is a page latch circuit for latching write data, and 86 is a transfer gate for electrically separating the memory cell 82 and the page latch circuit 85. A column gate, 87 is a column decoder for selecting the column gate 86, 88 is a bit line voltage detection circuit for detecting the voltage of the bit line 81,
Reference numeral 9 is a latch reset circuit that inverts the data of the page latch circuit 85 by the output of the bit line voltage detection circuit 87, 813 is an erase block, 814 is a user memory block used by the user, and 815 is redundant replacement for redundancy in erase units. 9, which is a memory block for use, 91 is an inspection board, 92 is a DUT socket in which the semiconductor memory device of FIG. 8 is fitted, 910 is a page latch data read circuit for reading the data of the page latch circuit 85 of FIG. 8, and 911 is reset. 8 is a counter that counts for each page latch circuit 85 in FIG.

The DUT socket 92 of the inspection board 91 is shown in FIG.
The semiconductor memory device having the above configuration is inserted, and the write verify is performed during the write inspection to determine whether the write is properly performed. At this time, the voltage of the bit line 81 is detected by the bit line voltage detection circuit 88, and when the writing to the memory cell 82 is normally performed, the page latch circuit 85.
Is reset by the latch reset circuit 89. If it is not reset, the memory cell becomes a defective write memory cell. The page latch circuit 85 provided for each bit line 81 is read by the page data reading circuit 910 mounted on the inspection board 91, and the counter 911 counts each page latch circuit 85 that has not been reset. To do.

In the semiconductor memory device according to the seventh embodiment of the present invention, since the redundant replacement is executed up to two blocks (two redundant replacement memory blocks 815 are installed) in the erase block 813, the erase block is executed. 813, word line 64 on the same bit line 81
Redundancy can be saved up to the book. Redundancy can be achieved by using bit line replacement redundancy, but in the case of flash memory, it is difficult to implement because there is an erase unit.

Therefore, the semiconductor memory device according to the seventh embodiment of the present invention employs the redundancy replacement method in units of erase block 813. Therefore, the judgment circuit 912 judges that the counter 911 has reached 65 or more, and it can be judged that the redundancy is impossible. In the current inspection, a long write inspection is performed to the end, and it is determined that a multi-block write failure is impossible for redundancy through complicated processing of the inspection device.

According to the configuration of the present invention, it is possible to make a defect determination as a non-redundant before a long write test, and to prevent a defect of only the test circuit by externally attaching a circuit used only for the test to a test board. It is possible to provide a semiconductor memory device and an inspection board that can prevent temperature characteristic deterioration due to a high temperature inspection of the inspection circuit.

[Embodiment 8] FIG. 10 shows a configuration of a semiconductor memory device according to an eighth embodiment of the present invention. The eighth embodiment of the semiconductor memory device of the present invention will be described below with reference to FIG.

In FIG. 10, 101 is a bit line connecting the drains of the memory cells, 102 is a memory cell having a floating gate, and a plurality of memory cells are arranged in an array to form a memory cell array, and 103 is the memory cell 10.
Word line connecting two control gates, 10
4 is a source line for connecting the sources of the memory cells, 10
5 is a page latch circuit for latching write data, 1
Reference numeral 06 is a column gate which is a transfer gate for electrically separating the memory cell 102 and the page latch circuit 105, 107 is a column decoder for selecting the column gate 106, 108 is a bit line voltage detection circuit for detecting the voltage of the bit line 101, 109 is a latch reset circuit that inverts the data of the page latch circuit 105 according to the output of the bit line voltage detection circuit 107, 1010 is a page latch data read circuit that reads the contents of the page latch circuit 105, and 1011 is a page latch circuit 105 that has not been reset. A first determination circuit that counts each time, a first determination circuit 1012 determines a fail when the first counter 1011 is counted more than a certain number, 1013 is an erase block, and 1014 is a user memory used by a user. Blocks 1015 are redundant blocks for redundancy in erase units, that is, redundant replacement memory blocks, 1016 selects an erase block 1013 according to a block address, and a block selection address decoder 1017 which recognizes a change in the block address and outputs a signal. A redundancy circuit for performing replacement in erase block units according to a redundancy address, 1018 is a second counter for counting the page latch circuits 105 that have not been reset for each erase block, and 1019 is a second counter 101.
A second determination circuit for determining a failure when 8 is counted more than a certain number, 1020 is a register for storing trimming information and redundant address information for suppressing process variations during operation, and 1021 is a register 102.
0 is a trimming information and redundant information memory block in which trimming information and redundant address information transferred during operation are stored.

During the write inspection, write verify is performed to determine whether the writing was properly performed. At this time, the voltage of the bit line 101 is changed to the bit line voltage detection circuit 10
8 and the writing to the memory cell 102 is normally performed, the page latch circuit 105 is reset by the latch reset circuit 109. If it is not reset, the memory cell becomes a defective write memory cell. The page data read circuit 1010 reads the page latch circuit 105 provided for each bit line 101 for the defective write memory cell, and the first counter 10 is provided for each page latch circuit 105 that has not been reset.
Count at 11.

In the semiconductor memory device according to the eighth embodiment of the present invention, the redundant replacement is executed up to two blocks (two redundant replacement memory blocks 1015 are installed) in units of the erase block 1013. Up to 64 word lines on the same bit line 101 in the block 1013 can be redundantly repaired. Therefore, the first determination circuit 1012 determines that the counter 1011 of the platform 1 has reached 65 or more, and determines that redundancy is impossible (Fa
il) Can be judged. Further, the redundancy replacement memory block 1015 for redundancy in the erase unit is provided with two blocks due to the increase of the redundancy rate and the chip area. Therefore, if there is a write failure of three erase blocks or more, redundancy cannot be relieved. Therefore, the block selection address decoder 1016 recognizes the block address change during the write test, and the page latch circuit 105 which is not reset is set to the second counter 10 every time the block address changes.
When counted at 18, when the number becomes 3 or more, the second determination circuit 1019 determines that the redundancy cannot be repaired. In the current inspection, a long write inspection is performed to the end, and it is determined that a multi-block write failure is impossible for redundancy through complicated processing of the inspection device.

With the configuration of the present invention, it is possible to provide a semiconductor memory device capable of judging a defect as non-redundant before a long write test.

[Ninth Embodiment] FIG. 11 shows the structure of a semiconductor memory device according to a ninth embodiment of the present invention. 12
The configuration of the inspection board according to the ninth embodiment of the present invention is shown in FIG. A semiconductor memory device and an inspection board according to the ninth embodiment of the present invention will be described below with the configuration of FIG. 11 and the inspection board of FIG.

In FIG. 11, 111 is a bit line connecting the drains of the memory cells, 112 is a memory cell having a floating gate, and 113 is the memory cell 11.
A word line connecting the two control gates, 11
Reference numeral 4 is a source line connecting the sources of the memory cells 112, 115 is a page latch circuit for latching write data, and 116 is a memory cell 112 and the page latch circuit 1.
A column gate that is a transfer gate that electrically separates 15 is a column decoder that selects the column gate 116, 118 is a bit line voltage detection circuit that detects the voltage of the bit line 111, and 119 is a bit line voltage detection circuit 117. Page latch circuit 1 by output
A latch reset circuit for inverting 15 data, 111
3 is an erase block, 1114 is a user memory block used by the user, 1115 is a redundant replacement memory block which is a redundant block for redundancy in erase units, and 1116 selects an erase block according to a block address and changes the block address. A block selection address decoder for recognizing and outputting a signal, 1117 a redundant circuit for replacing in erase block units according to a redundant address, 1120 a register for storing trimming information and redundant address information for suppressing process variations during operation, Reference numeral 1121 denotes a trimming information and redundant information memory block in which the register 1120 stores trimming information and redundant address information transferred at the time of operation.

In FIG. 12, 121 is an inspection board and 1
22 is a DUT socket into which the semiconductor memory device of FIG. 11 is fitted,
Reference numeral 1210 is a page latch data read circuit for reading the data of the page latch circuit 115 of FIG. 11, and 1211 is the page latch circuit 115 of FIG. 11 which is not reset.
A first counter that counts each time, 1212 is a first determination circuit that determines a fail when the first counter 1211 is counted more than a certain number, and 1218 is a page latch circuit 115 that is not reset for each erase block. The second counter, 1219, which counts to, fails if the second counter 1218 is counted more than a certain number (Fa
il) A second judgment circuit for judgment.

The semiconductor memory device having the structure shown in FIG. 11 is inserted into the DUT socket 122 of the inspection board 121, and the write verify is performed during the write inspection to determine whether the writing is properly performed. At this time, the voltage of the bit line 111 is detected by the bit line voltage detection circuit 118, and when the writing to the memory cell 112 is normally performed, the page latch circuit 115 is reset by the latch reset circuit 119. If it is not reset, the memory cell becomes a defective write memory cell. The page latch circuit 115 provided for each bit line 111 of the defective write memory cell is read by the page data read circuit 1210 mounted on the inspection board 121, and the first counter is provided for each page latch circuit 115 that is not reset. 1
Count at 211. In the semiconductor memory device according to the ninth embodiment of the present invention, erase block 1113 is used as a unit.
2 blocks (redundant replacement memory block 815 is 2
Since the redundant replacement is executed up to the block setting, up to 64 word lines on the same bit line 111 of the erase block 113 can be redundantly repaired. Redundancy can be achieved by using bit line replacement redundancy, but in the case of flash memory, it is difficult to implement because there is an erase unit. Therefore, the semiconductor memory device according to the ninth embodiment of the present invention employs a redundancy replacement system in erase block units. Therefore, the fact that the first counter 1211 has reached 65 or more is determined by the determination circuit 1 1212, and Fail can be determined to be impossible. Further, the redundancy replacement memory block 1115 for redundancy in the erase unit is provided with two blocks due to the increase of the redundancy rate and the chip area. Therefore, if there is a write failure of three erase blocks or more, redundancy cannot be relieved. Therefore, the block selection address decoder 1116 recognizes a block address change during the write test, and every time the block address changes, the page latch circuit 115 which is not reset is mounted on the test board 121 as the second counter. 1218, the second determination circuit 121
It is judged from 9 that the defect cannot be redundantly repaired. In the current inspection, a long write inspection is performed to the end, and it is determined that a multi-block write failure is impossible for redundancy through complicated processing of the inspection device.

According to the configuration of the present invention, it is possible to make a defect determination as a non-redundant before a long write inspection, and to prevent a defect of only the inspection circuit by externally attaching a circuit used only for inspection to the inspection board. It is possible to provide a semiconductor memory device and an inspection board that can prevent temperature characteristic deterioration due to a high temperature inspection of the inspection circuit.

[Embodiment 10] FIG. 13 shows a tenth embodiment of the present invention.
2 shows a configuration of a semiconductor memory device in the embodiment. Embodiment 10 of the semiconductor memory device of the present invention will be described below with reference to FIG.

In FIG. 13, reference numeral 131 is a bit line connecting the drains of the memory cells, 132 is a memory cell having a floating gate, and a plurality of memory cells constitute an arrayed memory cell array, and 133 is a control gate of the memory cell. Connected word line, 134 is a source line connecting the source of the memory cell 132, 13
5 is a page latch circuit for latching write data, 1
36 is a column gate which is a transfer gate for electrically separating the memory cell 132 and the page latch circuit 135, 137 is a column decoder for selecting the column gate 136, 138 is a bit line voltage detection circuit for detecting the voltage of the bit line 131, 139 is a latch reset circuit that inverts the data of the page latch circuit 135 by the output of the bit line voltage detection circuit 137, 1310 is a page latch data read circuit that reads the contents of the page latch circuit 135, and 1311 is the page latch circuit 105 that has not been reset. A first counter that counts each time, 1312 is a determination circuit 1 that determines a fail when the first counter 1311 is counted more than a certain number, 1313 is an erase block, and 1314 is a user memory block used by the user. 1315 is a memory block for redundancy replacement which is a redundant block for redundancy in erase units, 1316 is a block address decoder which selects an erase block according to a block address, recognizes a change in the block address and outputs a signal, and 1317 is A redundant circuit for performing replacement in erase block units according to a redundant address, 1318 is a second counter for counting the page latch circuits 135 that have not been reset for each erase block,
Reference numeral 1319 denotes a second judgment circuit for making a fail judgment when the second counter 1318 is counted more than a certain number, and 1320 is a register for storing trimming information and redundant address information for suppressing process variations during operation. , 1321 are trimming information and redundant information memory blocks in which the register 1320 stores the trimming information and redundant address information transferred at the time of operation.

In the semiconductor memory device according to the tenth embodiment of the present invention, trimming is performed by the trimming circuit in order to suppress process variations. When performing this trimming, appropriate trimming data is adopted while changing the data in the register 1320. This register 1
Since the data of 320 is lost when the power supply voltage is turned off, the trimming information and redundant address information must be stored even when the power is turned off. Therefore, the trimming information of the nonvolatile memory block and the redundant information memory block 1321 are written and stored in advance. In operation, this memory block 132
Information is always transferred from 1 to the register 1320. At present, when writing information of the register 1320 to the memory block 1321, the trimming data and redundant address information are temporarily stored by the inspection device, and the page latch circuit 135 latches this information and writes it to the memory block 1321. It is processing.

Therefore, the semiconductor memory device according to the tenth embodiment of the present invention uses the page latch used when writing to the register 1320 and the memory block 1321 for storing trimming data and redundant address information. By connecting the circuits 135, the information stored in the register 1320 can be collectively transferred to the page latch circuit 135 to perform writing. Further, the page latch data read circuit 1310 reads the content of the register 1320 in a state of being transferred to the page latch circuit 135, so that the content of the register 1320 can be known.
A circuit for reading 20 is also unnecessary.

With the configuration of the present invention, it is possible to provide a semiconductor memory device capable of writing trimming data and redundant address information in a memory block without performing complicated processing, and reducing the chip area by reducing the number of circuits. .

[Embodiment 11] FIG. 14 shows an eleventh embodiment of the present invention.
2 shows a configuration of a semiconductor memory device in the embodiment. The eleventh embodiment of the semiconductor memory device of the present invention will be described below with reference to FIG.

In FIG. 14, reference numeral 141 is a bit line connecting the drains of the memory cells, 142 is a memory cell that has a floating gate, and a plurality of memory cells form an arrayed memory cell array, and 143 is a control gate of the memory cell. Connected word lines, 144 are source lines connecting memory cell sources, 145 are page latch circuits for latching write data, and 146 are column gates which are transfer gates for electrically separating the memory cells 142 and the page latch circuits 145. , 14
7 is a column decoder for selecting the column gate 146, 1
Reference numeral 48 is a bit line voltage detection circuit for detecting the voltage of the bit line 141, and 149 is a bit line voltage detection circuit 1.
A latch reset circuit that inverts the data of the page latch circuit 145 by the output of 47, 1410 is a page latch data read circuit that reads the contents of the page latch circuit 145, and 1411 is a first latch for each page latch circuit 145 that is not reset. Counter, 141
Reference numeral 2 is a first determination circuit 141 for determining a failure when the first counter 1411 is counted more than a certain number.
3 is an erase block, 1414 is a user memory block used by the user, 1415 is a redundant replacement memory block which is a redundant block for making redundancy in erase units, 1416 selects an erase block according to a block address, and changes the block address. A block selection address decoder that recognizes and outputs a signal, 1417 is a redundant circuit that performs replacement in erase block units according to a redundant address, 1418 is a second counter that counts the page latch circuits 145 that have not been reset for each erase block, 14
Reference numeral 19 is a determination circuit 2, 1421 for determining a failure when the second counter 1418 is counted more than a certain number.
1422 is a trimming information and redundant information memory block storing trimming information and redundant address information,
Is a sense amplifier for reading the memory cell 142 and a sense amplifier data latch circuit for storing the data of the sense amplifier 1422 even after the read operation is completed.

In the eleventh embodiment, trimming is performed by a trimming circuit that suppresses process variations. In this case, in the current semiconductor memory device, the trimming data and the redundant address information are transferred to the register and used before being operated. However, since the information is complicated, the circuit scale of the register has increased. Therefore, the semiconductor memory device in the embodiment of abortion 11 of the present invention can omit the circuit by using the page latch circuit 145 and the sense amplifier data latch circuit 1422. During the write operation, the trimming data and the redundant address information are transferred to the sense amplifier data latch circuit 1422 for use, and used except for the write operation (page latch circuit 1
Page latch circuit 14 in the mode of not using 45)
5 is used as a register.

With the structure of the present invention, it is possible to provide a semiconductor memory device capable of realizing a reduction in chip size by eliminating the register circuit that transfers trimming data and redundant address information during operation.

[Embodiment 12] FIG. 15 shows a twelfth embodiment of the present invention.
2 shows a configuration of a semiconductor memory device in the embodiment. A twelfth embodiment of the semiconductor memory device of the present invention will be described below with reference to FIG.

In FIG. 15, 151 is a memory cell array, 152 is a row decoder, 153 is a column decoder,
154 is a column gate which is a transfer gate, and 15
5 is a page latch circuit for latching write data, 1
Reference numeral 56 is a sense amplifier, 157 is a power supply circuit that realizes a single power supply, 158 is a page latch data read circuit that reads the contents of the page latch circuit 155, and 159 is a write bit that counts the number of bits actually written in the write data in write page units. Number counter, 15
A control circuit 10 increases the number of bits to be written in parallel by the number of write bit number counters 159.

Further, this embodiment includes the bit line voltage detection circuit for detecting the voltage of the bit line described in the previous embodiment and the latch reset circuit for inverting the data of the latch by the output of the bit line voltage detection circuit. Have.

In the semiconductor memory device according to the twelfth embodiment of the present invention, the write page unit is 256 bits. Before the write operation, the number of bits actually written in the write page unit is counted by the counter 159. The semiconductor memory device according to the twelfth embodiment of the present invention includes eight write page units. By counting the number of bits to be really written in units of 8 pages, for example, the number of bits to be really written in 256 bits is
Assuming that the first page is 100 bits, the second page is 128 bits, the third page is 200 bits, and the fourth page is 20 bits, then the number of bits actually written in the first page, the second page, and the fourth page is 248 bits. Becomes Since this is less than 256 bits of write page unit,
The number of parallel write bits is increased by the control circuit 1510 so that the first page, the third page of the second page, and the fourth page are written in parallel. The third page is 200 bits, and if added, it will exceed 256 bits, so skip the third page. When the writing of the first page, the second page, and the fourth page is completed, the number of pages to be written is sequentially optimized by the above means from the third page. The writing time is reduced to a maximum of 1/8. By doing so, the write time can be optimized depending on the number of bits actually written, and the current capacity of the power supply current can be set to the minimum, so that the chip size can be reduced.

With the configuration of the present invention, it is possible to provide a semiconductor memory device capable of reducing the power supply circuit which occupies a large portion of the chip size, and shortening and optimizing the rewriting time.

[Embodiment 13] FIG. 16 shows a thirteenth embodiment of the present invention.
2 shows a configuration of a semiconductor memory device in the embodiment. The thirteenth embodiment of the semiconductor memory device of the present invention will be described below with reference to FIG.

In FIG. 16, 161 is a memory cell array, 162 is a row decoder, 163 is a column decoder,
164 is a column gate which is a transfer gate, 16
5 is a page latch circuit for latching write data, 1
Reference numeral 66 is a sense amplifier, 167 is a power supply circuit that realizes a single power supply, 168 is a page latch data read circuit that reads the contents of the page latch circuit 165, and 169 is a write bit that counts the number of bits actually written in the write data in write page units. Number counter, 16
Reference numeral 10 is a control circuit for increasing the number of bits to be written in parallel by the number of write bit counters 159, and 1611 is a power supply voltage detection circuit for further increasing the number of bits to be written in parallel when the power supply voltage is high.

In this embodiment, the bit line voltage detection circuit for detecting the voltage of the bit line described in the previous embodiment and the latch reset circuit for inverting the data in the latch by the output of the bit line voltage detection circuit are provided. Have.

In the semiconductor memory device according to the thirteenth embodiment of the present invention, the write page unit is 256 bits. Before the write operation, the counter 169 counts the number of bits to be actually written in write page units. The semiconductor memory device according to the thirteenth embodiment of the present invention includes eight write page units. By counting the number of bits to be really written in units of 8 pages, for example, the number of bits to be really written in 256 bits is
Assuming that the first page is 100 bits, the second page is 128 bits, the third page is 200 bits, and the fourth page is 20 bits, then the number of bits actually written in the first page, the second page, and the fourth page is 248 bits. Becomes Since this is less than 256 bits of write page unit,
The number of parallel write bits is increased by the control circuit 1610 so that the first page, the third page of the second page and the fourth page are written in parallel. The third page is 200 bits, and if added, it will exceed 256 bits, so skip the third page. When the writing of the first, second, and fourth pages is completed, the number of pages to be sequentially written is optimized by the above means from the third page. The writing time is reduced to a maximum of 1/8. Further, in response to a wide range power supply voltage, when the power supply voltage is high, the power supply voltage detection circuit 1611 detects and outputs a signal to the control circuit 1610, and the write page unit is 51
The number of write parallels is increased as 2 bits. By doing so, the write time can be optimized depending on the number of bits actually written, and the current capacity of the power supply current can be set to the minimum, so that the chip size can be reduced. When the power supply voltage is higher, the writing time can be further shortened.

With the structure of the present invention, it is possible to provide a semiconductor memory device capable of reducing the power supply circuit occupying a large chip size and further shortening and optimizing the rewriting time.

[Embodiment 14] FIG. 17 shows a fourteenth embodiment of the present invention.
2 shows a configuration of a semiconductor memory device in the embodiment. The fourteenth embodiment of the semiconductor memory device of the present invention will be described below with reference to FIG.

In FIG. 17, 171 is a memory cell array, 172 is a row decoder, 173 is a column decoder,
174 is a column gate which is a transfer gate, 17
5 is a page latch circuit for latching write data, 1
Reference numeral 76 is a sense amplifier, 177 is a power supply circuit that realizes a single power supply, 178 is a page latch data read circuit that reads out the contents of the page latch circuit 175, and 179 is a write verify whether or not writing to a memory cell is properly performed. 1710, a write fail bit number counter for counting the number of bits that have not been written properly by reading the content of the page latch circuit 175 by the page latch data read circuit 178, 1710
Is a control circuit for increasing the number of bits to be written in parallel by the number of write fail bit number counters 179 at the time of write verify during the write operation.

Further, this embodiment includes the bit line voltage detection circuit for detecting the voltage of the bit line described in the previous embodiment and the latch reset circuit for inverting the data of the latch by the output of the bit line voltage detection circuit. Have.

In the semiconductor memory device according to the fourteenth embodiment of the present invention, the write page unit is 256 bits. Also, eight write page units are provided.
During the write operation, at the time of write verify that determines whether the memory cells are properly programmed, the number of page latch circuits 175 that are not reset by the page latch data read circuit 178, that is, the number of memory cells that have not been written is determined. The counter 179 counts. For example, the number of unfinished writes during write verify is 20 for the first page and 1 for the second page.
When the counter 179 counts 00, the third page has 200, and the fourth page has 100, 1,
The total number of write fail bits for pages 2 and 3 is 320 bits, which exceeds 256 bits per write page. Since the total number of write fail bits on the 1st, 2nd, and 4th pages is 220 bits, 2
It will be 56 bits or less. Therefore, the control circuit 1710 controls the first, second, and fourth pages to be written in parallel.
Then, when writing progresses and the number of write fail bits decreases, the number of pages to be written in parallel is increased by the control circuit 1710 so that the total of the counter 179 does not exceed 256 bits. Write Fail
By increasing the number of memory cells to be written in parallel depending on the number of bits, the write time can be shortened and optimized, and the current capacity of the power supply current can be set to the minimum, so that the chip size can be reduced.

With the configuration of the present invention, it is possible to provide a semiconductor memory device capable of reducing the power supply circuit occupying a large chip size, and shortening and optimizing the rewriting time.

[Embodiment 15] FIG. 18 shows a fifteenth embodiment of the present invention.
2 shows a configuration of a semiconductor memory device in the embodiment. A fifteenth embodiment of the semiconductor memory device of the present invention will be described below with reference to FIG.

In FIG. 18, 181 is a memory cell array, 182 is a row decoder, 183 is a column decoder,
184 is a column gate, 185 is a page latch circuit for latching write data, 186 is a sense amplifier, 18
Reference numeral 7 is a power supply circuit that realizes a single power supply, 188 is a page latch data read circuit that reads the contents of the page latch circuit 185, and 189 is a page latch circuit 185 at the time of write verify that writing to a memory cell is properly performed. Page latch data read circuit 1
Write Fail that counts the number of bits that have not been read and written properly by 88.
A bit number counter, 1810 is a control circuit that increases the number of bits to be written in parallel by the number of write fail bit number counters 189 at the time of write verify during a write operation, and 1811 is a bit to be written in parallel when the power supply voltage is high. This is a power supply voltage detection circuit for increasing the number.

Further, this embodiment includes the bit line voltage detection circuit for detecting the voltage of the bit line described in the previous embodiment and the latch reset circuit for inverting the data of the latch by the output of the bit line voltage detection circuit. Have.

In the semiconductor memory device according to the fifteenth embodiment of the present invention, the write page unit is 256 bits. Also, eight write page units are provided. During a write operation, the page latch circuit 1 is read by the page latch data read circuit 188 at the time of write verify to determine whether the memory cell is properly programmed.
The counter 189 counts the number of memory cells 85 that have not been reset, that is, the number of memory cells that have not been written. For example, the number of unfinished writes at the time of write verify is 20 for the first page and 10 for the second page.
When the counter 189 counts 0, the number of the third page is 200, and the number of the fourth page is 100, the total number of write fail bits of the first page, the second page, and the third page is 320 bits, and the number of write pages is a write page unit. 256 bits. 1 page, 2 pages, 4
The total number of write fail bits on the page is 2
Since it is 20 bits, it is 256 bits or less. Therefore, the control circuit 1810 controls the first, second, and fourth pages to be written in parallel. Then, when the writing progresses and the number of write fail bits decreases, the number of pages to be written in parallel is increased by the control circuit 1810 so that the total of the counter 189 does not exceed 256 bits.
Further, in response to a wide range power supply voltage, a high voltage voltage is detected by the power supply voltage detection circuit 1811 and detected by the control circuit 1.
A signal is output to 810 to set the write page unit to 512 bits and the write parallel number is increased. Writing fail
By increasing the number of memory cells to be written in parallel by the number of (Fail) bits, the writing time can be shortened and optimized, and the current capacity of the power supply current can be set to the minimum, so that the chip size can be reduced. When the power supply voltage is higher, the writing time can be further shortened.

With the structure of the present invention, it is possible to provide a semiconductor memory device capable of reducing the power supply circuit occupying a large chip size, and further shortening and optimizing the rewriting time.

[Embodiment 16] FIG. 19 shows a sixteenth embodiment of the present invention.
2 shows a configuration of a semiconductor memory device in the embodiment. The sixteenth embodiment of the semiconductor memory device of the present invention will be described below with reference to FIG.

In FIG. 19, 191 is a memory cell array, 192 is a row decoder, 193 is a column decoder,
194 is a column gate, 195 is a page latch circuit for latching write data, 196 is a sense amplifier, 19
Reference numeral 7 is a power supply circuit for realizing a single power supply, 198 is a page latch data read circuit for reading the contents of the page latch circuit 195, 199 is a write bit number counter for counting the number of bits actually written in write data in write page units, and 1910 is A control circuit that increases the number of bits to be written in parallel by the number of write bit number counters 199 and increases the number of parallel write bits by decreasing the write current during the write operation.
Is a memory cell drain current detection circuit at the time of writing, which detects the drain current of the memory cell at the time of writing in page units.

Further, this embodiment includes the bit line voltage detection circuit for detecting the voltage of the bit line described in the previous embodiment and the latch reset circuit for inverting the data of the latch by the output of the bit line voltage detection circuit. Have.

In the semiconductor memory device according to the sixteenth embodiment of the present invention, the write page unit is 256 bits. Prior to the write operation, the counter 199 counts the number of bits to be actually written in write page units. The semiconductor memory device according to the sixteenth embodiment of the present invention has eight write page units. By counting the number of bits to be really written in units of 8 pages, for example, the number of bits to be really written in 256 bits is
Assuming that the first page is 100 bits, the second page is 128 bits, the third page is 200 bits, and the fourth page is 20 bits, then the number of bits actually written in the first page, the second page, and the fourth page is 248 bits. Becomes Since this is less than 256 bits of write page unit,
The number of parallel write bits is increased by the control circuit 1910 so that the first page, the second page, and the third page of the fourth page are written in parallel. The third page is 200 bits, and if added, it will exceed 256 bits, so skip the third page. When the writing of the first, second, and fourth pages is completed, the number of pages to be sequentially written is optimized by the above means from the third page. In addition, the memory cell drain current at the time of writing in units of 1 page is about 3 mA for 256 bits.
Is. The memory cell drain current is monitored in page units by the write current detection circuit 1911 during writing, and when the writing progresses and the memory cell drain current during writing decreases to 1.5 mA, the number of bits actually written by the control circuit 1910 is half. The write time can be shortened by selecting the following pages and increasing the pages to be written in parallel.

With the structure of the present invention, it is possible to provide a semiconductor memory device capable of reducing the power supply circuit which occupies a large portion of the chip size, and shortening and optimizing the rewriting time.

[Embodiment 17] FIG. 20 shows a seventeenth embodiment of the present invention.
2 shows a configuration of a semiconductor memory device in the embodiment. The seventeenth embodiment of the semiconductor memory device of the present invention will be described below with reference to FIG.

In FIG. 20, 201 is a memory cell array, 202 is a row decoder, 203 is a column decoder,
Reference numeral 204 is a column gate, 205 is a page latch circuit for latching write data, 206 is a sense amplifier, 20
7 is a power supply circuit that realizes a single power supply, 208 is a page latch data read circuit that reads the contents of the page latch circuit 205, 209 is a write bit number counter that counts the number of bits actually written in write data in write page units, and 2010 is A control circuit 2011 that increases the number of bits to be written in parallel by the number of write bit number counters 209 and increases the number of parallel write bits by decreasing the write current during a write operation.
Is a memory cell drain current detection circuit for writing, which detects the memory cell drain current during writing in page units.
Reference numeral 2012 denotes a power supply voltage detection circuit that increases the number of parallel writes when the power supply voltage is high.

In addition, this embodiment includes the bit line voltage detection circuit for detecting the voltage of the bit line described in the previous embodiment and the latch reset circuit for inverting the data of the latch by the output of the bit line voltage detection circuit. Have.

In the semiconductor memory device according to the seventeenth embodiment of the present invention, the write page unit is 256 bits. Before the write operation, the counter 209 counts the number of bits to be actually written in write page units. The semiconductor memory device according to the seventeenth embodiment of the present invention has eight write page units. By counting the number of bits to be really written in units of 8 pages, for example, the number of bits to be really written in 256 bits is
Assuming that the first page is 100 bits, the second page is 128 bits, the third page is 200 bits, and the fourth page is 20 bits, then the number of bits actually written in the first, second, and fourth pages is 248 bits. Become. Since this is less than 256 bits per write page, the control circuit 2010 increases the number of parallel write bits so that the first page, the second page, and the fourth page are written in parallel. The third page is 200 bits, and if added, it will exceed 256 bits, so skip the third page. 1
After writing page 2, page 2 and page 4,
From the third page, the number of pages to be written is sequentially optimized by the above means. Further, the memory cell drain current at the time of writing on a page basis is about 3 mA for 256 bits. When writing starts, the memory cell drain current is monitored by the write current detection circuit 2011 in page units, and when writing progresses and the memory cell drain current during writing decreases to 1.5 mA, the number of bits actually written by the control circuit 2010 is determined. Writing time can be shortened by selecting pages of 128 bits or less and increasing the pages to be written in parallel. Further, corresponding to a wider range, when the power supply voltage is high, the power supply voltage detection circuit 2012 sets the detection level of the memory cell drain current detection circuit 2011 during writing to 1.5 mA.
From 2 mA to 2 mA, the total number of parallel write bits can be further increased.

With the structure of the present invention, it is possible to provide a semiconductor memory device capable of reducing the size of the power supply circuit occupying a large chip size, and further shortening and optimizing the rewriting time.

[Embodiment 18] FIG. 21 shows an eighteenth embodiment of the present invention.
2 shows a configuration of a semiconductor memory device in the embodiment. The eighteenth embodiment of the semiconductor memory device of the present invention will be described below with reference to FIG.

In FIG. 21, 211 is a memory cell array, 212 is a row decoder, 213 is a column decoder,
Reference numeral 214 is a column gate, 215 is a page latch circuit for latching write data, 216 is a sense amplifier, 21
7 is a power supply circuit for realizing a single power supply, 218 is a page latch data read circuit for reading the contents of the page latch circuit 215, 219 is a write bit number counter for counting the number of bits actually written in write data in write page units, and 2110 is The control circuit 2111 increases the number of bits to be written in parallel by the number of write bit number counters 219 and increases the number of parallel write bits according to the level of the boosted voltage during the write operation. It is a write voltage detection circuit that detects a boosted voltage to be applied.

Further, this embodiment includes the bit line voltage detection circuit for detecting the voltage of the bit line and the latch reset circuit for inverting the data of the latch by the output of the bit line voltage detection circuit described in the previous embodiment. Have.

In the semiconductor memory device according to the eighteenth embodiment of the present invention, the write page unit is 256 bits. Prior to the write operation, the counter 219 counts the number of bits actually written in write page units. The semiconductor memory device according to the eighteenth embodiment of the present invention includes eight write page units. By counting the number of bits to be really written in units of 8 pages, for example, the number of bits to be really written in 256 bits is
Assuming that the first page is 100 bits, the second page is 128 bits, the third page is 200 bits, and the fourth page is 20 bits, then the number of bits actually written in the first page, the second page, and the fourth page is 248 bits. Becomes Since this is less than 256 bits of write page unit,
The control circuit 2010 increases the number of parallel write bits so that the first page, the second page, and the third page, the fourth page, are written in parallel. The third page is 200 bits, and if added, it will exceed 256 bits, so skip the third page. When the writing of the first page, the second page, and the fourth page is completed, the number of pages to be written is sequentially optimized by the above means from the third page. Furthermore, the boost voltage applied to the memory cell drain during the write is monitored by the write voltage detection circuit 2111, and when the write progresses to a certain extent and the boost voltage becomes 8 V or more, the write page is increased in parallel by the control circuit 2110. . When the number of pages for parallel writing is increased, the boosted voltage detection circuit 211
When the voltage is detected to be 6 V or less by 1, the write page is skipped and the next write page is written in parallel.

With the configuration of the present invention, it is possible to provide a semiconductor memory device capable of reducing the power supply circuit occupying a large chip size, and shortening and optimizing the rewriting time.

[Embodiment 19] FIG. 22 shows a nineteenth embodiment of the present invention.
2 shows a configuration of a semiconductor memory device in the embodiment. The nineteenth embodiment of the semiconductor memory device of the present invention will be described below with reference to FIG.

In FIG. 22, 221 is a memory cell array, 222 is a row decoder, 223 is a column decoder,
224 is a column gate, 225 is a page latch circuit for latching write data, 226 is a sense amplifier, 22
7 is a power supply circuit for realizing a single power supply, 228 is a page latch data read circuit for reading the contents of the page latch circuit 225, 229 is a write bit number counter for counting the number of bits actually written in write data in write page units, and 2210 is A control circuit that increases the number of bits to be written in parallel by the number of write bit number counters 229 and also increases the number of parallel write bits according to the level of the boosted voltage during the write operation, 2211 is applied to the memory cell drain at the time of writing in page unit Write voltage detection circuit 221 for detecting boosted voltage
Reference numeral 2 is a power supply voltage detection circuit that further increases the number of parallel writes when the power supply voltage is high.

Further, this embodiment includes the bit line voltage detection circuit for detecting the voltage of the bit line described in the previous embodiment and the latch reset circuit for inverting the data of the latch by the output of the bit line voltage detection circuit. Have.

In the semiconductor memory device according to the nineteenth embodiment of the present invention, the write page unit is 256 bits. Prior to the write operation, the counter 229 counts the number of bits actually written in write page units. The semiconductor memory device according to the nineteenth embodiment of the present invention has eight write page units. By counting the number of bits to be really written in units of 8 pages, for example, the number of bits to be really written in 256 bits is
Assuming that the first page is 100 bits, the second page is 128 bits, the third page is 200 bits, and the fourth page is 20 bits, then the number of bits actually written in the first page, the second page, and the fourth page is 248 bits. Becomes Since this is less than 256 bits of write page unit,
The control circuit 2010 increases the number of parallel write bits so that the first page, the second page, and the third page, the fourth page, are written in parallel. The third page is 200 bits, and if added, it will exceed 256 bits, so skip the third page. When the writing of the first page, the second page, and the fourth page is completed, the number of pages to be written is sequentially optimized by the above means from the third page. Further, the boosted voltage applied to the drain of the memory cell during writing is detected by the boosted voltage detection circuit 2
Monitoring is performed at 211, and when the writing progresses to some extent and the boosted voltage becomes 8 V or more, the number of writing pages is increased in parallel by the control circuit 2210. When the boosted voltage detection circuit 2211 detects 6V or less at the time when the number of parallel write pages is increased, the write page is skipped and the next write page is written in parallel. Further, corresponding to a wider range, when the power supply voltage is high, the power supply voltage detection circuit 2212 further increases the number of bits to be written in parallel or the number of pages to be written.

With the structure of the present invention, it is possible to provide a semiconductor memory device capable of reducing the power supply circuit occupying a large chip size and further shortening and optimizing the rewriting time.

[Embodiment 20] FIG. 23 shows a twentieth embodiment of the present invention.
2 shows a configuration of a semiconductor memory device in the embodiment. A twentieth embodiment of the semiconductor memory device of the present invention will be described below with reference to FIG.

In FIG. 23, 231 is a bit line connecting the drains of the memory cells, 232 is a floating gate, and a plurality of memory cells are arranged in an array to form a memory cell array. 233 is a memory cell 23.
A word line connecting the two control gates, 23
4 is a source line for connecting the sources of the memory cells, 23
5 is a page latch circuit for latching write data, 2
36 is a column gate which is a transfer gate for electrically separating the memory cell 232 and the page latch circuit 235; 237 is a latch circuit for latching sense amplifier and sense amplifier data; 238 is a row decoder for selecting the word line 13; 239 is a column gate 236
A column decoder 2310 for selecting a page latch reset circuit forcibly resetting the page latch circuit 235, and a rewrite prohibition recognition circuit 2311 for recognizing a rewrite prohibited area.

The semiconductor memory device according to the twentieth embodiment of the present invention has a rewrite prohibited area. This is a memory area for storing the program when the flash memory is rewritten using the user's program. When an address is input to the rewrite prohibited area, the recognition circuit 2311 detects it, and the page latch circuit 235 is forcibly reset by the reset circuit 2310. By doing so, the row decoder 238 and the column decoder 23
Writing can be easily prohibited without controlling 9. Further, it becomes possible to prevent write drain disturb.

With the configuration of the present invention, it is possible to provide a semiconductor memory device which realizes high write reliability without complicated control and prevents write drain disturbance and the like.

[0150]

According to the semiconductor memory device of the first aspect, by latching the write data in the page latch circuit, reading the content, and comparing with the write data, the short circuit of the page latch circuit can be detected, and the long It is possible to make defective because it cannot be redundant before the writing inspection.

According to the semiconductor memory device of the second aspect,
The write data is latched in the page latch circuit, and the contents of the page latch circuit are read while the transfer gate is also selected all at once, and the short circuit between the page latch circuit and the bit line with a high defect rate is detected by comparing with the write data. Therefore, it is possible to make a defect as a non-redundant before a long write test.

According to the inspection board of the third aspect, the circuit realizing the means for inspecting the data of the page latch circuit according to the second aspect is used only for the inspection, but when incorporated in the semiconductor memory device, only this circuit is provided. Even if it is defective, this chip will be defective. Therefore, by mounting this circuit on an inspection board, it is possible to prevent defects in the inspection circuit only, and also to improve the temperature characteristics of this inspection circuit by high temperature inspection, etc. Deterioration can be prevented.

According to the semiconductor memory device of the fourth aspect,
By measuring the power supply current while the inverted data is latched in the adjacent page latch circuits, it is possible to detect a short circuit in the adjacent page latch circuits, and it is possible to make it defective as a non-redundant before a long write test. .

According to the inspection method of claim 5, the same effect as that of claim 4 can be obtained.

According to the semiconductor memory device of the sixth aspect,
By latching inverted data in adjacent page latch circuits and measuring the power supply current with the column gate also selected at a time, it is possible to detect short circuits between adjacent page latch circuits and bit lines with a high defect rate. It is possible to make a defect as non-redundant before a long write test.

According to the inspection method of claim 7, the same effect as that of claim 6 can be obtained.

According to the semiconductor memory device of the eighth aspect,
During the write test, the number of page latch circuits provided for each bit line that is not reset, that is, the number of memory cells in which write failures occur in the same bit line is counted, and the number of page latch circuits that are the same or more When the number of defects is counted, it can be determined to be non-redundant and can be determined to be defective in the middle of a long write test, and can also be determined to be defective before performing complicated redundancy processing.

According to the inspection board of the ninth aspect, the circuit for realizing the means for inspecting the semiconductor device of the eighth aspect is used only for the inspection, but when incorporated, only this circuit is defective. Since this chip also becomes defective, mounting this circuit on an inspection board can prevent defects in the inspection circuit only, and can also prevent temperature characteristic deterioration due to high temperature inspection of this inspection circuit. it can.

According to the semiconductor memory device of the tenth aspect, in addition to the means of the eighth aspect, the number of page latch circuits which are not reset during the write test is counted in erase block units. Redundancy is performed in units of this erase block, so that defects exceeding the number of provided redundant blocks cannot be made redundant. That is, in the middle of a long write test, it is possible to make a defect as non-redundant and to make it defective before performing complicated redundant processing.

According to the inspection board of the eleventh aspect, the circuit for realizing the means for the inspection of the tenth aspect is used only for the inspection, but when it is built in, even if only this circuit is defective, this chip Therefore, by mounting this circuit on the inspection board, it is possible to prevent only the inspection circuit from being defective, and further to prevent the temperature characteristics from being deteriorated due to the high temperature inspection of the inspection circuit.

According to the semiconductor memory device of the twelfth aspect, complicated processing of writing address information redundant to the trimming information subjected to the trimming processing for suppressing the process variation into the memory cell is performed, for example, the trimming information and the redundant address information. This can be simplified by connecting the register for storing the data and the page latch circuit so that the contents of the register can be collectively transferred to the page latch circuit.

According to the semiconductor memory device of the thirteenth aspect, by using the page latch circuit and the latch portion of the sense amplifier data in the register for storing the trimming information and the redundant address information, the register circuit becomes unnecessary and the chip area is reduced. Reduction can be realized.

According to the semiconductor memory device of the fourteenth aspect, the number of bits to be really written in the write data at the start of writing is counted in the write page unit by reading the page latch circuit, and the bits are written in parallel according to the number. The writing time can be shortened and optimized by increasing the number of bits. Further, it is possible to provide a semiconductor memory device capable of reducing the size of a power supply circuit occupying a large chip area.

According to the semiconductor memory device of the fifteenth aspect, the semiconductor memory device of the fourteenth aspect is provided with a power supply voltage detection circuit, and in the case of a high power supply voltage, the number of bits to be written in parallel is further increased to achieve high speed operation. Write time can be realized.

According to the semiconductor memory device of the sixteenth aspect, the page latch circuit of the bit normally written by the write verify during writing is reset.
The contents of this page latch circuit are read in write page units, and the number of page latch circuits that have not been reset, that is, the number of memory cells that have not been written, is counted, and the number of memory cells that have not been written is less than or equal to a certain number. At this point, the write time can be shortened and optimized by increasing the number of memory cells to be written. Further, it is possible to provide a semiconductor memory device capable of reducing the size of a power supply circuit occupying a large chip area.

According to the semiconductor memory device of the seventeenth aspect, the semiconductor memory device of the sixteenth aspect is provided with a power supply voltage detection circuit, and in the case of a high power supply voltage, the number of bits to be written in parallel is further increased to achieve high speed operation. Write time can be realized.

According to the semiconductor memory device of the eighteenth aspect, the content of the page latch circuit is read in write page units, the number of data to be actually written is recorded in write page units, and the write-time memory in write page units is stored. The cell drain current is monitored by the detection circuit, and when the writing progresses and the writing current decreases to some extent, the writing time can be shortened and optimized by a means for increasing the number of pages to be written based on the recording. Further, it is possible to provide a semiconductor memory device capable of reducing the size of a power supply circuit occupying a large chip area.

According to the semiconductor memory device of the nineteenth aspect, the semiconductor memory device of the eighteenth aspect is provided with a power supply voltage detection circuit, and in the case of a high power supply voltage, by increasing the number of bits to be written in parallel, high speed operation can be achieved. Write time can be realized.

According to another aspect of the semiconductor memory device of the present invention, the content of the page latch circuit is read in write page units, the number of data to be actually written is recorded in write page units, and the write memory in write page units is set. The cell drain voltage is monitored by the detection circuit, and when the write voltage reaches a predetermined voltage level, the write time can be shortened and optimized by a means for increasing the number of pages to be written based on the recording of . Further, it is possible to provide a semiconductor memory device capable of reducing the size of a power supply circuit occupying a large chip area.

According to the semiconductor memory device of the twenty-first aspect, the semiconductor memory device of the twentieth aspect is provided with a power supply voltage detection circuit, and in the case of a high power supply voltage, by increasing the number of bits to be written in parallel, high speed operation can be achieved. Write time can be realized.

According to the semiconductor memory device of the twenty-second aspect, by recognizing the rewrite-prohibited area and forcibly resetting the page latch circuit, writing can be easily prevented and deterioration of reliability such as program drain disturb is prevented. be able to.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a configuration diagram of an inspection board according to a third embodiment of the present invention.

FIG. 5 is a configuration diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 6 is a configuration diagram of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 7 is a configuration diagram of a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 8 is a configuration diagram of a semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 9 is a configuration diagram of an inspection board according to a seventh embodiment of the present invention.

FIG. 10 is a configuration diagram of a semiconductor memory device according to an eighth embodiment of the present invention.

FIG. 11 is a configuration diagram of a semiconductor memory device according to a ninth embodiment of the present invention.

FIG. 12 is a configuration diagram of an inspection board according to a ninth embodiment of the present invention.

FIG. 13 is a configuration diagram of a semiconductor memory device according to a tenth embodiment of the present invention.

FIG. 14 is a configuration diagram of a semiconductor memory device according to an eleventh embodiment of the present invention.

FIG. 15 is a configuration diagram of a semiconductor memory device according to a twelfth embodiment of the present invention.

FIG. 16 is a configuration diagram of a semiconductor memory device according to a thirteenth embodiment of the present invention.

FIG. 17 is a configuration diagram of a semiconductor memory device according to a fourteenth embodiment of the present invention.

FIG. 18 is a configuration diagram of a semiconductor memory device according to a fifteenth embodiment of the present invention.

FIG. 19 is a configuration diagram of a semiconductor memory device according to a sixteenth embodiment of the present invention.

FIG. 20 is a configuration diagram of a semiconductor memory device according to a seventeenth embodiment of the present invention.

FIG. 21 is a configuration diagram of a semiconductor memory device according to an eighteenth embodiment of the present invention.

FIG. 22 is a configuration diagram of a semiconductor memory device according to a nineteenth embodiment of the present invention.

FIG. 23 is a configuration diagram of a semiconductor memory device according to a twentieth embodiment of the present invention.

FIG. 24 is a configuration diagram showing a conventional example of a semiconductor memory device.

[Explanation of symbols]

11, 21, 31, 51, 61, 71, 81, 101, 111,
131, 141, 231, 242 bit lines 12, 22, 32, 52, 62, 72, 82, 102, 112,
132, 142, 232, 243 memory cells 13, 23, 33, 53, 63, 73, 83, 103, 113,
133,143,233,244 word lines 14,24,34,54,64,74,84,104,114,
134,144,234,245 source lines 15,25,35,55,65,75,85,105,115,
135,145,155,165,175,185,195,
205, 215, 225, 234, 246 pages Latch circuit 16, 26, 36, 56, 66, 76, 86, 106, 116,
136,146,236 column gate 17,27,37,1422,156,166,176,18
6,196,206,216,226,237,247 sense amplifier and sense amplifier data latch circuit 18,28,38,152,162,172,182,192,
202,212,222,238 row decoder 19,29,39,57,67,77,87,107,117,
137, 147, 153, 163, 173, 183, 193,
203, 213, 223, 239 column decoders 110, 210, 310, 157, 167, 177, 187,
197, 207, 217, 227, 249 power supply circuit 1101, 2101, 311, 1020, 1120, 132
0,2410 trimming data and redundant address information storage registers 1102,2102,43,710,910,1010,12
10,1310,1410,158,168,178,18
8,198,208,218,228 Page latch data read circuit 1103,2103,44 Write data and page latch data comparison circuit 2104,314,69 Column gate batch select circuit 41,91,121 Inspection board (performance board) 42, 92,122 DUT socket 58,68 Inverted data batch latch circuit 78,108,118,138,148 Bit line voltage detection circuit 79,89,109,119,139,149,2310 Page latch reset circuit 711,911,1011, 1211, 1311, 1411,
179, 189 Counters 712, 912, 1012, 1212, 1312, 1412 that count for each page latch circuit that has not been reset
Judgment circuit 713, 813, 1013, 1113, 1313, 1413 based on the result of the counter of the page latch circuit which is not reset
Erase block (redundant replacement block unit) 714, 814, 1014, 1114, 1314, 1414
User memory unit (user block) 715, 815, 1015, 1115, 1315, 1415
Redundant replacement memory blocks 1016, 1116, 1316, 1416 Erase block address decoders 1017, 1117, 1317, 1417 Redundant replacement circuits 1018, 1218, 1318, 1418 Counters 1019, 1219 for counting page latch circuits that have not been reset for each erase block. , 1319, 1419 Judgment circuit 1021, 1121, 1321, 1421 trimming information and redundant information memory block 159, 169 based on the result of counting the page latch circuits that have not been reset for each erase block Counters 1510, 1610 for counting memory cells to be actually written , 1710,1810,1910,20
10, 2210 control circuits 1611, 1811, 2012, 2212 power supply voltage detection circuits 1911, 2011 write memory cell drain current detection circuits 2111, 2211 write voltage boost voltage detection circuit 2311 rewrite prohibited block address recognition circuit 248 address decoder

Claims (22)

[Claims] 1. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting a drain of the memory cell in the memory cell array, and a bit line provided for each bit line. A page latch circuit, a transfer gate electrically separating the page latch circuit from the bit line, a page latch read circuit for reading the contents of the page latch circuit, and comparing the data of the page latch read circuit with write data. A semiconductor memory device having a comparison circuit for making a fail judgment when they do not match. 2. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and a bit line provided for each bit line. A page latch circuit, a transfer gate for electrically separating the page latch circuit and the bit line, a transfer gate batch selection circuit for collectively selecting the transfer gate, and a page latch reading for reading the contents of the page latch circuit. A semiconductor memory device comprising: a circuit; and a comparison circuit that compares the data of the page latch read circuit with write data and determines a failure if they do not match. 3. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and a bit line provided for each bit line. Inspection used during inspection of a semiconductor memory device including a page latch circuit, a transfer gate electrically separating the page latch circuit from the bit line, and a transfer gate batch selection circuit collectively selecting the transfer gate A board for connecting the semiconductor memory device, means for reading the content of the page latch circuit connected to the connection portion, and comparing the read content of the page latch circuit with write data. Write data with a comparison circuit that determines if there is a mismatch Inspection board with 較回 road. 4. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and a bit line provided for each bit line. A semiconductor memory device including a page latch circuit, a transfer gate electrically separating the page latch circuit from the bit line, and an inverted data batch latch circuit for collectively latching inverted data in adjacent page latch circuits. . 5. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting a drain of the memory cell in the memory cell array, and a bit line provided for each bit line. A semiconductor memory including a page latch circuit, a transfer gate electrically separating the page latch circuit from the bit line, and an inverted data batch latch circuit for collectively latching inverted data in adjacent page latch circuits. A method for inspecting a device, comprising: measuring a power supply current with the page latch circuit latching inverted data. 6. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting a drain of the memory cell in the memory cell array, and a bit line provided for each bit line. A page latch circuit, a transfer gate that electrically separates the page latch circuit from the bit line, a batch latch circuit that collectively latches inverted data in the adjacent page latch circuits, and the transfer gate together. A semiconductor memory device including a transfer gate collective selection circuit for selecting by selecting. 7. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and a bit line provided for each bit line. A page latch circuit, a transfer gate that electrically separates the page latch circuit from the bit line, a batch latch circuit that collectively latches inverted data in the adjacent page latch circuits, and the transfer gate together. A method for inspecting a semiconductor memory device comprising a transfer gate batch selection circuit for selecting the transfer gate, wherein a power supply current is measured in a state where the page latch circuit latches inverted data and the transfer gates are collectively selected. Characterized inspection method. 8. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and a bit line provided for each bit line. A page latch circuit, a transfer gate that electrically separates the bit line from the page latch circuit, a bit line voltage detection circuit that detects the voltage of the bit line, and data latched by the output of the bit line voltage detection circuit. A latch reset circuit that inverts the data, a means for resetting the page latch circuit when the write is properly performed at the time of write verify for determining whether the write is properly performed, and a content of the page latch circuit is read. Page latch read circuit and reset A semiconductor memory device comprising: a counter that counts the page latch circuits that are not provided for each page latch circuit; and a determination circuit that determines a failure when the counter has counted a certain number or more. 9. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting a drain of the memory cell in the memory cell array, and a bit line provided for each bit line. An inspection board used for inspection of a semiconductor memory device, comprising: a page latch circuit, a transfer gate electrically separating the page latch circuit from the bit line, and means for reading the contents of the page latch circuit. A connection unit that connects a semiconductor memory device, the page latch read circuit that is connected to the connection unit and reads the contents of the page latch circuit, and a counter that counts the page latch circuit that has not been reset for each page latch circuit. And the counter was counted more than a certain number Test board with a slip failure determining circuit. 10. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a redundant circuit for redundancy in an erase block unit when there is a defective memory cell in the memory array, A redundant block for replacing an erase block having a defective memory cell, a block selection address decoder for switching the erase block, and a bit line connecting the drains of the memory cells in the memory cell array,
A page latch circuit provided for each bit line,
A transfer gate that electrically separates the page latch circuit and the bit line, a bit line voltage detection circuit that detects the voltage of the bit line, and a latch reset that inverts the data in the latch by the output of the bit line voltage detection circuit. A circuit, a means for resetting the page latch circuit when the write is properly performed at the time of write verify for determining whether or not the write is properly performed, and a page latch read circuit for reading the contents of the page latch circuit. A first counter that counts the page latch circuits that have not been reset for each page latch circuit; a first determination circuit that performs a fail determination when the first counter has counted a certain number or more; and the block selection Interlock with the address decoder and the first counter A second counter for counting the bad block, the semiconductor memory device having a fail-determining second determination circuit when the second counter is more than the number in the count. 11. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a redundant circuit for redundancy in an erase block unit when there is a defective memory cell in the memory array, A redundant block for replacing an erase block having a defective memory cell, a block selection address decoder for switching the erase block, and a bit line connecting the drains of the memory cells in the memory cell array,
A page latch circuit provided for each bit line,
A test board used when testing a semiconductor memory device, comprising: a transfer gate electrically separating the page latch circuit from the bit line; and a means for reading the contents of the page latch circuit, the test board being connected to the semiconductor memory device. A connection section, a page latch read circuit connected to the connection section for reading the contents of the page latch circuit, a first counter for counting the page latch circuit which is not reset for each page latch circuit, A first judgment circuit for making a fail judgment when the first counter counts more than a certain number; a second counter for counting defective blocks in cooperation with the block selection address decoder and the first counter; Second judgment circuit for making a fail judgment when the counter of 2 is counted more than a certain number Inspection board with. 12. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a redundant circuit for redundancy in an erase block unit when there is a defective memory cell in the memory array, A redundant block for replacing an erase block having a defective memory cell, a bit line connecting the drains of the memory cells in the memory cell array, a page latch circuit provided for each bit line, the page latch circuit and the A transfer gate that electrically separates the bit lines, a trimming circuit that suppresses process variations, a register that stores redundant address and trimming information, and information of the register that is transferred to the page latch circuit and is transferred to the memory cell. Semiconductor memory equipped with means for batch writing Storage device. 13. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a redundant circuit for redundancy in an erase block unit when there is a defective memory cell in the memory array, A redundant block for replacing an erase block having a defective memory cell, a bit line connecting the drains of the memory cells in the memory cell array, a sense amplifier for reading information from the memory cell, and data read by the sense amplifier. A latch circuit for holding, a page latch circuit provided for each bit line, a transfer gate electrically separating the page latch circuit and the bit line, and a trimming circuit for suppressing process variations are provided. Sometimes store redundant address and trimming information A semiconductor memory device, wherein a register to be stored is shared by using the latch circuit and the page latch circuit. 14. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting a drain of the memory cell in the memory cell array, and a bit line provided for each bit line. A page latch circuit, a transfer gate that electrically separates the bit line from the page latch circuit, a bit line voltage detection circuit that detects the voltage of the bit line, and data latched by the output of the bit line voltage detection circuit. A latch reset circuit that inverts, a page latch read circuit that reads the contents of the page latch circuit, a write bit number counter that counts the number of bits that are actually written in the write data at the start of writing in write page units,
A semiconductor memory device comprising a control circuit for increasing the number of bits to be written in parallel by the number of write bit number counters. 15. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and a bit line provided for each bit line. A page latch circuit, a transfer gate that electrically separates the bit line from the page latch circuit, a bit line voltage detection circuit that detects the voltage of the bit line, and data latched by the output of the bit line voltage detection circuit. A latch reset circuit that inverts, a page latch read circuit that reads the contents of the page latch circuit, a write bit number counter that counts the number of bits that are actually written in the write data at the start of writing in write page units,
A semiconductor memory device including a control circuit for increasing the number of bits to be written in parallel according to the number of write bit counters, and a power supply voltage detection circuit for further increasing the number of bits to be written in parallel when a power supply voltage is detected and the power supply voltage is high. . 16. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting a drain of the memory cell in the memory cell array, and a bit line provided for each bit line. A page latch circuit, a transfer gate that electrically separates the bit line from the page latch circuit, a bit line voltage detection circuit that detects the voltage of the bit line, and data latched by the output of the bit line voltage detection circuit. A latch reset circuit that inverts the data, a means for resetting the page latch circuit when the write is properly performed at the time of write verify for determining whether the write is properly performed, and a content of the page latch circuit is read. Page latch read circuit and reset A semiconductor memory device comprising a counter that counts the page latch circuits that are not written in write page units, and a control circuit that increases the number of bits to be written in parallel when the counter is within a certain number during a write operation. 17. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and a bit line provided for each bit line. A page latch circuit, a transfer gate that electrically separates the bit line from the page latch circuit, a bit line voltage detection circuit that detects the voltage of the bit line, and data latched by the output of the bit line voltage detection circuit. A latch reset circuit that inverts the data, a means for resetting the page latch circuit when the write is properly performed at the time of write verify for determining whether the write is properly performed, and a content of the page latch circuit is read. Page latch read circuit and reset A counter that counts the page latch circuit that has not been written in write page units, a control circuit that increases the number of bits to be written in parallel when the counter is within a certain number during the write operation, and detects the power supply voltage. A semiconductor memory device comprising a power supply voltage detection circuit that further increases the number of bits to be written in parallel when the power supply voltage is high. 18. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting a drain of the memory cell in the memory cell array, and a bit line provided for each bit line. A page latch circuit, a transfer gate that electrically separates the bit line from the page latch circuit, a bit line voltage detection circuit that detects the voltage of the bit line, and data latched by the output of the bit line voltage detection circuit. A latch reset circuit that inverts, a page latch read circuit that reads the contents of the page latch circuit, a write bit number counter that counts the number of bits that are actually written in the write data at the start of writing in write page units,
A write current detection circuit that detects the drain current of the memory cell at the time of writing in a page unit and a write current detection circuit that monitors the write current detection circuit when the writing in a page unit progresses and the write bit decreases to a certain extent. A semiconductor memory device having a control circuit for increasing the number of pages to be written based on the contents of a number counter. 19. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting a drain of the memory cell in the memory cell array, and a bit line provided for each bit line. A page latch circuit, a transfer gate that electrically separates the bit line from the page latch circuit, a bit line voltage detection circuit that detects the voltage of the bit line, and data latched by the output of the bit line voltage detection circuit. A latch reset circuit that inverts, a page latch read circuit that reads the contents of the page latch circuit, a write bit number counter that counts the number of bits that are actually written in the write data at the start of writing in write page units,
A write current detection circuit that detects the drain current of the memory cell at the time of writing in a page unit and a write current detection circuit that monitors the write current detection circuit when the writing in a page unit progresses and the write bit decreases to a certain extent. Semiconductor memory device having a control circuit for increasing the number of pages to be written based on the contents of the number counter and a power supply voltage detecting circuit for further increasing the number of bits to be written or the number of pages to be written in parallel when the power supply voltage is detected and the power supply voltage is high . 20. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and a bit line provided for each bit line. A page latch circuit, a transfer gate that electrically separates the bit line from the page latch circuit, a bit line voltage detection circuit that detects the voltage of the bit line, and data latched by the output of the bit line voltage detection circuit. A latch reset circuit that inverts, a page latch read circuit that reads the contents of the page latch circuit, a write bit number counter that counts the number of bits that are actually written in the write data at the start of writing in write page units,
Write voltage detection circuit that detects the boosted voltage level in write page units, and write in page units progresses,
A semiconductor memory device comprising: a control circuit that monitors the write voltage detection circuit and increases the number of pages to be written based on the content of the write bit number counter when the write voltage reaches a predetermined voltage level. 21. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and a bit line provided for each bit line. A page latch circuit, a transfer gate that electrically separates the bit line from the page latch circuit, a bit line voltage detection circuit that detects the voltage of the bit line, and data latched by the output of the bit line voltage detection circuit. A latch reset circuit that inverts, a page latch read circuit that reads the contents of the page latch circuit, a write bit number counter that counts the number of bits that are actually written in the write data at the start of writing in write page units,
The write voltage detection circuit for detecting the boosted voltage level in the write page unit and the write voltage detection circuit monitoring the write voltage detection circuit, and the write bit number when the write voltage reaches a predetermined voltage level. A semiconductor memory device comprising: a control circuit that increases the number of pages to be written based on the contents of a counter; and a power supply voltage detection circuit that detects the power supply voltage and, in the case of a high power supply voltage, further increases the number of bits to be written or the number of write pages. 22. A memory cell having a floating gate, a memory cell array in which the memory cells are arranged in an array, a bit line connecting the drains of the memory cells in the memory cell array, and a bit line provided for each bit line. A page latch circuit, a transfer gate that electrically separates the page latch circuit from the bit line, and a decoder that recognizes a write-protected area,
A semiconductor memory device comprising means for forcibly resetting the page latch circuit in conjunction with the decoder.