JP2003200839A - Controller for electric power steering device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely shut off through-current only when determining on failure of an FET in an H bridge circuit 18 and shorten a PWM control stop period to the utmost, in a controller for electric power steering device including a torque sensor 9, an assist motor 10, and a control unit 13 for driving the motor by the H bridge circuit 18 of a feedback system according to steering torque. <P>SOLUTION: A power source relay 13b is inserted in a cable way connecting the H bridge circuit 18 and a battery 14, and a relay 18e is inserted, for example, in an upper part of a left driving circuit and a relay 18f in an lower part thereof, respectively. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for an electric power steering system having an assist motor for generating a steering assist force for a steering system of a vehicle.

[0002]

2. Description of the Related Art A conventional electric power steering device is
In order to assist the steering torque at the time of steering by the driver, the steering torque is detected by the torque sensor, the vehicle speed is detected by the vehicle speed sensor, and the assist motor is driven according to the detected vehicle speed and torque. The assist torque was added to the steering wheel to improve the operability of the steering wheel.

As a circuit for driving the assist motor, a semiconductor control element, for example, an H-bridge circuit in which FETs (field effect transistors) are bridge-connected is used.

That is, the FE is placed between the positive and negative terminals of the battery.
When T is bridge-connected, an assist motor is connected between the bridge points of the bridge circuit, and at the time of right steering, the FETs on the upper and lower stages of the right driving circuit of the H-bridge circuit are pulse-width modulated (hereinafter, (Referred to as PWM), the assist motor is rotated to the right, and at the time of steering to the left, the FETs in the upper and lower stages of the left side drive circuit of the H bridge circuit are PWed.
The assist motor is rotated counterclockwise by M control.

As disclosed in Japanese Patent Laid-Open No. 2001-206236, for example, a control device in this electric power steering device includes relays between an H bridge circuit and a power source and a relay between the H bridge circuit and an assist motor. Is provided.

That is, when the apparatus is not in operation, the relay is kept open to disconnect the energizing line to avoid generation of a large current due to reverse battery connection, for example.

Further, when a short circuit failure of the FET occurs during the operation of the device, the relay is switched to an open state in order to avoid generation of a large current due to the failure, malfunction of the motor, or regenerative lock. The power line is cut off.

[0008]

However, the device disclosed in the above-mentioned Japanese Patent Laid-Open No. 2001-206236 is not
If the relay provided in the energization line between the bridge circuit and the power supply fails, and if the upper and lower FETs are simultaneously turned on (short-circuited) and a through current flows, an H bridge circuit and assist The relay provided between the motor and the motor has a problem that the through current cannot be interrupted.

Further, in the conventional control device for the electric power steering device, even if the FET is simply fixed to be ON due to external noise or the like, it is determined that it is an ON failure, and the above-described control is performed. Relay cutoff, PW
Since the M control is stopped, there is a problem that the assist stop frequency becomes very high.

Further, fine control such as determining which FET of the H-bridge circuit has an ON failure and performing appropriate control based on the determination result has not been performed.

The present invention has been made in view of the above points, and an object thereof is to surely interrupt a through current only when an on-failure of a semiconductor control element of an H-bridge circuit is confirmed and to stop PWM control. An object of the present invention is to provide a control device for an electric power steering device, which can shorten the period as much as possible and can perform appropriate control depending on which semiconductor control element is in an ON failure.

[0012]

A control device for an electric power steering system according to the present invention for solving the above-mentioned problems is provided as follows.
A torque sensor for detecting the steering torque of the steering wheel, a motor for energizing an auxiliary load to the steering shaft provided integrally with the steering wheel, and a H-bridge circuit of a feedback system for the motor according to the magnitude of the steering torque. A control device for an electric power steering device, comprising: a control unit for driving; a first relay inserted in an electric path connecting the H bridge circuit and a power source; and an upper stage portion of the H bridge circuit, which is a right side driving circuit. Or a second relay inserted in either one of the left side driving circuits and the H bridge circuit lower stage part,
It is characterized in that it has a relay and a third relay inserted in a drive circuit on the same side.

Further, after detecting an on-failure of the semiconductor control element constituting the H-bridge circuit, the on-failure is determined when the failure continues for a predetermined time, and the first and second
And an ON failure determination process for opening the third relay,
A control unit that performs an in-fault process for opening the second and third relays and stopping the pulse width modulation control of the semiconductor control element of the H-bridge circuit only for a predetermined time period before the on-fault is determined. It is characterized by that.

When the H-bridge circuit is on-failed, a determination process is performed to determine which of the semiconductor control elements forming the H-bridge circuit has an on-failure, and the H-bridge circuit of the H-bridge circuit is checked. Among the right-side driving circuit or the left-side driving circuit, when the ON failure of the semiconductor control element of the upper part or the lower part constituting the circuit on the side where the pulse width modulation control is performed is determined, the pulse width modulation control is performed. And the process of opening the first, second, and third relays by determining the on-failure after the on-failure continues for a predetermined time, and the right drive circuit of the H-bridge circuit or When it is determined that the semiconductor control element of the upper stage or the lower stage of the left side driving circuit that constitutes the circuit on the side where the pulse width modulation control is not performed is ON-failed, The process of stopping the control only for a minute period, the process of re-closing the second or third relay after the open state for a period longer than the minute period, and the process of continuing the ON failure until the re-closing time. It is characterized in that a control unit is provided for executing a process of establishing an on-failure and opening the first, second and third relays.

[0015]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of an electric power steering device to which the present invention is applied.
In FIG. 1, the steering wheel 1 is connected to a pinion shaft 6 via an input shaft side steering shaft 2a, an output shaft side steering shaft 2b, a universal joint 3, an intermediate shaft 4 and a universal joint 5.

The lower end of the pinion shaft 6 meshes with a horizontally extending rack shaft 7, and the rack shaft 7 and the pinion shaft 6 constitute a rack and pinion mechanism. Both ends of the rack shaft 7 are connected to steering wheels (not shown) via tie rods 8a and 8b, respectively, and the rack shaft 7 is horizontally moved so that the left and right wheels are steered. .

A torque sensor 9 for detecting the steering torque of the steering wheel 1 is provided on the steering shaft 2a, and an assist motor 10 for assisting the steering force of the steering wheel 1 is coupled to the steering shaft 2b via a speed reducer 11. ing.

Reference numeral 13 is a control unit for controlling the power steering device, which is supplied with electric power from a battery 14 through an ignition switch 15 and is based on a steering torque detected by a torque sensor 9 and a vehicle speed detected by a vehicle speed sensor 16. Then, the motor drive current (target current command value) is obtained, and the current supplied to the assist motor 10 is controlled based on the target current command value.

The control unit 13 has a function of detecting an ON failure of the semiconductor control element of the H-bridge circuit for driving the assist motor 10 and determining whether or not the failure continues for a predetermined time. For example, a microcomputer has a function of determining whether an ON failure has occurred, a function of stopping and executing PWM control according to the detection status of the ON failure, and the like. Is configured.

In FIG. 2, the same parts as those in FIG. 1 are designated by the same reference numerals. Reference numeral 18 denotes an FET (field effect transistor) 18a to 18d that is bridge-connected to form an H-bridge circuit, and a relay 18e (second relay) is inserted between the FET 18a and the common connection point P to provide an FET 18d.
And a common connection point N between the relay 18f (third relay).

An assist motor 10 is connected between the bridge points of the H bridge circuit, that is, between the common connection points R and L.

The common connection point P is a current detection resistor 13
c, the relay 13b (first relay) and the fuse F ₁ are connected to the positive electrode of the battery 14. The positive electrode of the battery 14 through an ignition switch 15 and a fuse F _2, is also connected to the power supply circuit 13a for supplying power to each circuit in the control unit 13. The common connection point N of the H bridge circuit is grounded.

The terminal voltage of the assist motor 10 is detected by the motor terminal voltage detecting means 13g, and the current flowing through the assist motor 10 is based on the current flowing through the current detecting resistor 13c, for example, a motor current detecting means including an operational amplifier. Detected by 13d.

Reference numeral 17a is a steering torque calculating means for calculating the steering torque based on the output of the torque sensor 9. 17
Reference numeral b is a vehicle speed calculating means for calculating the vehicle speed based on the output of the vehicle speed sensor 16.

Reference numeral 17c is an instruction current calculating means for calculating an instruction current based on the outputs of the steering torque calculating means 17a and the vehicle speed calculating means 17b. The FET 17a of the H bridge circuit 17d is based on the outputs of the motor current detector 13d and the instruction current calculator 17c.
Is a PWM duty determining means for determining an on / off duty ratio for PWM control of the.

13e is a PWM duty determining means 17
It is a power element drive circuit which performs PWM control of each FET of the H bridge circuit based on the duty ratio determined in d.

Reference numeral 17g is an instruction current calculation means 17c, PW
M duty determining means 17d, motor current detecting means 13
d, each FET of the H bridge circuit (motor drive circuit 18) based on each output of the motor terminal voltage detection circuit 13g
The relays 13a to 18d are detected, and the relay 13 is detected according to the failure status (which FET has an ON failure, whether the ON failure continues for a predetermined time, or the like).
It is an abnormality detecting means for sending a control signal for controlling opening / closing of b, 18e, 18f to the relay drive circuit 13f.

The relay drive circuit 13f, based on the control signal from the abnormality detecting means 17g, relays 13b,
The excitation currents of the coils 18e and 18f are supplied or stopped.

In the H bridge circuit of the motor drive circuit 18, for example, in the case of clockwise rotation, the FETs 18b and 18c are PW.
The FETs 18a and 18d are off-controlled while being M-controlled. Therefore, the current flowing from the battery 14 to the H bridge circuit via the fuse F ₁ , the relay 13b, and the current detection resistor 13c is FET 18c → assist motor 1
It flows in the path of 0 → FET 18b → ground.

In the case of counterclockwise rotation, FETs 18a and 18d
Is PWM-controlled and the FETs 18b and 18c are off-controlled. Therefore, from the battery 14, the fuse F
₁ , the current flowing through the H bridge circuit via the relay 13b and the current detection resistor 13c is relay 18e → FET 18
a-assist motor 10-FET 18d-relay 18f
→ It flows on the grounded route.

As a result, the assist motor 10 (hereinafter,
The motor may be simply referred to as a motor) and rotates in the direction in which the steering wheel 1 is in the steering operation to assist the steering force.

Next, the operation of the apparatus configured as described above will be described with reference to FIG. 3 showing a control flow chart, FIG. 4 showing a time chart, FIG. 5 showing a current path when the motor rotates right, and a current path when the motor rotates left. Fig. 6 shows all FEs when an ON failure occurs
A description will be given with reference to FIG. 7 showing a current path when T is turned off. 3 to 7, the same parts as those in FIGS. 1 and 2 are designated by the same reference numerals.

The broken line arrows in FIGS. 5 to 7 each represent a current path, and FIG. 5A and FIG. 6A both show the normal state of all FETs.

In FIG. 5 (b), the FET 18a during the off command is issued.
Turns on and a through current (short-circuit current) occurs.

In FIG. 5 (c), the FET 18 during PWM driving
b is turned on and the potential of the motor terminal L drops to the ground potential.

In FIG. 5D, the FET 18 in PWM driving
When c fails to turn on and the electric potential of the motor terminal R is the battery voltage V
rise to b.

In FIG. 5 (e), the FET 18d during the off command is issued.
Is turned on and a through current is generated.

In FIG. 6B, the FET 18 during PWM driving
a is ON failure and the potential of the motor terminal L is the battery voltage V
rise to b.

In FIG. 6 (c), the FET 18b during the off command is issued.
Is turned on and a through current is generated.

In FIG. 6 (d), the FET 18c during the off command is issued.
Is turned on and a through current is generated.

In FIG. 6 (e), the FET 18 in PWM driving
When d is turned on, the potential of the motor terminal R drops to the ground potential.

FIG. 7A shows a current path when all the FETs are turned off when the FET 18a, which is in the off command at the time of clockwise rotation, fails to turn on and a through current occurs.
FIG. 7B shows a current path when all the FETs are turned off when the FET 18d, which was in the off command at the time of right rotation, has an on failure and a through current is generated, and FIG. 7C shows an off command at the time of left rotation. FIG. 7D shows a current path when all the FETs are turned off when the inside FET 18b is turned on and a shoot-through current is generated. 2 shows a current path when all FETs are turned off when a through current is generated.

In the case of FIG. 7, a diode (parasitic diode) is formed between the drain and the source of each FET due to its structure, so that a closed loop is formed through the diode even if the FET is turned off.

In the flow chart of FIG. 3, first, in step S101, it is checked whether the FLAG in which the FET is in failure is 0 or 1, and if it is 1 (in the failure in ON), step S1.
If it is 0 (no ON failure), the process proceeds to step S118.

In step S102, a timer TMC during FET ON failure and a threshold value 2 (ON failure recheck time)
Are compared, and if TMC ≧ threshold value 2, step S10
3, and if TMC <threshold value 2, step S10
Go to 6.

In step S103, the relays 18e, 18
It is determined whether or not f is open (non-conductive state), and if it is open state, the process proceeds to step S104, and if it is not open state (conductive state), step S
Proceed to 112.

In step S104, PWM control is restarted for rechecking the FET ON failure, and step S1
At 05, the relay in the open state is closed (conducting state) and the power is supplied to the H-fridge circuit again. Step S10
At 6, the timer TMC during FET ON failure is incremented.

In step S107, the FET ON failure timer TMC is compared with the threshold value 3 (ON failure determination time). If TMC ≧ threshold value 3, the ON failure is determined, and the process proceeds to step S108. If TMC <threshold value 3, the process proceeds to step S125 and ends.

In step S108, the PWM control is stopped as the FET ON failure confirmation process, and in steps S109, the relays 18e and 18f are opened, the closed circuit is cut off, and the through current is stopped.

In step S110, the power supply relay 13b is opened to completely cut off the power supply to the motor drive circuit 18.

In step S111, the FET ON failure confirmation flag is set, and the flow advances to step S125 to end the processing.

If the relay is in the conductive state in step S103, the flow advances to step S112 to recheck the ON failure.

In step S112, it is checked whether or not the current value I is within a predetermined value, and the FET in the OFF command is instructed.
ON failure is judged.

FET in the 0FF command (18 in FIG. 5B)
a, 18d of FIG. 5 (e), 18b of FIG. 6 (c), FIG.
When 18c) in (d) is ON-failed, a through current is generated in the GND via the battery Bat and the ON-failure FET, so a large current equal to or higher than the current value (target current value) controlled according to the steering torque. Is detected by the current sensor, so that the ON failure can be detected.

If the current value is above a predetermined value, the FET turns off.
It is determined that there is N failure, and the process proceeds to step S106 and F
The process proceeds to the increment processing of the timer TMC during ET ON failure. If the current is within the predetermined value, it is determined that the 0FF command FET is not ON-failed, and the process proceeds to step S113.

At step S113, FE during PWM driving
It is determined whether T is ON-failed. If the FET in PWM driving on the battery power supply side has an ON failure (Fig. 5)
18c in (d), 18a in FIG. 6 (b), the motor terminal voltage connected to the arm on the power source side is the battery power source voltage Vb.
Rise to near. If the FET is normal, the power supply side motor terminal voltage will not rise to near the battery power supply voltage Vb unless the PWM duty is close to 100%.

On the other hand, the GND side FET during the PWM drive is O
When N failure occurs, the motor terminal voltage connected to the GND side arm drops to the GND level. As with the FET on the power supply side, if the FET is normal, the PWM duty is 1
If it is not close to 00%, the GND side motor terminal voltage becomes GND.
It does not fall to the level.

Therefore, the PWM duty is 90%, for example.
Despite the following, the power supply side motor terminal (Fig. 5 (a))
, R in FIG. 6 (a) is approximately Vb, and when the GND side motor terminal (L in FIG. 5 (a),
In (a), when the R) voltage is almost at the GND level, it can be determined that the FET being PWM-driven has an ON failure.

When it is determined that the FET being PWM-driven has an ON failure, the process proceeds to step S106.
The process proceeds to the increment process of the ON failure timer TMC. When it is determined that there is no ON failure, the process proceeds to step S114. In step S114, 1 is subtracted from the FET ON failure timer TMC, and the process proceeds to step S115.

In step S115, the FET TON failure timer TMC is compared with the threshold value 2. If TMC <threshold value, the process proceeds to step S116, and if TMC ≧ threshold value, the process proceeds to step S125 to end the process. .

In step S116, the FET ON failure flag is cleared by rechecking the FET ON failure, so the FET ON failure flag is cleared, and the timer TMC is set to 0 in step S117 to execute the processing. finish.

In this case, the last FET ON failure is due to the FET being turned on due to some unexpected cause such as external noise.
If it is determined that it is only fixed and the assist is stopped for a short time for determining the ON failure determination, normal assist control can be performed thereafter.

If the FET ON failure flag is 0 in step S101 (no ON failure), step S
Proceed to step 118 to perform ON failure check. In step S118, it is checked whether or not the current value I is within a predetermined value as in step S112, and the FFF in the 0FF command is checked.
Judge ON failure of ET. O if not within the specified value
It is determined that there is N failure, and the process proceeds to step S120.

If it is within the predetermined value, the FE in the 0FF command is issued.
It is determined that T has no ON failure, and the process proceeds to step S119. In step S119, the O of the FET during PWM drive
Detect N faults. The detection method is the same as in step S113. If no ON failure is detected here, the process proceeds to step S124 to end the process.

When an ON failure is detected, step S
Proceed to 120. In step S120, the FET ON failure timer TMC is incremented, and in step S121
Is compared with threshold 1.

If TMC ≧ threshold value, the first ON failure detection of the FET is confirmed, and if TMC <threshold value, the process directly proceeds to step S125 to end the processing.

The PWM control is stopped in step S122, and the relays 18e and 18f are set to 0P in step S123.
The closed circuit is cut off as EN (non-conducting state) to stop the through current. In step S124, the FET ON failure flag is set to 1 and the process ends.

Next, the flow of control when the FET-on failure is determined will be described with reference to FIGS. 3 and 4 (a). First, the time t at normal time
_{In 1} , NO in step S101, step S1
If YES in step 18 and NO in step S119, the process in one control cycle ends in step S125.

Next, when an ON failure occurs in any of the FETs at time t ₂ , NO is obtained in step S101, NO is obtained in step S118, or step S1 is performed.
It becomes YES in 19 (when the FET for which the OFF command is issued has an ON failure as shown in FIGS. 5B and 5E, it becomes NO in step S118, and PWM driving is performed as shown in FIGS. 5C and 5D). If the FET in the ON state has a failure, YES is obtained in step S119.
Will be). Then, in step S120, the FET on-failure timer TMC is incremented, and step S121
Is NO, and the process ends (step S125).

The control flow at the time t ₂ is the time t when the timer value of the timer TMC is less than the threshold value 1.
_The same applies to ₃ .

Next, the timer TMC of the FET on failure timer
Time t when the threshold value reaches the threshold value 1 _FourIn the
No in step S101, and NO in step S118.
Or YES in step S119, the step
In S120, the timer TMC is incremented,
It becomes YES in step S121. And step S1
The PWM control is stopped at step 22, and H-blocking is performed at step S123.
Open the relays 18e and 18f of the latch circuit (OPEN)
(This interrupts the shoot-through current), then step
In S124, the FET ON failure flag is set and the step
The process ends in step S125.

Next, time t _{5 when} the timer value of the FET on-failure timer TMC is greater than or equal to the threshold value 1 and less than the threshold value 2
In step S101, YES (because the FET ON failure flag is set), step S10
If NO in step 2, the timer TMC is set in step S106.
Is incremented, the result is NO in step S107, and the process ends in step S125.

Next, the timer TMC during the failure of the FET on
Time t when the threshold value reaches threshold 2 ₆In the
YES at step S101, YES at step S102
YES is obtained in step S103, and the process is repeated in step S104.
PWM control is restarted for checking, and step S105
To close the relays 18e and 18f (CLOSE)
It Then, in step S106, the timer TMC is turned on.
Is performed, and NO is obtained in step S107,
The process ends at step S125.

Next, the time t _{7 when} the timer value of the FET on-failure timer TMC is greater than or equal to the threshold value 2 and less than the threshold value 3
In step S101, YES, in step S1
If YES in step 02, NO in step S103. And it becomes NO in step S112 or step S113
NO in step S106, the timer TMC is incremented in step S106, NO in step S107, and the process ends in step S125.

Then, the timer TMC during the failure of FET on
Time t when the threshold value reaches the threshold value 3 ₈In the
YES at step S101, YES at step S102
It becomes NO in step S103. And step S112
Or NO in step S113, and
In step S106, the timer TMC is incremented.
Therefore, YES is determined in step S107. Therefore FE
As the T-on failure determination process, PWM is performed in step S108.
The control is stopped, and the H-bridge circuit is reset in step S109.
Rays 18e and 18f are opened, and in step S110
Open the relay 13b inserted in the battery power line.
The state is set, and the process ends in step S125.

The control flow is the same whether the motor is rotating clockwise or counterclockwise. Therefore, it is possible to reliably cut off the shoot-through current regardless of which FET in the H-bridge circuit has an ON failure.

Next, the control flow when the FET ON failure is undetermined (for example, when the FET is fixed to ON due to external noise or the like and returned to normal before the ON failure is determined) is shown in FIGS.
It will be described together with (b).

First, at a normal time t ₁ , NO is obtained in step S101, YES is obtained in step S118, NO is obtained in step S119, and the process in one control cycle is completed in step S125.

Next, if an ON failure occurs in any of the FETs at time t ₂ , NO is obtained in step S101, NO is obtained in step S118, or step S1 is performed.
It becomes YES in 19. Next, in step S120, the FET on-failure timer TMC is incremented, and in step S121, the determination is NO and the process ends (step S).
125).

The control flow at the time t ₂ is the time t when the timer value of the timer TMC is less than the threshold value 1.
_The same applies to ₃ .

Next, the timer TMC of the FET on failure timer
Time t when the threshold value reaches the threshold value 1 _FourIn the
No in step S101, and NO in step S118.
Or YES in step S119, the step
In S120, the timer TMC is incremented,
It becomes YES in step S121. And step S1
The PWM control is stopped at step 22, and H-blocking is performed at step S123.
Open the relays 18e and 18f of the latch circuit (OPEN)
(This interrupts the shoot-through current), then step
In S124, the FET ON failure flag is set and the step
The process ends in step S125.

Next, the time t _{5 when} the timer value of the FET on-failure timer TMC is greater than or equal to the threshold value 1 and less than the threshold value 2
In step S101, YES (because the FET ON failure flag is set), step S10
If NO in step 2, the timer TMC is set in step S106.
Is incremented, the result is NO in step S107, and the process ends in step S125.

Next, at the time t _{6 when the} ON failure is normally recovered and the timer value of the FET ON failure timer TMC reaches the threshold value 2, YES is obtained in step S101, YES is obtained in step S102, and YES is obtained in step S103. Then, in step S104, the PWM control is restarted for the recheck, and in step S105, the relays 18e and 18f are closed (CLOSE). And step S106
Then, the timer TMC is incremented, the result is NO in step S107, and the process in one control cycle is ended in step S125.

In the next control cycle, YES is obtained in step S101, YES is obtained in step S102, and NO is obtained in step S103. Then, in step S112, Y
ES and YES at step S113 (the FET is
ON failure has returned to normal), so step S11
At 4, the timer value of the timer TMC is decremented by one. Then, YES is obtained in the step S115, the FET ON failure flag is cleared in a step S116, and the step S117 is performed.
The timer value of the timer TMC is set to 0.

The flow of the control is the same whether the motor is rotating clockwise or counterclockwise.

As described above, for example, when the FET is fixed to the ON state due to the external noise or the like and is returned to the normal state before the ON failure is fixed, the PWM control is stopped (assistance is not performed) only for a short period from the time t _{4 to} t _6. Just stop).

Next, another embodiment of the present invention will be described with reference to FIGS. 8 and 9 showing a control flow chart, FIGS. 10 to 13 showing a time chart, and FIG. 1 showing a current path when the motor rotates rightward.
4. The current path when the motor rotates to the left will be described with reference to FIG. 8 to 15, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals.

The broken line arrows in FIGS. 14 and 15 each represent a current path, and FIG.
It shows the current path when the relay 18e is opened and the penetration current (short-circuit current) is interrupted when the ET 18a has an ON failure.

FIG. 14B shows F during PWM driving with right rotation.
It shows a current path when the PWM control is continued when the ET 18b has an ON failure.

FIG. 14C shows F during PWM driving with clockwise rotation.
The current path when the PWM control is continued when the ET 18c has an ON failure is shown.

FIG. 14 (d) shows the FE during the off command by the clockwise rotation.
The current path when the relay 18f is opened and the through current (short-circuit current) is interrupted when the T18d has an ON failure.

FIG. 15A shows F during PWM driving with left rotation.
The current path when the PWM control is continued when the ET 18a has an ON failure is shown.

FIG. 15B shows the FE which is in the left rotation and the OFF command is being issued.
It shows a current path when the relays 18e and 18f are opened and the through current is interrupted when the T18b has an ON failure.

FIG. 15C shows the FE which is in the left rotation and the OFF command is being issued.
It shows a current path when the relays 18e and 18f are opened and the through current is interrupted when the T18c has an ON failure.

FIG. 15D shows F during PWM driving with left rotation.
The current path is shown when the PWM control is continued when the ET 18d has an ON failure.

FIG. 8 is a flow chart when the motor rotates clockwise. First, in step S201, the rotation direction of the motor is determined. If it is rotating to the right, proceed to step S202,
Otherwise, it proceeds to step S237.

In step S202, the FETs 18a and 18 are
It is determined whether both d are ON-failed. Both are O
If there is no N failure, the process proceeds to step S203, and if either FET has an ON failure, step S22.
Go to 4.

In step S203, the FETs 18b and 18 are
It is determined whether both c are ON-failed. Both are O
If there is no failure, the process proceeds to step S204. If either of the FETs has an ON failure, step S22
Go to 1.

In step S204, it is determined whether or not the current value detected by the current sensor 13c is within a predetermined value. FETs 18a, 1 issuing 0FF command when the motor rotates right
When either of the 8d is ON-failed, a short circuit path is formed from the battery to the GND via the ON-failure FET and a through current is generated, so that a large current exceeding the motor drive maximum allowable current value is detected by the current sensor. ON failure of FET can be detected.

If it is determined that the current value is within the predetermined value and the 0FF command FET is not ON-failed, the process proceeds to step S205. If it is equal to or higher than the predetermined value, it is determined that the FET 18a or 18d in the 0FF command is ON-failed. Step S219
Proceed to.

In steps S205 and S206, it is determined whether the FET being PWM-driven has an ON failure. The FET in PWM drive on the battery power supply side turns on.
When a failure occurs (18c in FIG. 14C), the voltage of the motor terminal connected to the arm on the power supply side rises to near the battery power supply voltage Vb.

If the FET is normal, the power supply side motor terminal voltage will not rise to near the battery power supply voltage Vb unless the PWM duty is close to 100%. On the other hand, P
When the GND side FET during WM driving has an ON failure (18b in FIG. 14B), the motor terminal voltage connected to the GND side arm drops to the GND level.

As with the FET on the power supply side, if the FET is normal, the PWM duty is not close to 100%.
The D side motor terminal voltage never drops to the GND level. Therefore, when the PWM duty is, for example, 90% or less, the power supply side motor terminal (R in FIG. 14C) has a voltage of approximately Vb, and the GND side motor terminal (L in FIG. 14B). When the voltage is at the GND level, it can be determined that the FET being PWM-driven has an ON failure.

When the R terminal voltage is determined to be abnormal in step S205, the FET18cON failure flag is set in step S218, and when the L terminal voltage is determined to be abnormal in step S206, FET18bO is determined in step S211.
Set the N failure flag.

If the motor terminal voltage is not abnormal in steps S205 and S206, the process proceeds to step S207. In step S207, the failure detection counter COUNT
Is determined to be 0. If 0, step S208
If it is not 0, COUNT is decremented by 1 in step S209.

When COUNT is not 0, the case where the ON failure of the FET is detected once has returned to the normal state.
In step S208, the ON failure flag of each FET is cleared to 0, and in step S210, the processing in one control cycle ends. When the ON failure of the FET is not detected, the above steps are advanced to complete the processing.

P in steps S205 and S206
When the ON failure of the FET being driven by the WM is detected, the FE which has failed in step S211, step S218
The failure flag of T is set to 1, and the process proceeds to step S212. In step S212, the failure detection counter COUNT
Is incremented by 1, and the process proceeds to step S213.

In step S213, the failure detection counter C
COUNT is compared with the threshold value 1, and if COUNT ≧ threshold value 1, the process proceeds to step S214. If COUNT <threshold value 1, the process proceeds to step S210 and ends the process.

In steps S214 to S217, the FE is still in the ON failure even if a predetermined time (= threshold value 1) has elapsed after the ON failure of the FET was detected.
ON failure of T is confirmed, PWM is stopped and relay 18
Set e, 18f and power relay 13b to 0PEN and turn them ON.
The failure determination flag is set to 1 and the ON failure determination process is executed.

In step S219, step S204
When it is determined that the current value is equal to or more than the predetermined value and the through current is flowing, the FETs (18b, 18c) in the PWM drive are set to 0F.
In addition to the F state, the FET 18 is set in step S220.
Set ON failure flags of a and 18d, and step S2
Proceed to 12.

At this stage, the through current is equal to that of the FETs 18a and 1a.
It is not specified which ON failure of 8d is causing the failure, and by stopping the PWM, the short circuit path is cut off and the through current is immediately stopped to prevent the FET from being damaged.

In step S221, the FET1
When 8b or 18c is determined to be ON failure, both relays 18e and 18f are opened to prevent shoot-through current, so it is checked whether the relay is closed or open. If the relay is closed, step S
The process proceeds to 205 to check for abnormal terminal voltage. If the relay is open, the process proceeds to step S222 to close the relay, and PWM is started in step S223.

In step S224, when it is determined in step S204 that the FETs 18a and 18d that generate a through current at the time of right rotation are defective, the PWM drive is stopped (all FET OFF command), but at the time of left rotation, the FET 18 is turned off.
If it is determined that the a and 18d are out of order, the PWM drive is continuing, so it is determined whether the PWM drive is stopped. If the PWM driving is stopped, the process proceeds to step S225, and if the PWM driving is performed, the step S2 is performed.
Proceed to 30.

In step S225, an abnormality in the L terminal voltage of the motor is detected. If the L terminal voltage is equal to or higher than a predetermined value, the FET 18a failure flag is set in step S226.

If the L terminal voltage is within a predetermined value, the FET
It is determined that 18d has a failure, and F is determined in step S228.
Set the ET18d failure flag.

If the FET 18a has an ON failure, the relay 1 is turned on in step S227 to prevent shoot-through current.
8e is opened, and when the FET 18d has an ON failure, the relay 18f is similarly opened in step S229.

The above processing is performed by the 0FF command FE at the time of right rotation.
This is a process for identifying the ON failure FET of T.

In step S230, step S224
If it is determined that the PWM is being driven by, the relay 18
It is determined whether either e or 18f is open. If either is open, step S23
1. If both are closed, step S2
Proceed to 33.

In step S231, the failure detection counter C
COUNT is compared with the threshold value 2, and if COUNT ≧ threshold value 2, the through current is detected again, so step S2
At 32, both relays 18e and 18f are closed. CO
If UNT <threshold value 2, the process proceeds to step S212.

In step S233, when it is determined in step S230 that both relays 18e and 18f are closed, step S2 is performed again to check the through current.
Whether the relay was closed at 32, FET 18 by left rotation
It is determined whether the ON failure of the a and 18f is determined (in this case, the relays 18e and 18f are not opened).

That is, when the failure detection counter COUNT is below the threshold value 2 and the relay is closed,
Since it is the case where the ON failure of the FET 18a or 18d is determined by the left rotation, the PWM drive is stopped to stop the through current in step S234, and the FET 18 is stopped in step S235.
If "a" is out of order, the process proceeds to step S227 and the relay 18e is opened.

If it is determined in step S235 that the FET 18d is out of order, the process proceeds to step S229 to open the relay 18f.

At step S236, 0FF command FET1
For re-failure determination of 8a and 18d, it is determined whether the current value is within a predetermined value. If it is within the predetermined value, the process proceeds to step S207. If it is equal to or more than the predetermined value, it means that the shoot-through current is detected again. Therefore, the failure determination process from step S214 is performed.

The above is the control flow when the motor rotates right.

Next, a control flow chart when the motor is rotated counterclockwise will be described with reference to FIG. First, in step S237, it is determined whether the motor is rotating counterclockwise. If it is rotating to the left, the process proceeds to step S238, and if not, the process proceeds to step S261.

In step S238, the FETs 18b and 18 are
It is determined whether both c are ON-failed. Both are O
If there is no N failure, the process proceeds to step S239, and if either FET has an ON failure, step S25.
Go to 0.

In step S239, the FETs 18a and 18 are
It is determined whether both d are ON-failed. Both are O
If there is no failure, the process proceeds to step S240. If either of the FETs has an ON failure, step S24
Proceed to 7.

In step S240, it is determined whether or not the current value is within a predetermined value. If it is within the predetermined value, the flow-through current has not been generated, and thus the process proceeds to step S241.

In step S241, it is determined whether or not the voltage at the motor right terminal R is within a predetermined value and the PWMDUTY is within a predetermined value, and the FET 18 in PWM driving is determined.
Determine the ON failure of d.

R terminal voltage is within a predetermined value and PW
If MDUTY is within the predetermined value, it is determined that the FET 18d is normal, and the process proceeds to step S242.

If the R terminal voltage abnormality is detected, step S
At 244, the failure flag of the FET 18d is set to 1.

In step S242, it is determined whether the voltage of the motor left terminal L is within a predetermined value and the PWMDUTY is within a predetermined value. If each is within the predetermined value, the process proceeds to step S207.

This confirms that each FET was normal. On the other hand, if it is determined that the L terminal voltage is abnormal, the failure flag of the FET 18a is set to 1 in step S243. The above processing is the flow when each FET is normal.

If an abnormal motor terminal voltage is detected in steps S241 and S242, step S24
3, a failure flag is set in step S244, and the process proceeds to step S212.

In step S245, when an abnormal current is detected in step S240, all the FETs are set to 0FF in order to stop the through current, and the short circuit path is cut off.
Proceed to 46.

In step S246, the FETs 18b and 18 are
Set the failure flag in c. Step S2 for right rotation
As in the case of 20, the FET 18b, 18c, which of the ON failures is the current abnormality, is not specified at this stage, and the through current is immediately stopped in step S245.

In step S247, the FET is turned rightward.
Relay 18e or 1 if 18a or 18d fails
To open 8f, it is determined whether the relay is open. If the relays 18e and 18f are not open, the process proceeds to step S241, where the relays 18e and 18f are opened.
If either 18f is open, step S24
Go to 8.

In step S248, the open relay 18e or 18f is closed, and in step S249.
Starts PWM drive.

In step S250, the PWM drive is stopped when it is determined in step S240 that the FETs 18b and 18c, which generate the through current at the time of left rotation, have failed, but the FETs 18b and 18c have failed at the time of right rotation. If it is determined that there is a
Determine if the drive is stopped. If the PWM drive is stopped, the process proceeds to step S251. If the PWM drive is being performed, the process proceeds to step S255.

In step S251, an abnormality in the R terminal voltage of the motor is detected, and if the R terminal voltage is equal to or higher than a predetermined value, the FET 18c failure flag is set in step S252.
If the R terminal voltage is within the predetermined value, it is determined that the FET 18b has a failure, and the FET 18b failure flag is set in step S253.

In step S254, the relays 18e, 18
Through-current prevention processing is performed with both f open, and the process proceeds to step S249 to start PWM drive.

In step S255, step S250
If it is determined that the PWM drive is in progress, the relay 18
It is determined whether both e and 18f are open.

If it is open, the process proceeds to step S256, and if both are closed, the process proceeds to step S258.

In step S256, the failure detection counter C
COUNT is compared with the threshold value 2, and if COUNT ≧ threshold value 2, the through current is detected again, so step S2
At 57, both relays 18e and 18f are closed. CO
If UNT <threshold value 2, the process proceeds to step S212.

In step S258, when it is determined in step S255 that the relays 18e and 18f are both closed, step S2 is performed again to check the through current.
Whether the relay was closed at 57
It is determined whether or not b and 18c are determined to be ON failures (in this case, the relays 18e and 18f are not opened).

That is, when the failure detection counter COUNT is less than the threshold value 2 and the relays are both closed,
Since it is a case where the FET 18b or 18c is turned on by the right rotation, the PWM drive is stopped in step S259 to stop the through current, and the process proceeds to step S254 to open both the relays 18e and 18f.

At step S260, 0FF command FET1
For re-failure determination of 8b and 18c, it is determined whether the current value is within a predetermined value. If it is within the predetermined value, the process proceeds to step S207. If it is equal to or more than the predetermined value, it means that the shoot-through current is detected again. Therefore, the failure determination process from step S214 is performed.

The above is the processing flow when the motor is rotated counterclockwise.

If it is determined in step S237 that the motor is not rotating to the left, the motor is stopped in the neutral state, and the process proceeds to step S261. Step S261
Then, it is simply determined whether or not the ON failure of each FET is detected, and if it is in the failure detection state, the process proceeds to step S212, the failure detection counter is updated, and the counter update is continued until a predetermined time for failure confirmation is reached. If each FET is normal, the process proceeds to step S207 to continue the process.

The above is the processing flow in the motor neutral state.

Next, the FET 18 in the PWM drive with the right rotation.
The control flow when b has an ON failure (see FIG. 14B) will be described with reference to FIGS. 8 and 10. First, the time t ₁ at the normal time
In step S20, the determination results of steps S201 to S207 are all YES.
The FET failure flag is set to 0 in step 8, and step S21
When 0, the processing in one control cycle is completed.

Next, at time t ₂ , when an ON failure occurs in the FET 18b, steps S201 to S20 are performed.
The determination result of 5 is YES, but N in step S206
It becomes O. For this reason, the FET 18b ON failure flag is set in step S211, the failure detection counter COUNT is incremented by 1 in step S212, and N is determined in step S213.
It becomes O, and the process ends in step S210.

Next, at time t ₃ when the value of the failure detection counter COUNT does not reach the threshold value 1, step S
YES in step 201, YES in step S202, NO in step S203, NO in step S221, and step S221
If YES in step 205, NO in step S206 (GN)
Because it has fallen to the D level). Therefore, step S
The FET 18b ON failure flag is set at 211, the failure detection counter COUNT is incremented by 1 at step S212, and NO is obtained at step S213.
The process ends at 0.

The flow of control at the time t ₃ is the same from time t _{4 to} t ₆ when the value of the failure detection counter COUNT is less than the threshold value 1.

Next, at time t ₇ when the value of the failure detection counter COUNT reaches the threshold value 1, step S2 is performed.
YES at 01, YES at step S202, S
203: NO, Step S221: NO, Step S2
If YES in step S05, NO in step S206. Therefore, the FET 18b ON failure flag is set in step S211, and the failure detection counter COUNT is set in step S212.
T is incremented by 1, and YES is obtained in step S213. Therefore, as the FET on failure determination process, step S21
In step 4, all the FETs are turned off to stop the PWM control. In step S215, the relays 18e and 18f of the H-bridge circuit are opened, and in step S216, the relay 13b inserted in the battery power line is opened, and then step S216.
At 217, the ON failure confirmation flag 1 is set, and step S
The processing ends at 210.

The flow of the control is as follows.
When the driving FET 18c has an ON failure (see FIG. 14).
The same applies to (c) (however, in this case, step S2).
If NO in 05, the ON failure flag of the FET 18c is set in step S218).

As described above, according to the control in FIG.
The PWM control can be continued during the period until the failure of the FET 18b or 18c is determined during the clockwise rotation. In the above control, if the normal recovery is made between the detection of the FET on-failure and the determination of the on-failure, YES is obtained in steps S205 and S206, and step S20 is performed.
It goes without saying that the value of the failure detection counter COUNT is set to 0 and the FET-on failure flag is cleared to 0 by the processing of 7 to step S210.

Next, the FET 18a which is in the OFF command by the right rotation
The control flow when the ON failure occurs (see FIG. 14A) will be described with reference to FIGS. 8 and 11. First, in the time t ₁ in the normal, since all steps S201~ determination result in steps S207 becomes YES, a step S208
The FET failure flag to 0, and step S210
Then, the processing in one control cycle is completed.

Next, at time t ₂ , when an ON failure occurs in the FET 18a, steps S201 to S20 are performed.
The determination result of 3 is YES, but N in step S204
It becomes O (because a through current flows). Therefore, all the FETs are turned off in step S219 to stop the PWM control, the FET18a ON failure flag is set in step S220, the failure detection counter COUNT is incremented by 1 in step S212, and NO is obtained in step S213, and step S210 is performed. Ends the process.

[0160] Next, at time t ₂ time t ₃ of immediately after, YES in step S201, NO at step S202, YES in step S224, a YES at step S225 (because it is raised to the battery voltage Vb). Thus sets FET18a ON failure flag in step S226, PWM relay 18e is opened, and at time t ₄ in step S223 in step S227
The control is restarted, and in step S212, the failure detection counter C
OUNT is incremented by 1, NO is obtained in step S213, and the process ends in step S210.

Next, at time t _{5 when} the value of the failure detection counter COUNT is less than the threshold value 2, step S2
YES in 01, NO in step S202, and step S2
24 (NO because PWM control is restarted), YES in step S230, NO in step S231, increments the failure detection counter COUNT by 1 in step S212, NO in step S213, and in step S210. The process ends.

Next, at time t ₆ when the value of the failure detection counter COUNT reaches the threshold value 2, step S2
YES in 01, NO in step S202, and step S2
24, NO, step S230, YES, step S2
Since YES is obtained in 31, the relay 18e is closed in order to perform the current determination again in step S232. Then, the failure detection counter COUNT is incremented by 1 in step S212, NO is obtained in step S213, and step S2
The process ends at 10.

Next, at time t _{7 when} the value of the failure detection counter COUNT exceeds the threshold value 2, at step S20.
YES in step 1, NO in step S202, step S22
4, NO in step S230, NO in step S230
NO in step S236, and NO in step S236. Therefore F
As the ET-on failure confirmation processing, all Fs are processed in step S214.
ET is turned off to stop the PWM control, and step S21
5, the relays 18e and 18f of the H-bridge circuit are opened, the relay 13b inserted in the battery power line is opened in step S216, the on-failure confirmation flag 1 is set in step S217, and the process is performed in step S210. To finish.

The flow of the control is as follows.
The same applies when 18d has an ON failure (FIG. 14D) (however, in this case, NO is obtained in step S225, the FET 18d ON failure flag is set in step S228, and relay 18f is opened in step S229). .

As described above, according to the control in FIG.
During the period until failure FET18a or 18d is defined at the time of clockwise rotation, it is possible to continue the PWM control with the exception of a slight period of time t ₂ ~ time t _4. In the above control, if the FET is normally returned from the detection of the ON failure to the determination of the ON failure, after the time t _{6 when the} relay 18e or 18f is closed again for the current value determination, The determination result of step S236 is YES,
By the processing of steps S207 to S210,
It goes without saying that the value of the failure detection counter COUNT is set to 0 and the FET-on failure flag is cleared to 0.

Next, the FET 18 being PWM driven by left rotation
Flow of control when "a" fails to turn on (see FIG. 15 (a))
Will be described with reference to FIGS. 8, 9 and 12. First, in normal times
Tick t ₁In, the determination result of step S201 in FIG.
Is NO, step S237 to step S242 in FIG.
8 and the determination result of step S207 in FIG.
Since all the results are YES, step S208 of FIG.
The FET failure flag to 0, and step S210
Then, the processing in one control cycle is completed.

Next, when an ON failure occurs in the FET 18a at time t ₂ , NO in step S201, YES in steps S237 to S241, NO in step S242.
Becomes Therefore, the FET 18a ON failure flag is set in step S243, the failure detection counter COUNT is incremented by 1 in step S212 of FIG. 8, and step S213 is performed.
Is NO, and the process ends in step S210.

Next, at time t ₃ when the value of the failure detection counter COUNT does not reach the threshold value 1, step S
No in 201, YES in steps S237 and S238,
NO in step S239, NO in step S247, YES in step S241, NO in step S242, the FET18a ON failure flag is set in step S243, the failure detection counter COUNT is incremented by 1 in step S212, and NO in step S213. The processing ends in step S210.

The flow of control at the time t ₃ is the same from time t _{4 to} t ₆ when the value of the failure detection counter COUNT is less than the threshold value 1.

Next, at time t ₇ when the value of the failure detection counter COUNT reaches the threshold value 1, step S2
NO in 01, YES in steps S237 and S238, NO in step S239, NO in step S247, YES in step S241, NO in step S242, the FET 18a ON failure flag is set in step S243, and the failure detection counter COUNT is set in step S212. The number is incremented by 1, and YES is obtained in step S213. Therefore, as the FET on failure determination process, all the FETs are turned off in step S214 to stop the PWM control, and step S214 is performed.
At step 215, the relays 18e and 18f of the H-bridge circuit are opened, and at step S216, the relay 13b inserted in the battery power line is opened, and then step S21.
In step 7, the ON failure confirmation flag 1 is set, and step S21
The process ends at 0.

The flow of the control is as follows.
When the driving FET 18d has an ON failure (see FIG. 15)
The same applies to (d) (however, in this case, step S2).
If NO in 41, the ON failure flag of the FET 18d is set in step S244).

As described above, according to the control in FIG.
The PWM control can be continued during the period until the failure of the FET 18a or 18d is determined during left rotation. In the above control, if the normal recovery is made between the detection of the FET on-failure and the determination of the on-failure, YES is obtained in steps S241 and S242, and step S20 is performed.
It goes without saying that the value of the failure detection counter COUNT is set to 0 and the FET-on failure flag is cleared to 0 by the processing of 7 to step S210.

Next, the FET 18b which is in the off command by the left rotation
The control flow when the ON failure occurs (see FIG. 15B) will be described with reference to FIGS. 8, 9 and 13. First, at normal time t ₁ , the determination result of step S201 of FIG. 8 is NO, and the determination results of step S237 to step S242 of FIG. 9 and the determination result of step S207 of FIG. 8 are all YES. In step S208 of FIG. 8, the FET failure flag is set to 0, and in step S210, the processing in one control cycle ends.

Next, when the ON failure occurs in the FET 18b at time t ₂ , NO in step S201, YES in steps S237 to S239, NO in step S240.
Therefore, in step S245, all FETs are turned off and P
The WM control is stopped, the FET 18b ON failure flag is set at step S246, the failure detection counter COUNT is incremented by 1 at step S212, and N is returned at step S213.
It becomes O, and the process ends in step S210.

Next, at time t ₃ immediately after time t ₂ , NO in step S201, YES in step S237, NO in step S238, YES in step S250, NO in step S251. Therefore, the FET 18b ON failure occurs in step S253. Set the flag, step S2
Both the relays 18e and 18f are opened at 54, and the PWM control is restarted at step S249 at time t ₄ , and the failure detection counter COUNT is started at step S212.
Is incremented by 1, the result of step S213 is NO, and the process ends in step S210.

Next, at time t _{5 when} the value of the failure detection counter COUNT is less than the threshold value 2, step S2
01: NO, Step S237: YES, Step S2
NO in step S38, NO in step S250, step S25
Since YES is obtained in 5 and NO is obtained in step S256, the failure detection counter COUNT is incremented by 1 in step S212, NO is obtained in step S213, and step S21 is performed.
The process ends at 0.

Next, at time t ₆ when the value of the failure detection counter COUNT reaches the threshold value 2, step S2 is performed.
01: NO, Step S237: YES, Step S2
NO in step S38, NO in step S250, step S25
Since YES in step 5 and YES in step S256, the relay 18 is used to perform the current determination again in step S257.
e and 18f are closed. Then, in step S212, the failure detection counter COUNT is incremented by 1, and in step S2
If NO in step S13, the process ends in step S210.

Next, at time t _{7 when} the value of the failure detection counter COUNT exceeds the threshold value 2, at step S20.
1, NO in step S237, YES in step S237, step S23
8 NO, Step S250 NO, Step S255
NO in step S258, NO in step S258, and NO in step S260. Therefore, as the FET on failure confirmation processing, all the FETs are turned off in step S214 to stop the PWM control, the relays 18e and 18f of the H bridge circuit are opened in step S215, and the relays are inserted in the battery power supply line in step S216. The relay 13b is opened, the ON failure confirmation flag 1 is set in step S217, and the process ends in step S210.

The flow of the control is as follows.
The same applies when 18c has an ON failure (FIG. 15C) (however, in this case, YES is determined in step S251,
In step S252, the FET18c ON failure flag is set).

As described above, according to the control in FIG.
When the ON failure occurs in the FET 18b or 18c during counterclockwise rotation, the through current can be surely cut off.
In the above control, if the FET is normally restored from the time when the FET ON failure is detected to the time when the ON failure is determined, after the time t _{6 when the} relays 18e and 18f are closed again for current value determination, The determination result of step S260 is YES, and steps S207 to S21.
It goes without saying that the processing of 0 sets the value of the failure detection counter COUNT to 0 and clears the FET-on failure flag to 0.

In the embodiment described above, the relays 18e, 1
8f was inserted in the left side driving circuit of the H bridge circuit, but not limited to this, it is inserted in the right side driving circuit (that is, the relay 18e is inserted between the common connection point P and the FET 18c,
Even if the relay 18f is inserted between the common connection point N and the FET 18b), the same action and effect as described above can be obtained.

The semiconductor control element of the H-bridge circuit of the present invention is not limited to the FET, but may be another semiconductor control element having a diode structure.

[0183]

As described above, according to the present invention, the following excellent effects can be obtained. (1) According to the invention described in claims 1 to 3, it is possible to reliably cut off the through current (short-circuit current) regardless of which semiconductor control element of the H-bridge circuit has an ON failure.

Therefore, it is possible to prevent the semiconductor control element from being damaged or causing a fire due to overheating due to overcurrent.

When the ON failure occurs, both ends of the coil of the motor are connected to each other to generate a regenerative braking force of the motor, which makes it difficult to rotate the handle connected to the motor or disables the rotation operation. The so-called regenerative lock phenomenon does not occur. (2) According to the invention described in claim 2, it is sufficient to stop the PWM control only for a predetermined period before the on-failure is determined. Therefore, when an on-failure is detected due to external noise or the like and the on-failure does not continue for a predetermined time after that, the assist is stopped only for the predetermined period, and then the normal assist control can be performed. (3) According to the invention described in claim 3, it is possible to determine which semiconductor control element of the H-bridge circuit has the ON failure, and it is possible to perform appropriate control based on the determination result.

Before the on-failure is determined, it is sufficient to stop the PWM control only for a minute period. For this reason, if an on-failure is detected due to external noise or the like and the on-failure does not continue for a predetermined time after that, the assist is stopped only for the minute period, and then the normal assist control can be performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an example of an electric power steering device to which the present invention has been applied.

FIG. 2 is a block diagram of a main part of an embodiment of the present invention.

FIG. 3 is a control flowchart in the first embodiment of the present invention.

4A and 4B are control time charts of the first embodiment of the present invention, where FIG. 4A is a time chart when an FET ON failure is confirmed, and FIG. 4B is a time chart when an FET ON failure is not confirmed.

FIG. 5 is a circuit diagram showing a current path flowing through a main part when the motor rotates rightward in the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing a current path that flows through a main part when the motor rotates counterclockwise according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram of a main part for explaining control in the first embodiment example of the present invention.

FIG. 8 is a control flowchart when the motor rotates clockwise according to the second embodiment of the present invention.

FIG. 9 is a control flowchart when the motor rotates leftward in the second embodiment of the present invention.

FIG. 10 is a control time chart according to the second embodiment of the present invention, which is a time chart when an FET in PWM drive has an ON failure during clockwise rotation.

FIG. 11 is a control time chart according to the second embodiment of the present invention, which is a time chart when an FET under OFF control has an ON failure during clockwise rotation.

FIG. 12 is a control time chart of the second embodiment of the present invention, which is a time chart when the FET during PWM driving has an ON failure during left rotation.

FIG. 13 is a control time chart according to the second embodiment of the present invention, which is a time chart when an FET under OFF control has an ON failure during left rotation.

FIG. 14 is a circuit diagram showing a current path flowing through a main part when the motor rotates clockwise in the second embodiment of the present invention.

FIG. 15 is a circuit diagram showing a current path flowing through a main part when the motor rotates counterclockwise in the second embodiment of the present invention.

[Explanation of symbols] 1 ... Steering wheel 9 ... Torque sensor 10 ... Assist motor 13 ... Control unit 13b ... Power relay 14 ... Battery 16 ... Vehicle speed sensor 18: Motor drive circuit (H bridge circuit) 18a-18d ... FET 18e, 18f ... Relay

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroshi Sato             1370 Onna, Atsugi City, Kanagawa Prefecture Unisia             JK steering system             Within the corporation (72) Inventor Toshinori Aihara             1370 Onna, Atsugi City, Kanagawa Prefecture Unisia             JK steering system             Within the corporation F term (reference) 3D033 CA13 CA16 CA20 CA27 CA31                 5H576 AA15 BB10 CC04 DD01 EE10                       EE11 GG10 HA03 HB02 JJ03                       KK06 LL01 LL22 LL24 LL38                       MM02 MM07 MM20

Claims (3)

[Claims] 1. A torque sensor for detecting steering torque of a steering wheel, a motor for energizing an auxiliary load on a steering shaft provided integrally with the steering wheel, and a feedback system for the motor according to the magnitude of the steering torque. A control device for an electric power steering device, comprising: a control unit driven by the H-bridge circuit, and a first unit inserted in an electric path connecting the H-bridge circuit and a power source.
A relay, and a second upper part of the H-bridge circuit, which is inserted into either the right-side driving circuit or the left-side driving circuit.
A control device for an electric power steering device, comprising: a relay; and a third relay that is a lower stage part of the H bridge circuit and is inserted in a drive circuit on the same side as the second relay. 2. The first, second, and third relays are configured to detect an on-failure of a semiconductor control element forming the H-bridge circuit and then determine the on-failure when the failure continues for a predetermined time. ON failure determination processing for opening the ON state, and for only a predetermined time before the ON failure determination, the second and third relays are opened and the pulse width modulation control of the semiconductor control element of the H bridge circuit is stopped. The control device for the electric power steering device according to claim 1, further comprising a control unit that performs a process during failure. 3. When the H-bridge circuit has an ON failure, a determination process is performed to determine which of the semiconductor control elements forming the H-bridge circuit has an ON failure. Among the right-side driving circuit or the left-side driving circuit, when it is determined that the semiconductor control element of the upper stage or the lower stage, which constitutes the circuit on the side where the pulse width modulation control is performed, has an ON failure, the pulse width modulation control is performed. And a process for establishing an on-failure and opening the first, second, and third relays after the on-failure continues for a predetermined time, the right-side drive circuit of the H-bridge circuit or In the left side driving circuit, when the ON failure of the semiconductor control element in the upper part or the lower part constituting the circuit on the side where the pulse width modulation control is not performed is determined, the pulse width modulation is performed. Control for only a minute period, a process of re-closing the second or third relay after leaving the second or third relay open for a period longer than the minute period, and a process of continuing the ON failure until the re-closing time. 2. A control unit is provided for executing a process of establishing an on-failure and opening the first, second and third relays.
A control device for the electric power steering device according to.