JP2003197773A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein the reliability of a contact plug can be improved, and to provide its manufacturing method. <P>SOLUTION: This semiconductor device is provided with a plurality of gate electrodes 12 which are formed on first and second regions of a silicon substrate 10 via a gate insulating film 11, insulating films 13 which are formed on upper surfaces and side surfaces of the gate electrodes 12 and whose upper surfaces exist at positions where height in the second region is higher than height in the first region, cell contact plugs 18, 19 arranged on the silicon substrate 10 between the adjacent gate electrodes 12 in the first region, interlayer insulating films 14 arranged on the silicon substrate 10 between the adjacent gate electrodes 12 in the second region, and an insulating film 17 which is arranged on the insulating films 13 in the first region and mainly formed of the same material as the cell contact plugs 18, 19. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a DRAM (Dynamic Ran).
dom access memory) related technology for improving reliability.

[0002]

2. Description of the Related Art Recent advances in miniaturization technology for semiconductor devices have been remarkable. In particular, miniaturization technology in DRAM is accelerating more than ever before. For example, opening of contact holes using self-aligned contacts is also an essential technique for miniaturization.

A conventional DRAM manufacturing method will be described with reference to FIGS. 22 to 28 are cross-sectional views sequentially showing the manufacturing process of the DRAM.

First, as shown in FIG. 22, a silicon substrate 10
An element isolation region STI is formed in the element 0, and a plurality of element regions AA each electrically isolated by the element isolation region STI are formed. Then, the gate electrode 120 (word line WL) is formed in a stripe shape on the silicon substrate 100 with the gate insulating film 110 interposed. Further, a silicon nitride film 130 is formed so as to cover the gate electrode 120.

Next, as shown in FIG. 23, the gate electrode 120
An interlayer insulating film 140 that covers the silicon nitride film 130 is formed on the silicon substrate 100. Then, the silicon nitride film 130
CMP (Chemical Mechanical Polis)
The interlayer insulating film 140 is polished and flattened by a hing method.

Next, as shown in FIG. 24, the interlayer insulating film 140 on the element region AA is removed. At this time, the sacrificial film such as a resist protects the interlayer insulating film 140 on the element isolation region STI. In the element region AA, not only the interlayer insulating film 140 but also the upper surface of the silicon nitride film 130 is slightly etched.
As a result, the upper surface of the silicon nitride film 130 in the element region AA is lower than that in the element isolation region STI.

Next, as shown in FIG. 25, the silicon substrate 10
A polycrystalline silicon film 150 is formed on 0. Then, the silicon nitride film 130 on the element isolation region STI was used as a stopper.
The polycrystalline silicon film 150 is polished and flattened by the CMP method. As a result, the polycrystalline silicon film 150 remains only in the element region AA. However, since the upper surface of the silicon nitride film 130 on the element isolation region STI which serves as a stopper is lower than that on the element region AA, the polycrystalline silicon film 150 is formed on the adjacent gate electrode 1.
Shorted between 20.

Therefore, as shown in FIG. 26, the upper surface of the polycrystalline silicon film 150 is recessed by RIE (Reactive Ion Etching) or the like. As a result, the cell contact plugs 160 and 170 electrically separated between the adjacent gate electrodes 120 are completed.

Next, as shown in FIG. 27, an interlayer insulating film 180 is formed on the word line WL and the plug. And Figure 2
As shown in FIG. 8, a contact hole 190 reaching the cell contact plug 160 is formed in the interlayer insulating film 180 by the RIE method or the like.

After that, the bit line contact plug is completed by filling the contact hole 190 with a conductive member by a well-known technique. Then, form a node contact plug connected to the cell contact plug 170,
A cell capacitor having a storage node electrode electrically connected to the node contact plug is formed. Then, the DRAM is completed by forming an interlayer insulating film and a multi-layered metal wiring layer which cover the cell capacitors.

[0011]

However, the conventional method of manufacturing a semiconductor device described above has the following problems. (1) The height of the contact plug becomes uneven. According to the conventional manufacturing method, as described with reference to FIG. 26, it is necessary to recess the polycrystalline silicon film 150 by dry etching such as RIE. At this time, if the etching rate of the dry etching is not constant, there is a problem that the height of the cell contact plug is not uniform as shown in FIG.

(2) The bit line and the word line are short-circuited. According to the conventional manufacturing method, as described with reference to FIG. 24, the silicon nitride film 130 is also etched when the interlayer insulating film is etched. Further, the silicon nitride film 130 is slightly etched also in the step of opening the contact hole described with reference to FIG. By the way, if the etching amount of the polycrystalline silicon film 150 is too small, the cell contact contact plugs 160 and 170 are short-circuited. Therefore, it is necessary to secure a certain etching amount or more. On the contrary, if the etching amount of the polycrystalline silicon film 150 is too large, the silicon nitride film 130 is further etched in the process of FIG. 28. As a result, as shown in FIG. 190
It may be exposed inside. Then, contact hole 19
Since the bit line contact plug is formed in 0,
There is a problem that the bit line and the word line are short-circuited.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device capable of improving the reliability of a contact plug and a manufacturing method thereof.

[0014]

A semiconductor device according to the present invention includes a plurality of gate electrodes provided on the first and second regions of a semiconductor substrate with a gate insulating film interposed therebetween, an upper surface of the gate electrode, and A first insulating film that is provided on a side surface and has an upper surface that is higher in the second region than in the first region; and on the semiconductor substrate between the adjacent gate electrodes in the first region. A first contact plug, and a first interlayer insulating film provided on the semiconductor substrate between the adjacent gate electrodes in the second region,
A second insulating film provided on the first insulating film in the first region and mainly containing the same material as the first contact plug is provided.

A method of manufacturing a semiconductor device according to the present invention is
Forming a plurality of gate electrodes on the first and second regions of the semiconductor substrate with a gate insulating film interposed; forming a first insulating film on an upper surface and a side surface of the gate electrode; In a region, a step of forming a first conductive film on the semiconductor substrate and the first insulating film between the adjacent gate electrodes, and a surface of the first conductive film by oxidizing the first conductive film. To the step of forming a second insulating film having a thickness reaching the upper surface of the first insulating film.

According to the above semiconductor device and the method for manufacturing the same, the surface of the first contact plug is oxidized after the first conductive film serving as the first contact plug is embedded between the gate electrodes. Then, the second insulating film formed in this oxidation step causes the first insulating film to
The contact plug is electrically isolated. Therefore, RIE
The step of recessing the conductive film by dry etching is unnecessary. That is, it is possible to omit the dry etching process that causes the unevenness of the contact plug height. Therefore, the height of the contact plug can be made uniform.

Further, it is possible to prevent a short circuit between the bit line and the word line. According to the present invention, it is not necessary to recess the first conductive film as described above. Therefore, the upper surface of the first contact plug does not become excessively low. Then, in the subsequent step of forming contact holes for bit line contact plugs and node contact plugs connected to the first contact plugs, the time for exposing the first insulating film to RIE can be shortened. Then, since the etching amount of the first insulating film is reduced, it is possible to prevent the gate electrode from being exposed in the contact hole. As a result, it is possible to avoid a short circuit between the bit line and the word line in the DRAM or the like.

Further, since the RIE process of the first conductive film is not required, the process of confirming the etching rate of RIE is not required, and the manufacturing process can be simplified.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. When explaining this,
Common parts are designated by common reference numerals.

A semiconductor device according to the first embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 1 to 15 sequentially show manufacturing steps of a DRAM having a stack type cylinder capacitor. Note that FIG. 1A, FIG. 2A, FIG. 4A, FIG. 9 and FIG. 12 are plan views of the DRAM, and FIGS.
(A), FIG. 10 (a), FIG. 11 (a) and FIG. 13 (a)
1 is a perspective sectional view of a DRAM, and FIG. 1 (b), FIG. 2 (b),
FIG. 3, FIG. 4B, FIG. 5B to FIG. 7B, FIG.
10 (b), 11 (b), 13 (b), 14,
15 and 16 are sectional views of the DRAM. Each cross-sectional view of the DRAM shows a cross-section taken along the line X1-X1 ′ in the plan view and the perspective cross-sectional view, and all the drawings show the same region.

First, as shown in FIGS. 1A and 1B, an element isolation region STI is formed in a silicon substrate 10. As a result, as shown in FIG. 1A, a plurality of element regions AA arranged in a zigzag pattern and electrically isolated from each other are formed.

Next, as shown in FIGS. 2A and 2B, a MOS transistor is formed by a known technique. That is, a silicon oxide film as the gate insulating film 11 is formed on the silicon substrate 10 by, for example, a thermal oxidation method or the like. Next, for example, a polycrystalline silicon film and a tungsten film are deposited on the gate insulating film 11. Then, the polycrystalline silicon film and the tungsten film are patterned to form a plurality of stripe-shaped gate electrodes 12 (word lines WL). After that, impurities are selectively introduced into the silicon substrate 10 by ion implantation to form an impurity diffusion layer (not shown) to be source / drain regions. Formed in this way
The MOS transistor functions as a cell transistor of the DRAM cell. Next, a silicon nitride film 13 (first insulating film) is formed on the upper surface and the side surface of the gate electrode 12, for example, by CVD (Chemical Vap).
or Deposition) method or the like.

Next, as shown in FIG. 3, a silicon nitride film 13 is formed.
Then, a silicon oxide film 14 as an interlayer insulating film is formed on the silicon substrate 10 so as to cover the silicon substrate 10. The silicon oxide film 14 is, for example, BPSG (Boron Phosphorous Silica) obtained by adding phosphorus and boron to the silicon oxide film.
te Glass). After that, the silicon oxide film 14 is reflowed by heat treatment to be planarized, and then the silicon nitride film is formed.
The silicon oxide film 14 on the silicon nitride film 13 is removed by a CMP method using 13 as a stopper.

Next, as shown in FIGS. 4A and 4B, a mask material 15 such as a resist is formed on the silicon nitride film 13 and the silicon oxide film 14. As shown in FIG. 4A, the mask material 15 is provided adjacent to the element region AA in the direction along the word line WL and has a stripe shape along the direction orthogonal to the word line WL. Has been formed. In other words, the mask material 15 is provided on the element isolation region STI between the element regions AA that are adjacent to each other in the direction along the word line WL.

Next, as shown in FIGS. 5A and 5B, the silicon oxide film 14 is etched in a self-aligned manner with the gate electrode 12 (silicon nitride film 13) using the mask material 15 as a mask. To do. As a result, the silicon oxide film 14 in the region (first region) not covered with the mask material 15 is completely removed. At the same time, the silicon nitride film 13 in the region not covered with the mask material 15 is also slightly etched. Therefore, as shown in the drawing, the position of the upper surface of the silicon nitride film 13 in the region (second region) covered with the mask material 15 is higher than that in the region not covered. Note that etching is performed by a RIE method or the like using a C ₄ F ₈ system etching gas. Subsequently, the gate insulating film 11 exposed between the gate electrodes 12 is removed by etching.

Next, as shown in FIGS. 6A and 6B, a polycrystalline silicon film 16 is deposited on the entire surface. Amorphous silicon to which impurities such as arsenic are added may be used instead of polycrystalline silicon. Then, the CMP using the silicon nitride film 13 and the silicon oxide film 14 in the region covered with the mask material in the steps of FIGS. 5A and 5B as a stopper
The polycrystalline silicon film 16 is polished and flattened by the method. In this state, the polycrystalline silicon film 16 between the adjacent gate electrodes is short-circuited as shown in the figure.

Next, as shown in FIGS. 7A and 7B, the surface of the polycrystalline silicon film 16 is oxidized by, for example, a thermal oxidation method at a temperature of about 800 to 850 ° C. The region is the silicon oxide film 17 (second insulating film). On this occasion,
It is necessary to perform oxidation at least until the silicon oxide film 17 reaches the upper surface of the silicon nitride film 13 that covers the gate electrode 12. The heat treatment temperature is about the same as the reflow temperature of the silicon oxide film 14. As a result, the gate electrode
The polycrystalline silicon films 16 between 12 are electrically isolated from each other.
Each polycrystalline silicon film electrically separated in this way
16 becomes the cell contact plugs 18 and 19. See also FIG.
As shown in FIG. 5A, the region not covered with the mask material in the steps of FIGS. 5A and 5B is covered with the silicon oxide film 17.

Next, as shown in FIG. 8, the silicon oxide film 1
A silicon oxide film 20, for example, is formed as an interlayer insulating film on the entire surfaces of 4, 17 and the silicon nitride film 13.

Next, the cell contact plug 18 and the bit line
Form a bit line contact plug that connects to BL.
The bit line contact plug is formed in the region shown in the plan view of FIG. 9, and its longitudinal direction is formed to have a length of 3F, for example. In addition, "F" means the minimum processing dimension. First, in the structure shown in FIG.
A mask material such as a resist is formed on the entire surface of 20. Then, the mask material is patterned by the lithographic technique, and the pattern shown in FIG.
An opening reaching the silicon oxide film 20 is formed in the region where the plug is to be formed.

Next, as shown in FIGS. 10 (a) and 10 (b),
The silicon oxide films 20 and 17 are sequentially etched by a dry etching method such as RIE using the mask material as a mask, and then the mask material is removed. As a result, a plurality of contact holes 21 in which the upper surface of the cell contact plug 18 is exposed are formed at the bottom. The etching of the silicon oxide films 20 and 17 is performed by the RIE method using a C ₄ F ₈ etching gas.

Next, as shown in FIGS. 11 (a) and 11 (b),
A bit line contact plug 22 is formed by filling the contact hole 21 with a metal film or the like. The metal film is, for example, tungsten. It is desirable that the metal film fills the contact hole 21 with a barrier metal layer interposed. The barrier metal layer is, for example, TiN / Ti or TiN / Ti / T
iN / Ti. Next, a tungsten film 23 and a silicon nitride film 24 are sequentially formed on the silicon oxide film 20 and the bit line contact plug 22. The tungsten film 23 and the silicon nitride film 24 function as bit lines.
The bit line BL is completed by patterning the tungsten film 23 and the silicon nitride film 24 into stripes extending in the vertical direction with respect to the word lines WL by using the lithography technique and the RIE method. In addition, the bit line BL
A silicon oxide film 25 is formed on the silicon oxide film 20 between the upper part and the bit line BL and the bit line contact plug 22 by HDP (High D
ensity Plasma) -deposited by a CVD method or the like. Then, the silicon oxide film on the silicon nitride film 24 is removed by the CMP method using the silicon nitride film 24 as a stopper. As a result, as shown in FIG. 11A, a pattern in which stripe-shaped silicon nitride films 24 and silicon oxide films 25 are alternately present is formed.

Next, a node contact plug connecting the cell contact plug 19 and the storage node electrode of the cell capacitor is formed. The node contact plug is formed in the area shown in the plan view of FIG. First, FIG.
In the structure shown in (a) and (b), the silicon oxide film 20
A mask material such as a resist is formed on the entire surface of. Then, the mask material is patterned into a stripe shape along the word line WL by the lithography technique. Subsequently, the silicon oxide films 25, 20, 17 are sequentially etched by a dry etching method such as RIE using the mask material as a mask, and then the mask material is removed. As a result, as shown in FIGS. 13A and 13B, a plurality of contact holes 26 in which the upper surface of the cell contact plug 19 is exposed are formed at the bottom. In this step, a low etching rate for the silicon nitride film,
By using the selective etching method with high etching rate for the silicon oxide film, the contact hole
26 can be formed in self alignment with the bit line BL. The tungsten film 23 to be the bit line BL is exposed on the side surface of the contact hole 26 on the bit line BL side. Therefore, if the node contact plug is formed in the contact hole 26 as it is, the node contact plug and the bit line BL are short-circuited. In order to prevent this, a sidewall insulating film (not shown) is formed on the side surface of the contact hole 26.

Next, as shown in FIG. 14, the contact hole 26 is filled with a metal film or the like to form a node contact plug 27. The metal film is, for example, tungsten. It is desirable that the metal film fills the contact hole 21 with a barrier metal layer interposed, similarly to the bit line contact plug. The barrier metal layer is, for example, TiN / T
i, or TiN / Ti / TiN / Ti. After that, an interlayer insulating film 28 such as a silicon oxide film is formed on the entire surface.

After that, a cell capacitor is formed by a known technique. That is, a contact hole reaching the node contact plug 27 is formed in the interlayer insulating film 28. Then, a cylinder type storage node electrode 29 is formed which is in contact with the node contact plug through the contact hole. Subsequently, the capacitor insulating film 30 and the plate electrode 31 are formed on the storage node electrode 29. Then, the cell electrode is completed by patterning the plate electrode into a predetermined pattern. Further, an interlayer insulating film 32 covering the cell capacitor is formed, and a metal wiring layer (not shown) is formed to complete the DRAM shown in FIG.

According to the semiconductor device having the above structure and manufacturing method, the following effects can be obtained. (1) The height of the contact plug is uniform. In the method of manufacturing a DRAM according to this embodiment, the polycrystalline silicon film 16 to be the cell contact plugs 18 and 19 is buried between the gate electrodes, and then the surface thereof is oxidized. The contact plugs 18 and 19 are electrically separated by the silicon oxide film 17 formed in this oxidation process. Therefore, the recessing step of the polycrystalline silicon film 16 by dry etching such as RIE as in the prior art is not necessary. That is, it is possible to omit the dry etching process that causes the unevenness of the contact plug height. Therefore, the height of the contact plug can be made uniform.

(2) It is possible to prevent a short circuit between the bit line and the word line. As described in (1) above, in the DRAM manufacturing method according to the present embodiment, it is not necessary to recess the polycrystalline silicon film 16. Therefore, the upper surfaces of the cell contact plugs 18 and 19 are not excessively lowered as in the conventional case. That is, in the process described with reference to FIGS. 10A and 10B, the contact hole 21 must be formed so as to reach the cell contact plug 18, so that it is possible to prevent the position of the contact plug 18 from being lowered. The depth of the contact hole 21 can be reduced. The opening of the contact hole 21 is performed by dry etching such as RIE, but if the contact hole 21 can be made shallow, the time during which the silicon nitride film 13 is exposed to RIE can be shortened. Then, since the etching amount of the silicon nitride film 13 is reduced, it is possible to prevent the gate electrode 12 from being exposed in the contact hole 21. As a result, it is possible to avoid a short circuit between the bit line and the word line.

This effect also exists between the storage node electrode of the cell capacitor and the word line. That is, it is possible to prevent the gate electrode 12 from being exposed even in the step of forming the contact hole for the node contact plug described with reference to FIGS. 13A and 13B. Therefore, it is possible to avoid a short circuit between the storage node electrode and the word line.

(3) Short circuit between bit lines can be prevented. With the conventional structure, in the planar structure shown in FIG.
All areas where the mask material 15 is not provided are silicon oxide films.
Exposed to RIE to etch 14. Among them, the region where the contact plug is formed is further exposed to RIE for recessing the polycrystalline silicon film 16. Therefore, the upper surface of the word line WL and the silicon oxide film under the mask material 15
14 The upper surface is the word line WL in the area where the mask material 15 is not provided.
It is higher than the upper surface and the polycrystalline silicon film 16. Then,
Under the influence of these steps, the surface of the interlayer insulating film 20 formed in the step shown in FIG. 8 also has the same steps. That is, it becomes high in the area where the mask material 15 was provided and becomes low in the area where it was not provided. By the way, the bit line contact plug 22 is shown in FIG.
In the structure shown in (b), first, a barrier metal and a metal film are deposited on the entire surface, and thereafter, polishing and planarization are performed by the CMP method using the interlayer insulating film 20 as a stopper, so that only in the contact hole 21. Be left behind. However, if there is a step in the interlayer insulating film 20, the CMP naturally stops at the portion where the step is high, and the barrier metal and the metal film remain in the portion where the step is low. As described above, the lower portion of the interlayer insulating film 20 is the entire region where the mask material 15 is not provided,
The barrier metal and the metal film remain in all of these regions. Then, the remaining barrier metal and the metal film connect the bit lines, and a short circuit occurs between the bit lines.

However, in the manufacturing method according to this embodiment, instead of the recess of the polycrystalline silicon film 16 as described above, oxidation is performed to form the silicon oxide film 17. The silicon oxide film 17 is the entire area where the mask material 15 is not provided. That is, the upper surfaces of the silicon nitride film 13 and the silicon oxide film 14 in the area where the mask material 15 is provided and the upper surface of the silicon oxide film 17 in the area where the mask material 15 is not provided are substantially at the same height. Then, the interlayer insulating film 20 is formed on these.
Is formed. Therefore, it is possible to effectively prevent a step from being generated in the interlayer insulating film 20, and it is possible to prevent a short circuit between bit lines as in the conventional case.

(4) The manufacturing process can be simplified. As described above, according to the conventional manufacturing method, RIE is used to recess the polycrystalline silicon film 16. Since the etching rate of RIE varies relatively, it was necessary to confirm the etching rate with a sample before performing RIE. However, in the manufacturing method according to the present embodiment, since the polycrystalline silicon film 16 is not etched,
The process for confirming the etching rate as described above is unnecessary, and the manufacturing process can be simplified.

As described above, according to the semiconductor device and the method of manufacturing the same according to the present embodiment, the effects (1) to (4) can be obtained. As a result, the manufacturing process of the DRAM can be simplified, the manufacturing yield thereof can be improved, and the reliability of the DRAM can be improved.

In the first embodiment, the case where the length of the bit line contact plug in the longitudinal direction is 3F has been described as an example. In this case, all the silicon oxide film 17 on the cell contact plug 18 embedded between the gate electrodes is
The silicon oxide film 17 is removed by RIE and remains only on the insulating film 13 in the region between the adjacent bit lines BL (FIG. 13).
(See (a)). However, the length of the bit line contact plug 22 in the longitudinal direction may naturally be smaller than 3F. FIG.
(A) and (b) show the case where each side of the bit line contact plug 22 is formed to have a length of F.
10 is a plan view and FIG. 10B is a perspective sectional view.
This corresponds to the steps shown in (a) and (b).

As shown in the figure, the bit line contact plug 22 is provided in the region immediately below the bit line BL. Therefore, in that case, the silicon oxide film 17 remains in the region which does not overlap the bit line BL on the upper surface of the cell contact plug 18 in the longitudinal direction 3F.

Next, a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS. 17 to 21 are sectional views sequentially showing a part of the manufacturing process of the DRAM.

First, the structure shown in FIGS. 5A and 5B is obtained by the steps described in the first embodiment. Thereafter, as shown in FIG. 17, an undoped or low impurity concentration polycrystalline silicon film 33 is formed. Of course, amorphous silicon may be used instead of polycrystalline silicon. However, it is necessary to prevent the region between the gate electrodes 12 from being completely filled. Then, as shown in FIG. 18, the polycrystalline silicon film 33 is doped with impurities at a high concentration by an ion implantation method.

Subsequently, as shown in FIG. 19, an undoped or low impurity concentration polycrystalline silicon film 34 is formed on the polycrystalline silicon film 33. Of course, an amorphous silicon film may be used. And as shown in FIG. 20, the interlayer insulating film
The polycrystalline silicon films 33 and 34 are polished and flattened by the CMP method using 14 as a stopper.

Then, the polycrystalline silicon films 33 and 34 are oxidized by the same thermal oxidation as in the first embodiment to form the silicon oxide film 17. The oxidation of polycrystalline silicon has a characteristic that it progresses faster as the impurity concentration increases. Then, in this step, the oxidation of the polycrystalline silicon film 33 progresses faster than that of the polycrystalline silicon film 34. As a result, as shown in FIG. 21, the bottom surface of the silicon oxide film 17 is a polycrystalline silicon film.
It is formed so as to be lower than the polycrystalline silicon film 34 on the 33. After that, as in the first embodiment,
The DRAM is completed by the steps shown in FIGS.

The manufacturing method according to the present embodiment also provides the same effects as those of the first embodiment.

As described above, according to the embodiment of the present invention, it is possible to provide the semiconductor device capable of improving the reliability of the DRAM and the manufacturing method thereof. The cell contact plugs 18 and 19
The material is not limited to polycrystalline silicon, but may be any material that becomes an insulator by oxidation. Therefore, the silicon oxide film 17 can be used in place of another insulator. Further, in the first and second embodiments described above, the cylinder type DR
Although AM has been described as an example, it goes without saying that the present invention can also be applied to a DRAM having a stack type capacitor such as a concave type or a pillar type. Furthermore, the present invention can be applied not only to DRAM but also to, for example, Ferroelectric RAM or a mixed logic / DRAM product. Further, it can be widely applied not only to the semiconductor memory but also to general semiconductor devices having the problems described in the related art.

The invention of the present application is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the invention at the implementation stage. Furthermore, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, the problems described in the section of the problem to be solved by the invention can be solved, and the effects described in the section of the effect of the invention When the above is obtained, the configuration in which this constituent element is deleted can be extracted as the invention.

[0051]

As described above, according to the present invention, it is possible to provide a semiconductor device capable of improving the reliability of a contact plug and a method of manufacturing the same.

[Brief description of drawings]

1 shows a first manufacturing process of a DRAM according to a first embodiment of the present invention, FIG. 1 (a) is a plan view,
FIG. 6B is a sectional view taken along line X1-X1 ′ in FIG.

FIG. 2 shows a second manufacturing process of the DRAM according to the first embodiment of the present invention, FIG. 2 (a) is a plan view,
FIG. 6B is a sectional view taken along line X1-X1 ′ in FIG.

FIG. 3 is a sectional view of a third manufacturing process of the DRAM according to the first embodiment of the present invention.

FIG. 4 shows a fourth manufacturing process of the DRAM according to the first embodiment of the present invention, wherein FIG. 4 (a) is a plan view,
FIG. 6B is a sectional view taken along line X1-X1 ′ in FIG.

FIG. 5 shows a fifth manufacturing process of the DRAM according to the first embodiment of the present invention, FIG. 5 (a) is a perspective sectional view,
FIG. 6B is a sectional view taken along line X1-X1 ′ in FIG.

FIG. 6 shows a sixth manufacturing process of the DRAM according to the first embodiment of the present invention, and FIG. 6A is a perspective sectional view,
FIG. 6B is a sectional view taken along line X1-X1 ′ in FIG.

FIG. 7 shows a seventh manufacturing process of the DRAM according to the first embodiment of the present invention, wherein FIG. 7A is a perspective sectional view,
FIG. 6B is a sectional view taken along line X1-X1 ′ in FIG.

FIG. 8 is a cross-sectional view of the eighth manufacturing process of the DRAM according to the first embodiment of the present invention.

FIG. 9 is a plan view of the ninth manufacturing process of the DRAM according to the first embodiment of the present invention.

FIG. 10 is a ninth DRAM according to the first embodiment of the present invention.
FIG. 6A is a perspective sectional view, and FIG. 6B is a sectional view taken along line X1-X1 ′ in FIG.

FIG. 11 shows a first DRAM according to the first embodiment of the present invention.
0 shows the manufacturing process of 0, (a) is a perspective sectional view, (b) is a sectional view taken along the line X1-X1 'in (a).

FIG. 12 is a first DRAM according to the first embodiment of the present invention.
2 is a plan view of the manufacturing process of 1.

FIG. 13 shows a first DRAM according to the first embodiment of the present invention.
2A and 2B are shown, in which (a) is a perspective sectional view and (b) is a sectional view taken along line X1-X1 'in (a).

FIG. 14 shows a first DRAM according to the first embodiment of the present invention.
Sectional drawing of the manufacturing process of FIG.

FIG. 15 is a first DRAM according to the first embodiment of the present invention.
Sectional drawing of the manufacturing process of FIG.

FIG. 16 is a DR according to a modified example of the first embodiment of the present invention.
The figure which shows a part of manufacturing process of AM, (a) figure is a top view, (b) figure is a perspective sectional drawing.

FIG. 17 is a first DRAM of a second embodiment of the invention.
Sectional view of the manufacturing process of.

FIG. 18 is a second DRAM according to the second embodiment of the present invention.
Sectional view of the manufacturing process of.

FIG. 19 is a third DRAM according to the second embodiment of the present invention.
Sectional view of the manufacturing process of.

FIG. 20 is a fourth DRAM according to the second embodiment of the present invention.
Sectional view of the manufacturing process of.

FIG. 21 is a fifth DRAM according to the second embodiment of the present invention.
Sectional view of the manufacturing process of.

FIG. 22 is a sectional view of the first manufacturing process of the conventional DRAM.

FIG. 23 is a sectional view of the second manufacturing process of the conventional DRAM.

FIG. 24 is a sectional view of a third manufacturing process of the conventional DRAM.

FIG. 25 is a sectional view of a fourth manufacturing process of the conventional DRAM.

FIG. 26 is a sectional view of a fifth manufacturing process of the conventional DRAM.

FIG. 27 is a cross-sectional view of the sixth conventional manufacturing process of the DRAM.

FIG. 28 is a cross-sectional view of the seventh conventional manufacturing process of the conventional DRAM.

FIG. 29 is a sectional view of a conventional DRAM.

FIG. 30 is a sectional view of a conventional DRAM.

[Explanation of symbols]

10, 100… Silicon substrate 11, 110 ... Gate insulating film 12, 120 ... Gate electrode 13, 24, 130 ... Silicon nitride film 14, 17, 20, 25, 28, 140, 180 ... Silicon oxide film 15 ... Mask material 16, 33, 34, 150 ... Polycrystalline silicon film 18, 19, 160, 170 ... Cell contact plug 21, 26, 190 ... Contact holes 22 ... Bit line contact plug 23 ... Bit line 27 ... Node contact plug 29 ... Storage node electrode 30 ... Capacitor insulation film 31 ... Plate electrode 32 ... Interlayer insulation film

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F033 HH04 HH19 JJ04 JJ05 JJ18                       JJ19 JJ33 KK01 NN06 NN07                       QQ09 QQ48 QQ49 QQ58 QQ74                       QQ75 RR04 RR06 RR15 SS11                       SS25 SS27 VV06 VV10 VV16                       XX01                 5F083 AD24 AD56 JA19 JA32 JA33                       JA39 JA40 LA21 MA02 MA05                       MA06 MA17 MA20 PR03 PR06                       PR12 PR29

Claims (11)

[Claims] 1. A plurality of gate electrodes provided on the first and second regions of a semiconductor substrate with a gate insulating film interposed, and an upper surface and a side surface of the gate electrode, the upper surface of which is the first electrode. A first insulating film present at a position higher in the second region than the region; a first contact plug provided on the semiconductor substrate between the adjacent gate electrodes in the first region; and a second region in the second region. A first interlayer insulating film provided on the semiconductor substrate between the adjacent gate electrodes, and a first interlayer insulating film provided on the first insulating film in the first region, and mainly made of the same material as the first contact plug. And a second insulating film including the semiconductor device. 2. The second insulating film is an oxide film of a material of the first contact plug.
The semiconductor device described. 3. The semiconductor device according to claim 1, wherein the upper surface of the second insulating film is substantially at the same height as the upper surface of the first interlayer insulating film. 4. The second insulating film is also present on a part of the first contact plug.
4. The semiconductor device according to any one of 3 to 3. 5. The first contact plug is the first contact plug.
A first conductive film provided along the side surface of the insulating film and on the semiconductor substrate so as not to completely fill a region between the adjacent gate electrodes; and a first conductive film provided on the first conductive film. A second conductive film having an impurity concentration lower than that of the first conductive film, and a boundary between the first and second conductive films and the second insulating film is closer to the second conductive film than the first conductive film. 5. The semiconductor device according to claim 1, wherein the semiconductor device is located at a high position. 6. A second interlayer insulating film provided on the second insulating film in the first region, and on the first interlayer insulating film and the first insulating film in the second region, and the first interlayer insulating film. 6. The semiconductor device according to claim 1, further comprising a second contact plug provided on the first contact plug in a region. 7. A step of forming a plurality of gate electrodes on the first and second regions of a semiconductor substrate with a gate insulating film interposed, and a step of forming a first insulating film on an upper surface and a side surface of the gate electrode. A step of forming a first conductive film on the semiconductor substrate and the first insulating film between the gate electrodes adjacent to each other in the first region; and 1 forming a second insulating film having a thickness reaching from the surface of the conductive film to the upper surface of the first insulating film. 8. The second insulating film is formed and then the second insulating film is formed.
A step of forming a first interlayer insulating film on the insulating film, and a contact plug reaching the first conductive film from the surface of the first interlayer insulating film through the first interlayer insulating film and the second insulating film. The method for manufacturing a semiconductor device according to claim 7, further comprising: 9. A second interlayer insulating film is formed on the semiconductor substrate so as to cover the gate electrode and the first insulating film in the first and second regions after forming the first insulating film. A step of forming, a step of polishing and planarizing the second interlayer insulating film using the first insulating film as a stopper, and a step of removing the second interlayer insulating film in the first region by etching. 9. The method for manufacturing a semiconductor device according to claim 7, further comprising: 10. The step of etching and removing the second interlayer insulating film in the first region removes the second interlayer insulating film and scrapes the upper surface of the first insulating film in the first region. The upper surface of the first insulating film is
In the second region, the height is higher in the second region, and the step of forming the first conductive film is performed in the first region after the step of removing the second interlayer insulating film in the first region by etching. The second substrate on the semiconductor substrate and the second insulating film, and in the second region.
Forming the first conductive film on the interlayer insulating film and the second insulating film; and using the second interlayer insulating film or the second insulating film in the second region as a stopper, the first conductive film. Polishing,
10. The method for manufacturing a semiconductor device according to claim 9, further comprising the step of allowing the first conductive film to remain only in the first region by planarizing. 11. The step of etching and removing the second interlayer insulating film in the first region removes the second interlayer insulating film and removes the upper surface of the first insulating film in the first region. The upper surface of the first insulating film is
In the second region, the first conductive film has a stacked structure including third and fourth conductive films, and the step of forming the first conductive film is performed in the first region. After removing the second interlayer insulating film by etching, the second insulating film is formed on the semiconductor substrate and the second insulating film in the first region and the second region in the second region.
A third insulating layer is formed on the interlayer insulating film and the second insulating film so as not to completely fill a region between the adjacent gate electrodes.
Forming a conductive film, implanting an impurity into the third conductive film, and forming a fourth conductive film on the third conductive film so as to fill a region between adjacent gate electrodes. And the third and fourth conductive films are polished and planarized by using the second interlayer insulating film or the second insulating film in the second region as a stopper to polish the third and fourth conductive films. 10. The method for manufacturing a semiconductor device according to claim 9, further comprising: leaving the second insulating film only in the first region, wherein the second insulating film is formed by oxidizing the third and fourth conductive films. Method.