JP2003188208A - Method of mounting element, electronic device, flat panel display, system-in-package ic and optical-electrical ic - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new method of mounting an element which enables mounting, even a small chip on a substrate with a high accuracy of position. <P>SOLUTION: The method of mounting includes processes from (a) to (e), as follows: (a) a process of making a first laminated layer 100, having at least an isolation layer 12 and a device layer 16 including the element on a first substrate 10, (b) a process of isolating the laminated layer, including the device layer 16 and the isolation layer 12 in a prescribed pattern and making plural chips 30 and 30a including the element on the first substrate, (c) a process of making an opening 18, which reaches the isolation layer 12 of the chip into the first substrate, (d) a process of jointing the chip 30a selected among the chips to a second substrate 20 with them positioned, and (e) a process of isolating the chip 30a from the first substrate 10 and mounting it on the second substrate 20, by removing the isolation layer with etching solution 32 supplied from the opening 18. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an element mounting method,
For example, the present invention relates to a method for mounting a semiconductor chip on a substrate other than a semiconductor, an electronic device such as a flat panel display, a system-in-package type IC and an optical electrical IC.

[0002]

2. Description of the Related Art For mounting a semiconductor chip on a substrate, there are the following methods, for example. First, a wafer is attached to an adhesive sheet set by applying tension to a ring-shaped jig, and the wafer is divided by dicing to form chips. After that, the chip is handled by a suction cup and mounted on a desired substrate. However, with this mounting method, it is difficult to mount a small chip having a size of several μm to several tens of μm on the substrate.

An object of the present invention is to provide a method for mounting a novel element, for example, a method in which even a small-sized chip can be mounted on a substrate with high positional accuracy, and various electronic devices obtained by this method. Especially.

[0004]

A device mounting method according to the present invention includes the following steps (a) to (e).

(A) forming a first laminate having at least a separation layer and a device layer containing an element on a first substrate; (b) a laminate containing the device layer and the separation layer. Separating a plurality of chips in a predetermined pattern to form a plurality of chips including the element on the first substrate,
(C) a step of forming an opening reaching the separation layer in the first substrate, (d) a step of joining a predetermined chip among the chips and a second substrate in an aligned state, and ( e) separating the predetermined chip and the first substrate by supplying an etching liquid to the opening reaching the separation layer of the predetermined chip and removing the separation layer with the etching liquid; Step of mounting the predetermined chip on the second substrate.

In the present invention, the order of the steps is not particularly limited, and for example, the order of the step (b) and the step (c) may be first.

According to the mounting method of the present invention, the first substrate on which the device layer is formed and the second substrate on which the chip is mounted can be made of different materials. Therefore, for example, the device layer including a desired element can be formed. The first desired to form
It is possible to independently select the substrate and the desired second substrate, for example, from the product on which the element is mounted or the application.
As a result, the element and the second substrate on which the element is mounted can be optimized.

According to the mounting method of the present invention, the chip formed on the first substrate can be mounted on the second substrate with high precision by handling the first substrate. Therefore, even a small chip, which is difficult to mount by the conventional mounting method using a suction cup, for example, a chip having a size of about several μm to several tens of μm, can be surely mounted on the second substrate.

The first substrate is not particularly limited, but for example, a substrate suitable for forming the device layer including the element can be selected. As the first substrate, for example, when the element is a silicon semiconductor element such as a MOS transistor, a silicon substrate can be used. Further, as the first substrate, when the element is a compound semiconductor element such as a semiconductor laser, a compound semiconductor substrate can be used.

The element is not particularly limited, and the following can be exemplified in addition to the MOS transistor and the semiconductor laser described above. That is, as the element,
For example, compound semiconductor field effect transistors, hetero field effect transistors, heterobipolar transistors of various materials, diodes, photodetectors, photoelectric conversion elements (photosensors, solar cells) made of silicon PIN junctions, silicon resistance elements, thin film transistors. (TF
T), other thin film semiconductor devices, electrodes (eg IT
O, transparent electrode such as mesa film), memory, actuator such as piezoelectric element, micro mirror (piezo thin film ceramics), magnetic recording thin film head, coil, inductor,
There are thin film highly permeable materials and micro magnetic devices, filters, reflective films, dichroic mirrors, etc. that combine them.

The second substrate is selected according to the final product or application. For example, when the mounting method of the present invention is applied to a flat panel display, a flat panel display substrate (for example, a synthetic resin, glass, metal, or a substrate in which these are combined) can be used. When the mounting method of the present invention is applied to a system-in-package type IC or an optical electrical IC, these IC substrates (for example, silicon substrate) can be used.

The mounting method of the present invention can take the following modes.

(A) In the step (a), there may be a step of forming an etching stop layer between the separation layer and the device layer.

(B) After the step (e),
The first substrate is moved relative to the second substrate, and a predetermined chip on the first substrate and the second substrate are bonded in an aligned state, and thereafter, as in the step (e). Repeating the step (f) a predetermined number of times, including a step (f) of separating the first substrate and the predetermined chip by a different step and mounting the predetermined chip at a predetermined position of the second substrate. You can

By including this step (f), the chips on the first substrate can be mounted at a predetermined position on the second substrate without waste. For example, from the first substrate to the second
If the substrate is large and cannot be mounted on the chip at all predetermined positions of the second substrate in one series of steps (steps (a) to (e)), by adding step (f), The chips on the first substrate can be sequentially mounted in different regions of the two substrates.

An electronic device according to the present invention is formed by the method for mounting an element according to the present invention. As such an electronic device, a flat panel display (FP
D), system-in-package type IC, optical electrical IC, etc. can be exemplified. Here, the "flat panel display" means various display devices for displaying an image by driving pixel electrodes arranged in a matrix on a substrate by switching elements, for example, a liquid crystal display device and an electroluminescence (EL) display device. Say. The "system-in-package type IC" means an LSI in which ICs having different functions are hybrid-mounted in one package or one chip. In addition, "Optical Electrical I
“C” is an IC equipped with optical I / O, and is an IC in which minute light emitting and receiving elements are hybrid-mounted on a silicon LSI.
Say.

In the present invention, for example, a compound semiconductor element (for example, a silicon LSI formed by a semiconductor process)
It is suitable for hybrid mounting such as an optical electrical IC that mounts a semiconductor laser, a diode, and a photodetector.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. 1. First Embodiment FIGS. 1 to 6 are cross-sectional views showing a mounting method of an element according to a first embodiment.

(A) As shown in FIG. 1, the first laminated body 10
Form 0.

The first laminate 100 is formed on the first substrate 10 by
A separation layer 12, an etching stop layer 14, and a device layer 16 including an element (not shown) are sequentially formed. The separation layer 12 has a function of separating the first substrate 10 and the etching stop layer 14 by being removed by later etching. The etching stop layer 14 is
It functions as a layer for protecting the device layer 16 in the later etching. In addition, the etching stop layer 14 is
It may be omitted if the device layer 16 is not adversely affected by the etching of the separation layer 12. Device layer 1
A wiring layer 19 such as an electrode for driving the device is formed on the substrate 6.
Are formed.

The first substrate 10 is not particularly limited,
It is selected according to the type of elements included in the device layer 16. For example, when the element included in the device layer 16 is a compound semiconductor element such as a semiconductor laser, a compound semiconductor substrate such as GaAs can be used as the first substrate 10. In this case, the device layer 16 including various elements such as a semiconductor laser and a diode can be formed on the compound semiconductor substrate by the compound semiconductor process technology. When GaAs is used as the first substrate 10, AlGaAs (Al composition is 20% or more) is used as the separation layer 12.
Can be used, and GaAs can be used as the etching stop layer 14. In short, the separation layer 1
2 is composed of a substance that is easily dissolved in the etching liquid with respect to the first substrate 10 and the etching stop layer 14.

(B) As shown in FIG. 1, the first laminated body 10
The device layer 16 at 0 is separated in a predetermined pattern to form a chip 30 including elements. That is, in this example, the separation groove 17 is formed so as to penetrate the stacked body having the separation layer 12, the etching stop layer 14, and the device layer 16.

The separation groove 17 is preferably formed so as to completely divide the separation layer 12. By forming the separation groove 17 in this manner, the separation groove 17 functions as a retaining portion of the etching liquid, and the inflow of the etching liquid to the adjacent chips can be suppressed. As a result, only the separation layer 12 of the predetermined chip 30a to be mounted can be removed by etching. The width of the separation groove 17 is set in consideration of such a retention function of the etching solution. As a method of forming the separation groove 17, half dicing, etching, or the like can be used.

(C) As shown in FIG. 1, an opening 18 is formed in the first substrate 10 corresponding to each chip 30. The opening 18 is for supplying the etching liquid to the separation layer 12. Therefore, the opening 18 is formed so that at least the etching liquid can be injected and reaches the separation layer 12.

The opening 18 can be formed by a chemical method such as etching or a mechanical method such as cutting. For example, when the first substrate 10 is GaAs, it can be formed by wet etching using an ammonia-based etchant (including ammonia water, hydrogen peroxide solution and water). This ammonia-based etchant etches GaAs forming the first substrate 10, but hardly etches AlGaAs (having an Al composition of about 20% or more) forming the separation layer 12.

The steps (b) and (c) are the same as the step (b).
If the separation groove 17 can be formed without adversely affecting the element, the order may be reversed.

(D) As shown in FIG. 2, the adhesive 24 is finally applied to a predetermined position of the second laminated body 200 on which the predetermined chip 30a is mounted. As a method of applying the adhesive, a dispenser, an inkjet, or the like can be used. In the case of this example, the second stacked body 200 includes, for example, the wiring layer 22 including the electrodes 22a on the second substrate 20.
Are formed. The second stacked body 200 may include various elements depending on the device finally obtained.

(E) As shown in FIG. 2, the first laminated body 10
0 and the second stacked body 200 are aligned. Specifically, a wiring layer (for example, an electrode) 19 of a predetermined chip 30a
And the electrode 22a of the wiring layer 22 of the second stacked body 200 are arranged so as to face each other. Then, as shown in FIG.
The predetermined chip 30a and the second substrate 20 via the adhesive layer 26.
And are joined together to form the third stacked body 300. In the third stacked body 300, only the predetermined chip 30a is bonded to the second substrate 20, and the other chips 30 are not bonded to the second substrate 20. In addition, the electrode 19 of the predetermined chip 30a and the second
The electrode 22a of the stacked body 200 is electrically connected.

In this step, by handling the first laminated body 100, the predetermined chip 30a and the second substrate 20 are handled.
Since it is possible to align and bond with each other, it is possible to more easily and reliably mount a chip including a small-sized element as compared with, for example, handling by chip with a suction cup.

The second substrate 20 is not particularly limited, and is selected depending on the device finally obtained by mounting the chip 30a. Examples of the second substrate 20 include various substrates such as glass and plastic when the device is a flat panel display, and a silicon substrate and ceramics when the device is a system-in-package type IC.
Various substrates such as glass, resin and metal, and when the device is an optical electrical IC (OEIC), various substrates such as silicon substrate, glass, resin, ceramics and metal can be used.

The adhesive used for joining the first laminated body 100 and the second laminated body 200 is not particularly limited, and examples thereof include a light-curable adhesive, a thermosetting adhesive, and an ultraviolet curable adhesive. Examples include various adhesives such as curable adhesives. Specific examples of the organic polymer material that constitutes such an adhesive include polyolefins such as polyethylene and polypropylene, polyimide, polyamide, polyester, polymethylmethacrylate (PMMA), polyphenylene sulfide (PPS), polyether sulfone (PE).
S), epoxy resin and the like.

(F) As shown in FIG. 4, the etching solution 32 is put into the opening 18 formed in the first substrate 10. The etching liquid 32 is separated from the separation layer 12 through the opening 18.
And to etch it. The etching of the separation layer 12 proceeds laterally from the portion exposed at the opening 18,
The process is repeated until the separation groove 17 is reached. The etching liquid to be put into the opening 18 may be an amount capable of etching the separation layer 12 of a predetermined chip 30a, and an appropriate amount is selected. For example, if the amount of the etching liquid to be filled in the opening 18 is too large, the etching liquid may leak from the separation groove 17 and adversely affect the device layer 16 and the wiring layer 22.

The etching solution is selected depending on the material of the first substrate 10 and the like. For example, the first substrate 10 is GaAs
In the case of a substrate, hydrofluoric acid or hydrochloric acid solution can be used as the etching solution. The hydrofluoric acid or hydrochloric acid solution etches AlGaAs (Al composition is 20% or more) that constitutes the separation layer 12, but hardly etches GaAs that constitutes the first substrate 10 and the etching stop layer 14. Therefore, only the separation layer 12 made of AlGaAs is removed. At this time, the device layer 16 is protected by the etching stop layer 14.

Through the above steps, the predetermined chip 30a is formed.
FIG. 5 shows a state in which the separation layer of 1 is removed.

(G) As shown in FIG. 6, the first substrate 10 and the etching stop layer 14 are separated to form a fourth laminated body 400 and a fifth laminated body 500. In the fifth stacked body 500, the chip 30 is provided at a predetermined position on the second substrate 20.
a is implemented. In the fourth stacked body 400, the second substrate 20
The chips 30 other than the chip 30a mounted above are left.

Through the above steps, a device in which the chip 30a including various compound semiconductor elements such as a semiconductor laser, a diode and a photodetector is mounted at a predetermined position on the second substrate 20 can be formed.

In the steps described above, the following modes can be further adopted.

(1) The first laminated body 100 has the separation layer 12
The etching stop layer 14 is provided between the device layer 16 and the device layer 16. This etching stop layer may not be provided if the etching solution in the step (f) does not significantly affect the device layer 16.

(2) In the step (d), the second substrate 2
Although the adhesive 24 is applied to a predetermined position where the chip on the 0 side is mounted, of course, the adhesive may be applied to the adhesion surface of the predetermined chip 30a to be mounted.

(3) Particles having excellent thermal conductivity, for example, non-conductive particles such as diamond filler can be mixed with the adhesive used in the step (d). When such particles are included in the adhesive layer 26 (see FIG. 4), the heat of the chip 30a is effectively conducted to the second substrate 20, and the heat dissipation of the chip 30a is improved. An anisotropic conductive adhesive can also be used as the adhesive. The anisotropic conductive adhesive is an adhesive in which metal particles such as gold are dispersed in resin or rubber, and can be electrically conductive only in the vertical direction by pressure bonding.

The mounting method of this embodiment has the following effects.

That is, according to the mounting method of the present embodiment, the first substrate 10 on which the device layer 16 is formed and the second substrate 2 on which the chip 30a including the device layer 16 is mounted.
0 can be made of a different material. Therefore, for example, the first substrate 10 made of a compound semiconductor substrate desirable for forming the device layer 16 including a compound semiconductor element.
Therefore, for example, the desired second substrate 20 can be independently selected depending on the product or application in which the compound semiconductor element is mounted. As a result, the compound semiconductor element and the second substrate 20 on which the chip 30a including the element is mounted can be optimized.

In this embodiment, for example, an optical member having a compound semiconductor element (for example, an optical element such as a semiconductor laser, a light emitting diode or a photodetector) is mounted on a silicon LSI (second laminated body) formed by a semiconductor process. However, it is suitable for hybrid mounting such as an optical electrical IC in which optical interconnection is mounted on a silicon LSI.

Further, according to the mounting method of the present embodiment, the chip 30a and the second substrate 20 can be aligned and bonded by handling the first substrate 10, so that they are formed on the first substrate 10. Second chip 30
It can be mounted on the substrate 20 with high accuracy. Therefore, even a chip 30a having a size of, for example, several μm to several tens of μm can be reliably mounted on the second substrate 20. 2. Second Embodiment FIGS. 7 and 8 are cross-sectional views showing a mounting method of an element according to a second embodiment.

(A) As shown in FIG. 7, the first laminated body 11
Form 0.

The first laminated body 110 is formed on the first substrate 50 by
Device layer 56 including isolation layer 52 and device (not shown)
And are sequentially formed. The separation layer 52 has a function of separating the first substrate 50 and the device layer 56 by being removed by later etching. On the device layer 56, a wiring layer 19 such as an electrode for driving the element is formed.

The first substrate 50 is not particularly limited,
It is selected according to the type of elements included in the device layer 56 and the like. For example, if the elements included in the device layer 56 are MO
In the case of silicon semiconductor devices such as S-transistors,
A silicon substrate may be used as the first substrate 50. In this case, the device layer 56 including various semiconductor elements such as MOS transistors and diodes can be formed on the silicon substrate by the LSI process technology.

When a silicon substrate is used as the first substrate 50, silicon oxide can be used as the separation layer 52. In short, the separation layer 52 is the first substrate 50.
On the other hand, it is composed of a substance that is easily dissolved by an etching solution.

(B) As shown in FIG. 7, the first laminated body 11
The device layer 56 at 0 is separated in a predetermined pattern to form a chip 30 including elements. That is, in this example, the separation groove 17 is formed so as to penetrate the stacked body having the separation layer 52 and the device layer 56.

The isolation groove 17 is preferably formed so as to completely divide the isolation layer 52. By forming the separation groove 17 in this manner, the separation groove 17 functions as a retaining portion of the etching liquid, and the inflow of the etching liquid to the adjacent chips can be suppressed. As a result, only the separation layer 52 of the predetermined chip 30a to be mounted can be removed by etching. The width of the separation groove 17 is set in consideration of such a retention function of the etching solution. As a method of forming the separation groove 17, half dicing, etching, or the like can be used.

(C) As shown in FIG. 7, the opening 18 is formed in the first substrate 50 corresponding to each chip 30. The opening 18 is for supplying the etching liquid to the separation layer 52. Therefore, the opening 18 is formed so that at least the etching liquid can be injected and reaches the separation layer 52.

The opening 18 can be formed by using a chemical method such as etching or a mechanical method such as cutting. For example, when the first substrate 50 is a silicon substrate, it can be formed by wet etching using a potassium hydroxide-based etchant. This etchant etches the silicon forming the first substrate 50, but hardly etches the silicon oxide forming the separation layer 52.

The steps (b) and (c) are the same as the step (b).
If the separation groove 17 can be formed without adversely affecting the element, the order may be reversed.

(D) As shown in FIG. 8, the first laminated body 11
0 and the second stacked body 210 are aligned. In the case of this example, the second stacked body 210 is formed on the second substrate 20, for example,
The wiring layer 22 including the electrodes 22a is formed. The second stacked body 210 can include various elements depending on the device finally obtained.

The first laminated body 110 and the second laminated body 210 are the wiring layers (for example, electrodes) 19 of a predetermined chip 30a.
And the electrode 22a of the wiring layer 22 of the second stacked body 210 are arranged to face each other. Then, the predetermined chip 30 a and the second substrate 20 are bonded via the adhesive layer 26 to form the third stacked body 310. In the third stacked body 310, only the predetermined chip 30a is bonded to the second substrate 20, and the other chips 30 are not bonded to the second substrate 20. Further, the electrode 19 of the predetermined chip 30a and the electrode 22a of the second stacked body 210 are electrically connected.

In this step, by handling the first laminated body 110, the predetermined chip 30a and the second substrate 20 are handled.
Since it is possible to align and bond with each other, it is possible to more easily and reliably mount a chip including a small-sized element as compared with, for example, handling by chip with a suction cup.

The second substrate 20 is not particularly limited, and is selected depending on the device finally obtained by mounting the chip 30a. As the example of the second substrate 20, the same one as described in the first embodiment can be used.

The adhesive used for joining the first laminated body 110 and the second laminated body 210 is not particularly limited, and the same adhesive as described in the first embodiment can be used.

(E) As shown in FIG. 8, the etching solution 32 is put into the opening 18 formed in the first substrate 50. The etching liquid 32 is separated from the separation layer 52 through the opening 18.
And to etch it. The etching of the separation layer 52 proceeds laterally from the portion exposed in the opening 18,
The process is repeated until the separation groove 17 is reached. The etching liquid to be put into the opening 18 may be an amount capable of etching the separation layer 52 of a predetermined chip 30a, and an appropriate amount is selected. For example, if the amount of the etching liquid to be filled in the opening 18 is too large, the etching liquid may leak from the separation groove 17 and adversely affect the device layer 56, the wiring layer 22, and the like.

The etching solution is selected depending on the material of the first substrate 50 and the like. For example, when the first substrate 50 is a silicon substrate, a hydrofluoric acid solution can be used as the etching solution. The hydrofluoric acid solution etches the silicon oxide forming the separation layer 52, but hardly etches the silicon forming the first substrate 50. Therefore, only the separation layer 52 made of silicon oxide is removed.

Through the above steps, the predetermined chip 30a is formed.
Is removed.

After (f), as shown in FIG. 6 used in the first embodiment, the first substrate 50 and the device layer 56 are separated, and the fourth laminated body (not shown) and the fourth laminated body are formed. 5 stacks (not shown) are formed. In the fifth stack, the second substrate 2
The chip 30a is mounted at a predetermined position on 0. In the fourth stacked body, the chips 30 other than the chips 30a mounted on the second substrate 20 are left.

Through the above steps, a device in which a chip 30a including a silicon semiconductor element such as a MOS transistor is mounted at a predetermined position on the second substrate 20 can be formed.

In the steps described above, the following modes can be further adopted.

(1) The first laminated body 110 includes the separation layer 52.
An etching stop layer may be provided between the device layer 56 and the device layer 56. This etching stop layer can prevent the etching solution in the step (e) from affecting the device layer 56.

(2) In the step (d), the method of joining the predetermined chip 30a to be mounted and the second substrate 20 is not particularly limited, and the same method as in the first embodiment can be used. it can.

(3) The adhesive layer 26 formed in the step (d) can be mixed with particles having excellent thermal conductivity, for example, non-conductive particles such as diamond filler. When such particles are included in the adhesive layer 26, the chips 30a
Of the chip 30a is effectively conducted to the second substrate 20.
The heat dissipation of is improved. An anisotropic conductive adhesive can also be used as the adhesive. The anisotropic conductive adhesive is
It is an adhesive in which metal particles such as gold are dispersed in resin or rubber, and can be electrically conductive only in the vertical direction by pressure bonding.

The mounting method of this embodiment has the following effects.

That is, according to the mounting method of this embodiment, the first substrate 50 on which the device layer 56 is formed and the second substrate 2 on which the chip 30a including the device layer 56 is mounted.
0 can be made of a different material. Therefore, for example, the first substrate 50 made of a silicon substrate desirable for forming the device layer 56 including a semiconductor element and the second substrate 20 desirable for a product or application in which the silicon semiconductor element is mounted are independently selected. can do.
As a result, it is possible to optimize the silicon semiconductor element and the second substrate 20 on which the chip 30a including the element is mounted.

Further, according to the mounting method of the present embodiment, the chip 30a and the second substrate 20 can be aligned and bonded by handling the first substrate 10, so that they are formed on the second substrate 20. Second chip 30
It can be mounted on the substrate 20 with high accuracy. Therefore, even a chip 30a having a size of, for example, several μm to several tens of μm can be reliably mounted on the second substrate 20.

For example, an example in which the mounting method of this embodiment is applied to a flat panel display will be described.

In flat panel displays,
TFTs are used as pixel switching elements.
The TFTs are directly formed in a matrix on the substrate. Since the TFT is formed by a semiconductor process, the larger the flat-panel display, the more difficult the manufacturing becomes. Further, the number of switching elements may be one for each pixel, and the size thereof is constant regardless of the pixel area. Therefore, the larger the screen of the display, the smaller the element density, and the waste of element material generated during manufacturing increases.

When the mounting method of this embodiment is applied to such a flat panel display, a semiconductor element such as a MOS transistor manufactured by a semiconductor process can be mounted at a predetermined position on the substrate. It is possible to overcome the difficulty in forming a TFT directly on the substrate. Since the MOS transistor has excellent characteristics as compared with the TFT, the performance of the display can be improved. 3. Third Embodiment FIG. 9 is a perspective view showing an example of an element mounting method according to a third embodiment. This example can be applied to the case where chips cannot be mounted at all predetermined positions on the second substrate by the series of steps described in the first and second embodiments.

FIG. 9 shows an example in which switching elements are mounted in a matrix on a substrate of a flat panel display, for example. In FIG. 9, the second substrate 40 is
A substrate for a flat panel display. Second substrate 4
The first line 42 above 0 indicates the position of the first signal electrode, and the second line 44 indicates the position of the second signal electrode. The first line 42 and the second line 44 are orthogonal to each other, and the chip 30a is arranged at the intersection of the two. The chip 30a includes, for example, a MOS transistor as a switching element. The mounting of the chip 30a on the second substrate 20 is performed as follows.

First, through the steps (a) to (e) (see FIGS. 7 and 8) in the second embodiment, the chip 30a is mounted at a predetermined position in the first area A1 of the second substrate 40. Specifically, similar to the step (e) (see FIG. 8), the predetermined chip 30a is separated from the first substrate 50 by the separation layer 52, so that the first substrate 50 and the chip 30a are separated from each other. The four stacked body 400 and the fifth stacked body 500 are formed. In the fourth stacked body 400, the first stack on the second substrate 40
The chip 30a is mounted at a predetermined position in the area A1.
In the fifth stacked body 500, the chips 30 other than the mounted chips 30a are left on the first substrate 50.

Then, the fifth laminated body 500 is changed to the fourth laminated body 4
00 with respect to the second substrate 40 to move the predetermined chip 30a on the first substrate 50 and the second substrate 40 to the second substrate 40.
Bonding is performed at a predetermined position in the area A2. This joining can be performed in the same manner as the step (d) in the second embodiment. Then, as in step (e), the first
The substrate 50 and the predetermined chip 30a can be separated, and the predetermined chip 30a can be mounted at a predetermined position in the second area A2 of the second substrate 40. After that, by repeating the same process a predetermined number of times, the chips 30a can be sequentially mounted on the substrate (second substrate 40) of the flat panel display.

The wiring layers on the second substrate 40, for example, the wiring layers such as the first signal electrodes and the second signal electrodes are formed before the chips 30a are mounted on the second substrate 40, as shown in FIG. May be.

According to the present embodiment, the chips 30 on the first substrate 50 are repeatedly mounted on the second substrate 40, so that the chips 30 on the first substrate 50 are not wasted.
Can be implemented as 0. Further, according to the present embodiment, for example, the second substrate 40 is larger than the first substrate 50,
The series of steps (a) to (e) described in the second embodiment can be applied when the chip cannot be mounted at all predetermined positions of the second substrate 40. That is,
By repeating the steps (d) and (e) a predetermined number of times while moving the first substrate 50 and the second substrate 40 relatively, the chips 30 on the first substrate 50 are sequentially arranged at predetermined positions of the second substrate 40. Can be implemented in.

This embodiment can use not only the mounting method according to the first and second embodiments but also the mounting method according to the present invention.

Although the embodiments of the present invention have been described above, the present invention is not limited to these, and various modes can be adopted within the scope of the gist of the present invention.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a step of a method of mounting an element according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step of a method of mounting the element according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a step of a method of mounting the element according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step of a method of mounting the element according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a step of a method of mounting the element according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a step in the element mounting method of the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step of a method of mounting an element according to the second embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a step of a method of mounting the element according to the second embodiment of the present invention.

FIG. 9 is a perspective view showing a step of a device mounting method according to a third embodiment of the present invention.

[Explanation of symbols]

10 First substrate 12 separation layers 14 Etching stop layer 16 device layers 17 separation groove 18 openings 19 wiring layers 20,40 Second substrate 22 Wiring layer 24 Adhesive 26 Adhesive layer 30,30a chip 100,110 1st laminated body 200,210 Second laminated body 300,310 Third stack 400 Fourth Laminate 500 fifth stack A1 first area A2 second area

Claims (12)

[Claims] 1. The method includes the following steps (a) to (e):
Device mounting method. (A) a step of forming a first laminated body having at least a separation layer and a device layer including an element on a first substrate; (b) a predetermined laminate including the device layer and the separation layer. Forming a plurality of chips including the element on the first substrate by pattern separation, (c) forming an opening reaching the separation layer on the first substrate, (d) ) Bonding a predetermined chip of the chips and the second substrate in a aligned state, and (e) supplying an etching solution to the opening reaching the separation layer of the predetermined chip, A step of separating the predetermined chip and the first substrate by removing the separation layer with the etching solution, and mounting the predetermined chip on the second substrate. 2. The element mounting method according to claim 1, further comprising the step of forming an etching stop layer between the separation layer and the device layer in the step (a). 3. The device mounting method according to claim 1, wherein the first substrate is a compound semiconductor substrate, and the device is a compound semiconductor device. 4. The third substrate according to claim 3, wherein the first substrate is made of GaAs, and the separation layer is AlG.
A method of mounting an element, which is made of aAs. 5. The method for mounting an element according to claim 1, wherein the first substrate is a silicon substrate, the element is a silicon semiconductor element, and the separation layer is made of silicon oxide. 6. The method according to claim 1, wherein in the step (d), the predetermined chip and the second chip are used.
A method for mounting an element, which comprises using an adhesive mixed with non-conductive particles having high thermal conductivity when joining the substrate. 7. The method according to claim 1, wherein in the step (d), the predetermined chip and the second chip are used.
A method for mounting an element, wherein an anisotropic conductive adhesive is used when joining with a substrate. 8. The predetermined substrate on the first substrate according to claim 1, further comprising moving the first substrate relative to the second substrate after the step (e). The chip and the second substrate are bonded in a state of being aligned, and then the first substrate and the predetermined chip are separated by the same step as the step (e), and the predetermined chip is attached to the first chip. (2) A method of mounting an element, which includes a step (f) of mounting at a predetermined position on a substrate, the step (f) being performed a predetermined number of times. 9. An electronic device formed by the element mounting method according to claim 1. 10. A flat panel display formed by the method for mounting an element according to claim 1. 11. A system-in-package type IC formed by the element mounting method according to claim 1. 12. An optical electrical IC formed by the device mounting method according to claim 1.