JP2003188071A - Exposure method and device manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an exposure method capable of improving throughput with no degradation in superpositioning precision. <P>SOLUTION: The information about transfer error related to a plurality of compartments formed on a substrate is acquired (step 409). Based on the information on the transfer error, the target number of compartments to be transferred at the same time with a pattern under a single exposure among a plurality of compartments is selected, and the region of a pattern to be transferred while superposed on the compartments of the target number is decided (steps 414 and 434). If a transfer error is equal to a prescribed threshold or below, for example, simultaneous pattern transfer with a plurality of compartments is selected, while a pattern transfer for each single compartment is selected if the transfer error exceeds the prescribed threshold. And the pattern transfer is performed according to the decisions (steps 417 and 437). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure method and a device manufacturing method, and more particularly, to an exposure method used in a lithography process for manufacturing a semiconductor device, a liquid crystal display device and the like, and the exposure method. The present invention relates to a device manufacturing method.

[0002]

2. Description of the Related Art Conventionally, in a lithography process for manufacturing a semiconductor device, a liquid crystal display device, etc., a pattern formed on a mask or reticle (hereinafter referred to as "reticle") is resisted through a projection optical system. 2. Description of the Related Art An exposure apparatus that transfers a wafer or the like coated on a substrate such as a glass plate (hereinafter, also referred to as a “wafer” as appropriate) is used. As an apparatus of this type, in recent years, from the viewpoint of placing importance on throughput, a step-and-repeat type reduction projection exposure apparatus (so-called stepper) and an improved step-and-scan type scanning projection exposure apparatus (So-called scanning stepper) and the like are used relatively often.

In the exposure process for manufacturing semiconductor devices and the like, usually, a multilayer circuit pattern (chip pattern) is superposed and transferred onto a wafer coated with a resist or the like. At this time, from the viewpoint of productivity. There are cases where different exposure apparatuses are used for each layer. Moreover, when the chip pattern is not very large, the stepper and the scanning stepper are often used in a mixed manner.

For example, among the layers formed on the wafer, a layer transferred by using a stepper is used as an object layer for superimposing, and the plurality of shot areas on the wafer to which the pattern of the object layer is transferred are scanned. -There are cases where the chip patterns are transferred by superimposing them using a stepper. In this case, since the scanning stepper can take a larger exposure area than the stepper, a plurality of the same chip patterns are arranged on the reticle for the purpose of effectively using the exposure area and improving productivity. Is used to simultaneously transfer a chip pattern to a plurality of shot areas on a wafer.

[0005]

However, if there is a transfer error in each shot area in which the pattern of the layer to be superposed is formed, a plurality of shot areas on the wafer are exposed in one exposure as described above. When the chip patterns are transferred at the same time, it is not easy to strictly correct the transfer error in the shot area, and thus the overlay error may be larger than that in the case where transfer is performed in one shot area by one exposure. is there. For example, as shown in FIG. 14A, when each shot area has a rotation error as a transfer error and the chip pattern is simultaneously transferred to two shot areas on the wafer in one exposure, the transfer At this time, even if the wafer is rotated in consideration of the rotation error,
As shown in FIG. 14 (B), it is difficult to accurately and simultaneously transfer the chip patterns to both shot areas in an overlapping manner, and an overlay error occurs. If the overlay error exceeds the permissible range, the semiconductor element or the like cannot satisfy the predetermined circuit characteristics, which may result in a defective product and a decrease in product yield.

Further, in the future, semiconductor elements will be highly integrated, and with this, it is certain that the overlay accuracy required for the exposure apparatus will become more and more severe. further,
In order to effectively use the exposure apparatus and improve productivity, it is highly likely that different layers on the substrate will be exposed by using different types of exposure apparatuses. Misalignment is becoming more and more ignorable.

The present invention has been made under such circumstances, and a first object thereof is to provide an exposure method capable of improving throughput without lowering overlay accuracy.

A second object of the present invention is to provide a device manufacturing method capable of improving the productivity of highly integrated devices.

[0009]

[Means for Solving the Problems]

According to a first aspect of the present invention, there is provided an exposure method for transferring a predetermined pattern onto a substrate, the method comprising: obtaining information on a transfer error regarding a plurality of partitioned areas formed on the substrate; Based on the error information, the target number of divided areas to which the pattern is to be simultaneously transferred in one exposure of the plurality of divided areas and the target number of divided areas of the pattern are overlapped and transferred. An exposure method including: a step of determining a region of a pattern to be formed; and a step of performing transfer according to the determination.

In the present specification, the "target number" is not limited to an integer but includes a fraction.

According to this, when the information of the transfer error regarding the plurality of divided areas formed on the substrate is obtained, a predetermined pattern is obtained by one exposure of the plurality of divided areas based on the information of the transfer error. The target number of divided areas to be transferred at the same time and the area of the pattern to be transferred overlapping the target number of divided areas of the pattern are determined, and the transfer is performed according to the determined contents. For example, when the pattern is composed of a plurality of identical chip patterns and one of the chip patterns is transferred to each of the divided areas in an overlapping manner, for example, if the transfer error regarding the divided area is negligible, one exposure is performed. By simultaneously transferring the chip pattern to a plurality of divided areas, the throughput can be improved. On the other hand, for example, if the transfer error relating to the partitioned area cannot be ignored, the overlay error can be suppressed within an allowable range by transferring the chip pattern to only one partitioned area by one exposure.

Therefore, according to the invention described in claim 1,
Throughput can be improved without lowering overlay accuracy.

In this case, as in the exposure method according to the second aspect, the information on the transfer error is based on the position information of the marks formed in a plurality of specific partitioned areas among the plurality of partitioned areas. Good to get.

In this case, as in the exposure method according to the third aspect, the transfer error information may be obtained by a statistical calculation process using the position information of the mark.

In each of the exposure methods described in claims 1 to 3, various transfer errors can be considered. However, as in the exposure method described in claim 4, the transfer error is caused by the transfer error of the substrate. At least one of the orthogonality error of the coordinate axis, the orthogonality error of the coordinate axis of the partitioned area, the magnification error of the partitioned area, and the rotation error may be included.

In each of the exposure methods described in claims 1 to 4, as in the exposure method described in claim 5, in the target number and the pattern area, the transfer error is compared with a predetermined threshold value. You may decide.

In this case, as in the exposure method according to the sixth aspect, when the transfer error is equal to or less than the threshold value, the target number is determined to be n (n> 1), and one of the patterns is performed. An area including a pattern to be simultaneously transferred to the n divided areas by exposure can be determined as the area of the pattern.

In this case, when the transfer error exceeds the threshold value as in the exposure method according to the seventh aspect, the target number is determined to be m (1 ≦ m <n), and at the same time, the target number is set to m. An area containing a pattern to be simultaneously transferred to the m divided areas in one exposure may be determined as the area of the pattern.

In this case, various combinations of the n, m and pattern regions are conceivable.
For example, when the pattern is composed of two chip patterns and one of the chip patterns is transferred to the partitioned area in an overlapping manner, the transfer error is equal to or less than the threshold value as in the exposure method according to claim 8. Then, the n is determined to be 2, and a region including all of the patterns is determined as a region of the pattern. When the transfer error exceeds the threshold value, the m is determined to be 1 and the pattern The area including ½ can be determined as the area of the pattern.

In each of the exposure methods described in claims 5 to 8, when the transfer error exceeds the threshold value as in the exposure method described in claim 9, when the pattern is transferred,
The transfer error may be corrected based on the transfer error information.

In each of the exposure methods described in claims 1 to 9, as in the exposure method described in claim 10, the plurality of divided areas are formed by using a collective exposure apparatus, and the pattern is formed by a scan exposure apparatus. Can be used to be transcribed.

The invention described in Item 11 is a device manufacturing method including a lithography process, wherein the exposure method according to any one of Items 1 to 10 is used in the lithography process. It is a device manufacturing method.

According to this, in the lithographic process, by each of the exposure methods described in claims 1 to 10, exposure with high throughput and high precision is performed, and the productivity (including yield) of highly integrated devices is increased. It is possible to improve.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION << First Embodiment >> A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows an exposure apparatus 100 suitable for carrying out the exposure method according to the present invention. This exposure apparatus 1
Reference numeral 00 denotes a step-and-scan type scanning projection exposure apparatus, that is, a so-called scanning stepper.

The exposure apparatus 100 includes an illumination system IOP, a reticle stage RST that holds the reticle R, and a reticle stage drive system 2 that drives the reticle stage RST.
9. A projection optical system PL for projecting an image of a pattern formed on the reticle R onto a wafer W as a substrate, an XY stage 20 for holding the wafer W and moving in a two-dimensional plane (in the XY plane), and this XY stage A wafer stage drive system 22 for driving 20 and a control system for these are provided. This control system is mainly composed of a main control device 28 that integrally controls the entire device.

The illumination system IOP includes, for example, a light source composed of a KrF excimer laser or an ArF excimer laser and an optical integrator (fly-eye lens,
An illumination uniformizing optical system including an internal reflection type integrator or a diffractive optical element), a reticle blind as an illumination field stop, an illumination optical system including a relay lens system, a condenser lens system and the like (all not shown). ing.

According to the illumination system IOP, illumination light as exposure light generated by the light source (hereinafter referred to as "illumination light IL")
Is converted into a light flux having a substantially uniform illuminance distribution by the illuminance uniformizing optical system. The illumination light IL emitted from the illuminance uniformizing optical system reaches the reticle blind via the relay lens system. The light flux passing through the opening of the reticle blind passes through a relay lens system and a condenser lens system and illuminates a rectangular slit-shaped illumination area on the reticle R held on the reticle stage RST with a uniform illuminance distribution.

The reticle stage RST has an illumination system I.
It is located below the OP in FIG. The reticle R is suction-held on the reticle stage RST via a vacuum chuck (not shown) or the like. Reticle stage RST has a Y-axis direction (left and right direction on the paper surface in FIG. 1), an X-axis direction (direction orthogonal to the paper surface in FIG. 1), and θz.
In addition to being capable of being finely driven in a direction (a rotation direction around the Z axis orthogonal to the XY plane), it can be driven at a scanning speed designated in a predetermined scanning direction (here, the Y axis direction).

A movable mirror 15 for reflecting the laser beam from a reticle laser interferometer (hereinafter referred to as "reticle interferometer") 21 is fixed on reticle stage RST, and the position on the moving surface of reticle stage RST is fixed. The reticle interferometer 21 is constantly detected with a resolution of, for example, about 0.5 to 1 nm. Here, in practice, a moving mirror having a reflecting surface orthogonal to the Y-axis direction and a moving mirror having a reflecting surface orthogonal to the X-axis direction are provided on reticle stage RST and correspond to these moving mirrors. Although a reticle Y interferometer and a reticle X interferometer are provided as a moving mirror 15 and a reticle interferometer 21 in FIG. Note that, for example, the reticle stage RST
It is also possible to form a reflection surface (corresponding to the reflection surface of the movable mirror 15) by mirror-finishing the end surface of the. Here, one of the reticle Y interferometer and the reticle X interferometer, for example, the reticle Y interferometer is a biaxial interferometer having two length measuring axes, and the reticle stage RST of the reticle stage RST is based on the measurement value of the reticle Y interferometer. In addition to the Y position, the rotation in the θz direction can be measured.

The position information of the reticle stage RST from the reticle interferometer 21 is sent to the main controller 28, and the main controller 28 sends the reticle stage drive system 29 based on the position information of the reticle stage RST. Drive RST.

The reticle R is shown in FIG. 2 as an example.
As shown in (A), a rectangular pattern area PA having a long side in the Y-axis direction is formed at the center of a glass substrate 42 as a rectangular mask substrate, and the X of the pattern area PA is formed.
At least one pair of reticle alignment marks (not shown) are formed on both sides in the axial direction.

Returning to FIG. 1, the projection optical system PL has its optical axis A located below the reticle stage RST in FIG.
It is arranged so that the direction of Xp is the Z-axis direction orthogonal to the XY plane. As the projection optical system PL, here is used a bilateral telecentric reduction system, which is a refractive optical system including a plurality of lens elements having a common optical axis AXp in the Z-axis direction. Further, a plurality of specific ones of the lens elements are controlled by an imaging characteristic correction controller (not shown) based on a command from the main controller 28, and the imaging characteristics of the projection optical system PL (part of the optical characteristics are ), For example, magnification, distortion (compression), coma, and field curvature can be adjusted.

The XY stage 20 is, in fact, a Y stage that moves in the Y-axis direction on a base (not shown), and this Y stage.
Although it is composed of an X stage that moves on the stage in the X axis direction, these are shown as an XY stage 20 in FIG. 1. The wafer table 18 is mounted on the XY stage 20, and the wafer W is held on the wafer table 18 by vacuum suction or the like via a wafer holder (not shown).

The XY stage 20 moves not only in the scanning direction (Y-axis direction) but also positions a plurality of shot areas on the wafer W in a projection area within the field of view of the projection optical system PL which is conjugate with the illumination area. Therefore, it is configured to be movable also in a non-scanning direction (X-axis direction) orthogonal to the scanning direction. Then, a step-and-scan operation is performed in which the operation of scanning (scanning) each shot area on the wafer W and the operation of moving to the acceleration start position for the exposure of the next shot are repeated.

The wafer table 18 is for finely driving the wafer holder holding the wafer W in the Z-axis direction and in the inclination direction with respect to the XY plane. This wafer table 1
A movable mirror 24 is provided on the upper surface of 8, and a laser beam is projected onto the movable mirror 24 and the reflected light is received to measure the position of the wafer table 18 in the XY plane. A total of 26 is provided so as to face the reflecting surface of the moving mirror 24. Actually, the movable mirror is provided with an X movable mirror having a reflective surface orthogonal to the X axis and a Y movable mirror having a reflective surface orthogonal to the Y axis. Correspondingly, the laser interferometer also has an X movable mirror. An X laser interferometer for directional position measurement and a Y laser interferometer for Y direction position measurement are provided.
In FIG. 1, these are representative of the moving mirror 24 and the laser interferometer 2.
It is shown as 6. Note that, for example, the end surface of the wafer table 18 may be mirror-finished to form a reflection surface (corresponding to the reflection surface of the movable mirror 24). Further, for example, a voice coil motor or the like is used to move the wafer table 18 to X, Y
It may be configured to be capable of fine movement in the directions and fine rotation in the XY plane. Further, the X laser interferometer and the Y laser interferometer are multi-axis interferometers having a plurality of length measuring axes, and rotate (yaw (θz rotation around Z axis)) in addition to the X and Y positions of the wafer table 18. , Pitching (θx rotation around the X axis) and rolling (θy rotation around the Y axis) are also measurable. Therefore, in the following description, the laser interferometer 26 will be used to measure the wafer table 1.
It is assumed that 8 positions of X, Y, θz, θy, and θx in the 5-DOF direction are measured. The coordinate system (X, Y) composed of the X coordinate and the Y coordinate measured in this way is also referred to as “stage coordinate system” below.

The measurement value of the laser interferometer 26 is the main controller 2
8 to the main controller 28, the laser interferometer 26
The position control of the wafer table 18 is performed by driving the XY stage 20 via the wafer stage drive system 22 while monitoring the measurement value of 1.

A reference plate FP is fixed on the wafer table 18 so that its surface is at the same height as the surface of the wafer W. On the surface of the reference plate FP, various reference marks including reference marks used for so-called baseline measurement of an alignment detection system described later are formed.

On the side surface of the lens barrel of the projection optical system PL, off
An axis type alignment detection system AS is attached. As the alignment detection system AS, for example, an image of an alignment mark (or a reference mark on the reference plate FP) on the wafer W, which is imaged by a CCD camera or the like, which is illuminated with light having a wide wavelength band using a halogen lamp or the like as a light source. FIA (Fi
An off-axis alignment sensor of eld Image Alignment type is used.

The alignment control device 16 A / D-converts the information from the alignment detection system AS and detects the mark position by referring to the measurement value of the laser interferometer 26. The detection result is supplied from the alignment controller 16 to the main controller 28.

Further, in the exposure apparatus 100 of the present embodiment, although not shown, a reticle is provided above the reticle R via a projection optical system PL disclosed in, for example, Japanese Patent Laid-Open No. 7-176468. TTR (Through The Reticl) using an exposure wavelength for simultaneously observing a reticle mark (not shown) on R and a mark on the reference plate FP.
e) A pair of reticle alignment microscopes consisting of an alignment system is provided. Detection signals of these reticle alignment microscopes are supplied to main controller 28 via alignment controller 16.

The main controller 28 includes a CPU (central processing unit), a memory (ROM, RAM), a so-called microcomputer (or workstation) including various interfaces, and the like, and the exposure operation is performed accurately. As described above, for example, the synchronous scanning of the reticle R and the wafer W, the stepping of the wafer W, the exposure timing, etc. are centrally controlled. Further, the main controller 28 is connected to the storage device 27 so that various data can be stored in and read from the storage device 27.

Here, the pattern arranged in the pattern area PA of the reticle R in the first embodiment will be described. As an example, as shown in FIG. 2A, in the pattern area PA of the reticle R, two chip patterns CP1 and CP2 having the same pattern are arranged. Here, the chip pattern CP2 is the right side (+ Y side) of the chip pattern CP1 in FIG.
Are separated from each other by the center distance DP. The pattern shapes of the chip patterns CP1 and CP2 are not limited to particular patterns. Therefore, although not specified here, it is assumed that some pattern is arranged.

Next, the flow of the exposure processing operation by the exposure apparatus 100 configured as described above will be described with reference to the flowchart of FIG. The flowchart of FIG. 3 corresponds to a series of processing algorithms executed by the CPU of main controller 28.

As a precondition, on the wafer W, for example, a pattern of a layer to be superposed (hereinafter referred to as “target layer”) of layers up to the previous layer, together with an alignment mark, is collectively exposed ( It is assumed that a plurality of (for example, N) regions (shot regions) transferred by using a stepper have already been formed. As an example,
The respective shot areas are arranged in a matrix having a scanning direction (Y axis direction) and a non-scanning direction (X axis direction) as row and column directions, respectively, and an even number of shot areas are arranged in the row direction. It is assumed that Further, it is assumed that one chip pattern is transferred to each shot area as a pattern of the target layer.

Further, the center-to-center distance DP between the chip pattern CP1 and the chip pattern CP2 in the reticle R described above is the center-to-center distance DS in the Y-axis direction between the shot areas adjacent in the row direction on the wafer W (see FIG. )
(Reference) and the following equation (1).

DS = DP · β (1)

Here, β is the projection magnification of the projection optical system PL.

In step 401 of FIG. 3, the reticle R is loaded on the reticle stage RST using a reticle loader (not shown).

In step 403, the wafer W is loaded on the wafer table 18 by using a wafer loader (not shown).

In step 405, for example, at least a pair of reticle alignment marks and at least a pair of reference marks formed on the surface of the reference plate FP corresponding to the reticle alignment marks are projected by the reticle alignment microscope through the projection optical system PL. Detects the relative position of. Then, based on the measured values of the reticle interferometer 21 and the laser interferometer 26 at that time, the reticle stage coordinate system defined by the length measurement axis of the reticle interferometer 21 and the length measurement axis of the laser interferometer 26 are defined. Obtain the relationship with the wafer stage coordinate system. That is, reticle alignment is performed in this manner.

In step 407, three or more preselected shot areas (“sample shot areas” or “alignment shot areas”) on the wafer W are selected based on the designed arrangement coordinates of the shot areas on the wafer W. (Referred to as) is sequentially positioned directly below the alignment detection system AS, the position of the alignment mark attached to the sample shot area is detected with the detection center of the alignment detection system AS as a reference, and the position information of the alignment mark is obtained.

In step 409, based on the position information of this alignment mark, for example, Japanese Patent Laid-Open No. 61-444.
Statistical calculation using the least squares method as disclosed in Japanese Patent Publication No. 29, etc. to calculate the array coordinates of the shot area,
A so-called EGA (Enhanced Global Alignment) operation is performed.

Here, the statistical calculation performed in the EGA calculation will be briefly described.

First, the designed array coordinates of p (an integer of p ≧ 3) sample shot areas on the wafer are represented by (X _k ,
Y _k ) (k = 1, 2, ..., P), and a deviation (ΔX _k , ΔY _k ) from the designed array coordinates is assumed to be a linear model represented by the following equation (2).

[0057]

[Equation 1]

Further, the actual array coordinates of each sample shot area are calculated based on the position information of the alignment marks attached to each sample shot area. Then, the deviation (Δx _k , Δy _k ) from the designed array coordinates is _obtained . The sum of squares E of the residuals between this deviation and the deviation from the designed array coordinates assumed in the linear model is expressed by the following equation (3).

[0059]

[Equation 2]

Therefore, parameters a, b, c, d, e and f that minimize the sum of squares E are obtained. Next, the array coordinates of all shot areas on the wafer are calculated based on the parameters a to f obtained as described above and the designed array coordinates.

In the above description, the parameters a to f are used for simplification of the description, but each of these parameters is an error parameter for the next six wafers (hereinafter, "wafer parameter"). That is, rotation about the arrangement of each shot area on the wafer (wafer rotation error), scaling in the X and Y directions (linear expansion and contraction of the wafer), offset in the X and Y directions, orthogonality error of the stage coordinate system, Corresponds to a predetermined combination or replacement. That is, the above six wafer parameters can be obtained by obtaining the parameters a to f.

In step 411, it is determined whether or not the orthogonality error of the stage coordinate system is less than or equal to a preset threshold value SV1 among the six wafer parameters obtained by the above EGA calculation. If the orthogonality error of the stage coordinate system is less than or equal to the threshold value SV1, step 41
The determination at 1 is affirmative, and the process proceeds to step 413.

In step 413, 1 is set in the counter i indicating the array number of the shot area.

In step 414, the target number of shot areas to be transferred at the same time (hereinafter referred to as "shot target number" for convenience).
2), and the first shot area and the second shot area are exposure target areas, as shown in FIG. Here, the second shot area is shown in FIG.
As shown in (A), it is a shot area adjacent to the first shot area in the Y-axis direction.

Further, in the reticle R, as shown in FIG.
As shown in FIG. 5, the area including the chip pattern CP1 and the chip pattern CP2, that is, the entire area of the pattern area PA of the reticle R is the area of the pattern to be transferred (hereinafter referred to as “transfer pattern area” for convenience). .

In step 415 of FIG. 3, the XY stage 20 is set so that the position of the wafer W becomes the acceleration start position (scan start position) for exposing the exposure target area on the wafer W.
The reticle stage RST is moved so that the position of the reticle R becomes the acceleration start position (scanning start position) for illuminating the transfer pattern area.

In step 417, the reticle stage R
Relative scanning between the ST and XY stage 20 is started. Then, when both stages reach their respective target scanning speeds and reach the constant speed synchronized state, the transfer pattern area of the reticle R starts to be illuminated by the illumination light IL from the illumination system IOP, and scanning exposure is started. The above relative scanning is performed by the laser interferometer 2
6 and the reticle interferometer 21 while monitoring the measured values, the wafer stage drive system 22 and the reticle stage drive system 2
9 is controlled.

During the above scanning exposure, the moving speed Vr of the reticle stage RST in the Y-axis direction and the moving speed Vw of the XY stage 20 in the Y-axis direction are maintained at a speed ratio according to the projection magnification β of the projection optical system PL. Control is performed as described above.

Then, the different areas of the transfer pattern area are successively illuminated with the illumination light IL, and the scanning exposure is completed when the illumination of the transfer pattern area is completed.

As a result, the chip pattern CP1 and the chip pattern CP2 are transferred to the wafer W via the projection optical system PL.
The image is reduced and transferred to the upper exposure target area. That is, FIG.
As shown in (C), the chip pattern CP1 is transferred to the i-th shot area (here, the first shot area), and the chip pattern CP2 is transferred to the i + 1-th shot area (here, the second shot area). Is transcribed.

In step 419 of FIG. 3, the shot target number, that is, 2 is added to the value of the counter i.

In step 421, the counter i is referenced to determine whether or not the chip pattern has been transferred to all shot areas. When the value of the counter i is N or less, the determination in step 421 is denied, the i-th shot area and the i + 1-th shot area are set as the next exposure target area, and the process returns to step 415.

Thereafter, the processing / judgment of steps 415 → 417 → 419 → 421 is repeated until the judgment of step 421 becomes affirmative.

When the transfer of the chip pattern to all the shot areas is completed, the value of the counter i becomes N + 1, the judgment in step 421 is affirmed, and the processing is ended.

On the other hand, if the orthogonality error of the stage coordinate system exceeds the threshold value SV1 in step 411, the determination in step 411 is denied, and the process proceeds to step 433.

At step 433, 1 is set to the counter i indicating the array element number of the shot area.

At step 434, the shot target number is set to 1
Then, as shown in FIG. 5A, the first shot area is the exposure target area. Further, in the reticle R, as shown in FIG.
The area where 1 is arranged, that is, 1/2 of the pattern area PA of the reticle R is set as the transfer pattern area.

In step 435 of FIG. 3, step 41
5, the XY stage 20 and the reticle stage R
Move ST to each acceleration start position.

In step 437, scanning exposure is performed in the same manner as in step 417. As a result, the chip pattern CP1 is reduced and transferred onto the exposure target area on the wafer W via the projection optical system PL. That is, as shown in FIG. 5C, the chip pattern CP1 is transferred to the i-th shot area (here, the first shot area).

In step 439 of FIG. 3, the counter i is referred to and the chip pattern CP1 is set in all shot areas.
It is determined whether or not the transfer has been performed. Here, i = 1,
That is, since the transfer has only been performed on the first shot area, the determination at step 439 is negative, and the process proceeds to step 441.

At step 441, the shot target number, that is, 1 is added to the value of the counter i to set the next shot area as the next exposure target area, and the procedure returns to step 435.

Thereafter, the processing / judgment of steps 435 → 437 → 439 → 441 is repeated until the judgment of step 439 is affirmed.

Chip pattern C for all shot areas
When the transfer of P1 is completed, the value of the counter i becomes N,
The determination in step 439 is affirmed, and the process ends.

As described above, according to the first embodiment, when the orthogonality error of the stage coordinate system on the wafer W is equal to or less than the predetermined threshold value SV1, when the chip patterns are simultaneously transferred to the two shot areas. It is determined that the overlay error is within the allowable range, the target number of shots is 2, the transfer pattern area is the entire area of the pattern area PA, and the chip pattern is transferred to two shot areas simultaneously by one exposure. Therefore, the throughput can be improved.

On the other hand, if the orthogonality error of the stage coordinate system exceeds the predetermined threshold value SV1, it is judged that the overlay error when the chip patterns are simultaneously transferred to the two shot areas exceeds the allowable range, and the shot target is determined. The number is 1 and the transfer pattern area is 1/2 of the pattern area PA.
Since the chip pattern is transferred to only one shot area by one exposure, the overlay error can be maintained within the allowable range.

That is, according to the first embodiment, it is possible to improve the throughput without lowering the overlay accuracy.

Further, according to the first embodiment, the orthogonality error of the stage coordinate system is obtained by the statistical calculation process using the position information of the alignment marks of only some sample shot areas on the wafer W. In addition, the orthogonality error of the stage coordinate system can be obtained with high throughput and high accuracy. This makes it possible to reliably determine the target number of shots and the transfer pattern area, and as a result, it is possible to improve throughput without lowering overlay accuracy. In step 414 of FIG. 3, the EG in step 409 is preceded by the scanning exposure.
Based on the A calculation result (parameters a to f), the two shot areas on the wafer W may be virtually regarded as one shot area and the coordinate position thereof may be calculated, or the coordinate positions may be calculated by the conventional EGA method. The coordinate position of the shot area may be calculated, and one coordinate position may be determined from the coordinate positions of the two shot areas to which the pattern is transferred by one scanning exposure. In step 415, the XY stage 20 is moved according to this coordinate position. Movement is controlled. Also, step 434
Then, the coordinate position of each shot area on the wafer W is calculated by the conventional EGA method, and in step 435, the movement of the XY stage 20 is controlled in accordance with this coordinate position.

<< Second Embodiment >> A second embodiment of the present invention will be described below with reference to FIG.

The second embodiment is the same as the exposure apparatus 10 described above.
0, one of the two chip patterns CP1 and CP2 arranged in the pattern area PA of the reticle R is overlaid on each shot area on the wafer W under the same preconditions as in the first embodiment. It is also transferred.
However, in the second embodiment, it is assumed that four two-dimensional marks, whose positions in the X-axis direction and the Y-axis direction can be simultaneously detected, are formed as alignment marks in each shot area.

FIG. 6 is a flow chart corresponding to a series of processing algorithms executed by the CPU of the main control unit 28. The second embodiment will be described by using this flow chart with a focus on the differences from the first embodiment. The form will be described below.

In steps 501 to 505 of FIG. 6, the same processing as steps 401 to 405 in the first embodiment is performed.

In step 507, three or more preselected sample shot areas on the wafer W are sequentially positioned immediately below the alignment detection system AS based on the designed arrangement coordinates of each shot area on the wafer W. Positions of five or more alignment marks selected from three or more sample shot areas are detected with reference to the detection center of the alignment detection system AS, and position information of the alignment marks is obtained.

At step 509, based on the position information of the alignment mark, for example, Japanese Patent Laid-Open No. 6-3497.
As disclosed in Japanese Patent Publication No. 05, etc., a so-called multi-shot EGA calculation within a shot is performed, in which the regularity of the array of shot areas on the wafer is precisely specified by a statistical method.

Here, the statistical method used in the above-described intra-shot multipoint EGA calculation will be briefly described. A reference point (eg, the center of the shot area) for each alignment mark is set in advance in each shot area.

First, the selected alignment on the wafer
Mark AM_T(T = 1, 2, ..., s) (S ≧ 5
Number area) shot area SA_t(T = 1, 2, ...)
Design coordinates of the reference point of (Cx_{T, t}, C
y_{T, t}), Its alignment mark AM_TTo the reference point of
Relative design coordinate values (Sx_{T, t}, S
y_{T, t}) And its alignment mark AM_TThe
Calculated coordinate value (Fx _{T, t}, Fy
_{T, t}) For a linear model as shown in equation (4) below.
Suppose Dell.

[0096]

[Equation 3]

[0097] Further, by using the following equation (5) actually measured coordinate values of each of the alignment marks AM _T (FMx
_{T, t} , FMy _{T, t} ) and their calculated coordinate values (Fx
_{T, t} , Fy _{T, t} ) and the sum of squares E ₁ of the differences.

[0098]

[Equation 4]

Then, this sum of squares E₁To minimize
Parameter a₁, B₁, C₁, D ₁, E₁, F₁, G
₁, H₁, I₁, J₁To calculate. The power calculated here
Parameter a₁~ J₁And setting the reference point in each shot area.
Alignment mark for position information and reference point of accounting
The position of each shot area from the relative position information in the design of
Calculate information.

By the way, in the above description, the parameters a _{1 to} j ₁ are used for simplification of the description, but each of these parameters is the above-mentioned 6 wafer parameters and 4 shots. An error parameter related to the area (hereinafter, appropriately referred to as “shot parameter”), that is, a rotation error of the shot area, an orthogonality error of the shot area, a scaling of the shot area in X and Y directions (linear expansion / contraction of the shot area, so-called magnification error ), A predetermined combination or replacement.
That is, by obtaining the parameters a _{1 to} j ₁ ,
The above four shot parameters and six wafer parameters can be obtained.

In step 511, it is determined whether or not the orthogonality error of the shot area is less than or equal to a preset threshold value SV2 among the four shot parameters obtained by the above-described intra-shot multipoint EGA calculation. . Then, when the threshold value is equal to or lower than the threshold value SV2, the determination in step 511 is affirmative, and the process proceeds to step 513.

In step 513, it is determined whether or not the rotation error of the shot area is less than or equal to a preset threshold value SV3 among the above-mentioned shot parameters. Then, when the threshold value is equal to or lower than the threshold value SV3, the determination in step 513 is affirmative, and the process proceeds to step 515.

In step 515, it is determined whether the magnification error of the shot area is less than or equal to a preset threshold value SV4 among the above-mentioned shot parameters. If the magnification error is less than or equal to the threshold value SV4 in both the X-axis direction and the Y-axis direction, the determination at step 515 is affirmative, and the process proceeds to step 517.

In steps 517 to 525, steps 413 to 421 in the first embodiment are executed.
Perform the same processing as. As a result, the chip patterns are transferred to the two shot areas by one exposure.

On the other hand, if the orthogonality error of the shot area exceeds the threshold value SV2 in step 511, the determination in step 511 is denied, and the process proceeds to step 529.

In step 529, it is checked whether or not the rotation error of the shot area needs to be corrected. For example, if the rotation error of the shot area is equal to or smaller than the threshold value SV3, it is determined that the correction is not necessary, and if it exceeds the threshold value SV3, it is determined that the correction is necessary. Note that the criterion here is not limited to the threshold value SV3, and other criterion may be used.

At step 531, it is checked whether or not it is necessary to correct the magnification error of the shot area. For example, if the magnification error of the shot area is equal to or less than the threshold value SV4, it is determined that the correction is not necessary, and if it exceeds the threshold value SV4, it is determined that the correction is necessary. Here, the magnification error in the X-axis direction and the magnification error in the Y-axis direction are respectively determined. In addition, the criterion here is the threshold S
The criterion is not limited to V4, and other criteria may be used.

At steps 533 and 534,
The same processing as steps 433 and 434 of the first embodiment is performed.

In step 535, when it is necessary to correct the magnification error of the shot area in the X-axis direction, the imaging characteristic correction controller (not shown) of the projection optical system PL is considered in consideration of the magnification error of the shot area in the X-axis direction. Is controlled to adjust the projection magnification of the projection optical system PL. And X
The Y stage 20 and the reticle stage RST are moved to their respective acceleration start positions.

In step 537, scanning exposure is performed in the same manner as in step 417 of the first embodiment. However, here, when the relative scanning axis direction between the reticle R and the wafer W is adjusted and the magnification error of the shot area in the Y axis direction needs to be corrected in consideration of the orthogonality error of the shot area. Is to adjust the relative speed between the scanning speed of the reticle stage RST and the scanning speed of the XY stage 20 in consideration of the magnification error of the shot area in the Y-axis direction, and when it is necessary to correct the rotation error of the shot area. In consideration of the rotation error of the shot area, the XY stage 20 is rotated in advance with respect to the reticle stage RST to perform relative scanning.

As a result, the orthogonality error of the shot area and the rotation error and the magnification error of the shot area, which are determined to need correction, are corrected, and the chip pattern CP1 passes through the projection optical system PL. The reduced transfer is performed on the exposure target area on the wafer W.

In step 539, the counter i is referred to, and it is determined whether or not the chip pattern CP1 has been transferred to all shot areas. In this case, i = 1, that is, the transfer is performed only to the first shot area, so the determination in step 539 is negative, and step 54
Move to 1.

At step 541, the target number of shots, that is, 1 is added to the value of the counter i to set the next shot area as the next exposure target area, and the procedure returns to step 535.

Thereafter, the processing / determination of steps 535 → 537 → 539 → 541 is repeated until the determination of step 539 is affirmed.

Chip pattern C for all shot areas
When the transfer of P1 is completed, the value of the counter i becomes N,
The determination at step 539 is affirmative, and the process ends.

If the rotation error of the shot area exceeds the threshold value SV3 in step 513, the determination in step 513 is denied and the process moves to step 531. Then, in step 531, as described above, after checking whether or not the correction of the magnification error of the shot area is necessary, the processing of step 533 is performed, and further, the determination of step 539 is affirmed. Step 535
The process / judgment of → 537 → 539 → 541 is repeated. However, in this case, the orthogonality error of the shot area is the threshold value SV.
Since it is 2 or less, in step 537, the correction of the orthogonality error of the shot area is not performed.

Furthermore, if the magnification error of the shot area exceeds the threshold value SV4 in step 515, the determination in step 515 is denied and the routine moves to step 533. Then, the process of step 533 is performed, and further,
Until the determination at step 539 is affirmative, step 5
The processing / judgment of 35 → 537 → 539 → 541 is repeated. However, in this case, since the orthogonality error and the rotation error of the shot area are equal to or less than the threshold values SV2 and SV3, respectively, the orthogonality error and the rotation error of the shot area are not corrected in step 537.

As described above, according to the second embodiment, if all of the orthogonality error, the rotation error and the magnification error of the shot area are equal to or less than the predetermined threshold, the chip patterns are simultaneously formed in the two shot areas. It is judged that the overlay error at the time of transfer is within the allowable range, the shot target number is determined to be 2, the transfer pattern area is determined to be the entire area of the pattern area PA, and one shot is simultaneously applied to two shot areas. Since the pattern is transferred, the throughput can be improved.

On the other hand, if at least one of the orthogonality error, the rotation error, and the magnification error of the shot area exceeds a predetermined threshold value, the overlay error when the chip patterns are simultaneously transferred to the two shot areas is within an allowable range. The number of shots is determined to be 1 and the transfer pattern area is determined to be 1/2 of the pattern area PA, and the transfer error related to the shot area is corrected, and only one shot area is chipped by one exposure. Since the pattern is transferred, it is possible to perform the superposed transfer with high accuracy.

Therefore, according to the second embodiment, it is possible to improve the throughput without lowering the overlay accuracy.

Further, according to the second embodiment, since shot parameters are obtained by statistical calculation processing using position information of alignment marks of only some sample shot areas on the wafer W, high throughput is achieved. It is possible to accurately obtain the orthogonality error, the rotation error, and the magnification error in the shot area. This makes it possible to reliably determine the target shot number and the transfer pattern area, and as a result, it is possible to improve throughput without lowering overlay accuracy.

In the second embodiment, the shot parameters obtained by the intra-shot multipoint EGA calculation are used, but the present invention is not limited to this, and, for example,
You may use the correction value of the orthogonality error of a shot area | region, rotation error, and magnification error input by an operator via an input device which is not shown in figure.

Further, in the second embodiment, as for the magnification error of the shot area, the same threshold value SV4 is used in the X-axis direction and the Y-axis direction, but different threshold values may be used. In step 518 and step 534 of FIG. 6 in the second embodiment, the coordinate position of the shot area is calculated in exactly the same manner as step 414 and step 434 of FIG. 3 in the first embodiment. Then, in steps 519 and 535 of FIG. 6, the movement of the XY stage 20 is controlled according to the coordinate position.

Further, in the first and second embodiments,
When the shot target number is 1, only the chip pattern CP1 is used, but the number is not limited to this.
The chip pattern CP2 may be used, or the chip patterns CP1 and CP2 may be used alternately. This is because both have the same pattern.

In the first and second embodiments described above,
The case where an even number of shot areas are arranged in the scanning direction has been described, but the present invention is not limited to this. When the number of shot areas arranged in the scanning direction is an odd number, the chip pattern may be transferred for each shot area for the last one row regardless of the size of the transfer error. In this case, for example, Japanese Patent Laid-Open No. 10-3
As disclosed in Japanese Patent No. 03126, a search method (linear programming, Lin &Kernighan's solution, k
-OPT method, or genetic algorithm)
The optimum movement sequence may be determined from the visit order of all shot areas on the wafer to be scan-exposed and the combination of the scanning directions in each shot area. This makes it possible to minimize the decrease in throughput.

Further, in the first and second embodiments,
The case where two chip patterns CP1 and CP2 having the same pattern are arranged on the reticle R has been described, but it goes without saying that the present invention is not limited to this. For example, when four chip patterns are arranged on the reticle R, in the first and second embodiments described above, if the transfer error in the shot area is less than or equal to a predetermined threshold value, the shot target number is four and the transfer pattern is If the area is determined to be the entire area of the pattern area PA and the transfer error of the shot area exceeds a predetermined threshold value, the shot target number may be set to 1 and the transfer pattern area may be set to 1/4 of the pattern area PA.

<< Third Embodiment >> A third embodiment of the present invention will be described below with reference to FIGS.

In the third embodiment, the exposure apparatus 1 described above is used.
00, the chip pattern arranged in the pattern area PA of the reticle R is transferred onto the wafer W.

Here, the pattern area PA of the reticle R is
For example, as shown in FIG. 7A, three chip patterns CP3, CP4, C having the same pattern are included in the inside.
P5 is arranged. And the chip pattern CP4
Are arranged on the right side (+ Y side) of the chip pattern CP3 in FIG. 7A with a center distance DP1 between them, and the chip pattern CP5 is the right side of the chip pattern CP4 in FIG. (+ Y side), the center-to-center distance DP1 is provided. The pattern shape of each chip pattern is not limited to a specific pattern. Therefore, although not explicitly shown here, it is assumed that some pattern is formed.

As a prerequisite, on the wafer W,
For example, the pattern of the target layer including the alignment marks is transferred by using a collective exposure apparatus (for example, N
It is assumed that the individual areas (shot areas) have already been formed. As an example, the shot areas are arranged in a matrix having a scanning direction (Y-axis direction) and a non-scanning direction (X-axis direction) as row and column directions, respectively, and an integer of 3 in the row direction. It is assumed that twice as many shot areas are arranged. In addition, in the third embodiment,
The pattern of the target layer is a so-called one-shot / two-chip taking pattern in which two chip patterns are transferred by one exposure, and each shot area has a chip pattern as shown in FIG. 7B. It is assumed that two transferred areas TP are formed.

Further, the center-to-center distance DP1 of each chip pattern in the reticle R described above is the center-to-center distance DS1 in the Y-axis direction of the region TP on the wafer W onto which the chip pattern of the target layer is transferred (see FIG. )reference)
And the relationship expressed by the following equation (6).

DS1 = DP1 · β (6)

FIG. 8 is a flow chart corresponding to a series of processing algorithms executed by the CPU of the main control unit 28. The third embodiment will be described by using this flow chart focusing on the difference from the first embodiment. The form will be described below.

In steps 601 to 609 of FIG. 8, the same processing as steps 401 to 409 in the first embodiment is performed.

In step 611, it is determined whether or not the orthogonality error of the stage coordinate system is less than or equal to a preset threshold value SV1 among the six wafer parameters obtained in step 609. Then, when the orthogonality error of the stage coordinate system is less than or equal to the threshold value SV1, the determination in step 611 is affirmative, and the process proceeds to step 613.

At step 613, 1 is set to the counter i indicating the array number of the shot area, and 1 is set to the judgment value z for judging whether or not the chip patterns CP3 and CP4 are transferred to the same shot area.
Set.

At step 614, the shot target number is set to 3
/ 2 (= 1.5), and as shown in FIG.
The first shot area and half of the second shot area are exposure target areas. That is, 1.5 shot areas are set as the exposure target area. Further, as shown in FIG. 9B, three chip patterns CP3, CP4, C
An area including P5, that is, the entire area of the pattern area PA of the reticle R is set as a transfer pattern area.

In step 615 of FIG. 8, the XY stage 20 and the reticle stage RST are moved to their respective acceleration start positions in the same manner as step 415 in the first embodiment.

In step 617, scanning exposure is performed in the same manner as step 417 in the first embodiment.

Accordingly, the three chip patterns CP
3, CP4 and CP5 are placed on the wafer W via the projection optical system PL.
The image is reduced and transferred to the upper exposure target area. That is, FIG.
As shown in (C), the chip pattern CP3 and the chip pattern CP4 are transferred to the i-th shot area (here, the first shot area), and half of the i + 1st shot area (here, the second shot area) is transferred. The chip pattern CP5 is transferred to.

In step 619 of FIG. 8, the shot target number, that is, 1.5 is added to the judgment value z.

At step 621, the value of the integer part of the judgment value z is extracted and set in the counter i.

In step 627, the counter i is referred to, and it is determined whether or not the chip pattern has been transferred to all shot areas. If the value of the counter i is N or less, the determination at step 627 is denied and step 62
Move to 9.

At step 629, the next 1.5 shot areas are set as the next exposure target area. Here, if the value of the judgment value z is an integer, as shown in FIG. 10A, the i-th shot area and half of the i + 1-th shot area are set as the next exposure target area, and one of the judgment values is If the value of z is not an integer, half of the i-th shot area and the i + 1-th shot area are set as the next exposure target area, as shown in FIG. Then, step 6 in FIG.
Return to 15.

Thereafter, the processes and judgments of steps 615 to 629 are repeated until the judgment of step 627 is affirmed.

When the transfer of the chip pattern to all the shot areas is completed, the determination at step 627 in FIG. 8 is affirmed and the processing is completed.

On the other hand, if the orthogonality error of the stage coordinate system exceeds the threshold value SV1 in step 611, the determination in step 611 is denied, and the process proceeds to step 633.

At step 633, 1 is set to the counter i indicating the array element number of the shot area.

At step 634, the shot target number is set to 1
Then, as shown in FIG. 11A, the first shot area is the exposure target area. Further, as shown in FIG. 11B, an area including the chip patterns CP3 and CP4, that is, 2/3 of the pattern area PA of the reticle R is set as a transfer pattern area.

In step 635 of FIG. 8, the reticle stage RST and the XY stage 20 are moved to their respective acceleration start positions in the same manner as step 415 in the first embodiment.

In step 637, scanning exposure is performed in the same manner as in step 417 in the first embodiment.

As a result, the chip pattern CP3 and the chip pattern CP4 are transferred to the wafer W via the projection optical system PL.
The image is reduced and transferred to the upper exposure target area. Here, FIG.
As shown in (C), the chip pattern CP3 and the chip pattern CP4 are transferred to the i-th shot area.

In step 639 of FIG. 8, the counter i is referred to and the chip pattern CP is applied to all shot areas.
3. Judge whether CP4 is transferred. Here, i = 1, that is, only the transfer to the first shot area is performed, so the determination in step 639 is negative, and the process proceeds to step 641.

At step 641, the target number of shots, that is, 1 is added to the value of the counter i to set the next shot area as the next exposure target area, and the procedure returns to step 635.

Thereafter, the processing / judgment of steps 635➝637➝639➝641 is repeated until the judgment in step 639 is affirmed.

Chip pattern C for all shot areas
When the transfer of P3 and CP4 is completed, the value of the counter i becomes N.
Then, the determination in step 639 is affirmed, and the process ends.

As described above, according to the third embodiment, the orthogonality error of the stage coordinate system has a predetermined threshold value SV.
If it is 1 or less, it is determined that the overlay error when the chip patterns are simultaneously transferred to 1.5 shot areas is within the allowable range, and the shot target number is 1.5 and the transfer pattern area is the pattern area. Since the entire area of the PA is determined and the chip pattern is transferred to 1.5 shot areas in one exposure, the throughput can be improved.

On the other hand, if the orthogonality error of the stage coordinate system exceeds the predetermined threshold value SV1, it is judged that the overlay error when the patterns are simultaneously transferred to 1.5 shot areas exceeds the allowable range. , The shot target number is 1 and the transfer pattern area is ⅔ of the pattern area PA.
Since the chip pattern is transferred to only one shot area by one exposure, the overlay error can be maintained within the allowable range.

Therefore, according to the third embodiment, it is possible to improve the throughput without lowering the overlay accuracy.

In the third embodiment, the chip pattern CP3 and the chip pattern CP4 are used when the shot target number is 1, but the present invention is not limited to this, and the chip pattern CP4 and the chip pattern CP4 are used. Pattern CP
5 may be used, or they may be used alternately.

Furthermore, in the third embodiment described above, three chip patterns are formed in the pattern area PA of the reticle R, and two chip patterns of the target layer are transferred to each shot area on the wafer W. Although described, it should be understood that the invention is not so limited. Also, step 614 of FIG. 8 in the third embodiment.
In step 634, just like step 414 and step 434 in FIG. 3 in the first embodiment, the coordinate positions of 1.5 shot areas or 1 shot area are detected. Then, in steps 615 and 635 of FIG. 8, the movement of the XY stage 20 is controlled in accordance with the coordinate position.

In the third embodiment described above, the case where the number of shot areas is an integer multiple of 3 is arranged in the scanning direction, but the present invention is not limited to this, and the scanning direction is not limited to this. The number of shot areas arranged in
If it is not an integral multiple of, the chip pattern may be transferred to the shot area for one or ½ shots for the last one row regardless of the magnitude of the orthogonality error of the stage coordinate system. In this case, the optimum wafer movement sequence may be determined using the above-described search method.

Further, in each of the above embodiments, the case where the pattern of the target layer is transferred by using the collective exposure apparatus has been described, but the present invention is not limited to this. For example, the exposure area may be transferred using a scan exposure apparatus having the same size as that of the batch exposure apparatus (stepper). Further, in each of the above-described embodiments, the reticle pattern is superimposed and transferred onto the pattern of the target layer using the scan exposure apparatus, but a batch exposure apparatus (stepper) having an exposure area similar to that of the scan exposure apparatus is used. May be.

Further, in each of the above-mentioned embodiments, each threshold value is set in advance by an operator through an input device (not shown), and can be appropriately changed according to the allowable accuracy and the like.

In each of the above embodiments, the case where the target number of shots is two has been described, but the number of shots is not limited to this. For example, three chip patterns are arranged in the pattern area PA of the reticle R. , When the chip pattern of one target layer is transferred to each shot area, the shot target number is set to 1 in accordance with the size of the transfer error.
It is also possible to set it to any one of the two types.

In each of the above embodiments, the chip pattern arranged in the pattern area PA of the reticle R is
Although described as the same pattern, different patterns may be included.

Further, the light source of the exposure apparatus to which the present invention is applied is not limited to the KrF excimer laser or the ArF excimer laser, and may be an F ₂ laser (wavelength 157 nm) or another pulsed laser light source in the vacuum ultraviolet region. good. In addition, for example, erbium (or both erbium and ytterbium) -doped fiber is used as exposure illumination light, for example, a single-wavelength laser light in the infrared region or visible region emitted from a DFB semiconductor laser or a fiber laser. It is also possible to use a harmonic wave that is amplified by an amplifier and converted into ultraviolet light by using a nonlinear optical crystal.

The projection optical system PL may be any of a refraction system, a catadioptric system, and a reflection system, and may be a reduction system, a unit magnification system, or an enlargement system.

Further, the present invention is not limited to an exposure apparatus used for manufacturing a semiconductor element, but an exposure apparatus for transferring a device pattern onto a glass plate, which is used for manufacturing a display including a liquid crystal display element and a plasma display. The present invention can also be applied to an exposure apparatus used for manufacturing a thin film magnetic head, which transfers a device pattern onto a ceramic wafer, an exposure apparatus used for manufacturing an image pickup device (such as CCD), a micromachine, and a DNA chip. it can.

<< Device Manufacturing Method >> Next, an embodiment of a device manufacturing method using each of the exposure methods described above will be described.

In FIG. 12, devices (semiconductor chips such as IC and LSI, liquid crystal panel, CCD, thin film magnetic head,
A flow chart of a manufacturing example of a DNA chip, a micromachine, etc. is shown. As shown in FIG. 12, first, in step 301 (design step), function / performance design of a device (for example, circuit design of a semiconductor device) is performed, and pattern design for realizing the function is performed. Subsequently, in step 302 (mask manufacturing step), a mask on which the designed circuit pattern is formed is manufactured. On the other hand, in step 303 (wafer manufacturing step), a wafer is manufactured using a material such as silicon.

Next, in step 304 (wafer processing step), the mask and wafer prepared in steps 301 to 303 are used to form an actual circuit or the like on the wafer by a lithography technique, as will be described later. Next, step 305 (device assembly step)
In step 3, device assembly is performed using the wafer processed in step 304. This step 305 includes processes such as a dicing process, a bonding process, and a packaging process (chip encapsulation) as needed.

Finally, step 306 (inspection step)
In step 3, inspections such as an operation confirmation test and a durability test of the device manufactured in step 305 are performed. After these steps, the device is completed and shipped.

FIG. 13 shows a detailed flow example of step 304 in the case of a semiconductor device. In step 311 (oxidation step), the surface of the wafer is oxidized. In step 312 (CVD step), an insulating film is formed on the wafer surface. In step 313 (electrode forming step), electrodes are formed on the wafer by vapor deposition. In step 314 (ion implantation step), ions are implanted in the wafer.
Each of the above steps 311 to 314 constitutes a pretreatment process of each stage of wafer processing, and is selected and executed according to the required process at each stage.

At each stage of the wafer process, when the above-mentioned pretreatment process is completed, the posttreatment process is executed as follows. In this post-treatment process, first, step 3
In 15 (resist formation step), a photosensitive agent is applied to the wafer. Subsequently, in step 316 (exposure step), the circuit pattern of the mask is transferred onto the wafer by the exposure method of each of the above embodiments. Next, in step 317 (developing step), the exposed wafer is developed, and in step 318 (etching step), exposed members other than the portion where the resist remains are removed by etching. And step 319
In the (resist removing step), the unnecessary resist after etching is removed.

By repeating these pre-processing and post-processing steps, multiple circuit patterns are formed on the wafer.

When the device manufacturing method of this embodiment as described above is used, the exposure method of each of the above-described embodiments is used in the exposure step, so that high-precision overlay exposure is performed with high throughput and high integration is achieved. It becomes possible to manufacture the desired device with high productivity.

[0178]

As described above in detail, the exposure method according to the present invention has an effect that the throughput can be improved without lowering the overlay accuracy.

Further, according to the device manufacturing method of the present invention, there is an effect that the productivity of highly integrated devices can be improved.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a configuration of an exposure apparatus used in a first embodiment.

FIG. 2 (A) is a diagram showing an example of a reticle used in the first embodiment, and FIG. 2 (B) is a diagram for explaining a center distance DS of shot areas.

FIG. 3 is a flowchart for explaining the first embodiment of the exposure method according to the present invention.

FIG. 4A to FIG. 4C are diagrams for explaining the exposure method according to the first embodiment when the transfer error is small.

5A to 5C are views for explaining the exposure method according to the first embodiment when a transfer error is large.

FIG. 6 is a flowchart for explaining a second embodiment of the exposure method according to the present invention.

FIG. 7A is a diagram showing an example of a reticle used in the third embodiment, and FIG. 7B is a view for explaining a region to which a chip pattern of a target layer in a shot region is transferred. FIG.

FIG. 8 is a flowchart for explaining a third embodiment of an exposure method according to the present invention.

9A to 9C are diagrams for explaining an exposure method according to a third embodiment when a transfer error is small.

10A and 10B respectively show
It is a figure for demonstrating the exposure object area | region when a transfer error is small in 3rd Embodiment.

11A to 11C are diagrams for explaining an exposure method according to the third embodiment when a transfer error is large.

FIG. 12 is a flowchart for explaining an embodiment of a device manufacturing method according to the present invention.

13 is a flowchart of the process in step 304 of FIG.

14A and 14B respectively show
FIG. 6 is a diagram showing an example of a case where a shot area has a rotation error and a chip pattern is transferred to two shot areas by one exposure.

[Explanation of symbols]

100 ... Exposure device (scan exposure device), CP1 ... Chip pattern (part of pattern), CP2 ... Chip pattern (part of pattern), CP3 ... Chip pattern (part of pattern), CP4 ... Chip pattern (of pattern) Part), CP5 ... Chip pattern (part of pattern), W
... wafer (substrate).

Claims (11)

[Claims] 1. An exposure method for transferring a predetermined pattern onto a substrate, the method comprising: obtaining information on a transfer error relating to a plurality of divided areas formed on the substrate; based on the information on the transfer error, Of the plurality of divided areas, a target number of divided areas to which the pattern is to be simultaneously transferred in one exposure and a region of the pattern to be transferred in the pattern so as to overlap the target number of divided areas are determined. And a step of performing transfer according to the above determination; 2. The exposure according to claim 1, wherein the transfer error information is obtained based on position information of marks formed in a plurality of specific partitioned areas among the plurality of partitioned areas. Method. 3. The exposure method according to claim 2, wherein the transfer error information is obtained by a statistical calculation process using position information of the mark. 4. The transfer error includes at least one of an orthogonality error of a coordinate axis of the substrate, an orthogonality error of a coordinate axis of the partitioned area, a magnification error of the partitioned area, and a rotation error. Item 4. The exposure method according to any one of Items 1 to 3. 5. The target number and the area of the pattern are
The exposure method according to claim 1, wherein the transfer error is determined by comparing the transfer error with a predetermined threshold value. 6. When the transfer error is less than or equal to the threshold value, the target number is determined to be n (n> 1), and at the same time, one exposure of the pattern should be transferred to n partition areas. The exposure method according to claim 5, wherein an area including a pattern is determined as an area of the pattern. 7. When the transfer error exceeds the threshold value, the target number is determined to be m (1 ≦ m <n), and at the same time, in one exposure of the pattern, the m divided areas are simultaneously formed. The exposure method according to claim 6, wherein an area including a pattern to be transferred is determined as an area of the pattern. 8. When the transfer error is less than or equal to the threshold value, the n is determined to be 2, and a region including all of the patterns is determined as a region of the pattern, and when the transfer error exceeds the threshold value, The m is determined to be 1, and a region including 1/2 of the pattern is determined as a region of the pattern.
The exposure method described in. 9. The transfer error is corrected based on information of the transfer error when the pattern is transferred when the transfer error exceeds the threshold value.
9. The exposure method according to any one of 8 to 10. 10. The plurality of divided areas are formed by using a batch exposure apparatus, and the pattern is transferred by using a scan exposure apparatus. Exposure method. 11. A device manufacturing method including a lithography step, wherein the exposure method according to claim 1 is used in the lithography step.