JP2003186736A - Memory controller with setup time error avoided - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller that can sufficiently secure a setup margin for the clock for an address signal or a control signal. <P>SOLUTION: In the memory controller that supplies a synchronized type memory module with the address signal, the control signal and the clock as a strobe signal for them, with the memory controller comprising a clock generation circuit that generates a timing of the supplied clock at a timing almost same with a leaf clock being a reference and a signal generation circuit that generates and outputs the address signal or the control signal in response to a given trigger clock, the timing of the trigger clock is controlled to be faster than the leaf clock. Corresponding to the difference between a transfer delay time of the supplied clock until it arrives at the memory module and the transfer delay time of the address signal or the control signal, the timing of the trigger clock is made to be faster than the timing of the leaf clock, so that the sufficient setup margin can be secured on the memory module side. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory controller for controlling a synchronous memory such as SDRAM, and more particularly,
The present invention relates to a memory controller capable of avoiding a setup time error in a controlled synchronous memory.

[0002]

2. Description of the Related Art A synchronous memory such as SDRAM is supplied with an address signal, a control signal, a write data signal, etc. from a memory controller in synchronization with a clock as a strobe signal, and outputs a read data signal in synchronization with the clock. To do. By using the clock for the strobe signal,
It enables operation in high-speed cycles.

On the other hand, an SDRAM device is generally used as a large-capacity memory of a computer, and a plurality of SDRAMs are mounted on a board to be modularized. For these SDRAMs, address signals and control are performed in synchronization with a common clock. Signals, write data signals, etc. may be supplied. In that case, the load capacity of the bus wiring between the memory controller and the SDRAM module becomes large, and inconsistency may occur between the phase of the clock and the phase of the address signal, the control signal and the like.

FIG. 1 is a diagram showing a conventional SDRAM controller and bus structure. Memory controller 10 and DIMM
Between the SDRAM module 20 having a (Dual In-line Memory Module) configuration, a clock, an address signal, a control signal,
A bus 30 including wiring for data signals is provided.

In the memory controller 10, an address is generated by a clock source circuit 11 which generates a source clock SCLK and a leaf clock LCLK which is generated through a tree wiring having a buffer 14 and has a common phase. It has an address generation circuit 13 including a flip-flop whose timing is controlled, and an address output circuit Add-OUT which outputs the address signal. The address output circuit Add-OUT drives the address signal wiring 32 of the bus 30 and supplies the address signal to the SDRAM module 20. Control signals such as clock enable signals and chip select signals, and write data signals are also supplied to the SDRAM module 20 with the same configuration.

Further, the memory controller 10 is an SDRAM
The clock adjustment circuit SD-CLK has a timing adjustment circuit 12 and a clock output circuit CLK-OUT for outputting the output clock of the timing adjustment circuit 12, and the clock output circuit CLK
-OUT drives the clock signal wiring 34 of the bus 30.
Timing (phase) of clock SD-CLK supplied to SDRAM
Is controlled by a PLL circuit or a DLL circuit configured by the timing adjustment circuit 12 and the feedback loop 15 so as to substantially match the phase of the leaf clock LCLK. The timing adjustment circuit 12 has a variable delay circuit inside and operates so as to match the phases of the leaf clock LCLK and the fed-back clock.
As a result, the phase of the SDRAM clock SD-CLK output from the controller is earlier than the leaf clock LCLK by the delay time Tin of the clock input buffer CLK-IN. Since this delay time Tin is very small, the phase of the SDRAM clock SD-CLK almost matches the phase of the leaf clock LCLK. That is, the phase of the clock SD-CLK output is the leaf clock LCLK regardless of the driving load of the clock signal wiring 34 (the size of the transmission delay time).
Is adjusted to match the phase of.

[0007]

Of the bus wiring 30,
Since the bus lines for address signals and control signals are connected in parallel to a plurality of SDRAMs mounted on the memory module 20, the load is very heavy. Therefore, the signals supplied to the memory module via those bus lines have a relatively large delay time.

On the other hand, the clock signal is similar to the address signal and the control signal, and the plurality of SDRAMs of the memory module 20.
Need to be supplied in parallel. However, in order to eliminate the deviation (skew) between the output timing on the memory control side and the input timing on the SDRAM side due to the driving load of the clock bus wiring 34, a relay buffer 36 incorporating a PLL circuit is provided. And this relay buffer 36
SD drive the four clock bus lines 38 again in parallel.
Four clocks are supplied to four clock input pins of the RAM module 20.

Since there is only one clock SD-CLK, it is possible to reduce the driving load on the memory controller side by providing the above-mentioned relay buffer 36. On the other hand, since there are multiple address signals and control signals,
Providing a relay buffer like a clock increases the circuit scale and is not a practical problem.

As described above, since the relay buffer 36 is provided, the bus wiring 34 driven by the clock output buffer CLK-OUT of the memory controller 10 is lighter than the address signal wiring 32. Moreover, in the memory controller 10, the DLL circuit prevents the SDRAM clock SD-CLK from being delayed by the bus 34,
Further, the PLL circuit built in the relay buffer 36 is also configured so that the delay due to the DIMM side bus 38 does not occur.

As a result, as compared with the SDRAM clock SD-CLK, the transmission of the address signal and the control signal on the bus becomes very slow, and the SDRAM side sets up the input address signal and control signal with respect to the clock SD-CLK. It may not be possible to secure a sufficient time margin. The setup time is, for example, the time when an address signal or a control signal should be input earlier than the rising timing of the clock. If the transmission time of the address signal or the control signal becomes long, it becomes difficult to secure the setup time.

Therefore, when designing with a high-speed clock cycle such as the PC133 standard (133 MHz clock cycle), it becomes difficult to transmit an address signal and a control signal in one clock cycle, and normally the memory controller 10
The address signal and the control signal are held for two clock cycles.

This means that a burst read operation with a burst length of 1 becomes impossible, and it is necessary to supply a command such as burst stop or precharge interrupt from one clock cycle before, which hinders the high speed operation of SDRAM. Has occurred.

Burst read is an operation mode in which a row address is supplied, a word line is driven by an active command, and then a column address is supplied to continuously output a predetermined number of read data. When set to 1, one read data is output for the supplied column address while driving the same word line. In that case, when the column address is changed, one read data is output. As mentioned above,
When supplying the column address, the memory controller 1
When 0 has to hold the column address for 2 clock cycles, it is 1 every 2 clock cycles even though there is only 1 read data output.
Only one read data can be output, which impairs high speed.

The burst stop operation is an operation for masking specific read data during burst read to prohibit the output, but the burst stop command is issued one clock cycle before the clock cycle of the read data to be masked. Need to supply. The precharge interrupt operation is an operation of causing the word line to fall together with the burst stop operation, but similarly, the precharge interrupt operation must be supplied from one clock cycle before.

Therefore, an object of the present invention is to provide a memory controller which can secure a sufficient setup time margin of an address signal and a control signal on the SDRAM side and supply these signals in one clock cycle. is there.

[0017]

In order to achieve the above object, one aspect of the present invention is to provide a synchronous memory module with an address signal and a control signal, and further a clock as a strobe signal thereof. In the memory controller to be supplied, a clock generation circuit for generating and outputting the timing of the supply clock at substantially the same timing as the reference leaf clock, and generating and outputting an address signal or control signal in response to a predetermined trigger clock. And a signal generating circuit for controlling the timing of the trigger clock of the leaf clock.

By making the timing of the trigger clock earlier than the timing of the leaf clock in response to the difference between the transmission delay time of the supply clock to the memory module and the transmission delay time of the address signal and the control signal, the memory module On the side, a sufficient setup margin can be secured.

In a more preferred embodiment, the clock generation circuit has a timing adjustment circuit for adjusting the leaf clock and the feedback clock of the supply clock in a predetermined timing relationship, and a predetermined delay is provided on the output side of the timing adjustment circuit. A delay buffer with time is provided and the trigger clock is generated from the input clock of the delay buffer. With such a configuration, it is possible to generate a trigger clock whose phase is earlier than that of the leaf clock while minimizing the circuit scale.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. However, the scope of protection of the present invention is not limited to the following embodiments,
The invention extends to the inventions described in the claims and their equivalents.

FIG. 2 is a connection wiring diagram of address signals and control signals in the DIMM of the SDRAM module. In the DIMM structure, a maximum of 8 SDRAM devices can be mounted on each of the front side 20A and the back side 20B of the module board, so that a maximum of 16 SDRAM devices can be mounted on both sides. The module board is provided with external pins 40 for DIMM,
The bus 30 is connected to the external pin 40. External pin 4
The signal supplied to 0 is the connection wiring 4 in the module board.
2 to each SDRAM device. When the address bus is composed of N lines, N sets of external pins 40 and connection wirings 42 of FIG. 2 are provided.

As shown in FIG. 2, the address signal Add
Since the control signal CON and the control signal CON are commonly provided to each SDRAM device, they are supplied from the external pins 40 for DIMM to the maximum 16 SDRAMs through the common connection wiring 42. Moreover,
Since there are many address signals and control signals, it is impossible to provide a relay buffer on the bus like a clock. Therefore, for the output buffer of the memory controller 10, the driving load of the bus line 32, the external pin 40 of the module substrate and the in-board connection line 42 is very heavy, and the transmission of the address signal Add and the control signal CON is accompanied by a large delay.

FIG. 3 is a connection wiring diagram of data signals in the DIMM of the SDRAM module. Generally, in the case of a data signal, each SDRAM device has eight data input / output terminals (DQ terminals), and a 64-bit data bus is formed by data input / output from eight SDRAM devices. That is, the external pins for the data signal of the DIMM are provided in eight groups of 64, which is eight groups. Therefore, the maximum number of DIMMs is 16
Since a SDRAM device can be mounted, one data signal Data can be output from the external pin 44 of the DIMM up to two SD
Supplied to RAM. Therefore, the load on the external pin 44 for the data signal is lighter than that of the address signal and the control signal.

FIG. 4 is a connection wiring diagram of clocks in the DIMM of the SDRAM module. D for clock
4 external pins 48 for 4 areas SDRAM in IMM
A clock is supplied through the four-system signal wiring 50 in the board. The four external pins 48 are driven by the relay buffer 36 described in FIG. With this configuration,
Delays caused by the buses 34 and 38 are prevented, and the timing of the clock SD-CLK input to the SDRAM is slightly delayed from the timing of the clock output from the memory controller.

As has been clarified in the concrete examples of FIGS. 2, 3 and 4, the driving load of the address signal and the control signal is relatively heavy and the driving load of the clock is light for the output buffer of the memory controller.

FIG. 5 is a diagram showing a memory controller and a bus structure in this embodiment. The memory controller 10 includes a clock source circuit 11 including a PLL and the like.
The source clock SCLK generated by the SDRAM is used as the leaf clock LCLK through the tree wiring having the buffer 14 as the SDRAM.
The clock is supplied to the timing adjustment circuit 12 for the clock. This is the same as the conventional example of FIG.
Are supplied to a large number of circuits (not shown) via a tree wiring having a buffer 14.

A delay buffer 16 having a predetermined delay amount is added to the DLL circuit including the timing adjusting circuit 12 and the feedback loop 15 between the timing adjusting circuit 12 and the clock output buffer CLK-OUT.

Even if the delay buffer 16 is inserted, the timing of the SDRAM clock SD-CLK output from the clock output buffer CLK-OUT is the same as in FIG. 1 due to the delay adjusting function of the timing adjusting circuit 12. Leaf clock LCLK to clock input buffer CLK-IN delay time Ti
The timing is adjusted by n.

On the other hand, in the present embodiment, not the leaf clock LCLK but the clock CLK12 output from the timing adjustment circuit 12 and input to the added delay buffer 16 is used as the trigger clock of the flip-flop 13 which is the address generation circuit. input. That is, the delay buffer 16 generates the trigger clock CLK12 that is earlier than the leaf clock LCLK, and the address signal Add is generated based on the trigger clock CLK12. The control signal CON is the same as the address signal Add. In that case, the address generation circuit 13 and the address output buffer Add-
OUT constitutes a control signal generating circuit and a control signal output buffer (not shown), respectively.

As described above, the timing of the SDRAM clock SD-CLK is almost matched with the timing of the leaf clock LCLK by the DLL circuit, while the timing of the address signal generation and the control signal generation is set to the leaf clock. LC
It is a certain time earlier than LK. As a result, the output timing of the address signal or control signal with a heavy drive load from the memory controller can be made earlier than the output timing of the clock with a light drive load, and the input timing and clock of the address signal or control signal on the SDRAM side and the clock SD
-The input timing of CLK can be matched. Therefore, it is possible to avoid the occurrence of setup time errors on the SDRAM side, which has been a problem in the past.

In order to advance the timing of the generation of the address signal and the generation of the control signal by a predetermined time relative to the leaf clock LCLK, in the example of FIG. 5, the delay buffer 16 is inserted in the DLL circuit to trigger the timing. Clock CLK12
Is generated and the input clock CLK1 to the delay buffer 16 is generated.
2 is used for the trigger clock of the address generator and control signal generator. With such a configuration, it is possible to minimize an increase in circuit scale and easily generate a trigger clock whose timing is earlier than that of the leaf clock LCLK (more accurately, SDRAM clock SD-CLK).

The clock CLK12 is supplied to a plurality of address signal generating circuits 13 (not shown) through a tree wiring having a buffer 18. With such a configuration, it is not necessary to request the timing adjustment circuit 12 to have an excessive driving capability.

As another configuration example, the DLL circuit of FIG. 1 may be left as it is and the DLL circuit of FIG. 5 may be added. Then, with the added DLL circuit, the leaf clock L
Generates a trigger clock CLK12 that is earlier than CLK and uses it as a trigger clock for the address signal generation circuit and control signal generation circuit.

A tree wiring having a buffer 14 is provided between the source clock SCLK generated by the clock source circuit 11 and the leaf clock LCLK. Therefore,
A delay buffer can be added in this tree wiring to generate a trigger clock that is generated earlier than the leaf clock LCLK. However, the leaf clock LCLK is supplied to a large number of flip-flops in addition to the timing adjustment circuit 12. Therefore, with the above-described configuration, it is necessary to add a buffer to all of these tree wirings, and the circuit scale is large. Will lead to an increase.

FIG. 6 is a transmission timing chart of the address signal of FIG. The control signal is also the same as the address signal, and the address signal will be described below as an example.

The reference leaf clock LCLK in the memory controller 10 is shown at the top of FIG. The leaf clock LCLK is
It is adjusted to have the same phase as the clock of the feedback loop 15. Therefore, the SDRAM on the memory controller 10 side
The phase of the clock SD-CLK for use is the feedback loop 15
The delay time Tin of the clock input buffer CLK-IN in the inside is advanced. Further, the trigger clock CLK12 for the address generation circuit has a total delay time (Td + Tout + Ti) of the clock input buffer CLK-IN, the clock output buffer CLK-OUT, and the delay buffer 16 rather than the leaf clock LCLK.
n) faster. That is, trigger clock CLK12
Is earlier than the SDRAM clock SD-CLK on the memory controller side.

Therefore, the output timing of the address signal on the memory controller side is delayed by the total delay time (TFF + Tout) of the flip-flop 13 and the address output buffer Add-OUT from the leaf clock LCLK in the example before improvement in FIG. ing. On the other hand, in the example after improvement in FIG.
It is delayed from the trigger clock CLK12 by the total delay time (TFF + Tout + Tb) of the flip-flop 3, the address output buffer Add-OUT, and the buffer 18. Since the trigger clock CLK12 leads the leaf clock LCLK in phase, the output timing of the address signal is earlier than that of the conventional example.

A timing chart on the SDRAM side in the DIMM is shown in the lower half of FIG. The clock SD-CLK input to the SDRAM side in the DIMM has a timing slightly delayed from the timing on the memory controller 10 side by the relay buffer 36. That is, as shown in the figure, the phase is delayed by the sum of the bus wiring delay and the wiring delay in the DIMM.

On the other hand, the address signal input to the SDRAM side in the DIMM has a timing considerably delayed from the timing on the memory controller 10 side. That is, the phase is delayed by the sum of the address signal bus wiring delay and the DIMM wiring delay. Therefore, in the example before improvement in Fig. 1, the DIMM
The address signal on the SDRAM side of the above is delayed in phase from the rising edge of the clock SD-CLK which is a strobe signal, and the setup time cannot be secured. Therefore, conventionally, the address signal is held for two clock cycles and input at the next rising edge of the clock SD-CLK.

On the other hand, in the example after improvement shown in FIG.
The address signal on the SDRAM side in the MM leads the phase of the rising edge of the clock SD-CLK, which is a strobe signal, and secures a sufficient setup time.
Therefore, even if the memory controller holds the address signal only for one clock cycle period, the SDRAM in the DIMM can surely fetch the address signal.

The delay amount Td of the delay buffer 16 added in the DLL circuit is determined by the delay time of the bus wiring of the address signal and the DIMM.
The difference between the total time of the internal wiring delay time and the same total time of the clock signal, and the flip-flop 14 and the buffer 1
Considering the delay times TFF and Tb of 8, it is designed to ensure a sufficient setup time on the SDRAM side. Address output buffer Add-OUT and clock output buffer CLK-OUT
If the delay time Tout of is different, it also needs to be taken into consideration.

The above improvement of the timing of the address signal can be similarly applied to the control signal.
Further, in the case of data, as shown in FIG. 3, the driving load is relatively light, but the driving load is heavier than the clock. Therefore, if it is necessary to accelerate the output timing, a large number of buffer circuits are used. The generation of write data may be controlled with reference to the clock in the middle of the delay buffer 16 configured by connection. That is, the output timing of the address signal and the control signal is the earliest, the output timing of the write data is next, and then the clock SD-CLK is output.

The above embodiments are summarized below.

(Supplementary Note 1) In a memory controller for supplying an address signal and a control signal to a synchronous memory module, and further a clock as a strobe signal thereof, a reference leaf clock and a feedback clock of the supply clock. To a predetermined timing relationship, a clock generation circuit for generating and outputting the timing of the supply clock at substantially the same timing as the leaf clock, and the address signal in response to a predetermined trigger clock. Or a signal generating circuit for generating and outputting a control signal, and at the output side of the timing adjusting circuit in the clock generating circuit,
A memory controller comprising a delay buffer having a predetermined delay time, wherein the trigger clock is generated from an input clock of the delay buffer.

(Supplementary Note 2) In Supplementary Note 1, the delay time of the delay buffer includes a transmission delay time of the supply clock to the memory module and a transmission delay time of the address signal or the control signal to the memory module. A memory controller characterized in that the time is selected according to the difference.

(Supplementary Note 3) In Supplementary Note 1, the delay time of the delay buffer is selected so that the address signal or the control signal on the memory module side has a proper setup time with respect to the supplied supply clock. A memory controller characterized by the fact that it is a different time.

(Supplementary note 4) The memory controller according to supplementary note 1, wherein the input clock of the delay buffer is supplied in parallel to a plurality of signal generating circuits via a tree wiring having a buffer.

(Supplementary Note 5) In Supplementary Note 1, the delay buffer has a structure in which a plurality of buffers are connected in series,
A memory controller, wherein a trigger clock of a data signal generating circuit is generated from clocks in the middle of the plurality of buffers.

(Supplementary Note 6) In the memory controller for supplying the address signal and the control signal to the synchronous memory module, and further the clocks as the strobe signals thereof, the reference leaf clock and the supply clock are fed back. A clock generation circuit that has a timing adjustment circuit that adjusts the clock to a predetermined timing relationship and that generates and outputs the timing of the supply clock at substantially the same timing as the leaf clock; and the clock generation circuit that responds to a predetermined trigger clock. A signal generation circuit for generating and outputting an address signal or a control signal, wherein the timing of the trigger clock is controlled to be earlier than the leaf clock.

[0050]

As described above, according to the present invention, the trigger pulse of the address signal or the control signal having a long transmission delay time of the bus can be set to a timing earlier than the leaf clock which is the reference of the clock, and the memory module side can It is possible to secure a sufficient setup margin.

[Brief description of drawings]

FIG. 1 is a diagram showing a conventional SDRAM controller and a bus structure.

FIG. 2 is a connection wiring diagram of address signals and control signals in the DIMM of the SDRAM module.

FIG. 3 is a connection wiring diagram of data signals in a DIMM of an SDRAM module.

FIG. 4 is a wiring diagram for connecting clocks in a DIMM of an SDRAM module.

FIG. 5 is a diagram showing a memory controller and a bus structure in the present embodiment.

6 is a transmission timing chart of the address signal of FIG.

[Explanation of symbols]

10 memory controller 12 Timing adjustment circuit 15 Feedback loop 16 delay buffer 20 memory modules, SDRAM DIMMs 30 bus

Claims (5)

[Claims] 1. A memory controller for supplying an address signal and a control signal to a synchronous memory module, and a clock as a strobe signal for the address signal and the control signal.
A clock generation circuit having a timing adjustment circuit for adjusting a reference leaf clock and a feedback clock of the supply clock to a predetermined timing relationship, and generating and outputting the timing of the supply clock at substantially the same timing as the leaf clock. And a signal generation circuit that generates and outputs the address signal or the control signal in response to a predetermined trigger clock, and provides a predetermined delay time to the output side of the timing adjustment circuit in the clock generation circuit. A memory controller comprising a delay buffer having the trigger clock, wherein the trigger clock is generated from an input clock of the delay buffer. 2. The delay time of the delay buffer is a difference between a transmission delay time of the supply clock to the memory module and a transmission delay time of the address signal or control signal to the memory module. A memory controller characterized in that the time is selected according to. 3. The delay time of the delay buffer according to claim 1, wherein the address signal or control signal on the memory module side has a proper setup time with respect to a supplied clock. A memory controller characterized by being time. 4. The clock according to claim 1, wherein the input clock of the delay buffer is passed through a tree wiring having a buffer,
A memory controller characterized by being supplied in parallel to a plurality of signal generation circuits. 5. A memory controller for supplying an address signal and a control signal to a synchronous memory module and a clock as a strobe signal for the address signal and the control signal.
A clock having a timing adjustment circuit for adjusting a reference leaf clock and a clock fed back from the supply clock to a predetermined timing relationship, and generating and outputting the timing of the supply clock at substantially the same timing as the leaf clock. A generation circuit and a signal generation circuit that generates and outputs the address signal or the control signal in response to a predetermined trigger clock, and the timing of the trigger clock is controlled to be earlier than the leaf clock. A memory controller characterized in that.