JP2003185698A - Apparatus and method for detecting failure of integrated circuit and recording medium with record of integrated circuit failure detection program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit failure detector which allows the minimum resolution to be reduced low against increase of a source current, and provide an insulation failure detecting method and a recording medium with a record of integrated circuit failure detection programs. <P>SOLUTION: A current detector unit 30 observes a source current to be fed to an integrated circuit 31 under test to send information of the observed source current as an observed current signal to a DC component eliminator unit 31. This unit removes DC components from the observed current signal sent from the detection unit 30 to take out only AC components, and amplifies the AC components of the taken observed current signal to regenerate and send the observed current signal to a sampling unit 34. This unit samples only the AC components except of the DC components and discrete-Fourier-transforms them, thereby enabling the failure detection. Thus, a lower resolution is obtainable by sampling only the AC components except the DC components of the source current. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure detection device for detecting the presence / absence of a failure in an integrated circuit by analyzing the value of a power supply current flowing in the integrated circuit, a failure detection method, and a computer readable recording failure detection program. The present invention relates to a recording medium, and more particularly to a failure detection device for an integrated circuit, which suppresses the minimum resolution, a failure detection method for the integrated circuit, and a computer-readable recording medium which records a failure detection program for the integrated circuit.

[0002]

2. Description of the Related Art Conventionally, an integrated circuit failure detection method is disclosed in, for example, Japanese Patent Laid-Open No. 11-142468 (Patent No. 30925).
No. 90). In the method disclosed in this publication, in order to detect the presence or absence of a failure in the integrated circuit, a test signal is applied to the integrated circuit under test, and in the power supply current flowing at that time, an abnormal power supply current caused by the presence of the failure is detected. is doing.

FIG. 7 is a block diagram showing the configuration of a conventional integrated circuit failure detection device disclosed in Japanese Patent Application Laid-Open No. 11-142468.

In this conventional failure detection device, an integrated circuit under test (DUT) 4 is electrically connected to the LSI tester 3. The test pattern storage unit 1 and the program storage unit 2 are connected to the LSI tester 3. The test pattern storage unit 1 has an integrated circuit 4 under test.
The data of the test signal to be applied to is stored. The program storage unit 2 stores data for driving the LSI tester 3.

The LSI tester 3 generates a test signal for testing the integrated circuit under test 4 based on the data stored in each of the test pattern storage unit 1 and the program storage unit 2, and tests the test signal. It is applied to the integrated circuit 4.

The integrated circuit under test 4 has a current detection unit 6
A power source 5 is connected via the power source 5 and the power source 5 supplies power to the integrated circuit under test 4 for operating the integrated circuit under test 4. The magnitude of the power supply current supplied to the integrated circuit under test 4 is successively observed by the current detection unit 6 and the information is sent to the spectrum analysis unit 7.

A judgment device 8 is connected to the spectrum analysis unit 7 and judges whether or not there is a failure in the integrated circuit under test 4 from the frequency spectrum of the power supply current flowing through the integrated circuit under test 4.

FIG. 8 is a flow chart showing a failure detecting method using the failure detecting device shown in FIG.

When detecting a failure of an integrated circuit, first,
The LSI tester 3 inputs the test pattern information from the test pattern storage unit 1 (step S1) and the test program information from the program storage unit 2 (step S2).

Next, the LSI tester 3 generates a test signal from the test pattern information and the test program information, and continuously applies the test signal to the integrated circuit under test 4 (step S3). In this case, the application cycle of the test signal by the LSI tester 3 is T.

Power is supplied from the power supply 5 to the integrated circuit under test 4 via the current detection unit 6 (step S).
4). The current detection unit 6 observes the power supply current supplied to the integrated circuit under test 4 (step S5), and the observed information is sent to the spectrum analysis unit 7.

The spectrum analysis unit 7 analyzes the frequency spectrum of the power supply current information sent from the current detection unit 6, and sends the result to the decision unit 8 (step S).
6).

The judging device 8 compares the observed value of the spectrum power of the frequency f1 = 1 / T and its harmonics with a predetermined specified value, and all the observed values are included within the specified range. It is determined whether or not there is (step S7). In this case, the judging device 8 judges that the integrated circuit under test 4 is a good product if all are within the specified value, and otherwise judges the integrated circuit 4 under test as a defective product.

Further, Japanese Unexamined Patent Publication No. 2000-46899 (Japanese Patent No. 3085284) discloses a method for obtaining spectrum information of a power supply current flowing through an integrated circuit under test.

FIG. 9 is a block diagram showing the configuration of a conventional integrated circuit failure detection device disclosed in Japanese Patent Laid-Open No. 2000-46899.

In this conventional failure detection device, the LS
A test pattern storage unit 17 and a program storage unit 18 are connected to the I tester 16. The test pattern storage unit 17 stores information on a test signal applied to the integrated circuit under test 21, and the program storage unit 1
8 is an LSI tester 1 for generating the test signal.
Information for operating 6 is stored. LSI tester 16
The integrated circuit under test 21 is connected to the LSI tester 16
Therefore, a test signal can be applied to the integrated circuit 21 under test.

The integrated circuit under test 21 is connected to the power supply 19 via the current unit 20, and the power supply current required for the operation of the integrated circuit under test 21 is supplied. The current detection unit 20 observes the power supply current and sends the information to the sampling unit 24 as a current observation signal.

The timing signal generation unit 23 is an LSI
It is connected to the tester 16 and receives the application information of the test signal to generate a timing signal. The control unit 22 is connected to the timing signal generation unit 23, receives the timing signal, and notifies the sampling unit 24 of the start and end of sampling. The sampling unit 24 is connected to the control unit 22 and performs sampling of the current observation signal according to the sampling start signal and the end signal. The sampling unit 24 sends the sampled data to the data storage unit 26, and the data storage unit 26 stores and holds the data. The arithmetic unit 25 is connected to the control unit 22 and the data storage unit 26, and the sampling data is read from the data storage unit 26 by an arithmetic instruction from the control unit 22.
Performs a discrete Fourier transform operation. The operation unit 25 is connected to the LSI tester 16, and the result of executing the discrete Fourier transform operation is sent to the LSI tester 16. The LSI tester 16 determines whether there is a failure in the integrated circuit under test 21 based on the result.

Next, the operation of the conventional failure detecting device constructed as described above will be described.

First, the LSI tester 16 generates a test signal to be applied to the integrated circuit under test 21. The test signal is the test pattern information stored in the test pattern storage unit 17 and the L stored in the program storage unit 18.
From the programming information of SI tester 16, it is generated as a series of electrical signals of appropriate voltage and speed.

This series of test signals is continuously and repeatedly applied to the integrated circuit under test 21 based on the program information. The number of repetitions is 1 or more.

Power supply 1 for operating integrated circuit under test 21
9 is provided, the power supply current supplied to the integrated circuit under test 21 is observed by the current detection unit 20, and the information of the observed power supply current is sent to the sampling unit 24 as a current observation signal.

The LSI tester 16 generates a series of test signals and repeatedly applies them to the integrated circuit under test 21,
For each repetition, the repetition information is sent to the timing signal generation unit 23.

The timing signal generation unit 23 is an LSI
Based on the repetition information sent from the tester 16, a timing signal synchronized with the cycle of the test signal is generated. For example, a pulse signal is generated in synchronization with the cycle of the test signal. The timing signal is sent to the control unit 22 to generate sampling start and end cues of the current observation signal.

The sampling unit 24 starts sampling the current observation signal with a sampling start signal. The sampling interval in the sampling unit 24 is predetermined. The sampled data is sequentially sent to the data storage unit 26 for storage and storage. Sampling of the current observation signal is continued until a sampling end signal is received.

The control unit 22 sends an operation instruction to the operation unit 25 after generating the sampling end signal. The arithmetic unit 25 reads the sampling data from the data storage unit 26 according to the arithmetic instruction, and executes the discrete Fourier transform operation.

Further, if the sampling data is data for two cycles or more instead of one cycle of the application period of the test signal, even if the measurement noise is reduced by averaging the data for one cycle. Good.

The calculation result is the magnitude of each frequency component of the 0th order, the 1st order, the 2nd order, ... Of the repetition period of the power supply current, and the result is sent to the LSI tester 16.

The LSI tester 16 judges the magnitude of each frequency component based on a predetermined specified value, and judges whether the integrated circuit under test 21 has a failure.

An AD converter is usually used in the sampling of the current observation signal as described above. The maximum input voltage and the resolution are set in the AD converter, and in the sampling of the current observation signal, the maximum voltage value of the current observation signal does not exceed the maximum input voltage of the AD converter in order not to impair the dynamic range. It is adjusted to the maximum in the range.

[0031]

However, in recent years,
Since the power supply current value flowing in the integrated circuit continues to increase due to the high integration and miniaturization of the integrated circuit, the minimum resolution obtained by the AD converter becomes relatively large, and a minute abnormal power supply current cannot be detected. There is a problem. That is, the maximum current value is 10 m with the same AD converter.
The minimum resolution when sampling the current value of A is 1μ
In the case of A, the minimum resolution when sampling a current having a maximum current value of 100 mA is 10 μA. In this way, the increase in the minimum resolution makes it impossible to detect a minute abnormal power supply current in the observation of the abnormal power supply current due to a failure.

The present invention has been made in view of the above problems, and has an integrated circuit failure detection device, an integrated circuit failure detection method, and an integrated circuit which can suppress the minimum resolution to a low level even if the power supply current value increases. An object of the present invention is to provide a recording medium recording a circuit failure detection program.

[0033]

A failure detecting device for an integrated circuit according to the present invention analyzes a frequency of a power supply current flowing through the integrated circuit when a test signal is applied to the integrated circuit to analyze the failure of the integrated circuit. A failure detecting device for an integrated circuit, which performs detection, is characterized by having a direct current component removing means for removing a direct current component from a current observation signal indicating a value of a power supply current flowing through the integrated circuit and extracting only an alternating current component.

In the present invention, the direct current component of the current observation signal is removed by the direct current component removing means, but it is sufficient that the alternating current component remains for the failure detection.
Then, by removing the DC component, fine resolution can be obtained, so that the sensitivity of failure detection is improved.

The DC component removing means may have a high-pass filter, and a capacitive element connected to one end of a resistive element provided on a path through which the power supply current flows, the capacitive element and the resistive element. And a resistance element for removing a direct current component, which is connected between the other end and the other end. in this case,
It is preferable that the DC component removing means further includes an amplifier that amplifies a current flowing across the DC component removing resistive element.

The DC component removing means may include a transformer for extracting the AC component of the current, and preferably an amplifier for amplifying the secondary side current of the transformer.

The failure detection method for an integrated circuit according to the present invention comprises:
In a failure detection method of an integrated circuit for detecting a failure of the integrated circuit by analyzing a frequency of a power supply current flowing through the integrated circuit when a test signal is applied to the integrated circuit, a value of a power supply current flowing through the integrated circuit is calculated. The method is characterized by including a step of removing a DC component from the current observation signal shown and extracting only an AC component.

A computer-readable recording medium recording the integrated circuit failure detection program according to the present invention,
When a test signal is applied to the integrated circuit, the frequency of a power supply current flowing through the integrated circuit is analyzed to detect a failure of the integrated circuit. The present invention is characterized by having a direct current component removing means for removing the direct current component from the current observation signal indicating the value of the power supply current and extracting only the alternating current component.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an integrated circuit failure detecting device and a failure detecting method according to embodiments of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a block diagram showing the configuration of an integrated circuit failure inspection apparatus according to an embodiment of the present invention.

In this embodiment, a test pattern storage unit 27 and a program storage unit 28 are connected to the LSI tester 26. The test pattern storage unit 27 stores information on a test signal applied to the integrated circuit under test (DUT) 31, and the program storage unit 28 stores the information.
In order to generate the test signal, the LSI tester 26
Information for operating is stored. An integrated circuit under test (DUT) 31 is connected to the LSI tester 26, and a test signal can be applied from the LSI tester 26 to the integrated circuit under test (DUT) 31.

The integrated circuit under test (DUT) 31 has a power supply 29.
To the integrated circuit under test (DUT) 31 and is supplied with a power supply current necessary for the operation of the integrated circuit under test (DUT) 31. The current detection unit 30 observes the power supply current and sends the information as a current observation signal to the DC component removal unit 37.

The DC component removing unit 37 is connected to the current detecting unit 30, removes the DC component from the current observation signal transmitted from the current detecting unit 30, generates the current observation signal only from the AC component, and the sampling unit 34. I am sending it to.

The timing signal generation unit 33 is an LSI
It is connected to the tester 26 and receives the application information of the test signal to generate a timing signal. The control unit 32 is connected to the timing signal generation unit 33, receives the timing signal, and notifies the sampling unit 34 of the start and end of sampling. The sampling unit 34 is connected to the control unit 32, and performs sampling of the current observation signal sent from the DC component removing unit 37 according to the sampling start signal and the end signal. The sampling unit 34 sends the sampled data to the data storage unit 36, and the data storage unit 36 stores and holds the data. The arithmetic unit 35 is the control unit 32
And the data storage unit 36, and the data storage unit 36 is operated by an operation command from the control unit 32.
The sampling data is read from and the discrete Fourier transform operation is executed. The arithmetic unit 35 is the LSI tester 26.
The result of performing the discrete Fourier transform operation is L
It is sent to the SI tester 26. The LSI tester 26 determines whether there is a failure in the integrated circuit under test (DUT) 31 based on the result.

Next, the operation of the fault detecting apparatus of the present embodiment constructed as described above, that is, the fault detecting method will be described. FIG. 2 is a flowchart showing the operation of the failure detection device for an integrated circuit according to the embodiment of the present invention.

First, the LSI tester 26 generates a test signal to be applied to the integrated circuit under test (DUT) 31 (step S11). The test signal is generated as a series of electric signals of appropriate voltage and speed from the test pattern information stored in the test pattern storage unit 27 and the program information of the LSI tester 26 stored in the program storage unit 28.

This series of test signals is continuously repeated based on the program information to be tested integrated circuit (DUT) 3
1 (step S12). The number of repetitions is 1
More than once.

A power supply 29 is provided for the operation of the integrated circuit under test (DUT) 31, and the integrated circuit under test (DU) is provided.
T) 31 is the power supply current supplied to the current detection unit 30.
The information of the observed power supply current is transmitted to the DC component removing unit 37 as a current observation signal (step S13).

The DC component removing unit 37 removes the DC component from the current observation signal sent from the current detecting unit 30,
Take out only the AC component. The direct current component removing unit 37 further amplifies the extracted alternating current component of the current observation signal to an appropriate size to regenerate the current observation signal and transmits it to the sampling unit 34 (step S14).

The LSI tester 26 generates a series of test signals and repeatedly applies them to the integrated circuit under test (DUT) 31, but sends the repetition information to the timing signal generating unit 33 at each repetition (step S15).

The timing signal generation unit 33 is an LSI
Based on the repetition information sent from the tester 26, a timing signal synchronized with the cycle of the test signal is generated. For example, a pulse signal is generated in synchronization with the cycle of the test signal. The timing signal is sent to the control unit 32 to generate a sampling start signal and an end signal of the current observation signal (step S16).

When the sampling unit 34 receives the sampling start signal, it starts sampling the current observation signal sent from the DC component removing unit 37. The sampling interval in the sampling unit 34 is predetermined. The sampled data is sequentially sent to the data storage unit 36 and stored and held. Sampling of the current observation signal is continued until the sampling end signal is received (step S17).

After generating the sampling end signal, the control unit 32 sends an operation instruction to the operation unit 35. The arithmetic unit 35 reads the sampling data from the data storage unit 36 in accordance with the arithmetic instruction, and executes the discrete Fourier transform operation (step S18).

If the sampling data is data for two cycles or more instead of one cycle of the application period of the test signal, averaging processing may be performed for one cycle data and measurement noise may be reduced. Good.

The calculation result is the magnitude of each frequency component of the primary, secondary, tertiary ... Of the repetition cycle of the power supply current, and the result is sent to the LSI tester 26 (step S19).

The LSI tester 26 determines the magnitude of each frequency component based on a predetermined stipulated value, and determines whether or not there is a failure in the integrated circuit under test (DUT) 31 (step S20).

The results obtained by performing the discrete Fourier transform on the sampling result of the current observation signal are the 0th, 1st, 2nd, ... Each frequency component based on the repetition period T of the power supply current. In this embodiment, the presence or absence of a failure in the integrated circuit under test is determined by comparing the magnitudes of these frequency components. Here, the 0th-order frequency component represents the magnitude of the DC component of the power supply current value, and failure detection is possible without this information.

That is, only the AC component excluding the DC component of the power supply current is sampled and subjected to the discrete Fourier transform, and the failure is detected by using each of the obtained primary, secondary, ... Frequency components. But there is no problem.

On the contrary, by excluding the direct current component of the power supply current and sampling only the alternating current component by the AD converter,
A smaller resolution can be obtained in sampling the power supply current. This effect becomes more remarkable as the magnitude of the direct current component in the power supply current increases. That is,
As shown in FIG. 3, when the entire power supply current is converted by the AD converter, the minimum resolution becomes a large value because the AD conversion is performed in accordance with the maximum value of the entire power supply current.
On the other hand, if the direct current component of the power supply current is excluded and only the alternating current component is converted by the AD converter, it is not necessary to perform the AD conversion including the extra direct current component, so that the minimum resolution can be reduced.

Therefore, according to this embodiment, it is possible to reduce the resolution and improve the sensitivity of failure detection.

Note that the series of operations may be described by describing the control operation as a control program and executing the control program by the control unit 32 to control the operation of each unit. In this case, the control unit 3
A control program can be stored in a recording medium (not shown) such as a ROM or a floppy disk attached to the control unit 2, and the control program can be loaded into the control unit 32 and executed.

The configurations of the DC component removing unit 37, the current detecting unit 30 and the like are not particularly limited. FIG. 4 is a block diagram showing an example of the DC component removing unit 37.

In this example, a high-pass filter 37-1 is provided as the DC component removing unit 37. The high-pass filter allows signals above the specified frequency to pass,
It has a characteristic of blocking other frequencies, and by setting the frequency to an extremely low value, only the DC component can be removed. Further, the lower limit value of the frequency to be passed may be effectively set, for example, between the frequency f = 1 / T and 0 determined by the cycle T of repeated application of the test signal.

FIG. 5 is a block diagram showing an example of a set of the DC component unit 37 and the current detection unit 30.

In this example, the detection resistor 30-1 is provided as the current detection unit 30, and the DC component removal unit 37 is provided.
A circuit including a capacitor C and a resistor R and an amplifier 38 are provided. A current observation signal that changes according to the magnitude of the power supply current is generated by the detection resistor 30-1, and the circuit including the resistor R and the capacitor C removes the direct current component from the current observation signal to generate a current observation signal that includes only the alternating current component. Is generated. Then, this signal is amplified by the amplifier 38 into a signal of an appropriate size and output.

The resistance value and the capacitance value of the resistor R and the capacitor C may be appropriately determined so that the signal of the frequency f = 1 / T is passed.

Although the amplifier 38 is provided in the above-mentioned example, if the amplifying means is provided in the sampling unit 34, the amplifier 38 may not be provided in the DC component removing unit 37.

FIG. 6 is a block diagram showing another example of a set of the DC component unit 37 and the current detection unit 30.

In this example, the transformer 39 and the amplifier 40 form a current detecting unit 30 and a DC component removing unit 37 which are integrated. When the power supply current flows to the primary side of the transformer 39, a current observation signal representing an alternating current component of the power supply current is generated on the secondary side of the transformer 39. This current observation signal is amplified to an appropriate size by the amplifier 40 and transmitted to the sampling unit 34. In addition,
If the sampling unit 34 is provided with amplification means, the amplifier 40 may not be provided.

[0069]

As described in detail above, according to the present invention,
Fine resolution can be obtained by removing the DC component. Therefore, the sensitivity of failure detection can be improved. Even if the DC component of the current observation signal is removed, it is sufficient to extract the AC component in order to detect the failure.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an integrated circuit failure inspection apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the failure detection device for an integrated circuit according to the exemplary embodiment of the present invention.

FIG. 3 is a graph showing a direct current component and an alternating current component of a power supply current forming a current observation signal.

FIG. 4 is a block diagram showing an example of a DC component removing unit 37.

FIG. 5 is a DC component unit 37 and a current detection unit 30.
3 is a block diagram showing an example of a set of FIG.

FIG. 6 is a DC component unit 37 and a current detection unit 30.
It is a block diagram showing another example of a set of.

FIG. 7 is a block diagram showing a configuration of a conventional integrated circuit failure detection device disclosed in Japanese Patent Application Laid-Open No. 11-142468.

8 is a flowchart showing a failure detection method using the failure detection device shown in FIG.

FIG. 9 is a block diagram showing the configuration of a conventional integrated circuit failure detection device disclosed in Japanese Patent Laid-Open No. 2000-46899.

[Explanation of symbols]

1, 17, 27; test pattern storage unit 2, 18, 28; program storage unit 3, 16, 26; LSI tester 4, 21, 31; integrated circuit under test (DUT) 5, 19, 29; power supply 6, 20, 30; current detection unit 7; Spectrum analysis unit 8: Judgment device 22, 32; control unit 23, 33; timing signal generation unit 24, 34; sampling unit 25, 35; arithmetic unit 26, 36; data storage unit 30-1: Detection resistor 37; DC component removal unit 37-1; High-pass filter 38, 40; amplifier 39; Transformer

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Claims (8)

[Claims] 1. A failure detection device for an integrated circuit, which detects a failure of the integrated circuit by analyzing a frequency of a power supply current flowing through the integrated circuit when a test signal is applied to the integrated circuit. A failure detecting device for an integrated circuit, comprising a DC component removing means for removing a DC component from a current observation signal indicating a value of a power supply current and extracting only an AC component. 2. The failure detecting device for an integrated circuit according to claim 1, wherein the DC component removing means has a high-pass filter. 3. The DC component removing means is connected between a capacitive element connected to one end of a resistive element provided on a path through which the power supply current flows, and between the capacitive element and the other end of the resistive element. 2. The failure detecting device for an integrated circuit according to claim 1, further comprising a resistance element for removing a direct current component. 4. The failure detection device for an integrated circuit according to claim 3, wherein the direct current component removing means has an amplifier for amplifying a current flowing across the direct current component removing resistance element. 5. The direct current component removing means includes a transformer for extracting an alternating current component of the current.
A failure detection device for an integrated circuit according to item 1. 6. The failure detection device for an integrated circuit according to claim 5, wherein the DC component removing means has an amplifier for amplifying a secondary current of the transformer. 7. A failure detection method for an integrated circuit, wherein a failure of the integrated circuit is detected by analyzing a frequency of a power supply current flowing through the integrated circuit when a test signal is applied to the integrated circuit. A method of detecting a failure in an integrated circuit, comprising a step of removing a DC component from a current observation signal indicating a value of a power supply current and extracting only an AC component. 8. A recording medium in which a failure detection program for an integrated circuit for detecting a failure of the integrated circuit by analyzing a frequency of a power supply current flowing through the integrated circuit when a test signal is applied to the integrated circuit is recorded. A computer readable recording program of a failure detection program for an integrated circuit, comprising a DC component removing means for removing a DC component from a current observation signal indicating a value of a power supply current flowing through the integrated circuit and extracting only an AC component. Recording medium.